US20210296453A1 - Split gate structure, power mos device, and manufacturing method - Google Patents

Split gate structure, power mos device, and manufacturing method Download PDF

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US20210296453A1
US20210296453A1 US15/931,603 US202015931603A US2021296453A1 US 20210296453 A1 US20210296453 A1 US 20210296453A1 US 202015931603 A US202015931603 A US 202015931603A US 2021296453 A1 US2021296453 A1 US 2021296453A1
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polysilicon
split gate
gate structure
trench
characteristic oxide
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Yuan Cheng Zheng
Xin Huan Shi
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Hejian Technology Suzhou Co Ltd
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Definitions

  • the present invention relates to the technical field of semiconductor, particularly to a split gate structure which can effectively improve the breakdown performance and the IGSS performance, a power MOS device, and a manufacturing method.
  • split gate power MOS split gate power FET
  • IGSS performance and the breakdown performance are important parameters for evaluating the performance of a split gate power MOS. Therefore, the improvement of the breakdown performance and the IGSS performance of a split gate power MOS becomes a problem to be solved in the technical field of semiconductor.
  • a split gate structure which can effectively improve the breakdown performance and the IGSS performance, a power MOS device having the same, and a manufacturing method of the same are provided in the present invention.
  • a split gate structure comprises a first polysilicon, a characteristic oxide, and a second polysilicon sequentially disposed in a trench in a vertical direction upward from a bottom of the trench.
  • An upper surface of the characteristic oxide has a height difference less than 1500 ⁇ between a higher center portion and a lower periphery portion.
  • the characteristic oxide is further disposed between the first polysilicon and a wall and the bottom of the trench.
  • an effective distance between the first polysilicon and the second polysilicon which is the smallest distance between the first polysilicon and the second polysilicon, is larger than 0.2 mm.
  • a power MOS device comprises any split gate structure as described above.
  • a manufacturing method of a split gate structure comprises:
  • step 2 performing a first etching process on the first polysilicon
  • step 3 dipping in an acid solution such that a portion of the characteristic oxide is removed
  • step 4 performing a second etching process on the first polysilicon such that the first polysilicon has a height lower than a height of the characteristic oxide disposed in the trench;
  • step 5 performing a thermal oxidation process such that a characteristic oxide with an upper surface having a height difference less than 1500 ⁇ between a higher center portion and a lower periphery portion is formed on a top of the first polysilicon;
  • step 6 depositing a second polysilicon in the trench.
  • a height difference between the first polysilicon and the characteristic oxide is 0.05 to 0.15 mm.
  • an effective distance between the first polysilicon and the second polysilicon which is the smallest distance between the first polysilicon and the second polysilicon, is larger than 0.2 mm.
  • the present invention has the following advantages over the existing technology. Compared to a conventional split gate structure, in the new split gate structure fabricated by the manufacturing method of a split gate structure according to the present invention, the flatness of the contact surface between the characteristic oxide and the polysilicon is improved, and thereby the effective distance between the first polysilicon and the second polysilicon is increased. As such, the breakdown performance and the IGSS performance of the split gate power MOS are effectively improved.
  • FIG. 1 is a flow diagram of the manufacturing processes of a split gate structure according to the existing technology.
  • FIGS. 2A-2E illustrate the manufacturing processes of a split gate structure of FIG. 1 .
  • FIG. 3 is a flow diagram of the manufacturing processes of a split gate structure according to embodiments of the present invention.
  • FIGS. 4A-4F illustrate the manufacturing processes of a split gate structure of FIG. 3 .
  • FIG. 5 shows the composition of leakage performance between a split gate according to the present invention and a split gate according to the existing technology.
  • FIG. 6 illustrates the test sites for the leakage test of FIG. 5 .
  • a conventional manufacturing method typically comprises the processes of etching back-etching-dipping-oxidation-deposition. Specifically, an etching back process is firstly performed on a first polysilicon 112 in a trench 104 with a characteristic oxide 110 A on a wall thereof such that the first polysilicon 112 has a height higher than a depth of the trench 104 ( FIG. 2A ). Then, a first etching process is performed on the first polysilicon 112 such that the first polysilicon 112 has a height lower than the depth of the trench 104 ( FIG. 2B ).
  • a dipping step is performed, in which the split gate is dipped into an acid solution such that a portion of the characteristic oxide 110 A at an upper part of the trench 104 is removed.
  • the first polysilicon 112 has a height higher than a height of an upper surface of the characteristic oxide 110 A in the trench 104 ( FIG. 2C ).
  • a layer of characteristic oxide 110 B is formed on a top of the first polysilicon 112 by means of illumination or the like ( FIG. 2D ).
  • the newly formed characteristic oxide 110 B is combined with the original characteristic oxide 110 A and together form the characteristic oxide 110 .
  • the first polysilicon 112 is isolated from the empty space at the upper part of the trench 104 .
  • a second polysilicon 114 is deposited into the empty space at the upper part of the trench 104 , and a split gate structure is formed ( FIG. 2E ). Because the first polysilicon 112 has a height higher than a height of an upper surface of the original characteristic oxide 110 A, the characteristic oxide 110 B formed by the oxidation of the first polysilicon 112 is higher than the original characteristic oxide 110 A. As such, the characteristic oxide 110 between the first polysilicon 112 and the second polysilicon 114 typically has a convex configuration, i.e., an upper surface of the characteristic oxide 110 has a larger height difference H between a higher center portion and a lower periphery portion.
  • the trench 104 is formed in a substrate 102 , and an oxide 106 and SiN 108 may be optionally formed on the substrate 102 having the trench 104 .
  • FIG. 3 and FIGS. 4A-4F illustrate a manufacturing method of a split gate structure according to the present invention.
  • a second etching step is additionally performed before the oxidation step such that the split gate structure as fabricated has a substantially flat characteristic oxide layer.
  • the manufacturing method of a split gate structure according to the present invention comprises:
  • step 1 performing an etching back process on a first polysilicon 212 in a trench 204 with a characteristic oxide 210 A on a wall thereof such that the first polysilicon 212 has a height higher than a depth of the trench 204 ( FIG. 4A );
  • step 2 performing a first etching process on the first polysilicon 212 such that the first polysilicon 212 has a height lower than the depth of the trench 204 ( FIG. 4B );
  • step 3 performing a dipping process on the split gate, in which the split gate is dipped into an acid solution such that a portion of the characteristic oxide 210 A at an upper part of the trench 204 is removed, and at this time, the first polysilicon 212 has a height higher than a height of an upper surface of the characteristic oxide 210 A in the trench 204 ( FIG. 4C );
  • step 4 performing a second etching process on the first polysilicon 212 such that the first polysilicon 212 has a height lower than a height of the characteristic oxide 210 A disposed in the trench 204 ( FIG. 4D ), wherein, preferably, a height difference between the first polysilicon 212 and the characteristic oxide 210 A is 0.05 to 0.15 mm;
  • step 5 forming a characteristic oxide 210 B on a top of the first polysilicon 212 by means of illumination or the like, wherein the newly formed characteristic oxide 210 B is combined with the original characteristic oxide 210 A and together form the characteristic oxide 210 , and as such, the first polysilicon 212 is isolated from the empty space at the upper part of the trench 204 ( FIG.
  • the characteristic oxide 210 B formed by the oxidation of the first polysilicon 212 has an upper surface substantially flush with an upper surface of the original characteristic oxide 110 A, therefore finally a flat upper surface is formed, and, preferably, an upper surface of the characteristic oxide 210 has a height difference h less than 1500 ⁇ between a higher center portion and a lower periphery portion; and
  • step 6 finally, a second polysilicon 214 is deposited into the empty space at the upper part of the trench 204 , and a split gate structure is formed ( FIG. 4F ).
  • the new split gate structure fabricated by the method described above has a characteristic oxide 210 with a flat surface and a uniform thickness distribution, it makes the effective distance, i.e., the smallest distance, between the first polysilicon 212 and the second polysilicon 214 significantly larger than that in the existing technology, preferably, the effective distance is larger than 0.2 mm, and thereby the anti-breakdown performance and the anti-leakage performance at the characteristic oxide 210 are effectively improved.
  • the trench 204 is formed in a substrate 202 , and an oxide 206 and SiN 208 may be optionally formed on the substrate 202 having the trench 204 .
  • FIG. 5 shows the composition result of leakage performance between a split gate according to the present invention and a split gate according to the existing technology, wherein VG on the x-axis represents the energizing voltage, and IG on the y-axis represents the energizing current.
  • VG on the x-axis represents the energizing voltage
  • IG on the y-axis represents the energizing current.
  • various sites (Site1, Site2, Site3, Site4) on a wafer having split gates through one etching process (Poly1 recess std et) and on a wafer having split gates through two etching processes (Poly1 recess double et) are energized, wherein the specific energized sites are illustrated in FIG. 6 .
  • composition result shows that: (1) in the entire energizing process, all the current values of the split gates through one etching process are significantly larger than the current values of the split gates through two etching processes at the same voltage, and it means that the split gates through two etching processes have better anti-leakage performance than that of the split gates through one etching process; and (2) as the increase of voltage, the anti-leakage advantage of the split gates through two etching processes increases.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Manufacturing & Machinery (AREA)
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  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A split gate structure is disclosed. The split gate structure includes a first polysilicon, a characteristic oxide, and a second polysilicon sequentially disposed in a trench in a vertical direction upward from a bottom of the trench. An upper surface of the characteristic oxide has a height difference less than 1500 Å between a higher center portion and a lower periphery portion. The split gate structure effectively improves the breakdown performance and the IGSS performance. A power MOS device having the split gate structure and a manufacturing method of the split gate structure are also provided.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims the priority of CN patent application No. 202010193258.3, filed on Mar. 18, 2020, which is incorporated herewith by reference.
    • BACKGROUND OF THE INVENTION 1. Field of the Invention
  • The present invention relates to the technical field of semiconductor, particularly to a split gate structure which can effectively improve the breakdown performance and the IGSS performance, a power MOS device, and a manufacturing method.
    • 2. The Prior Arts
  • Generally, a split gate power MOS (split gate power FET) is used as a switching device in an integrated circuit. When the device is turned off, it is preferable to have a small leakage, otherwise, the electric device will be power consuming. As such, the IGSS performance and the breakdown performance are important parameters for evaluating the performance of a split gate power MOS. Therefore, the improvement of the breakdown performance and the IGSS performance of a split gate power MOS becomes a problem to be solved in the technical field of semiconductor.
    • SUMMARY OF THE INVENTION
  • In order to solve the existing technical problem, a split gate structure which can effectively improve the breakdown performance and the IGSS performance, a power MOS device having the same, and a manufacturing method of the same are provided in the present invention.
  • According to the present invention, a split gate structure is provided. The split gate structure comprises a first polysilicon, a characteristic oxide, and a second polysilicon sequentially disposed in a trench in a vertical direction upward from a bottom of the trench. An upper surface of the characteristic oxide has a height difference less than 1500 Å between a higher center portion and a lower periphery portion.
  • According to one embodiment of the present invention, the characteristic oxide is further disposed between the first polysilicon and a wall and the bottom of the trench.
  • According to one embodiment of the present invention, an effective distance between the first polysilicon and the second polysilicon, which is the smallest distance between the first polysilicon and the second polysilicon, is larger than 0.2 mm.
  • According to the present invention, a power MOS device is provided. The power MOS device comprises any split gate structure as described above.
  • According to the present invention, a manufacturing method of a split gate structure is provided. The manufacturing method comprises:
      • step 1: performing an etching back process on a first polysilicon in a trench with a characteristic oxide on a wall thereof;
  • step 2: performing a first etching process on the first polysilicon;
  • step 3: dipping in an acid solution such that a portion of the characteristic oxide is removed;
  • step 4: performing a second etching process on the first polysilicon such that the first polysilicon has a height lower than a height of the characteristic oxide disposed in the trench;
  • step 5: performing a thermal oxidation process such that a characteristic oxide with an upper surface having a height difference less than 1500 Å between a higher center portion and a lower periphery portion is formed on a top of the first polysilicon; and
  • step 6: depositing a second polysilicon in the trench.
  • According to one embodiment of the present invention, in said step 4, a height difference between the first polysilicon and the characteristic oxide is 0.05 to 0.15 mm.
  • According to one embodiment of the present invention, an effective distance between the first polysilicon and the second polysilicon, which is the smallest distance between the first polysilicon and the second polysilicon, is larger than 0.2 mm.
  • Since the technical solutions as described above are adopted, the present invention has the following advantages over the existing technology. Compared to a conventional split gate structure, in the new split gate structure fabricated by the manufacturing method of a split gate structure according to the present invention, the flatness of the contact surface between the characteristic oxide and the polysilicon is improved, and thereby the effective distance between the first polysilicon and the second polysilicon is increased. As such, the breakdown performance and the IGSS performance of the split gate power MOS are effectively improved.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a flow diagram of the manufacturing processes of a split gate structure according to the existing technology.
  • FIGS. 2A-2E illustrate the manufacturing processes of a split gate structure of FIG. 1.
  • FIG. 3 is a flow diagram of the manufacturing processes of a split gate structure according to embodiments of the present invention.
  • FIGS. 4A-4F illustrate the manufacturing processes of a split gate structure of FIG. 3.
  • FIG. 5 shows the composition of leakage performance between a split gate according to the present invention and a split gate according to the existing technology.
  • FIG. 6 illustrates the test sites for the leakage test of FIG. 5.
    •  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The present invention will be described in detail through the following embodiments with appending drawings such that the objectives, technical solutions, and advantages of the present invention will be more clear. It should be understood that the specific embodiments are provided for an illustrative purpose only, and should not be interpreted in a limiting manner.
  • As illustrated in FIG. 1 and FIGS. 2A-2E, a conventional manufacturing method typically comprises the processes of etching back-etching-dipping-oxidation-deposition. Specifically, an etching back process is firstly performed on a first polysilicon 112 in a trench 104 with a characteristic oxide 110A on a wall thereof such that the first polysilicon 112 has a height higher than a depth of the trench 104 (FIG. 2A). Then, a first etching process is performed on the first polysilicon 112 such that the first polysilicon 112 has a height lower than the depth of the trench 104 (FIG. 2B). A dipping step is performed, in which the split gate is dipped into an acid solution such that a portion of the characteristic oxide 110A at an upper part of the trench 104 is removed. At this time, the first polysilicon 112 has a height higher than a height of an upper surface of the characteristic oxide 110A in the trench 104 (FIG. 2C). Thereafter, a layer of characteristic oxide 110B is formed on a top of the first polysilicon 112 by means of illumination or the like (FIG. 2D). The newly formed characteristic oxide 110B is combined with the original characteristic oxide 110A and together form the characteristic oxide 110. As such, the first polysilicon 112 is isolated from the empty space at the upper part of the trench 104. Finally, a second polysilicon 114 is deposited into the empty space at the upper part of the trench 104, and a split gate structure is formed (FIG. 2E). Because the first polysilicon 112 has a height higher than a height of an upper surface of the original characteristic oxide 110A, the characteristic oxide 110B formed by the oxidation of the first polysilicon 112 is higher than the original characteristic oxide 110A. As such, the characteristic oxide 110 between the first polysilicon 112 and the second polysilicon 114 typically has a convex configuration, i.e., an upper surface of the characteristic oxide 110 has a larger height difference H between a higher center portion and a lower periphery portion. Such a convex configuration leads to a nonuniform thickness distribution of the characteristic oxide 110. Therefore, an effective distance, i.e., the smallest distance, between the first polysilicon 112 and the second polysilicon 114 is smaller. The problems of breakdown, leakage, and the like are prone to occur in weak areas of the characteristic oxide 110. In one embodiment, as shown in FIG. 2A, the trench 104 is formed in a substrate 102, and an oxide 106 and SiN 108 may be optionally formed on the substrate 102 having the trench 104.
  • FIG. 3 and FIGS. 4A-4F illustrate a manufacturing method of a split gate structure according to the present invention. Compared to the conventional manufacturing method, a second etching step is additionally performed before the oxidation step such that the split gate structure as fabricated has a substantially flat characteristic oxide layer. Specifically, the manufacturing method of a split gate structure according to the present invention comprises:
  • step 1: performing an etching back process on a first polysilicon 212 in a trench 204 with a characteristic oxide 210A on a wall thereof such that the first polysilicon 212 has a height higher than a depth of the trench 204 (FIG. 4A);
  • step 2: performing a first etching process on the first polysilicon 212 such that the first polysilicon 212 has a height lower than the depth of the trench 204 (FIG. 4B);
  • step 3: performing a dipping process on the split gate, in which the split gate is dipped into an acid solution such that a portion of the characteristic oxide 210A at an upper part of the trench 204 is removed, and at this time, the first polysilicon 212 has a height higher than a height of an upper surface of the characteristic oxide 210A in the trench 204 (FIG. 4C);
  • step 4: performing a second etching process on the first polysilicon 212 such that the first polysilicon 212 has a height lower than a height of the characteristic oxide 210A disposed in the trench 204 (FIG. 4D), wherein, preferably, a height difference between the first polysilicon 212 and the characteristic oxide 210A is 0.05 to 0.15 mm;
  • step 5: forming a characteristic oxide 210B on a top of the first polysilicon 212 by means of illumination or the like, wherein the newly formed characteristic oxide 210B is combined with the original characteristic oxide 210A and together form the characteristic oxide 210, and as such, the first polysilicon 212 is isolated from the empty space at the upper part of the trench 204 (FIG. 4E), and wherein because the first polysilicon 212 has a height lower than a height of an upper surface of the original characteristic oxide 210A, the characteristic oxide 210B formed by the oxidation of the first polysilicon 212 has an upper surface substantially flush with an upper surface of the original characteristic oxide 110A, therefore finally a flat upper surface is formed, and, preferably, an upper surface of the characteristic oxide 210 has a height difference h less than 1500 Å between a higher center portion and a lower periphery portion; and
  • step 6: finally, a second polysilicon 214 is deposited into the empty space at the upper part of the trench 204, and a split gate structure is formed (FIG. 4F).
  • The new split gate structure fabricated by the method described above has a characteristic oxide 210 with a flat surface and a uniform thickness distribution, it makes the effective distance, i.e., the smallest distance, between the first polysilicon 212 and the second polysilicon 214 significantly larger than that in the existing technology, preferably, the effective distance is larger than 0.2 mm, and thereby the anti-breakdown performance and the anti-leakage performance at the characteristic oxide 210 are effectively improved. In one embodiment, as shown in FIG. 4A, the trench 204 is formed in a substrate 202, and an oxide 206 and SiN 208 may be optionally formed on the substrate 202 having the trench 204.
  • FIG. 5 shows the composition result of leakage performance between a split gate according to the present invention and a split gate according to the existing technology, wherein VG on the x-axis represents the energizing voltage, and IG on the y-axis represents the energizing current. Specifically, various sites (Site1, Site2, Site3, Site4) on a wafer having split gates through one etching process (Poly1 recess std et) and on a wafer having split gates through two etching processes (Poly1 recess double et) are energized, wherein the specific energized sites are illustrated in FIG. 6. The composition result shows that: (1) in the entire energizing process, all the current values of the split gates through one etching process are significantly larger than the current values of the split gates through two etching processes at the same voltage, and it means that the split gates through two etching processes have better anti-leakage performance than that of the split gates through one etching process; and (2) as the increase of voltage, the anti-leakage advantage of the split gates through two etching processes increases. These further proves that, in a new split gate structure fabricated by the manufacturing method according to the present invention, the breakdown performance and the IGSS performance of the split gate power MOS are effectively improved compared to a conventional split gate structure.
  • While the present invention has been described in terms of the specific and detailed embodiments, the present invention is not limited thereto. It should be understood that various modifications and variations can be made without departing the scope and spirit of the present invention, and these modifications and variations therefore should be encompassed in the present invention. As such, the scopes of the present invention should be defined and indicated by the following claims and their equivalents.

Claims (9)

1. A split gate structure, comprising:
a first polysilicon, a characteristic oxide, and a second polysilicon sequentially disposed in a trench in a vertical direction upward from a bottom of the trench;
wherein an upper surface of the characteristic oxide has a height difference less than 1500 Å between a higher center portion and a lower periphery portion; and
wherein an effective distance between the first polysilicon and the second polysilicon, which is a smallest distance between the first polysilicon and the second polysilicon, is larger than 0.2 mm.
2. The split gate structure according to claim 1, wherein the characteristic oxide is further disposed between the first polysilicon and a wall and the bottom of the trench.
3. (canceled)
4. A power MOS device, comprising:
the split gate structure according to claim 1.
5. A power MOS device, comprising:
the split gate structure according to claim 2.
6. A power MOS device, comprising:
the split gate structure according to claim 1.
7. A manufacturing method of a split gate structure, comprising:
step 1: performing an etching back process on a first polysilicon in a trench with a characteristic oxide on a wall thereof;
step 2: performing a first etching process on the first polysilicon;
step 3: dipping in an acid solution such that a portion of the characteristic oxide is removed;
step 4: performing a second etching process on the first polysilicon such that the first polysilicon has a height lower than a height of the characteristic oxide disposed in the trench;
step 5: performing a thermal oxidation process such that another characteristic oxide with an upper surface having a height difference less than 1500 Å between a higher center portion and a lower periphery portion is formed on a top of the first polysilicon; and
step 6: depositing a second polysilicon in the trench;
wherein an effective distance between the first polysilicon and a second polysilicon, which is a smallest distance between the first polysilicon and the second polysilicon, is larger than 0.2 mm.
8. The manufacturing method according to claim 7, wherein, in said step 4, a height difference between the first polysilicon and the characteristic oxide is 0.05 to 0.15 mm.
9. (canceled)
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US20220020858A1 (en) * 2020-07-16 2022-01-20 Shanghai Huahong Grace Semiconductor Manufacturing Corporation Trench gate device and method for making the same

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US8889532B2 (en) * 2011-06-27 2014-11-18 Semiconductor Components Industries, Llc Method of making an insulated gate semiconductor device and structure
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