US20210242135A1 - Display devices and methods for manufacturing the same - Google Patents
Display devices and methods for manufacturing the same Download PDFInfo
- Publication number
- US20210242135A1 US20210242135A1 US17/237,154 US202117237154A US2021242135A1 US 20210242135 A1 US20210242135 A1 US 20210242135A1 US 202117237154 A US202117237154 A US 202117237154A US 2021242135 A1 US2021242135 A1 US 2021242135A1
- Authority
- US
- United States
- Prior art keywords
- alignment mark
- light
- substrate
- distance
- limited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims description 78
- 239000010410 layer Substances 0.000 description 94
- 239000000463 material Substances 0.000 description 60
- 230000008569 process Effects 0.000 description 19
- 238000006243 chemical reaction Methods 0.000 description 12
- 239000011241 protective layer Substances 0.000 description 9
- 230000000903 blocking effect Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- 239000002096 quantum dot Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 239000003086 colorant Substances 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- 230000001154 acute effect Effects 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- 229920003023 plastic Polymers 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 239000011669 selenium Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/50—Wavelength conversion elements
- H01L33/501—Wavelength conversion elements characterised by the materials, e.g. binder
- H01L33/502—Wavelength conversion materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Definitions
- the embodiments of the disclosure relate to a display device, and in particular to a display device with an alignment mark on a light-emitting module.
- the display devices are becoming more widely used. Since mass production has recently become the tendency in the light-emitting diode industry, any increase in the yield of manufacturing light-emitting diodes, such as increasing the alignment accuracy. Therefore, the manufacturing method for the display devices may need to be continuously improved.
- a method for manufacturing a display device includes providing an array module having at least one first alignment mark.
- the method also includes providing a light-emitting module having at least one second alignment mark.
- the method further includes aligning the light-emitting module and the array module by the first alignment mark and the second alignment mark.
- the method includes bonding the light-emitting module onto the array module.
- a display device includes an array module having a first alignment mark.
- the array module includes a first substrate and a circuit layer disposed on the first substrate.
- the array module also includes a plurality of pads disposed on the circuit layer.
- the display device also includes a light-emitting module having a second alignment mark.
- the light-emitting module includes a second substrate and a plurality of light-emitting elements. The plurality of light-emitting elements disposed on the second substrate and electrically connected to the plurality of pads.
- the second alignment mark is aligned with the first alignment mark.
- FIG. 1 is a flow chart for manufacturing a display device in accordance with some embodiments of the present disclosure
- FIGS. 2A-2G are top views of various stages of a process for manufacturing a display device in accordance with some embodiments of the present disclosure
- FIGS. 3A-3D are cross-sectional views of various stages of a process for manufacturing a display device in accordance with some embodiments of the present disclosure
- FIGS. 4A and 4B are top views of a first alignment and a second alignment of a display device in accordance with some embodiments of the present disclosure
- FIGS. 5-8 is a cross-sectional view of a display device in accordance with some embodiments of the present disclosure.
- FIG. 9A is a top view of a display device in accordance with some embodiments of the present disclosure.
- FIGS. 9B and 9C are top views of light-emitting modules in accordance with some embodiments of the present disclosure.
- first material layer disposed on/over a second material layer may indicate the direct contact of the first material layer and the second material layer, or it may indicate a non-contact state with one or more intermediate layers between the first material layer and the second material layer. In the above situation, the first material layer may not be in direct contact with the second material layer.
- a layer is disposed above another layer may indicate that the layer is in direct contact with the other layer, or that the layer is not in direct contact with the other layer, there being one or more intermediate layers disposed between the layer and the other layer.
- the terms “about” and “substantially” typically mean +/ ⁇ 20% of the stated value, +/ ⁇ 10% of the stated value, +/ ⁇ 5% of the stated value, +/ ⁇ 3% of the stated value, +/ ⁇ 2% of the stated value, +/ ⁇ 1% of the stated value or +/ ⁇ 0.5% of the stated value.
- the stated value of the present disclosure is an approximate value. When there is no specific description, the stated value includes the meaning of “about” or “substantially”.
- first, second, third etc. may be used herein to describe various elements, components, regions, layers, portions and/or sections, these elements, components, regions, layers, portions and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, portion or section from another region, layer or section. Thus, a first element, component, region, layer, portion or section discussed below could be termed a second element, component, region, layer, portion or section without departing from the teachings of the present disclosure.
- relative terms such as “lower,” “upper,” “horizontal,” “vertical,”, “on,”, “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivative thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation.
- Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.
- FIG. 1 is a flow chart 100 for manufacturing a display device.
- the flow chart 100 includes multiple steps 102 , 104 , 106 , 108 , 110 , 112 and 114 .
- Each of steps may correspond to FIGS. 2A-2G or FIGS. 3A-3D .
- FIGS. 2A-2G illustrate the steps in the top view.
- FIGS. 3A-3D illustrate the steps in the cross-sectional view.
- other steps may be appropriately added before or after above the steps.
- the above partial steps may be appropriately deleted or replaced.
- the above sequence of steps can be changed or modulated as needed.
- the method for manufacturing the display device includes the step 102 of providing an array module having at least one first alignment mark and a light-emitting module having at least one second alignment mark.
- an array module 200 and a light-emitting module 300 are provided.
- the array module 200 includes a first substrate 210 .
- the first substrate 210 may include a glass substrate, a ceramic substrate, a plastic substrate or another suitable substrate, but not limited.
- the first substrate 210 may include polyimide (PI), polycarbonate (PC), or polyethylene terephthalate (PET), but not limited thereto.
- the array module 200 includes a plurality of pads 220 .
- the pads 220 are disposed on the first substrate 210 .
- the material of the pad 220 may include copper (Cu), aluminum (Al), molybdenum (Mo), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), iridium (Ir), other suitable material, or the above alloy, but is not limited.
- FIG. 2A illustrates a pixel P that may correspond to (or electrically connected to) six pads 220 , and a sub-pixel (correspond to one light-emitting elements 320 ) may respectively correspond to two pads 220 , but is not limited thereto.
- the dotted line may correspond to a position where the pixel (not shown in FIG. 2A ) is expected to be bonded. As shown in FIG.
- one pixel P may include three sub-pixels, and a sub-pixel may respectively correspond to or electrically connected to two pads 220 after bonding (subsequent step 114 will be described).
- a pixel P may correspond to (or electrically connected to) four pads 220 , for example, one of the four pads 220 is a shared pad, the shared pad is electrically connected to three sub-pixels of the pixel P, and other pads may respectively correspond to (or electrically connected to) three sub-pixels with different colors.
- at least part of the pixel P may overlap with corresponding pads 220 in Z direction, and Z direction may defined as a normal direction of the first substrate 210 of the array module 200 .
- the array module 200 includes at least one first alignment mark 230 on the first substrate 210 .
- the light-emitting module 300 includes a second substrate 310 .
- the second substrate 310 may be a carrier substrate or growth substrate, but is not limited.
- the second substrate 310 may include a glass substrate, a ceramic substrate, a plastic substrate, a sapphire substrate or another suitable substrate, but is not limited.
- the growth substrate may include silicon or a sapphire substrate, which includes alumina oxide, GaP, GaAs, AlGaAs, SiC, Si, or another suitable material, but is not limited.
- the light-emitting module 300 includes a plurality of light-emitting elements 320 .
- the light-emitting elements 320 may be disposed on the second substrate 310 .
- the light-emitting element 320 may be a red sub-pixel, a green sub-pixel or a blue sub-pixel, an infrared (IR) sub-pixel, or other sub-pixel with other colors.
- the light-emitting element 320 may include light-emitting diode (LED), micro LED (pLED), mini LED, quantum dot (QD), quantum dot LED (QLED or QDLED) or other suitable element, but is not limited.
- the light-emitting element 320 may emit blue light (or UV light), but is not limited.
- the light-emitting element 320 may respectively emit the light with different colors (such as red, green, blue or other suitable colors).
- the light-emitting module 300 may include the light conversion elements, the light conversion elements (such as quantum dot, but is not limited) may be disposed on or adjacent to the light-emitting module 300 .
- the light-emitting module 300 includes at least one second alignment mark 330 on the second substrate 310 .
- at least one pixel P may be disposed between two adjacent second alignment marks 330 , but not limited, the quantity of pixel P can be adjusted as needed.
- the position of the second alignment mark 330 of the light-emitting module 300 may correspond to the position of the first alignment mark 230 of the array module 200 .
- four second alignment marks 330 of the light-emitting module 300 may respectively correspond to one of four first alignment marks 230 on the right part (or on the left part) of the array module 200 , but not limited.
- T 1 there is a distance between two adjacent first alignment marks 230 along the X direction
- T 2 between two adjacent second alignment marks 330 along the X direction
- X direction may be defined as a direction parallel to an extension direction of the long side of the first substrate 210 , but not limited.
- the X direction may be defined as an arrangement direction of adjacent pixels. In some embodiments, the X direction may be defined as an arrangement direction of sub-pixels of the pixel P. Y direction may be perpendicular with Z direction and X direction.
- Distance T 1 may be defined as a distance between a center of one of the first alignment marks 230 and a center of another the first alignment mark 230 adjacent to the one of the first alignment marks 230 along the X direction (or Y direction).
- Distance T 2 may be defined as a distance between a center of one of the second alignment marks 330 and a center of another the second alignment marks 330 adjacent to the one of the second alignment marks 330 along the X direction(or Y direction).
- the ratio of the distance T 1 to the distance T 2 is in a range from 0.8 to 1.2, but not limited. In some embodiments, the ratio of the distance T 1 to the distance T 2 is in a range from 0.9 to 1.1.
- Distance T 3 may be defined as a distance between a center of one of the first alignment marks 230 and a center of another first alignment mark 230 along a direction of the diagonal line.
- Distance T 4 may be defined as a distance between a center of one of the second alignment marks 330 and a center of another second alignment marks 330 along a direction of the diagonal line.
- the ratio of distance T 3 to distance T 4 is in a range from 0.8 to 1.2, but not limited. In some embodiments, the ratio of distance T 3 to distance T 4 is in a range from 0.9 to 1.1.
- the accuracy of bonding the array module 200 and the light-emitting module 300 may be increased.
- the distance between two adjacent first alignment marks 230 along the X direction is the same as or different from the distance between two adjacent first alignment marks 230 along the Y direction. In some embodiments, the distance between two adjacent second alignment marks 330 along the X direction (such as distance T 2 ) is the same as or different from the distance between two adjacent second alignment marks 330 along the Y direction.
- the second alignment mark 330 has a width W 1 .
- the light-emitting element 320 has a width W 2 .
- the width W 2 may be a maximum width of one of the light-emitting elements 320 in X direction.
- the width W 1 may be a maximum width of one of the second alignment mark 330 in X direction. In some embodiments, the width W 1 is less than or equal to the width W 2 . In some embodiments, the width W 1 is greater than the width W 2 .
- an area of the light-emitting element 320 may be defined as a lighting area of one sub-pixel operating at a highest grayscale in Z direction, but not limited.
- an area of the light-emitting element 320 may defined as a lighting surface (such top surface of the light-emitting element 320 ) of one sub-pixel, but not limited. In some embodiments, an area of the light-emitting element 320 may be defined by the openings of the light blocking layer 630 (shown in FIG. 5 to FIG. 6 ).
- the method for manufacturing the display device includes the step 104 that aligning the array module 200 and the light-emitting module 300 by the first alignment mark 230 and the second alignment mark 330 . As shown in FIG. 2C , the light-emitting module 300 may approach (or be transferred to) the right part (or left part) of the array module 200 .
- the method for manufacturing the display device includes the step 106 that approaching the at least one second alignment mark 330 with the at least one first alignment mark 230 into a detecting region S.
- the detecting region S may be a region that can be detected by a charge-coupled device (CCD) camera (not shown) or other suitable image equipment (or camera equipment), but not limited.
- CCD charge-coupled device
- the light-emitting module 300 or the array module 200 may be transferred, so that the second alignment mark 330 and the first alignment mark 230 would be inside the detecting region S.
- the method for manufacturing the display device includes the step 108 that detecting the distance between the second alignment mark 330 and the first alignment mark 230 , and comparing the distance with a predetermined value.
- the distance between the second alignment mark 330 and the first alignment mark 230 detected by the step 108 may be defined as a mismatch between the second alignment mark 330 and the first alignment mark 230 .
- FIG. 2E which is an enlarged view of the region R shown in FIG. 2C .
- one pixel pitch P has a width W 3 , and the predetermined value is less than or equal to half of the width W 3 .
- the width W 3 may be a distance between the centers (left sides or right sides) of the two adjacent pixels P, but not limited.
- the pixel pitch P may be a distance between the centers (left sides or right sides) of two adjacent sub-pixels with the same color. That is, the mismatch between the second alignment mark 330 and the first alignment mark 230 is less than half of the pixel pitch P of the display device.
- the method for manufacturing the display device includes the step 110 that determining whether the distance (ex. mismatch) is less than or equal to the predetermined value.
- the step 110 includes determining whether the distance (ex. mismatch) X 1 along the X direction (or the distance (ex. mismatch) Y 1 along the Y direction) is less than or equal to the predetermined value.
- the step 112 includes reducing the distance between the second alignment mark 330 and the first alignment mark 230 .
- the step 112 includes adjusting the position of the array module 200 or the light-emitting module 300 , so that the first alignment mark 230 would be aligned with (or overlapped with) the second alignment mark 330 .
- the step 112 includes approaching the array module 200 or the light-emitting module 300 along the X direction (or the Y direction or other directions), so that the first alignment mark 230 would be aligned with (or overlapped with) the second alignment mark 330 , but not limited.
- the step 108 is performed to detect the distance between the first alignment mark 230 and the second alignment mark 330 along the X direction (or the Y direction or other directions).
- the step 114 includes bonding the light-emitting module 300 onto the array module 200 .
- the second substrate 310 may be disposed on the right part (left part or other part) of the first substrate 210 , but not limited.
- the light-emitting elements 320 may be electrically connected to the corresponding pad 220 . In some embodiments, the light-emitting elements 320 may respectively overlap with part of the corresponding pad 220 in Z direction.
- the predetermined value is less than or equal to half of the width W 3 of the pixel pitch P. In some embodiments, the predetermined value is equal to the width W 2 . When the predetermined value is in the range mentioned above, the production yield of bonding the array module 200 and the light-emitting module 300 may be increased.
- the second substrate 310 may be removed (as shown in FIG. 2G ), and the light-emitting elements 320 are disposed on (or bonded onto) the pad 220 .
- the second substrate 310 may be removed by a laser or other suitable methods.
- the second substrate 310 may not be removed, and the second substrate 310 and the light-emitting elements 320 may disposed on the array module 200 .
- the process shown in FIGS. 2A-2G may be repeated so that another light-emitting module 300 may be disposed on (or bonded on) the another part (such as left part) of the array module 200 .
- the process shown in FIGS. 2A-2G may be used in mass production of the display device, but not limited. For example, nine pixels may be disposed on (or bonded onto) the corresponding pads 220 in same bonding process, but not limited.
- the second substrate 310 may be used as a growth substrate, and the second alignment marks may be disposed on (or formed on) the second substrate 310 .
- the second substrate 310 may be used as a carrier substrate, and the light-emitting elements 320 may be transferred onto the second substrate 310 , and then transferred onto (or disposed on) the array module 200 , but not limited.
- the quantity (number) of first alignment marks 230 may be greater than or equal to the quantity (number) of the second alignment marks 330 , but not limited.
- the light-emitting module 300 may have four second alignment marks 330 , and the four second alignment marks 330 may respectively be disposed at four corners of the second substrate 310 , but not limited.
- the quantity of the second alignment marks 330 in light-emitting module 300 is greater than (or less than) four, and the second alignment marks 330 may be disposed at other suitable position of the second substrate 310 .
- the light-emitting module 300 has two second alignment marks 330 , and two second alignment marks 330 may respectively be disposed at two diagonal corners of the second substrate 310 . In some embodiments, the light-emitting module 300 may have at least one second alignment mark 330 . The quantity of the first alignment marks 230 or the position of the first alignment marks 230 may be correspond to the second alignment marks 330 , which can be adjusted according to the needs.
- the array module 200 includes a circuit layer 240 , and the circuit layer 240 is disposed on (or formed on) the first substrate 210 .
- the circuit layer 240 may include wires 250 , other conductive elements (not shown), other dielectric layers (not shown), but not limited.
- the pads 220 may be disposed on (or electrically connected to) the circuit layer 240 .
- the first alignment mark 230 may be disposed on the circuit layer 240 .
- the first alignment mark 230 may be disposed in (or formed in) the circuit layer 240 (not shown in FIGS. 3A-3G , but shown in FIG. 5 ).
- the material of the wires 250 may be the same as or different from the pads 220 , the wires 250 or other conductive elements of the circuit layer 240 .
- the first alignment mark 230 and the pads 220 , the wires 250 or other conductive elements of the circuit layer 240 may be formed in the same process or different process, but not limited.
- the first alignment mark 230 may be formed before the process of forming the circuit layer 240 .
- the first alignment mark 230 may be formed after the process of forming the pad 220 .
- the material of the first alignment mark 230 may include opaque materials, shading materials, reflective materials or a combination of the above, but is not limited thereto. In some embodiment, the material of the first alignment mark 230 may include metal material, metal alloy, black photoresist or other suitable material, but is not limited thereto.
- the light-emitting module 300 includes a plurality of pads 322 disposed on the light-emitting element 320 .
- the distance D 1 may be a distance between a center of the first alignment mark 230 and a center of the second alignment mark 330 along the X direction (or the Y direction). If the distance D 1 is greater than the predetermined value, the position of the light-emitting module 300 will be fine-tuned.
- the position of the light-emitting module 300 is fine-tuned. If the distance D 1 is less than or equal to the predetermined value, the light-emitting module 300 is bonded onto the array module 200 as shown in FIG. 3C . After the bonding process, the second alignment mark 330 may approximately overlap with the first alignment mark 230 in Z direction, or the second alignment mark 330 may approximately aligned with the first alignment mark 230 .
- the second substrate 310 may be removed, but not limited.
- the light-emitting elements 320 and the pads 322 may be disposed on the array module 200 .
- the pads 322 of the light-emitting module 300 may electrically connected to (or contact with) the corresponding pads 220 of the array module 200 .
- the light-emitting element 320 may be electrically connected to the pad 220 through the pad 322 . If the distance D 1 is less than or equal to the predetermined value, the production yield in mass producing the display device can increase.
- FIGS. 4A and 4B are top views of a first alignment and a second alignment in accordance with some embodiments.
- the profile of the first alignment marks and second alignment marks shown in FIGS. 4A and 4B are merely examples, and the present disclosure is not limited thereto.
- the first alignment mark 230 A and the second alignment mark 330 A are in different shapes.
- the second alignment mark 330 A may be adjacent to the first alignment mark 230 A.
- the second alignment mark 330 A may enclose the first alignment mark 230 A, as shown in FIG. 4A .
- the second alignment mark may have an opening O, at least part the opening O may overlap with the first alignment mark 230 A in Z direction, but not limited.
- the second alignment mark 330 A may overlap with at least part of the first alignment mark 230 A in Z direction.
- the shape of the first alignment mark 230 A and the shape of the second alignment mark 330 A may include rectangle, circle, triangle, polygon, arc shape, obtuse angle shape, acute angle shape, round shape or other suitable shapes, but is not limited.
- the shape of the first alignment mark 230 A may be the same as or different from the shape of the second alignment mark 330 A.
- a distance dm between the second alignment mark 330 A and the first alignment mark 230 A in X direction (or Y direction) is greater than or equal to 0, and less than or equal to the width W 2 (shown in FIG. 2B ).
- Distance dm may be defined as the minimum distance between the second alignment mark 330 A and the first alignment mark 230 A in X direction (or Y direction).
- the position of the first alignment mark 230 A and the position of the second alignment mark 330 A can be exchanged.
- the second alignment mark 330 B may have discontinuous parts, as shown in FIG. 4B .
- the profile of the shape of the second alignment mark 330 B is different from or the same as the shape of the first alignment mark 230 B.
- the first alignment mark 230 B may have a cross-shape, rectangular shape, polygonal shape, curved shape, circular shape, arc shape, obtuse angle shape, acute angle shape, round shape or other suitable shapes, but not limited.
- the first alignment mark 230 B may include protruding portions.
- the second alignment mark 330 B may be adjacent to the first alignment mark 230 B, and the second alignment mark 330 B may have any shape correspond to (or in accordance with) the shape of the first alignment mark 230 B, but not limited.
- the second alignment mark 330 B may have an L-shape (or other shape) and extend into the space between two adjacent protruding portions of the first alignment mark 230 B, but not limited.
- the above “the alignment mark 330 B has any shape correspond to (or in accordance with) the shape of the first alignment mark 230 B” includes that the alignment mark 330 B has any shape correspond to at least one side of the first alignment mark 230 B.
- one of the second alignment marks 330 B may have discontinuous parts, these parts may correspond to one of the first alignment marks 230 B, these parts can form a second alignment marks 330 B, and these parts may have similar or different shapes.
- the position of the first alignment mark 230 B and the position of the second alignment mark 330 B can be exchanged.
- the shape of the first alignment mark 230 B and the shape of the second alignment mark 330 B may be complement each other.
- the display device 400 A may include an array module 500 and a light-emitting module 600 .
- the array module 500 may include a substrate 502 .
- the material of the substrate 502 may be the same as or similar to the material of the first substrate 210 .
- some insulating layers 504 , 506 , 508 ′, 508 may be sequentially disposed on the substrate 502 .
- the insulating layers 504 , 506 , 508 may include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride or another suitable material.
- the transistor 510 may be a thin film transistor (TFT).
- the transistor 510 may include a gate electrode 512 , a source/drain electrode 518 , and a semiconductor layer 516 .
- the gate electrode 512 may be disposed on the insulating layer 504 and the semiconductor layer 516 .
- the source/drain electrode 518 may be disposed on the semiconductor layer 516 and the doping layers 514 , and the semiconductor layer 516 may be disposed between the doping layers 514 .
- the material of the gate electrode 512 and the source/drain electrode 518 may include, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), gold (Au), chromium (Cr), nickel (Ni), titanium (Ti), other suitable material or alloy.
- the material of the semiconductor layer 516 may include, but is not limited to, amorphous silicon, polysilicon such as low-temp polysilicon (LTPS), metal oxide or other suitable materials.
- the metal oxide may include indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium zinc tin oxide (IGZTO) or other suitable material.
- the array module 500 may include a plurality of wires 509 and pads 520 .
- the pads 520 may be disposed on the insulating layer 508 and the wires 509 .
- the transistor 510 may be electrically connected to the pad 520 through the wire 509 , but not limited.
- the material of the wire 509 and the pad 520 may be the same as or different from the material of the source/drain electrode 518 .
- the first alignment mark 522 may be disposed on the insulating layer 504 . In some embodiments, the first alignment mark 522 and the gate electrode 512 may be formed in the same process. In some embodiments, the material of the first alignment mark 522 and the material of the gate electrode 512 may be same. In some embodiments, the first alignment mark 522 may include metal material that is disposed in the insulating layer 506 . In other embodiments, the first alignment mark 522 and the pad 520 may be formed in the same process. In some embodiments, the material of the first alignment mark 522 and the material of the gate electrode 512 may be same. In other embodiments, the material of the first alignment mark 522 and the material of source/drain electrode 518 may be same.
- the light-emitting module 600 includes a substrate 602 .
- the substrate 602 may include a glass substrate, a ceramic substrate, a plastic substrate or another suitable substrate, but not limited.
- the material of the substrate 602 may include sapphire, Si, SiC, other suitable materials or combinations thereof, but are not limited thereto.
- the light-emitting module 600 may include insulating layers 604 , 606 , 608 , and the insulating layers 604 , 606 , 608 are disposed on the substrate 602 .
- the insulating layers 604 , 606 , 608 may include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride or another suitable material.
- the light-emitting module 600 may include a plurality of the transistors 610 .
- the transistor 610 may include a gate electrode 612 , a source/drain electrode 614 , and a semiconductor layer 616 .
- the gate electrode 612 may be disposed on the insulating layer 604 .
- the materials of the gate electrode 612 , the source/drain electrode 614 and the semiconductor layer 616 may be the same as, similar to or different from those of the gate electrode 512 , the source/drain electrode 518 and the semiconductor layer 516 , respectively.
- the light-emitting module 600 includes a plurality of wires 618 and pads 620 . In some embodiments, the transistor 610 may be electrically connected to the pad 620 through the wire 618 .
- the transistor 510 may be electrically connected to the transistor 610 .
- the pad 520 may be electrically connected to (or contact with) the pad 620 .
- the transistor 610 may use as a driving transistor.
- the transistor 510 may use as a switch transistor.
- more transistors (or elements) may be disposed on the substrate 602 or the substrate 502 , such as reset transistor or capacitor, but not limited.
- the transistor 610 and the transistor 510 may disposed on the same substrate (such as substrate 602 or the substrate 502 ).
- the structure of the transistor 610 (or the transistor 510 ) described above is an example, and the disclosure is not limited thereto.
- the transistor 610 (or the transistor 510 ) can be top gate thin film transistor, bottom gate thin film transistor, double gate thin film transistor, but not limited.
- the transistor 610 (or the transistor 510 ) can include amorphous germanium (a-Si:H) transistor, low temperature polycrystalline germanium transistor (LTPS), indium gallium zinc oxide transistor (IGZO) or other suitable transistor, but not limited.
- the light-emitting element 626 may be electrically connected to the transistor 610 and the transistor 510 through the conductive elements which are disposed in the array module 500 or the light-emitting module 600 .
- the light-emitting module 600 includes insulating layer 622 and 624 .
- the light-emitting module 600 includes a plurality of light-emitting elements 626 and pads 628 .
- the light-emitting element 626 and the pad 628 may be surrounded by the insulating layer 622 , but not limited.
- the insulating layers 622 may be disposed to protect the light-emitting element 626 or the pad 628 from damage or pollution (such as water or air), but not limited.
- the material of the insulating layer 622 (or the insulating layer 624 ) may include, but is not limited to, resin or another suitable material.
- the light-emitting element 626 and the pad 628 may be the same as or similar to the light-emitting element 320 and the pad 322 shown in FIG. 3A , respectively.
- the order of the above layers or elements can be changed or replaced as needed.
- the above layers can be replaced or removed as needed.
- the light-emitting module 600 includes a light blocking layer 630 .
- the light blocking layer 630 may be disposed on the light-emitting element 626 .
- the light blocking layer 630 has a plurality of openings B-O, the openings B-O may overlap with the light-emitting element 626 in Z direction. In some embodiments, the light blocking layer 630 does not overlap with the light-emitting element 626 in Z direction.
- the light-emitting module 600 may include a plurality of light conversion layer 632 .
- the light conversion layer 632 may be disposed on (or cover) the light-emitting element 626 . In some embodiments, the light conversion layer 632 may be adjacent to the light-emitting element 626 .
- the material of the light conversion layer 632 may include, but is not limited to, quantum dot, fluorescent material, phosphorescent material or another conversion material.
- the light conversion layer 632 may be an organic or an inorganic layer blended with a quantum dot.
- the quantum dot may include, but is not limited to, zinc, cadmium, selenium, sulfur, InP, GaSb, GaAs, CdSe, CdS, ZnS or a combination thereof, but not limited.
- the light-emitting module 600 further includes a protective layer 634 and a color filter layer 636 .
- the light-emitting element 626 may be disposed between the protective layer 634 and the substrate 602 .
- the color filter layer 636 may be disposed between the light conversion layer 632 and the protective layer 634 , but not limited.
- the protective layer 634 may be single layer structure, multilayer structure, composite structure, but not limited.
- the material of the protective layer 634 may include organic material, inorganic material, or a combination thereof. In some embodiments, the material of the protective layer 634 may be a transparent substrate.
- the material of the protective layer 634 may include phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, or silicon oxynitride, but not limited.
- the color filter layer 636 may be disposed on at least one of the light conversion layer 632 . In some embodiments, the color filter layer 636 may be respectively disposed on the corresponding light conversion layer 632 . In some embodiments, the color filter layer 636 may overlap with at least part of the light blocking layer 630 in Z direction in order to reduce light leakage. In some embodiments (not shown), the color filter layer 636 may disposed between the light conversion layer 632 and the light-emitting element 626 .
- the second alignment mark may be disposed in (or formed in) the second substrate.
- the second substrate 602 may be a transparent substrate or non-transparent substrate
- a through hole TH may penetrate the second substrate 602
- the through hole TH may be regarded as the second alignment mark 638 .
- the through hole TH may penetrate at least part of the layers (or the elements) formed on the second substrate 602 .
- the through hole TH may penetrate the second substrate 602 , the insulating layers 604 , 606 , 608 , 622 , 624 , the light blocking layer 630 and the protective layer 634 , but not limited.
- a shape of the through hole TH may include rectangle, circle, triangle, polygon, arc shape, obtuse angle shape, acute angle shape, round shape or other suitable shapes, but not limited.
- the through hole in the direction of the cross section, has an inverted trapezoid profile, rectangular profile or other shape profile, but not limited.
- the scope of the disclosure is not limiting.
- the second alignment mark 638 approximately overlap with (or aligned with) the first alignment mark 522 in Z direction.
- the second alignment mark 638 (such as through hole TH) have a bottom surface BS and top surface TS opposite to the bottom surface BS, and the bottom surface BS is near to the array module 500 .
- the bottom surface BS of the second alignment mark 638 (such as through hole TH) may have a length L 1
- the top surface TS of the second alignment mark 638 may have length L 3 .
- the length L 3 may be greater than or equal to the length L 1 .
- the length L 3 may be less than or equal to the length L 1 .
- the length L 3 also may be defined as the maximum length of the top surface TS of the second alignment mark 638 in top view
- length L 1 also may be defined as the maximum length of the bottom surface BS of the second alignment mark 638 in top view.
- the cross section, the first alignment mark 522 has a length L 2 .
- the length L 1 is greater than or equal to the length L 2 .
- the length L 1 is greater than the length L 2 so that the CCD camera could receive both images of the first alignment mark 522 and the second alignment mark 638 .
- the angle ⁇ may be in a range from about 30° to about 110°, but not limited.
- the angle ⁇ is in a range from about 50° to about 90°.
- the angle ⁇ is in a range from about 70° to about 90°.
- the side surface of the second alignment mark 638 (such as through hole TH) is a curved edge or an irregular edge. For example, in the Z direction, viewers can see the elements (such as first alignment mark 522 or other layers (or elements) of the array module 500 ) through the second alignment mark 638 (through hole TH).
- At least one spacer 524 may be disposed between the array module 500 and the light-emitting module 600 .
- the spacer 524 may include resin or other suitable materials, but not limited.
- at least one space 526 may be formed between the array module 500 and the light-emitting module 600 by the spacer 524 .
- the space 526 may include air, transparent material or other suitable materials, but not limited.
- a second alignment mark 640 of the display device 400 A may include a filling materials FM
- the filling materials FM may be disposed in (or filled in) the through hole TH
- the through hole TH with the filling materials FM may be regarded as the second alignment mark 330 .
- the filling materials may include transparent material.
- the filling materials FM may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride or another suitable material.
- FIG. 7 illustrates a cross-sectional view of a display device 400 C in accordance with some embodiments.
- a notch 642 may penetrate part of layers (or elements) in the light-emitting module 600 .
- the notch 642 may penetrate the insulating layers 622 , 624 , the light blocking layer 630 and the protective layer 634 .
- the display device 400 C may include a second alignment mark 644 .
- the material of the second alignment mark 644 may be the same as or similar to the material of the gate electrode 612 of the transistor 610 , but not limited.
- the second alignment mark 644 and a portion of the transistor 610 may be formed in the same process or different process.
- the material of the second alignment mark 644 may be the same as or different from the material of a portion of the transistor 610 (such as source/drain electrode 614 ).
- the notch 642 has a bottom surface BS′, and the bottom surface BS′ is near to the array module 500 .
- the bottom surface BS′ of the notch 642 may have a length L 1 ′.
- the length L 1 ′ also may be defined as the maximum length of the bottom surface BS′ of the notch 642 in top view.
- the second alignment mark 644 has length L 4 , the length L 4 may be defined as the maximum length of the second alignment mark 644 in X direction (or Y direction). In some embodiments, the length L 4 is less than or equal to the length L 1 ′.
- At least part of the second alignment mark 644 may overlap with the first alignment mark 522 in Z direction. In some embodiments, at least part of the second alignment mark 644 may be aligned with the first alignment mark 522 . In some embodiments, the shape of the notch 642 may be the same as or different from of shape of the second alignment mark 644 in Z direction.
- FIG. 8 illustrates a cross-sectional view of a display device 400 D in accordance with some embodiments.
- the array module 500 of the display device 400 D may include a spacer 528 and a protruding portion 530 that is disposed on the spacer 528 .
- the protruding portion 530 may be regarded as the first alignment mark of the array module 500 .
- the profile of a second alignment mark 646 of the light-emitting module 600 may be correspond to (or accordance with) the profile of the protruding portion 530 .
- the protruding portion 530 may protrude into the second alignment mark 646 of the light-emitting module 600 .
- the display device 400 may include a plurality of solders 532 that are electrically connected to the pads 520 and the pads 620 .
- a display device 700 may include two or more light-emitting modules with different arrangements. As shown in FIG. 9A , the display device 700 may include an active region 710 and a peripheral region 720 that is adjacent to (or surrounds) the active region 710 . The display device 700 may include a plurality of second alignment marks 830 A and 830 B on the active region 710 and the peripheral region 720 . As shown in FIG. 9B , a light-emitting module 800 A may have a second substrate 810 , light-emitting elements 820 and second alignment marks 830 A. As shown in FIG.
- a light-emitting module 800 B may have a second substrate 810 , light-emitting elements 820 and second alignment marks 830 B.
- One of the differences between the light-emitting module 800 A and the light-emitting module 800 B is the arrangement of the light-emitting elements 820 .
- the display device 700 may include a plurality of second alignment marks 830 A of the light-emitting module 800 A and a plurality of second alignment marks 830 B of the light-emitting module 800 B.
- the arrangement of the light-emitting module 800 A and the light-emitting module 800 B may be adjusted according to the active region 710 and the peripheral region 720 .
- the second alignment mark 830 A may be disposed on the active region 710 and the peripheral region 720 .
- the second alignment mark 830 B may be disposed on the active region 710 .
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electroluminescent Light Sources (AREA)
- Led Device Packages (AREA)
Abstract
Description
- This application is a Divisional of U.S. patent application Ser. No. 16/242,228, filed Jan. 8, 2019 and entitled “Display devices and methods for manufacturing the same”, the entirety of which is incorporated by reference herein.
- The embodiments of the disclosure relate to a display device, and in particular to a display device with an alignment mark on a light-emitting module.
- The display devices are becoming more widely used. Since mass production has recently become the tendency in the light-emitting diode industry, any increase in the yield of manufacturing light-emitting diodes, such as increasing the alignment accuracy. Therefore, the manufacturing method for the display devices may need to be continuously improved.
- A method for manufacturing a display device is provided. The method includes providing an array module having at least one first alignment mark. The method also includes providing a light-emitting module having at least one second alignment mark. The method further includes aligning the light-emitting module and the array module by the first alignment mark and the second alignment mark. In addition, the method includes bonding the light-emitting module onto the array module.
- A display device is provided. The display device includes an array module having a first alignment mark. The array module includes a first substrate and a circuit layer disposed on the first substrate. The array module also includes a plurality of pads disposed on the circuit layer. The display device also includes a light-emitting module having a second alignment mark. The light-emitting module includes a second substrate and a plurality of light-emitting elements. The plurality of light-emitting elements disposed on the second substrate and electrically connected to the plurality of pads. The second alignment mark is aligned with the first alignment mark.
- A detailed description is given in the following embodiments with reference to the accompanying drawings.
- The disclosure may be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
-
FIG. 1 is a flow chart for manufacturing a display device in accordance with some embodiments of the present disclosure; -
FIGS. 2A-2G are top views of various stages of a process for manufacturing a display device in accordance with some embodiments of the present disclosure; -
FIGS. 3A-3D are cross-sectional views of various stages of a process for manufacturing a display device in accordance with some embodiments of the present disclosure; -
FIGS. 4A and 4B are top views of a first alignment and a second alignment of a display device in accordance with some embodiments of the present disclosure; -
FIGS. 5-8 is a cross-sectional view of a display device in accordance with some embodiments of the present disclosure; -
FIG. 9A is a top view of a display device in accordance with some embodiments of the present disclosure; -
FIGS. 9B and 9C are top views of light-emitting modules in accordance with some embodiments of the present disclosure; - The display device of the present disclosure is described in detail in the following description. The drawings of different embodiments may use like and/or corresponding numerals to denote like and/or corresponding elements in order to clearly describe the present disclosure. However, the use of like and/or corresponding numerals in the drawings of different embodiments does not suggest any correlation between different embodiments. In addition, in this specification, expressions such as “first material layer disposed on/over a second material layer”, may indicate the direct contact of the first material layer and the second material layer, or it may indicate a non-contact state with one or more intermediate layers between the first material layer and the second material layer. In the above situation, the first material layer may not be in direct contact with the second material layer.
- It should be noted that the elements or devices in the drawings of the present disclosure may be present in any form or configuration known to those skilled in the art. In addition, the expression “a layer is disposed above another layer”, “a layer is disposed on another layer” may indicate that the layer is in direct contact with the other layer, or that the layer is not in direct contact with the other layer, there being one or more intermediate layers disposed between the layer and the other layer.
- The terms “about” and “substantially” typically mean +/−20% of the stated value, +/−10% of the stated value, +/−5% of the stated value, +/−3% of the stated value, +/−2% of the stated value, +/−1% of the stated value or +/−0.5% of the stated value. The stated value of the present disclosure is an approximate value. When there is no specific description, the stated value includes the meaning of “about” or “substantially”.
- It should be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers, portions and/or sections, these elements, components, regions, layers, portions and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, portion or section from another region, layer or section. Thus, a first element, component, region, layer, portion or section discussed below could be termed a second element, component, region, layer, portion or section without departing from the teachings of the present disclosure.
- Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It should be appreciated that, in each case, the term, which is defined in a commonly used dictionary, should be interpreted as having a meaning that conforms to the relative skills of the present disclosure and the background or the context of the present disclosure, and should not be interpreted in an idealized or overly formal manner unless so defined.
- This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. The drawings are not drawn to scale. In addition, structures and devices are shown schematically in order to simplify the drawing.
- In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,”, “on,”, “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivative thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.
- The present disclosure provides a method for manufacturing a display device. Refer to
FIG. 1 , which is aflow chart 100 for manufacturing a display device. Theflow chart 100 includesmultiple steps FIGS. 2A-2G orFIGS. 3A-3D .FIGS. 2A-2G illustrate the steps in the top view.FIGS. 3A-3D illustrate the steps in the cross-sectional view. In some embodiments, other steps may be appropriately added before or after above the steps. In some embodiments, the above partial steps may be appropriately deleted or replaced. In some embodiments, the above sequence of steps can be changed or modulated as needed. - The method for manufacturing the display device includes the
step 102 of providing an array module having at least one first alignment mark and a light-emitting module having at least one second alignment mark. As shown inFIGS. 2A and 2B , anarray module 200 and a light-emittingmodule 300 are provided. As shown inFIG. 2A , thearray module 200 includes afirst substrate 210. Thefirst substrate 210 may include a glass substrate, a ceramic substrate, a plastic substrate or another suitable substrate, but not limited. Thefirst substrate 210 may include polyimide (PI), polycarbonate (PC), or polyethylene terephthalate (PET), but not limited thereto. Thearray module 200 includes a plurality ofpads 220. Thepads 220 are disposed on thefirst substrate 210. The material of thepad 220 may include copper (Cu), aluminum (Al), molybdenum (Mo), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), iridium (Ir), other suitable material, or the above alloy, but is not limited.FIG. 2A illustrates a pixel P that may correspond to (or electrically connected to) sixpads 220, and a sub-pixel (correspond to one light-emitting elements 320) may respectively correspond to twopads 220, but is not limited thereto. The dotted line may correspond to a position where the pixel (not shown inFIG. 2A ) is expected to be bonded. As shown inFIG. 2B , one pixel P may include three sub-pixels, and a sub-pixel may respectively correspond to or electrically connected to twopads 220 after bonding (subsequent step 114 will be described). In other embodiments (not shown), a pixel P may correspond to (or electrically connected to) fourpads 220, for example, one of the fourpads 220 is a shared pad, the shared pad is electrically connected to three sub-pixels of the pixel P, and other pads may respectively correspond to (or electrically connected to) three sub-pixels with different colors. In some embodiments, at least part of the pixel P may overlap withcorresponding pads 220 in Z direction, and Z direction may defined as a normal direction of thefirst substrate 210 of thearray module 200. In some embodiments (shown inFIG. 2A ), thearray module 200 includes at least onefirst alignment mark 230 on thefirst substrate 210. - As shown in
FIG. 2B , the light-emittingmodule 300 includes asecond substrate 310. Thesecond substrate 310 may be a carrier substrate or growth substrate, but is not limited. In some embodiments, thesecond substrate 310 may include a glass substrate, a ceramic substrate, a plastic substrate, a sapphire substrate or another suitable substrate, but is not limited. The growth substrate may include silicon or a sapphire substrate, which includes alumina oxide, GaP, GaAs, AlGaAs, SiC, Si, or another suitable material, but is not limited. - The light-emitting
module 300 includes a plurality of light-emittingelements 320. The light-emittingelements 320 may be disposed on thesecond substrate 310. The light-emittingelement 320 may be a red sub-pixel, a green sub-pixel or a blue sub-pixel, an infrared (IR) sub-pixel, or other sub-pixel with other colors. In some embodiments, the light-emittingelement 320 may include light-emitting diode (LED), micro LED (pLED), mini LED, quantum dot (QD), quantum dot LED (QLED or QDLED) or other suitable element, but is not limited. In some embodiments, the light-emittingelement 320 may emit blue light (or UV light), but is not limited. In some embodiments, the light-emittingelement 320 may respectively emit the light with different colors (such as red, green, blue or other suitable colors). In some embodiments, the light-emittingmodule 300 may include the light conversion elements, the light conversion elements (such as quantum dot, but is not limited) may be disposed on or adjacent to the light-emittingmodule 300. - As shown in
FIG. 2B , the light-emittingmodule 300 includes at least onesecond alignment mark 330 on thesecond substrate 310. In some embodiments, at least one pixel P may be disposed between two adjacent second alignment marks 330, but not limited, the quantity of pixel P can be adjusted as needed. - In some embodiments, the position of the
second alignment mark 330 of the light-emittingmodule 300 may correspond to the position of thefirst alignment mark 230 of thearray module 200. For example, four second alignment marks 330 of the light-emittingmodule 300 may respectively correspond to one of four first alignment marks 230 on the right part (or on the left part) of thearray module 200, but not limited. As shown inFIGS. 2A and 2B , there is a distance T1 between two adjacent first alignment marks 230 along the X direction, and there is a distance T2 between two adjacent second alignment marks 330 along the X direction. X direction may be defined as a direction parallel to an extension direction of the long side of thefirst substrate 210, but not limited. In some embodiments, the X direction may be defined as an arrangement direction of adjacent pixels. In some embodiments, the X direction may be defined as an arrangement direction of sub-pixels of the pixel P. Y direction may be perpendicular with Z direction and X direction. Distance T1 may be defined as a distance between a center of one of the first alignment marks 230 and a center of another thefirst alignment mark 230 adjacent to the one of the first alignment marks 230 along the X direction (or Y direction). Distance T2 may be defined as a distance between a center of one of the second alignment marks 330 and a center of another the second alignment marks 330 adjacent to the one of the second alignment marks 330 along the X direction(or Y direction). In some embodiments, the ratio of the distance T1 to the distance T2 is in a range from 0.8 to 1.2, but not limited. In some embodiments, the ratio of the distance T1 to the distance T2 is in a range from 0.9 to 1.1. In addition, there is a distance T3 between two first alignment marks 230 which are respectively disposed on two sides of a diagonal line of the right part (or the left part) of thefirst substrate 210, and there is a distance T4 between two second alignment marks 330 which are respectively disposed on two sides of diagonal line of thesecond substrate 310. Distance T3 may be defined as a distance between a center of one of the first alignment marks 230 and a center of anotherfirst alignment mark 230 along a direction of the diagonal line. Distance T4 may be defined as a distance between a center of one of the second alignment marks 330 and a center of another second alignment marks 330 along a direction of the diagonal line. In some embodiments, the ratio of distance T3 to distance T4 is in a range from 0.8 to 1.2, but not limited. In some embodiments, the ratio of distance T3 to distance T4 is in a range from 0.9 to 1.1. When the ratio of distance T3 to distance T4 (or distance T1 to distance T2) is in the range mentioned above, the accuracy of bonding thearray module 200 and the light-emittingmodule 300 may be increased. - In some embodiments, the distance between two adjacent first alignment marks 230 along the X direction is the same as or different from the distance between two adjacent first alignment marks 230 along the Y direction. In some embodiments, the distance between two adjacent second alignment marks 330 along the X direction (such as distance T2) is the same as or different from the distance between two adjacent second alignment marks 330 along the Y direction.
- As shown in
FIG. 2B , thesecond alignment mark 330 has a width W1. The light-emittingelement 320 has a width W2. The width W2 may be a maximum width of one of the light-emittingelements 320 in X direction. The width W1 may be a maximum width of one of thesecond alignment mark 330 in X direction. In some embodiments, the width W1 is less than or equal to the width W2. In some embodiments, the width W1 is greater than the width W2. In some embodiments, an area of the light-emittingelement 320 may be defined as a lighting area of one sub-pixel operating at a highest grayscale in Z direction, but not limited. In some embodiments, an area of the light-emittingelement 320 may defined as a lighting surface (such top surface of the light-emitting element 320) of one sub-pixel, but not limited. In some embodiments, an area of the light-emittingelement 320 may be defined by the openings of the light blocking layer 630 (shown inFIG. 5 toFIG. 6 ). - The method for manufacturing the display device includes the
step 104 that aligning thearray module 200 and the light-emittingmodule 300 by thefirst alignment mark 230 and thesecond alignment mark 330. As shown inFIG. 2C , the light-emittingmodule 300 may approach (or be transferred to) the right part (or left part) of thearray module 200. - The method for manufacturing the display device includes the
step 106 that approaching the at least onesecond alignment mark 330 with the at least onefirst alignment mark 230 into a detecting region S. Refer toFIG. 2D , which is an enlarged view of region R shown inFIG. 2C . As shown inFIG. 2D , the detecting region S may be a region that can be detected by a charge-coupled device (CCD) camera (not shown) or other suitable image equipment (or camera equipment), but not limited. When at least one of thesecond alignment mark 330 and thefirst alignment mark 230 is outside the detecting region S, the light-emittingmodule 300 or thearray module 200 may be transferred, so that thesecond alignment mark 330 and thefirst alignment mark 230 would be inside the detecting region S. - The method for manufacturing the display device includes the
step 108 that detecting the distance between thesecond alignment mark 330 and thefirst alignment mark 230, and comparing the distance with a predetermined value. In some embodiment, the distance between thesecond alignment mark 330 and thefirst alignment mark 230 detected by thestep 108 may be defined as a mismatch between thesecond alignment mark 330 and thefirst alignment mark 230. Refer toFIG. 2E , which is an enlarged view of the region R shown inFIG. 2C . After thesecond alignment mark 330 and thefirst alignment mark 230 are inside the detecting region S, the distance between thefirst alignment mark 230 and thesecond alignment mark 330 is detected by the CCD camera or other suitable image equipment (or camera equipment), but not limited, and the distance between thefirst alignment mark 230 and thesecond alignment mark 330 will be compared with the predetermined value. In some embodiments (shown inFIG. 2B ), one pixel pitch P has a width W3, and the predetermined value is less than or equal to half of the width W3. The width W3 may be a distance between the centers (left sides or right sides) of the two adjacent pixels P, but not limited. For example, the pixel pitch P may be a distance between the centers (left sides or right sides) of two adjacent sub-pixels with the same color. That is, the mismatch between thesecond alignment mark 330 and thefirst alignment mark 230 is less than half of the pixel pitch P of the display device. - The method for manufacturing the display device includes the
step 110 that determining whether the distance (ex. mismatch) is less than or equal to the predetermined value. For example, thestep 110 includes determining whether the distance (ex. mismatch) X1 along the X direction (or the distance (ex. mismatch) Y1 along the Y direction) is less than or equal to the predetermined value. - If the distance X1 (or the distance Y1) is greater than the predetermined value, the
step 112 will be performed. Thestep 112 includes reducing the distance between thesecond alignment mark 330 and thefirst alignment mark 230. In addition, thestep 112 includes adjusting the position of thearray module 200 or the light-emittingmodule 300, so that thefirst alignment mark 230 would be aligned with (or overlapped with) thesecond alignment mark 330. In some embodiments, thestep 112 includes approaching thearray module 200 or the light-emittingmodule 300 along the X direction (or the Y direction or other directions), so that thefirst alignment mark 230 would be aligned with (or overlapped with) thesecond alignment mark 330, but not limited. After the performing of thestep 112, thestep 108 is performed to detect the distance between thefirst alignment mark 230 and thesecond alignment mark 330 along the X direction (or the Y direction or other directions). - In some embodiments, if both the distance X1 and the distance Y1 are less than or equal to the predetermined value, the
step 114 will be performed. Thestep 114 includes bonding the light-emittingmodule 300 onto thearray module 200. As shown inFIG. 2F , after bonding the light-emittingmodule 300 onto thearray module 200, thesecond substrate 310 may be disposed on the right part (left part or other part) of thefirst substrate 210, but not limited. Moreover, the light-emittingelements 320 may be electrically connected to thecorresponding pad 220. In some embodiments, the light-emittingelements 320 may respectively overlap with part of thecorresponding pad 220 in Z direction. - In some embodiments, the predetermined value is less than or equal to half of the width W3 of the pixel pitch P. In some embodiments, the predetermined value is equal to the width W2. When the predetermined value is in the range mentioned above, the production yield of bonding the
array module 200 and the light-emittingmodule 300 may be increased. - In some embodiments, the
second substrate 310 may be removed (as shown inFIG. 2G ), and the light-emittingelements 320 are disposed on (or bonded onto) thepad 220. In some embodiments, thesecond substrate 310 may be removed by a laser or other suitable methods. In some embodiments, thesecond substrate 310 may not be removed, and thesecond substrate 310 and the light-emittingelements 320 may disposed on thearray module 200. The process shown inFIGS. 2A-2G may be repeated so that another light-emittingmodule 300 may be disposed on (or bonded on) the another part (such as left part) of thearray module 200. - The process shown in
FIGS. 2A-2G may be used in mass production of the display device, but not limited. For example, nine pixels may be disposed on (or bonded onto) thecorresponding pads 220 in same bonding process, but not limited. In some embodiments, thesecond substrate 310 may be used as a growth substrate, and the second alignment marks may be disposed on (or formed on) thesecond substrate 310. In some embodiments, thesecond substrate 310 may be used as a carrier substrate, and the light-emittingelements 320 may be transferred onto thesecond substrate 310, and then transferred onto (or disposed on) thearray module 200, but not limited. In some embodiments, the quantity (number) of first alignment marks 230 may be greater than or equal to the quantity (number) of the second alignment marks 330, but not limited. In some embodiments, the light-emittingmodule 300 may have four second alignment marks 330, and the four second alignment marks 330 may respectively be disposed at four corners of thesecond substrate 310, but not limited. In some embodiments, the quantity of the second alignment marks 330 in light-emittingmodule 300 is greater than (or less than) four, and the second alignment marks 330 may be disposed at other suitable position of thesecond substrate 310. In some embodiments, the light-emittingmodule 300 has two second alignment marks 330, and two second alignment marks 330 may respectively be disposed at two diagonal corners of thesecond substrate 310. In some embodiments, the light-emittingmodule 300 may have at least onesecond alignment mark 330. The quantity of the first alignment marks 230 or the position of the first alignment marks 230 may be correspond to the second alignment marks 330, which can be adjusted according to the needs. - Refer to
FIGS. 3A-3G , which are cross-sectional views of various stages of a process for manufacturing the display device. In some embodiments, thearray module 200 includes acircuit layer 240, and thecircuit layer 240 is disposed on (or formed on) thefirst substrate 210. Furthermore, thecircuit layer 240 may includewires 250, other conductive elements (not shown), other dielectric layers (not shown), but not limited. In some embodiments, thepads 220 may be disposed on (or electrically connected to) thecircuit layer 240. In some embodiments (shown inFIG. 3A ), thefirst alignment mark 230 may be disposed on thecircuit layer 240. In some embodiments, thefirst alignment mark 230 may be disposed in (or formed in) the circuit layer 240 (not shown inFIGS. 3A-3G , but shown inFIG. 5 ). In some embodiments, the material of thewires 250 may be the same as or different from thepads 220, thewires 250 or other conductive elements of thecircuit layer 240. In some embodiments, thefirst alignment mark 230 and thepads 220, thewires 250 or other conductive elements of thecircuit layer 240 may be formed in the same process or different process, but not limited. In some embodiment, thefirst alignment mark 230 may be formed before the process of forming thecircuit layer 240. In some embodiment, thefirst alignment mark 230 may be formed after the process of forming thepad 220. In some embodiment, the material of thefirst alignment mark 230 may include opaque materials, shading materials, reflective materials or a combination of the above, but is not limited thereto. In some embodiment, the material of thefirst alignment mark 230 may include metal material, metal alloy, black photoresist or other suitable material, but is not limited thereto. - As shown in
FIG. 3A , the light-emittingmodule 300 includes a plurality ofpads 322 disposed on the light-emittingelement 320. - As shown in
FIG. 3A , the distance D1 may be a distance between a center of thefirst alignment mark 230 and a center of thesecond alignment mark 330 along the X direction (or the Y direction). If the distance D1 is greater than the predetermined value, the position of the light-emittingmodule 300 will be fine-tuned. - As shown in
FIGS. 3B , the position of the light-emittingmodule 300 is fine-tuned. If the distance D1 is less than or equal to the predetermined value, the light-emittingmodule 300 is bonded onto thearray module 200 as shown inFIG. 3C . After the bonding process, thesecond alignment mark 330 may approximately overlap with thefirst alignment mark 230 in Z direction, or thesecond alignment mark 330 may approximately aligned with thefirst alignment mark 230. - As shown in
FIG. 3D , after the light-emittingmodule 300 is disposed on (or bonded onto) thearray module 200, thesecond substrate 310 may be removed, but not limited. The light-emittingelements 320 and thepads 322 may be disposed on thearray module 200. In some embodiment, thepads 322 of the light-emittingmodule 300 may electrically connected to (or contact with) thecorresponding pads 220 of thearray module 200. In some embodiment, the light-emittingelement 320 may be electrically connected to thepad 220 through thepad 322. If the distance D1 is less than or equal to the predetermined value, the production yield in mass producing the display device can increase. - Refer to
FIGS. 4A and 4B , which are top views of a first alignment and a second alignment in accordance with some embodiments. The profile of the first alignment marks and second alignment marks shown inFIGS. 4A and 4B are merely examples, and the present disclosure is not limited thereto. In some embodiments, thefirst alignment mark 230A and thesecond alignment mark 330A are in different shapes. In some embodiments, thesecond alignment mark 330A may be adjacent to thefirst alignment mark 230A. In some embodiments, thesecond alignment mark 330A may enclose thefirst alignment mark 230A, as shown inFIG. 4A . In some embodiments, the second alignment mark may have an opening O, at least part the opening O may overlap with thefirst alignment mark 230A in Z direction, but not limited. In some embodiments, at least part of thesecond alignment mark 330A may overlap with at least part of thefirst alignment mark 230A in Z direction. In some embodiments, the shape of thefirst alignment mark 230A and the shape of thesecond alignment mark 330A may include rectangle, circle, triangle, polygon, arc shape, obtuse angle shape, acute angle shape, round shape or other suitable shapes, but is not limited. In some embodiments, the shape of thefirst alignment mark 230A may be the same as or different from the shape of thesecond alignment mark 330A. In some embodiments, a distance dm between thesecond alignment mark 330A and thefirst alignment mark 230A in X direction (or Y direction) is greater than or equal to 0, and less than or equal to the width W2 (shown inFIG. 2B ). Distance dm may be defined as the minimum distance between thesecond alignment mark 330A and thefirst alignment mark 230A in X direction (or Y direction). In some embodiments, the position of thefirst alignment mark 230A and the position of thesecond alignment mark 330A can be exchanged. - In some embodiments, the
second alignment mark 330B may have discontinuous parts, as shown inFIG. 4B . In some embodiments, the profile of the shape of thesecond alignment mark 330B is different from or the same as the shape of thefirst alignment mark 230B. Thefirst alignment mark 230B may have a cross-shape, rectangular shape, polygonal shape, curved shape, circular shape, arc shape, obtuse angle shape, acute angle shape, round shape or other suitable shapes, but not limited. In some embodiments, thefirst alignment mark 230B may include protruding portions. Thesecond alignment mark 330B may be adjacent to thefirst alignment mark 230B, and thesecond alignment mark 330B may have any shape correspond to (or in accordance with) the shape of thefirst alignment mark 230B, but not limited. For example, thesecond alignment mark 330B may have an L-shape (or other shape) and extend into the space between two adjacent protruding portions of thefirst alignment mark 230B, but not limited. The above “thealignment mark 330B has any shape correspond to (or in accordance with) the shape of thefirst alignment mark 230B” includes that thealignment mark 330B has any shape correspond to at least one side of thefirst alignment mark 230B. It should be noted that, one of the second alignment marks 330B may have discontinuous parts, these parts may correspond to one of the first alignment marks 230B, these parts can form a second alignment marks 330B, and these parts may have similar or different shapes. In some embodiments, the position of thefirst alignment mark 230B and the position of thesecond alignment mark 330B can be exchanged. In some embodiments, the shape of thefirst alignment mark 230B and the shape of thesecond alignment mark 330B may be complement each other. - Refer to
FIG. 5 , which is a cross-sectional view of adisplay device 400A in accordance with some embodiments. Thedisplay device 400A may include anarray module 500 and a light-emittingmodule 600. Thearray module 500 may include asubstrate 502. The material of thesubstrate 502 may be the same as or similar to the material of thefirst substrate 210. In some embodiments, some insulatinglayers substrate 502. The insulatinglayers - A plurality of
transistors 510 is disposed on thesubstrate 502. Thetransistor 510 may be a thin film transistor (TFT). For example, thetransistor 510 may include agate electrode 512, a source/drain electrode 518, and asemiconductor layer 516. Thegate electrode 512 may be disposed on the insulatinglayer 504 and thesemiconductor layer 516. The source/drain electrode 518 may be disposed on thesemiconductor layer 516 and the doping layers 514, and thesemiconductor layer 516 may be disposed between the doping layers 514. The material of thegate electrode 512 and the source/drain electrode 518 may include, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), gold (Au), chromium (Cr), nickel (Ni), titanium (Ti), other suitable material or alloy. The material of thesemiconductor layer 516 may include, but is not limited to, amorphous silicon, polysilicon such as low-temp polysilicon (LTPS), metal oxide or other suitable materials. The metal oxide may include indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium zinc tin oxide (IGZTO) or other suitable material. - The
array module 500 may include a plurality ofwires 509 andpads 520. Thepads 520 may be disposed on the insulatinglayer 508 and thewires 509. Thetransistor 510 may be electrically connected to thepad 520 through thewire 509, but not limited. The material of thewire 509 and thepad 520 may be the same as or different from the material of the source/drain electrode 518. - In some embodiments, the
first alignment mark 522 may be disposed on the insulatinglayer 504. In some embodiments, thefirst alignment mark 522 and thegate electrode 512 may be formed in the same process. In some embodiments, the material of thefirst alignment mark 522 and the material of thegate electrode 512 may be same. In some embodiments, thefirst alignment mark 522 may include metal material that is disposed in the insulatinglayer 506. In other embodiments, thefirst alignment mark 522 and thepad 520 may be formed in the same process. In some embodiments, the material of thefirst alignment mark 522 and the material of thegate electrode 512 may be same. In other embodiments, the material of thefirst alignment mark 522 and the material of source/drain electrode 518 may be same. - As shown in
FIG. 5 , the light-emittingmodule 600 includes asubstrate 602. Thesubstrate 602 may include a glass substrate, a ceramic substrate, a plastic substrate or another suitable substrate, but not limited. The material of thesubstrate 602 may include sapphire, Si, SiC, other suitable materials or combinations thereof, but are not limited thereto. In some embodiments, the light-emittingmodule 600 may include insulatinglayers layers substrate 602. The insulatinglayers module 600 may include a plurality of thetransistors 610. For example, thetransistor 610 may include agate electrode 612, a source/drain electrode 614, and a semiconductor layer 616. Thegate electrode 612 may be disposed on the insulatinglayer 604. The materials of thegate electrode 612, the source/drain electrode 614 and the semiconductor layer 616 may be the same as, similar to or different from those of thegate electrode 512, the source/drain electrode 518 and thesemiconductor layer 516, respectively. The light-emittingmodule 600 includes a plurality ofwires 618 andpads 620. In some embodiments, thetransistor 610 may be electrically connected to thepad 620 through thewire 618. In some embodiments, and thetransistor 510 may be electrically connected to thetransistor 610. In some embodiments, thepad 520 may be electrically connected to (or contact with) thepad 620. In some embodiments, thetransistor 610 may use as a driving transistor. In some embodiments, thetransistor 510 may use as a switch transistor. In some embodiments, more transistors (or elements) may be disposed on thesubstrate 602 or thesubstrate 502, such as reset transistor or capacitor, but not limited. In some embodiments, thetransistor 610 and thetransistor 510 may disposed on the same substrate (such assubstrate 602 or the substrate 502). The structure of the transistor 610 (or the transistor 510) described above is an example, and the disclosure is not limited thereto. In some embodiments, the transistor 610 (or the transistor 510) can be top gate thin film transistor, bottom gate thin film transistor, double gate thin film transistor, but not limited. In addition, the transistor 610 (or the transistor 510) can include amorphous germanium (a-Si:H) transistor, low temperature polycrystalline germanium transistor (LTPS), indium gallium zinc oxide transistor (IGZO) or other suitable transistor, but not limited. The light-emittingelement 626 may be electrically connected to thetransistor 610 and thetransistor 510 through the conductive elements which are disposed in thearray module 500 or the light-emittingmodule 600. - As shown in
FIG. 5 , the light-emittingmodule 600 includes insulatinglayer module 600 includes a plurality of light-emittingelements 626 and pads 628. In some embodiments, the light-emittingelement 626 and the pad 628 may be surrounded by the insulatinglayer 622, but not limited. The insulatinglayers 622 may be disposed to protect the light-emittingelement 626 or the pad 628 from damage or pollution (such as water or air), but not limited. The material of the insulating layer 622 (or the insulating layer 624) may include, but is not limited to, resin or another suitable material. The light-emittingelement 626 and the pad 628 may be the same as or similar to the light-emittingelement 320 and thepad 322 shown inFIG. 3A , respectively. In some embodiments, the order of the above layers or elements can be changed or replaced as needed. In some embodiments, the above layers can be replaced or removed as needed. - As shown in
FIG. 5 , the light-emittingmodule 600 includes alight blocking layer 630. Thelight blocking layer 630 may be disposed on the light-emittingelement 626. Thelight blocking layer 630 has a plurality of openings B-O, the openings B-O may overlap with the light-emittingelement 626 in Z direction. In some embodiments, thelight blocking layer 630 does not overlap with the light-emittingelement 626 in Z direction. The light-emittingmodule 600 may include a plurality oflight conversion layer 632. Thelight conversion layer 632 may be disposed on (or cover) the light-emittingelement 626. In some embodiments, thelight conversion layer 632 may be adjacent to the light-emittingelement 626. The material of thelight conversion layer 632 may include, but is not limited to, quantum dot, fluorescent material, phosphorescent material or another conversion material. For example, thelight conversion layer 632 may be an organic or an inorganic layer blended with a quantum dot. The quantum dot may include, but is not limited to, zinc, cadmium, selenium, sulfur, InP, GaSb, GaAs, CdSe, CdS, ZnS or a combination thereof, but not limited. - The light-emitting
module 600 further includes aprotective layer 634 and acolor filter layer 636. The light-emittingelement 626 may be disposed between theprotective layer 634 and thesubstrate 602. Thecolor filter layer 636 may be disposed between thelight conversion layer 632 and theprotective layer 634, but not limited. Theprotective layer 634 may be single layer structure, multilayer structure, composite structure, but not limited. The material of theprotective layer 634 may include organic material, inorganic material, or a combination thereof. In some embodiments, the material of theprotective layer 634 may be a transparent substrate. In some embodiments, the material of theprotective layer 634 may include phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, or silicon oxynitride, but not limited. In some embodiments, thecolor filter layer 636 may be disposed on at least one of thelight conversion layer 632. In some embodiments, thecolor filter layer 636 may be respectively disposed on the correspondinglight conversion layer 632. In some embodiments, thecolor filter layer 636 may overlap with at least part of thelight blocking layer 630 in Z direction in order to reduce light leakage. In some embodiments (not shown), thecolor filter layer 636 may disposed between thelight conversion layer 632 and the light-emittingelement 626. - In some embodiments, the second alignment mark may be disposed in (or formed in) the second substrate. For example (
FIG. 5 ), thesecond substrate 602 may be a transparent substrate or non-transparent substrate, a through hole TH may penetrate thesecond substrate 602, and the through hole TH may be regarded as thesecond alignment mark 638. In some embodiments, the through hole TH may penetrate at least part of the layers (or the elements) formed on thesecond substrate 602. For example (shown asFIG. 5 ), the through hole TH may penetrate thesecond substrate 602, the insulatinglayers light blocking layer 630 and theprotective layer 634, but not limited. In some embodiments, in Z direction, a shape of the through hole TH may include rectangle, circle, triangle, polygon, arc shape, obtuse angle shape, acute angle shape, round shape or other suitable shapes, but not limited. In some embodiments, in the direction of the cross section, the through hole has an inverted trapezoid profile, rectangular profile or other shape profile, but not limited. However, the scope of the disclosure is not limiting. - As shown in
FIG. 5 , thesecond alignment mark 638 approximately overlap with (or aligned with) thefirst alignment mark 522 in Z direction. The second alignment mark 638 (such as through hole TH) have a bottom surface BS and top surface TS opposite to the bottom surface BS, and the bottom surface BS is near to thearray module 500. In the cross section, the bottom surface BS of the second alignment mark 638 (such as through hole TH) may have a length L1, and the top surface TS of thesecond alignment mark 638 may have length L3. In some embodiments, the length L3 may be greater than or equal to the length L1. In some embodiments, the length L3 may be less than or equal to the length L1. In some embodiments, the length L3 also may be defined as the maximum length of the top surface TS of thesecond alignment mark 638 in top view, and length L1 also may be defined as the maximum length of the bottom surface BS of thesecond alignment mark 638 in top view. - As shown in
FIG. 5 , the cross section, thefirst alignment mark 522 has a length L2. In some embodiments, the length L1 is greater than or equal to the length L2. The length L1 is greater than the length L2 so that the CCD camera could receive both images of thefirst alignment mark 522 and thesecond alignment mark 638. In addition, there is an angle θ constituted by an extension direction of the side surface of the second alignment mark 638 (such as through hole TH) and an extension direction of the bottom surface BS of thesecond alignment mark 638. In some embodiments, the angle θ may be in a range from about 30° to about 110°, but not limited. In some embodiments, the angle θ is in a range from about 50° to about 90°. In some embodiments, the angle θ is in a range from about 70° to about 90°. In some embodiments, the side surface of the second alignment mark 638 (such as through hole TH) is a curved edge or an irregular edge. For example, in the Z direction, viewers can see the elements (such asfirst alignment mark 522 or other layers (or elements) of the array module 500) through the second alignment mark 638 (through hole TH). - As shown in
FIG. 5 , at least onespacer 524 may be disposed between thearray module 500 and the light-emittingmodule 600. Thespacer 524 may include resin or other suitable materials, but not limited. In some embodiments, at least onespace 526 may be formed between thearray module 500 and the light-emittingmodule 600 by thespacer 524. Thespace 526 may include air, transparent material or other suitable materials, but not limited. - Refer to
FIG. 6 , which illustrates a cross-sectional view of adisplay device 400B in accordance with some embodiments. In some embodiments, one of the differences between thedisplay device 400B and thedisplay device 400A is that asecond alignment mark 640 of thedisplay device 400A may include a filling materials FM, the filling materials FM may be disposed in (or filled in) the through hole TH, and the through hole TH with the filling materials FM may be regarded as thesecond alignment mark 330. In some embodiments, the filling materials may include transparent material. The filling materials FM may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride or another suitable material. - Refer to
FIG. 7 , which illustrates a cross-sectional view of adisplay device 400C in accordance with some embodiments. In some embodiments, one of the differences between thedisplay device 400C and thedisplay device 400A is that anotch 642 may penetrate part of layers (or elements) in the light-emittingmodule 600. In some embodiments (FIG. 7 ), thenotch 642 may penetrate the insulatinglayers light blocking layer 630 and theprotective layer 634. Thedisplay device 400C may include asecond alignment mark 644. The material of thesecond alignment mark 644 may be the same as or similar to the material of thegate electrode 612 of thetransistor 610, but not limited. In some embodiments, thesecond alignment mark 644 and a portion of the transistor 610 (such as source/drain electrode 614) may be formed in the same process or different process. In some embodiments, the material of thesecond alignment mark 644 may be the same as or different from the material of a portion of the transistor 610 (such as source/drain electrode 614). - As shown in
FIG. 7 , thenotch 642 has a bottom surface BS′, and the bottom surface BS′ is near to thearray module 500. In the cross section, the bottom surface BS′ of thenotch 642 may have a length L1′. In some embodiments, the length L1′ also may be defined as the maximum length of the bottom surface BS′ of thenotch 642 in top view. As shown inFIG. 7 , thesecond alignment mark 644 has length L4, the length L4 may be defined as the maximum length of thesecond alignment mark 644 in X direction (or Y direction). In some embodiments, the length L4 is less than or equal to the length L1′. In some embodiments, at least part of thesecond alignment mark 644 may overlap with thefirst alignment mark 522 in Z direction. In some embodiments, at least part of thesecond alignment mark 644 may be aligned with thefirst alignment mark 522. In some embodiments, the shape of thenotch 642 may be the same as or different from of shape of thesecond alignment mark 644 in Z direction. - Refer to
FIG. 8 , which illustrates a cross-sectional view of adisplay device 400D in accordance with some embodiments. In some embodiments, one of the differences between thedisplay device 400D and thedisplay device 400A is that thearray module 500 of thedisplay device 400D may include aspacer 528 and a protrudingportion 530 that is disposed on thespacer 528. The protrudingportion 530 may be regarded as the first alignment mark of thearray module 500. Moreover, the profile of asecond alignment mark 646 of the light-emittingmodule 600 may be correspond to (or accordance with) the profile of the protrudingportion 530. The protrudingportion 530 may protrude into thesecond alignment mark 646 of the light-emittingmodule 600. In addition, the display device 400 may include a plurality ofsolders 532 that are electrically connected to thepads 520 and thepads 620. - As shown in
FIGS. 9A-9C , adisplay device 700 may include two or more light-emitting modules with different arrangements. As shown inFIG. 9A , thedisplay device 700 may include anactive region 710 and aperipheral region 720 that is adjacent to (or surrounds) theactive region 710. Thedisplay device 700 may include a plurality of second alignment marks 830A and 830B on theactive region 710 and theperipheral region 720. As shown inFIG. 9B , a light-emittingmodule 800A may have asecond substrate 810, light-emittingelements 820 and second alignment marks 830A. As shown inFIG. 9C , a light-emittingmodule 800B may have asecond substrate 810, light-emittingelements 820 and second alignment marks 830B. One of the differences between the light-emittingmodule 800A and the light-emittingmodule 800B is the arrangement of the light-emittingelements 820. As shown inFIG. 9A , thedisplay device 700 may include a plurality of second alignment marks 830A of the light-emittingmodule 800A and a plurality of second alignment marks 830B of the light-emittingmodule 800B. The arrangement of the light-emittingmodule 800A and the light-emittingmodule 800B may be adjusted according to theactive region 710 and theperipheral region 720. For example, thesecond alignment mark 830A may be disposed on theactive region 710 and theperipheral region 720. Thesecond alignment mark 830B may be disposed on theactive region 710. - Although some embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present disclosure. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/237,154 US20210242135A1 (en) | 2019-01-08 | 2021-04-22 | Display devices and methods for manufacturing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/242,228 US11018089B2 (en) | 2019-01-08 | 2019-01-08 | Display devices and methods for manufacturing the same |
US17/237,154 US20210242135A1 (en) | 2019-01-08 | 2021-04-22 | Display devices and methods for manufacturing the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/242,228 Division US11018089B2 (en) | 2019-01-08 | 2019-01-08 | Display devices and methods for manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20210242135A1 true US20210242135A1 (en) | 2021-08-05 |
Family
ID=69055841
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/242,228 Active US11018089B2 (en) | 2019-01-08 | 2019-01-08 | Display devices and methods for manufacturing the same |
US17/237,154 Pending US20210242135A1 (en) | 2019-01-08 | 2021-04-22 | Display devices and methods for manufacturing the same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/242,228 Active US11018089B2 (en) | 2019-01-08 | 2019-01-08 | Display devices and methods for manufacturing the same |
Country Status (4)
Country | Link |
---|---|
US (2) | US11018089B2 (en) |
EP (1) | EP3680933A1 (en) |
KR (1) | KR20200086617A (en) |
CN (1) | CN111415955A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI799272B (en) * | 2022-03-01 | 2023-04-11 | 南亞科技股份有限公司 | Method for preparing a semiconductor device structure including overlay mark structure |
TWI815661B (en) * | 2022-02-28 | 2023-09-11 | 群創光電股份有限公司 | Electronic device |
US12125800B2 (en) | 2022-03-01 | 2024-10-22 | Nanya Technology Corporation | Semiconductor device structure including overlay mark structure |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220157854A1 (en) * | 2019-02-26 | 2022-05-19 | Kyocera Corporation | Micro-light-emitting diode mounting board and display device including micro-light-emitting diode mounting board |
US11088306B2 (en) * | 2019-04-08 | 2021-08-10 | Innolux Corporation | Light-emitting devices and methods for manufacturing the same |
KR102657174B1 (en) * | 2019-04-08 | 2024-04-15 | 삼성디스플레이 주식회사 | Electronic panel and method of manufacturing the same |
CN110634839B (en) * | 2019-09-26 | 2021-11-26 | 京东方科技集团股份有限公司 | Micro light-emitting diode display substrate, device and preparation method |
US11362038B2 (en) * | 2020-05-28 | 2022-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Photolithography alignment process for bonded wafers |
DE102020126211A1 (en) | 2020-05-28 | 2021-12-02 | Taiwan Semiconductor Manufacturing Co. Ltd. | Photolithography alignment process for bonded wafers |
US11837590B2 (en) * | 2020-06-19 | 2023-12-05 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Display panel, manufacturing method thereof, and display device |
EP3958308A1 (en) * | 2020-08-19 | 2022-02-23 | Lumileds LLC | Lighting element alignment |
CN112164334B (en) * | 2020-10-27 | 2022-08-26 | 湖北长江新型显示产业创新中心有限公司 | Display panel, display device and preparation method of display panel |
KR20220072098A (en) * | 2020-11-24 | 2022-06-02 | 삼성디스플레이 주식회사 | Device and method for manufacturing display device |
CN113380865A (en) * | 2021-06-07 | 2021-09-10 | 京东方科技集团股份有限公司 | Display device |
WO2023123270A1 (en) * | 2021-12-30 | 2023-07-06 | 厦门市芯颖显示科技有限公司 | Display panel, display apparatus and manufacturing method for display panel |
CN115274528B (en) * | 2022-09-22 | 2022-12-06 | 西北电子装备技术研究所(中国电子科技集团公司第二研究所) | Calibration glass sheet for flip chip bonding |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6838689B1 (en) * | 2002-02-14 | 2005-01-04 | Finisar Corporation | Backside alignment and packaging of opto-electronic devices |
US20160141552A1 (en) * | 2013-07-05 | 2016-05-19 | Industrial Technology Research Institute | Flexible display and method for fabricating the same |
US20170200916A1 (en) * | 2016-01-08 | 2017-07-13 | Samsung Display Co., Ltd. | Display apparatus and manufacturing method thereof |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4701537B2 (en) * | 2001-05-16 | 2011-06-15 | ソニー株式会社 | Device transfer method and image display device manufacturing method |
CN102812541B (en) | 2011-03-24 | 2016-02-03 | 松下知识产权经营株式会社 | The image display device of flexible semiconductor device and manufacture method and use flexible semiconductor device and manufacture method thereof |
DE102012112530A1 (en) * | 2012-12-18 | 2014-06-18 | Osram Opto Semiconductors Gmbh | Method for producing optoelectronic semiconductor chips and optoelectronic semiconductor chip |
US9799719B2 (en) | 2014-09-25 | 2017-10-24 | X-Celeprint Limited | Active-matrix touchscreen |
US9478583B2 (en) * | 2014-12-08 | 2016-10-25 | Apple Inc. | Wearable display having an array of LEDs on a conformable silicon substrate |
CN104576964A (en) * | 2014-12-17 | 2015-04-29 | 深圳市华星光电技术有限公司 | Transparent flexible encapsulation substrate and flexible OLED encapsulation method |
TWI557831B (en) * | 2015-05-15 | 2016-11-11 | 友達光電股份有限公司 | Method for transferring micro device |
KR102524805B1 (en) | 2016-02-12 | 2023-04-25 | 삼성전자주식회사 | Lighting source module, display panel and display apparatus |
KR102480220B1 (en) | 2016-04-08 | 2022-12-26 | 삼성전자주식회사 | Lighting emitting diode module and display panel |
CN107768498B (en) * | 2016-08-19 | 2019-07-30 | 群创光电股份有限公司 | Light emitting display device and preparation method thereof |
US20180190672A1 (en) | 2017-01-03 | 2018-07-05 | Innolux Corporation | Display device |
CN108573660B (en) * | 2017-03-12 | 2021-04-09 | 美科米尚技术有限公司 | Display device |
JP6823717B2 (en) * | 2017-05-26 | 2021-02-03 | シャープ株式会社 | Semiconductor module and its manufacturing method |
KR101902566B1 (en) * | 2017-07-25 | 2018-09-28 | 엘지디스플레이 주식회사 | Light emitting diode display apparatus and manufacturing method of the same |
KR102481818B1 (en) * | 2017-08-22 | 2022-12-28 | 삼성디스플레이 주식회사 | Electronic component, electric device including the same |
CN108039415B (en) * | 2017-11-02 | 2019-06-07 | 厦门市三安光电科技有限公司 | The packaging method of microcomponent |
KR102538411B1 (en) * | 2018-07-25 | 2023-05-31 | 삼성디스플레이 주식회사 | Display device |
-
2019
- 2019-01-08 US US16/242,228 patent/US11018089B2/en active Active
- 2019-12-04 KR KR1020190159838A patent/KR20200086617A/en not_active Application Discontinuation
- 2019-12-30 EP EP19220015.2A patent/EP3680933A1/en active Pending
-
2020
- 2020-01-02 CN CN202010000737.9A patent/CN111415955A/en active Pending
-
2021
- 2021-04-22 US US17/237,154 patent/US20210242135A1/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6838689B1 (en) * | 2002-02-14 | 2005-01-04 | Finisar Corporation | Backside alignment and packaging of opto-electronic devices |
US20160141552A1 (en) * | 2013-07-05 | 2016-05-19 | Industrial Technology Research Institute | Flexible display and method for fabricating the same |
US20170200916A1 (en) * | 2016-01-08 | 2017-07-13 | Samsung Display Co., Ltd. | Display apparatus and manufacturing method thereof |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI815661B (en) * | 2022-02-28 | 2023-09-11 | 群創光電股份有限公司 | Electronic device |
TWI799272B (en) * | 2022-03-01 | 2023-04-11 | 南亞科技股份有限公司 | Method for preparing a semiconductor device structure including overlay mark structure |
US12125800B2 (en) | 2022-03-01 | 2024-10-22 | Nanya Technology Corporation | Semiconductor device structure including overlay mark structure |
Also Published As
Publication number | Publication date |
---|---|
KR20200086617A (en) | 2020-07-17 |
EP3680933A1 (en) | 2020-07-15 |
US20200219820A1 (en) | 2020-07-09 |
CN111415955A (en) | 2020-07-14 |
US11018089B2 (en) | 2021-05-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20210242135A1 (en) | Display devices and methods for manufacturing the same | |
EP3343611B1 (en) | Display device | |
KR20170023268A (en) | Organic light emitting display apparatus and method for manufacturing the same | |
US11749709B2 (en) | Display device | |
WO2020203702A1 (en) | Display device | |
US20230275197A1 (en) | Display device | |
KR20210148536A (en) | Display device and method for fabrication thereof | |
US11881541B2 (en) | Display device | |
US10879218B2 (en) | Display device and method of manufacturing the same | |
KR102571288B1 (en) | Display device | |
KR102650144B1 (en) | Display device and method of manufacturing the same | |
US12120933B2 (en) | Display device and tiled display device including the same | |
US20220085098A1 (en) | Tiled display device | |
KR102723516B1 (en) | Display device and method of manufacturing the same | |
US20240014363A1 (en) | Display device | |
EP3955293B1 (en) | Display device and tiled display device including the same | |
US11652189B2 (en) | Display device | |
US20230268464A1 (en) | Light emitting element, method of manufacturing light emitting element, and method of manufacturing display device | |
US20230189560A1 (en) | Display device and method of manufacturing the same | |
US20220262870A1 (en) | Display device | |
KR20240156356A (en) | Display device and method of manufacturing the same | |
KR20170086159A (en) | Organic light emitting display apparatus and method for manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INNOLUX CORPORATION, TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, JIA-YUAN;TSAI, TSUNG-HAN;LEE, KUAN-FENG;AND OTHERS;REEL/FRAME:056000/0075 Effective date: 20181205 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: APPLICATION DISPATCHED FROM PREEXAM, NOT YET DOCKETED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |