US20210210037A1 - Control chip for use in variable refresh rate and related display device and driving method - Google Patents
Control chip for use in variable refresh rate and related display device and driving method Download PDFInfo
- Publication number
- US20210210037A1 US20210210037A1 US17/136,210 US202017136210A US2021210037A1 US 20210210037 A1 US20210210037 A1 US 20210210037A1 US 202017136210 A US202017136210 A US 202017136210A US 2021210037 A1 US2021210037 A1 US 2021210037A1
- Authority
- US
- United States
- Prior art keywords
- switching signal
- processing circuit
- frequency
- vertical refresh
- refresh rate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3406—Control of illumination source
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3618—Control of matrices with row and column drivers with automatic refresh of the display panel using sense/write circuits
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0257—Reduction of after-image effects
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/06—Adjustment of display parameters
- G09G2320/0626—Adjustment of display parameters for control of overall brightness
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
- G09G2340/0435—Change or adaptation of the frame rate of the video stream
Definitions
- the present disclosure generally relates to a display device. More particularly, the present disclosure relates to a control chip capable of providing a constant brightness under variable refresh rate and related driving method.
- LCD monitors that support variable refresh rate (VRR) often use high-brightness but short-duration strobe backlight to solve the problem of motion blur, and further constantly turn on the backlight at low brightness level, when refresh period extends, to ensure that user feels constant equivalent brightness.
- VRR variable refresh rate
- the above method requires rapidly switching the duty cycle of analog dimming control signals of the backlight module. Based on capacitor charge and discharge characteristics of the circuit, those control signals are hardly to be immediately changed to target waveforms. Therefore, backlight modules on the market cannot provide a constant equivalent brightness under the variable refresh rate.
- the disclosure provides a control chip configured to be coupled with a backlight driving chip and a display panel.
- the control chip includes a storage element and a processing circuit.
- the storage element is configured to store a predetermined vertical refresh rate of the display panel.
- the processing circuit is coupled with the storage element, and is configured to provide a switching signal to the backlight driving chip so that the backlight driving chip enables a backlight module according to the switching signal.
- a frequency of the switching signal is set according to the predetermined vertical refresh rate. If the processing circuit has not received a vertical refresh starting pulse for more than a predetermined frame time corresponding to the predetermined vertical refresh rate, the processing circuit increases the frequency of the switching signal.
- the disclosure provides a display device including a display panel, a backlight driving chip coupled with the backlight module, and a control chip coupled with the display panel and the backlight driving chip.
- the control chip includes a storage element and a processing circuit.
- the storage element is configured to store a predetermined vertical refresh rate of the display panel.
- the processing circuit is coupled with the storage element, and is configured to provide a switching signal to the backlight driving chip so that the backlight driving chip enables the backlight module according to the switching signal.
- a frequency of the switching signal is set according to the predetermined vertical refresh rate. If the processing circuit has not received a vertical refresh starting pulse for more than a predetermined frame time corresponding to the predetermined vertical refresh rate, the processing circuit increases the frequency of the switching signal.
- the disclosure provides a driving method suitable for a control chip configured to be coupled with a display panel and a backlight driving chip.
- the driving method includes the following operations: providing a switching signal to the backlight driving chip so that the backlight driving chip enables a backlight module according to the switching signal, and a frequency of the switching signal is set according to a predetermined vertical refresh rate of the display panel; determining whether a vertical refresh starting pulse has not been received for more than a predetermined frame time corresponding to the predetermined vertical refresh rate; and if the vertical refresh starting pulse has not been received for more than the predetermined frame time, increasing the frequency of the switching signal.
- FIG. 1 is a simplified functional block diagram of a display device according to one embodiment of the present disclosure.
- FIG. 2 is a waveform schematic diagram of a plurality of signals related to the display device of FIG. 1 according to one embodiment of the present disclosure.
- FIG. 3 is a flowchart of a driving method according to one embodiment of the present disclosure.
- FIG. 4 is a waveform schematic diagram of a plurality of signals related to the display device of FIG. 1 according to another embodiment of the present disclosure.
- FIG. 1 is a simplified functional block diagram of a display device 100 according to one embodiment of the present disclosure.
- FIG. 2 is a waveform schematic diagram of a plurality of signals related to the display device 100 according to one embodiment of the present disclosure.
- the display device 100 comprises a control chip 110 , a backlight driving chip 120 , a backlight module 130 , and a display panel 140 .
- the display device 100 supports variable refresh rate.
- Variable refresh rate means that the vertical refresh rate of displayed images may be non-constant.
- other functional blocks of the display device 100 are not shown in FIG. 1 .
- the control chip 110 is coupled with the backlight driving chip 120 and the display panel 140 , and comprises a processing circuit 112 , an interface circuit 114 , and a storage element 116 .
- the storage element 116 stores a predetermined vertical refresh rate (e.g., 120 Hz or 144 Hz) of the display panel 140 .
- the predetermined vertical refresh rate is the maximum vertical refresh rate that the display panel 140 supports.
- the interface circuit 114 is configured to receive a display signal Ds from an external device (e.g., an independent graphic card or a CPU, not shown in FIG. 1 ), and is configured to obtain a vertical sync signal Vsync and a data signal Da from the display signal Ds.
- the processing circuit 112 is coupled with the interface circuit 114 and the storage element 116 , and is configured to provide a pulse width modulation (PWM) control signal Pm and a switching signal Sw to the backlight driving chip 120 .
- PWM pulse width modulation
- the processing circuit 112 adjusts, according to the vertical sync signal Vsync and the predetermined vertical refresh rate of the display panel 140 , waveforms of the PWM control signal Pm and the switching signal Sw. Methods for adjusting those waveforms will be described in detail in the following paragraphs.
- the processing circuit 112 is further configured to optimize the data signal Da. For example, the processing circuit 112 may adjust the image resolution, the image aspect ratio, and other image parameters carried by the data signal Da.
- the display panel 140 comprises a display driver 142 and a pixel array 144 , and the display driver 142 is configured to drive, according to the optimized data signal Da′, the pixel array 144 to display images.
- the backlight driving chip 120 is coupled with the backlight module 130 , and is configured to provide a driving current Idr to enable the backlight module 130 .
- the backlight driving chip 120 determines, according to the switching signal Sw, whether to provide the driving current Idr.
- the backlight driving chip 120 further determines, according to a duty cycle of the PWM control signal Pm, the value of the driving current Idr.
- the duty cycle of the PWM control signal Pm is positively correlated to the value of the driving current Idr.
- duty cycle in this disclosure means that a ratio of the signal ON time (logical 1) to the signal period.
- the processing circuit 112 can be realized by general purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), other programmable logic circuits, or combinations thereof.
- the interface circuit 114 can be realized by any suitable receiver circuit supporting the signal format of DisplayPort, HDMI and/or DVI.
- the storage element 116 may be a non-volatile memory, such as the read-only memory (ROM), the flash memory, or other suitable type of memory, but this disclosure is not limited thereto.
- the display panel 140 can be realized by the liquid crystal display panel.
- the control chip 110 may be the scaler IC.
- FIG. 3 is a flowchart of a driving method 300 according to one embodiment of the present disclosure.
- the control chip 110 may execute the driving method 300 to adaptively determines, according to the vertical refresh rate currently being applied, the frequency that the backlight module 130 being switched on and off (herein after referred to as “switching frequency of the backlight module 130 ”).
- switching frequency of the backlight module 130 the frequency that the backlight module 130 being switched on and off.
- the processing circuit 112 receives a vertical refresh starting pulse Ptv of the vertical sync signal Vsync
- the processing circuit 112 provides the switching signal Sw to the backlight driving chip 120 .
- the frequency of the switching signal Sw is set according to the predetermined vertical refresh rate stored in the storage element 116 .
- the frequency of the switching signal Sw can be set to equal to the predetermined vertical refresh rate of the display panel 140 .
- the time length of the first stage S 1 of each frame i.e., one period of the switching signal Sw
- the first stage S 1 has 8.33 microseconds ( ⁇ s).
- the backlight driving chip 120 when the switching signal Sw has a logic high level (e.g., a high voltage), the backlight driving chip 120 outputs the driving current Idr to enable the backlight module 130 .
- the switching signal Sw when the switching signal Sw has a logic low level (e.g., a low voltage), the backlight driving chip 120 disables the backlight module 130 .
- the switching signal Sw may have a rather low duty cycle (e.g., 10%) to realize strobe backlight, but this disclosure is not limited thereto.
- the processing circuit 112 provides the PWM control signal Pm to the backlight driving chip 120 , thereby controlling the value of the driving current Idr by the duty cycle of the PWM control signal Pm.
- the processing circuit 112 determines the duty cycle of the PWM control signal Pm, according to a brightness parameter specified by an user by using an external input interface (not shown), to adjust the brightness of the backlight module 130 .
- the processing circuit 112 determines whether the processing circuit 112 has not received the vertical refresh starting pulse Ptv for more than a predetermined frame time corresponding to the predetermined vertical refresh rate. For example, if the predetermined vertical refresh rate is 120 Hz, the predetermined frame time is 8.33 ⁇ s. In other words, the processing circuit 112 in this embodiment determines whether has not received the vertical refresh starting pulse Ptv for more than the time length of the first stage S 1 . If the vertical refresh starting pulse Ptv has not been received in the predetermined frame time, the processing circuit 112 then conduct operation S 308 to adaptively adjust, in response to the decreased vertical refresh rate, the switching frequency of the backlight module 130 . On the contrary, the processing circuit 112 may repeatedly conduct operation S 302 .
- the processing circuit 112 increases the frequency of the switching signal Sw, and may keep the duty cycle of the switching signal Sw unchanged. Therefore, if a frame has a second stage S 2 which results from the decreased vertical refresh rate and follows the first stage S 1 , the user will feel substantially the same equivalent brightness in the first stage S 1 and the second stage S 2 , which is because the switching signal Sw has the same duty cycle (e.g., remaining in 10%) in both of the first stage S 1 and the second stage S 2 .
- the processing circuit 112 when the processing circuit 112 increases the frequency of the switching signal Sw, the processing circuit 112 may keep the duty cycle of the PWM control signal Pm unchanged.
- the processing circuit 112 determines whether the vertical refresh starting pulse Ptv is received after the frequency of the switching signal Sw is increased. If the vertical refresh starting pulse Ptv is received after the frequency of the switching signal Sw is increased, the processing circuit 112 then conducts operation S 312 . On the contrary, the processing circuit 112 may repeatedly conduct operation S 310 .
- the processing circuit 112 switches the frequency of the switching signal Sw back to according to the predetermined vertical refresh rate. For example, the processing circuit 112 can switch the frequency of the switching signal Sw back to equal to the predetermined vertical refresh rate. That is, the processing circuit 112 may interrupt the waveform that the switching signal Sw currently have and then configure the switching signal Sw to have a waveform the same as that of in the first stage S 1 . Then, the processing circuit 112 may conduct operation S 302 again.
- the storage element 116 stores a predetermined horizontal refresh rate of the display panel 140 .
- the predetermined horizontal refresh rate means that a predetermined refresh rate for a row of pixels in the display panel 140 .
- the predetermined horizontal refresh rate of the display panel 140 may be calculate by Formula 1. In this case, the frequency of the switching signal Sw is increased to a value smaller than or equal to the predetermined horizontal refresh rate of the display panel 140 .
- the switching signal Sw has higher frequency
- the last period of the switching signal Sw has less part going to be cut off.
- the user feels more constant equivalent brightness in the first stage S 1 and the second stage S 2 .
- the horizontal refresh rate of the display panel 140 is set to be constant, while the time length of a frame may be extended in units of the refresh time for one row (i.e., the reciprocal of the predetermined horizontal refresh rate). Therefore, in some embodiments, the time interval between two successive vertical refresh starting pulses Ptv (e.g., the first stage S 1 of the (N ⁇ 1)-th frame, or the first stage S 1 and the second stage S 2 of the N-th frame) is configured as an integer multiple of the reciprocal of the predetermined horizontal refresh rate.
- the frequency of the switching signal Sw is increased, in the second stage S 2 , to equal to the predetermined horizontal refresh rate, the time interval between two successive vertical refresh starting pulses Ptv will be an integer multiple of the period of the switching signal Sw, and thus the last period of the switching signal Sw, in the second stage S 2 , will not be cut off.
- FIG. 4 is a waveform schematic diagram of a plurality of signals related to the display device 100 according to another embodiment of the present disclosure.
- the processing circuit 112 switches the switching signal Sw from the rectangular waveform to substantially similar to the triangular waveform.
- the processing circuit 112 configures the switching signal Sw, in the second stage S 2 , to have step waveform that rises step by step and then falls step by step so that the waveform of the switching signal Sw is approximate to the triangular waveform.
- the triangular waveform can be generated by circuits with slower charge and discharge speeds, and thus the processing circuit 112 in this embodiment has lower design difficulty.
- an area ratio of the triangular part to a rectangular 410 is equal to the duty cycle of the triangular waveform.
- the rectangular 410 may have an area 10 times to that of the triangular part to achieve a 10% duty cycle.
- the switching signal Sw provided by the control chip 110 may be a voltage signal that the waveform thereof can be rapidly changed, while the duty cycle of the PWM control signal Pm may remain the same and the backlight driving chip 120 simply determines whether to output the driving current Idr. Therefore, when the control chip 110 executes the driving method 300 , the display device 100 avoids the problem that the PWM control signal Pm cannot rapidly changes the waveform thereof, and thus is capable of providing constant equivalent brightness under variable refresh rate.
Abstract
Description
- This application claims priority to Taiwan Patent Application Serial Number 109100102, filed on Jan. 2, 2020, which is herein incorporated by reference in its entirety.
- The present disclosure generally relates to a display device. More particularly, the present disclosure relates to a control chip capable of providing a constant brightness under variable refresh rate and related driving method.
- LCD monitors that support variable refresh rate (VRR) often use high-brightness but short-duration strobe backlight to solve the problem of motion blur, and further constantly turn on the backlight at low brightness level, when refresh period extends, to ensure that user feels constant equivalent brightness. However, the above method requires rapidly switching the duty cycle of analog dimming control signals of the backlight module. Based on capacitor charge and discharge characteristics of the circuit, those control signals are hardly to be immediately changed to target waveforms. Therefore, backlight modules on the market cannot provide a constant equivalent brightness under the variable refresh rate.
- The disclosure provides a control chip configured to be coupled with a backlight driving chip and a display panel. The control chip includes a storage element and a processing circuit. The storage element is configured to store a predetermined vertical refresh rate of the display panel. The processing circuit is coupled with the storage element, and is configured to provide a switching signal to the backlight driving chip so that the backlight driving chip enables a backlight module according to the switching signal. A frequency of the switching signal is set according to the predetermined vertical refresh rate. If the processing circuit has not received a vertical refresh starting pulse for more than a predetermined frame time corresponding to the predetermined vertical refresh rate, the processing circuit increases the frequency of the switching signal.
- The disclosure provides a display device including a display panel, a backlight driving chip coupled with the backlight module, and a control chip coupled with the display panel and the backlight driving chip. The control chip includes a storage element and a processing circuit. The storage element is configured to store a predetermined vertical refresh rate of the display panel. The processing circuit is coupled with the storage element, and is configured to provide a switching signal to the backlight driving chip so that the backlight driving chip enables the backlight module according to the switching signal. A frequency of the switching signal is set according to the predetermined vertical refresh rate. If the processing circuit has not received a vertical refresh starting pulse for more than a predetermined frame time corresponding to the predetermined vertical refresh rate, the processing circuit increases the frequency of the switching signal.
- The disclosure provides a driving method suitable for a control chip configured to be coupled with a display panel and a backlight driving chip. The driving method includes the following operations: providing a switching signal to the backlight driving chip so that the backlight driving chip enables a backlight module according to the switching signal, and a frequency of the switching signal is set according to a predetermined vertical refresh rate of the display panel; determining whether a vertical refresh starting pulse has not been received for more than a predetermined frame time corresponding to the predetermined vertical refresh rate; and if the vertical refresh starting pulse has not been received for more than the predetermined frame time, increasing the frequency of the switching signal.
- It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the disclosure as claimed.
-
FIG. 1 is a simplified functional block diagram of a display device according to one embodiment of the present disclosure. -
FIG. 2 is a waveform schematic diagram of a plurality of signals related to the display device ofFIG. 1 according to one embodiment of the present disclosure. -
FIG. 3 is a flowchart of a driving method according to one embodiment of the present disclosure. -
FIG. 4 is a waveform schematic diagram of a plurality of signals related to the display device ofFIG. 1 according to another embodiment of the present disclosure. - Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
-
FIG. 1 is a simplified functional block diagram of adisplay device 100 according to one embodiment of the present disclosure.FIG. 2 is a waveform schematic diagram of a plurality of signals related to thedisplay device 100 according to one embodiment of the present disclosure. Referring toFIGS. 1-2 , thedisplay device 100 comprises acontrol chip 110, abacklight driving chip 120, abacklight module 130, and adisplay panel 140. In this embodiment, thedisplay device 100 supports variable refresh rate. Variable refresh rate means that the vertical refresh rate of displayed images may be non-constant. For the sake of brevity, other functional blocks of thedisplay device 100 are not shown inFIG. 1 . - The
control chip 110 is coupled with thebacklight driving chip 120 and thedisplay panel 140, and comprises aprocessing circuit 112, aninterface circuit 114, and astorage element 116. Thestorage element 116 stores a predetermined vertical refresh rate (e.g., 120 Hz or 144 Hz) of thedisplay panel 140. In some embodiments, the predetermined vertical refresh rate is the maximum vertical refresh rate that thedisplay panel 140 supports. Theinterface circuit 114 is configured to receive a display signal Ds from an external device (e.g., an independent graphic card or a CPU, not shown inFIG. 1 ), and is configured to obtain a vertical sync signal Vsync and a data signal Da from the display signal Ds. Theprocessing circuit 112 is coupled with theinterface circuit 114 and thestorage element 116, and is configured to provide a pulse width modulation (PWM) control signal Pm and a switching signal Sw to thebacklight driving chip 120. Theprocessing circuit 112 adjusts, according to the vertical sync signal Vsync and the predetermined vertical refresh rate of thedisplay panel 140, waveforms of the PWM control signal Pm and the switching signal Sw. Methods for adjusting those waveforms will be described in detail in the following paragraphs. - The
processing circuit 112 is further configured to optimize the data signal Da. For example, theprocessing circuit 112 may adjust the image resolution, the image aspect ratio, and other image parameters carried by the data signal Da. Thedisplay panel 140 comprises adisplay driver 142 and apixel array 144, and thedisplay driver 142 is configured to drive, according to the optimized data signal Da′, thepixel array 144 to display images. - The
backlight driving chip 120 is coupled with thebacklight module 130, and is configured to provide a driving current Idr to enable thebacklight module 130. Thebacklight driving chip 120 determines, according to the switching signal Sw, whether to provide the driving current Idr. Thebacklight driving chip 120 further determines, according to a duty cycle of the PWM control signal Pm, the value of the driving current Idr. In one embodiment, the duty cycle of the PWM control signal Pm is positively correlated to the value of the driving current Idr. The term duty cycle in this disclosure means that a ratio of the signal ON time (logical 1) to the signal period. - In practice, the
processing circuit 112 can be realized by general purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), other programmable logic circuits, or combinations thereof. Theinterface circuit 114 can be realized by any suitable receiver circuit supporting the signal format of DisplayPort, HDMI and/or DVI. Thestorage element 116 may be a non-volatile memory, such as the read-only memory (ROM), the flash memory, or other suitable type of memory, but this disclosure is not limited thereto. Thedisplay panel 140 can be realized by the liquid crystal display panel. In some embodiments, thecontrol chip 110 may be the scaler IC. -
FIG. 3 is a flowchart of adriving method 300 according to one embodiment of the present disclosure. Thecontrol chip 110 may execute thedriving method 300 to adaptively determines, according to the vertical refresh rate currently being applied, the frequency that thebacklight module 130 being switched on and off (herein after referred to as “switching frequency of thebacklight module 130”). Referring toFIGS. 1 and 3 , in operation S302, when theprocessing circuit 112 receives a vertical refresh starting pulse Ptv of the vertical sync signal Vsync, theprocessing circuit 112 provides the switching signal Sw to thebacklight driving chip 120. In this situation, the frequency of the switching signal Sw is set according to the predetermined vertical refresh rate stored in thestorage element 116. For example, the frequency of the switching signal Sw can be set to equal to the predetermined vertical refresh rate of thedisplay panel 140. In other words, the time length of the first stage S1 of each frame (i.e., one period of the switching signal Sw) is equal to the reciprocal of the predetermined vertical refresh rate. For example, if the predetermined vertical refresh rate is 120 Hz, the first stage S1 has 8.33 microseconds (ρs). - As shown in
FIG. 2 , when the switching signal Sw has a logic high level (e.g., a high voltage), thebacklight driving chip 120 outputs the driving current Idr to enable thebacklight module 130. On the contrary, when the switching signal Sw has a logic low level (e.g., a low voltage), thebacklight driving chip 120 disables thebacklight module 130. In this embodiment, the switching signal Sw may have a rather low duty cycle (e.g., 10%) to realize strobe backlight, but this disclosure is not limited thereto. - In operation S304, the
processing circuit 112 provides the PWM control signal Pm to thebacklight driving chip 120, thereby controlling the value of the driving current Idr by the duty cycle of the PWM control signal Pm. In some embodiments, theprocessing circuit 112 determines the duty cycle of the PWM control signal Pm, according to a brightness parameter specified by an user by using an external input interface (not shown), to adjust the brightness of thebacklight module 130. - In operation S306, the
processing circuit 112 determines whether theprocessing circuit 112 has not received the vertical refresh starting pulse Ptv for more than a predetermined frame time corresponding to the predetermined vertical refresh rate. For example, if the predetermined vertical refresh rate is 120 Hz, the predetermined frame time is 8.33 μs. In other words, theprocessing circuit 112 in this embodiment determines whether has not received the vertical refresh starting pulse Ptv for more than the time length of the first stage S1. If the vertical refresh starting pulse Ptv has not been received in the predetermined frame time, theprocessing circuit 112 then conduct operation S308 to adaptively adjust, in response to the decreased vertical refresh rate, the switching frequency of thebacklight module 130. On the contrary, theprocessing circuit 112 may repeatedly conduct operation S302. - In operation S308, the
processing circuit 112 increases the frequency of the switching signal Sw, and may keep the duty cycle of the switching signal Sw unchanged. Therefore, if a frame has a second stage S2 which results from the decreased vertical refresh rate and follows the first stage S1, the user will feel substantially the same equivalent brightness in the first stage S1 and the second stage S2, which is because the switching signal Sw has the same duty cycle (e.g., remaining in 10%) in both of the first stage S1 and the second stage S2. - In some embodiments, when the
processing circuit 112 increases the frequency of the switching signal Sw, theprocessing circuit 112 may keep the duty cycle of the PWM control signal Pm unchanged. - In operation S310, the
processing circuit 112 determines whether the vertical refresh starting pulse Ptv is received after the frequency of the switching signal Sw is increased. If the vertical refresh starting pulse Ptv is received after the frequency of the switching signal Sw is increased, theprocessing circuit 112 then conducts operation S312. On the contrary, theprocessing circuit 112 may repeatedly conduct operation S310. - In operation S312, the
processing circuit 112 switches the frequency of the switching signal Sw back to according to the predetermined vertical refresh rate. For example, theprocessing circuit 112 can switch the frequency of the switching signal Sw back to equal to the predetermined vertical refresh rate. That is, theprocessing circuit 112 may interrupt the waveform that the switching signal Sw currently have and then configure the switching signal Sw to have a waveform the same as that of in the first stage S1. Then, theprocessing circuit 112 may conduct operation S302 again. - In some embodiments, the
storage element 116 stores a predetermined horizontal refresh rate of thedisplay panel 140. The predetermined horizontal refresh rate means that a predetermined refresh rate for a row of pixels in thedisplay panel 140. For example, if thedisplay panel 140 has a resolution of 2000×1144 (a resolution of 1920×1080 for the active area) and the predetermined vertical refresh rate of 120 Hz, the predetermined horizontal refresh rate of thedisplay panel 140 may be calculate byFormula 1. In this case, the frequency of the switching signal Sw is increased to a value smaller than or equal to the predetermined horizontal refresh rate of thedisplay panel 140. -
Predetermined horizontal refresh rate=120×1144 Hz (Formula 1) - In the second stage S2, when the switching signal Sw has higher frequency, the last period of the switching signal Sw has less part going to be cut off. As a result, the user feels more constant equivalent brightness in the first stage S1 and the second stage S2.
- In practice, to achieve variable vertical refresh rate, the horizontal refresh rate of the
display panel 140 is set to be constant, while the time length of a frame may be extended in units of the refresh time for one row (i.e., the reciprocal of the predetermined horizontal refresh rate). Therefore, in some embodiments, the time interval between two successive vertical refresh starting pulses Ptv (e.g., the first stage S1 of the (N−1)-th frame, or the first stage S1 and the second stage S2 of the N-th frame) is configured as an integer multiple of the reciprocal of the predetermined horizontal refresh rate. As a result, if the frequency of the switching signal Sw is increased, in the second stage S2, to equal to the predetermined horizontal refresh rate, the time interval between two successive vertical refresh starting pulses Ptv will be an integer multiple of the period of the switching signal Sw, and thus the last period of the switching signal Sw, in the second stage S2, will not be cut off. -
FIG. 4 is a waveform schematic diagram of a plurality of signals related to thedisplay device 100 according to another embodiment of the present disclosure. In this embodiment, when thecontrol chip 110 conducts operation S308, theprocessing circuit 112 switches the switching signal Sw from the rectangular waveform to substantially similar to the triangular waveform. In specific, theprocessing circuit 112 configures the switching signal Sw, in the second stage S2, to have step waveform that rises step by step and then falls step by step so that the waveform of the switching signal Sw is approximate to the triangular waveform. In contrast with the rectangular waveform, the triangular waveform can be generated by circuits with slower charge and discharge speeds, and thus theprocessing circuit 112 in this embodiment has lower design difficulty. In addition, in the aforesaid embodiments that use triangular waveform to achieve equivalent average brightness, an area ratio of the triangular part to a rectangular 410, formed by the period of the triangular waveform, is equal to the duty cycle of the triangular waveform. For example, the rectangular 410 may have an area 10 times to that of the triangular part to achieve a 10% duty cycle. - As can be appreciated from the foregoing descriptions, the switching signal Sw provided by the
control chip 110 may be a voltage signal that the waveform thereof can be rapidly changed, while the duty cycle of the PWM control signal Pm may remain the same and thebacklight driving chip 120 simply determines whether to output the driving current Idr. Therefore, when thecontrol chip 110 executes thedriving method 300, thedisplay device 100 avoids the problem that the PWM control signal Pm cannot rapidly changes the waveform thereof, and thus is capable of providing constant equivalent brightness under variable refresh rate. - Certain terms are used throughout the description and the claims to refer to particular components. One skilled in the art appreciates that a component may be referred to as different names. This disclosure does not intend to distinguish between components that differ in name but not in function. In the description and in the claims, the term “comprise” is used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to.” The term “couple” is intended to compass any indirect or direct connection. Accordingly, if this disclosure mentioned that a first device is coupled with a second device, it means that the first device may be directly or indirectly connected to the second device through electrical connections, wireless communications, optical communications, or other signal connections with/without other intermediate devices or connection means.
- The term “and/or” may comprise any and all combinations of one or more of the associated listed items. In addition, the singular forms “a,” “an,” and “the” herein are intended to comprise the plural forms as well, unless the context clearly indicates otherwise.
- Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW109100102A TWI727593B (en) | 2020-01-02 | 2020-01-02 | Control chip for use in variable refresh rate and related driving method |
TW109100102 | 2020-01-02 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20210210037A1 true US20210210037A1 (en) | 2021-07-08 |
US11335288B2 US11335288B2 (en) | 2022-05-17 |
Family
ID=76655594
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/136,210 Active 2041-01-14 US11335288B2 (en) | 2020-01-02 | 2020-12-29 | Control chip for use in variable refresh rate and related display device and driving method |
Country Status (2)
Country | Link |
---|---|
US (1) | US11335288B2 (en) |
TW (1) | TWI727593B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115083357A (en) * | 2022-06-14 | 2022-09-20 | 惠科股份有限公司 | Backlight module brightness refreshing method and display device |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI744089B (en) | 2020-11-11 | 2021-10-21 | 瑞昱半導體股份有限公司 | Display backlight control method |
TWI768828B (en) | 2021-04-14 | 2022-06-21 | 瑞昱半導體股份有限公司 | Display device and displaying method |
TWI789005B (en) | 2021-09-10 | 2023-01-01 | 瑞昱半導體股份有限公司 | Display control circuit and backlight control method thereof having dynamic backlight adjusting mechanism |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7692642B2 (en) * | 2004-12-30 | 2010-04-06 | Intel Corporation | Method and apparatus for controlling display refresh |
KR101253271B1 (en) * | 2006-08-03 | 2013-04-10 | 삼성디스플레이 주식회사 | Display device and display device testing system and method for testing display device using the same |
KR101501481B1 (en) * | 2008-12-24 | 2015-03-30 | 삼성디스플레이 주식회사 | Display apparatus, backlight unit and driving method of the display apparatus |
JP5081208B2 (en) * | 2009-08-07 | 2012-11-28 | シャープ株式会社 | Liquid crystal display |
KR101325314B1 (en) * | 2009-12-11 | 2013-11-08 | 엘지디스플레이 주식회사 | Liquid crystal display |
EP2943948B1 (en) * | 2013-01-14 | 2020-07-29 | Apple Inc. | Low power display device with variable refresh rate |
US9773460B2 (en) * | 2013-10-18 | 2017-09-26 | Nvidia Corporation | System, method, and computer program product for combining low motion blur and variable refresh rate in a display |
KR102583828B1 (en) * | 2018-09-19 | 2023-10-04 | 삼성디스플레이 주식회사 | Liquid crystal display apparatus and method of driving the same |
KR102545078B1 (en) * | 2018-10-01 | 2023-06-19 | 삼성전자주식회사 | Display apparatus, method for controlling thereof and system |
CN109920040B (en) * | 2019-03-01 | 2023-10-27 | 京东方科技集团股份有限公司 | Display scene processing method and device and storage medium |
-
2020
- 2020-01-02 TW TW109100102A patent/TWI727593B/en active
- 2020-12-29 US US17/136,210 patent/US11335288B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115083357A (en) * | 2022-06-14 | 2022-09-20 | 惠科股份有限公司 | Backlight module brightness refreshing method and display device |
Also Published As
Publication number | Publication date |
---|---|
TW202127430A (en) | 2021-07-16 |
US11335288B2 (en) | 2022-05-17 |
TWI727593B (en) | 2021-05-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11335288B2 (en) | Control chip for use in variable refresh rate and related display device and driving method | |
US8384652B2 (en) | Liquid crystal display | |
CN110114818B (en) | Display driving method, driving device and display device | |
EP1376528B1 (en) | Image display and displaying method | |
US20200051484A1 (en) | Backlight device and display device provided with same | |
WO1998027538A1 (en) | Display system with modulation of an electrode voltage to alter state of the electro-optic layer | |
US11043171B2 (en) | Anti-flicker and motion-blur improvement method and display device thereof | |
US11501704B2 (en) | Method for sending driving data of backlight source, control circuit and display device | |
US10770023B2 (en) | Dynamic overdrive for liquid crystal displays | |
US11289045B2 (en) | Display rescan | |
US20080198181A1 (en) | Video display method and apparatus | |
EP3438961B1 (en) | Image display method and display system capable of avoiding an image flickering effect | |
CN110930952A (en) | Liquid crystal display device | |
US20140191936A1 (en) | Driving Module and Driving Method | |
CN112735313B (en) | Display panel and electronic device | |
US11705077B2 (en) | Control method and control device | |
CN111341278A (en) | Overdrive processing method and overdrive device for image data | |
US11380271B2 (en) | Backlight driving method, display driving method, drive device and display device | |
JP2008533519A (en) | Backlit LCD display device and driving method thereof | |
CN112908242B (en) | Driving method and driving device of display panel and display device | |
CN113096609B (en) | Control chip applied to dynamic update rate and related driving method | |
US20130257706A1 (en) | Backlight driving circuit and method | |
JP2011075800A (en) | Liquid crystal display device | |
WO1998027537A1 (en) | Display system which applies reference voltage to pixel electrodes before display of new image | |
JP2008051912A (en) | Liquid crystal display |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: REALTEK SEMICONDUCTOR CORPORATION, TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHEN, LI-ANG;REEL/FRAME:054762/0652 Effective date: 20201223 |
|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |