US20210194479A1 - Power-on reset circuit - Google Patents
Power-on reset circuit Download PDFInfo
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- US20210194479A1 US20210194479A1 US17/194,474 US202117194474A US2021194479A1 US 20210194479 A1 US20210194479 A1 US 20210194479A1 US 202117194474 A US202117194474 A US 202117194474A US 2021194479 A1 US2021194479 A1 US 2021194479A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/30—Modifications for providing a predetermined threshold before switching
Definitions
- a power-on reset (POR) circuit causes a logic circuit to remain in a reset state following a power cycle until the power supply voltage has increased to a safe operating voltage, A logic circuit attempting to operate from a supply voltage below its pre-designated safe operating voltage may cause the logic circuit to operate in an unpredictable manner.
- an integrated circuit includes a power-on reset (POR) circuit and a digital logic circuit.
- the POR has first and second control outputs.
- the POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage terminal exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage.
- the digital logic circuit has a first control input coupled to the first control output of the POR circuit and has a second control input coupled to the second control output of the POR circuit.
- the digital logic circuit is configured to initiate a first read transaction responsive to assertion of the first control signal and to initiate a second read transaction responsive to assertion of the second control signal.
- FIG. 1 illustrates an example of at least a portion of an integrated circuit including a power-on reset (POR) circuit coupled to a digital logic circuit with the digital logic circuit coupled to non-volatile memory.
- POR power-on reset
- FIG. 2 shows an example implementation of the POR circuit.
- FIG. 3 illustrates various voltages monitored by the POR circuit.
- FIG. 4 illustrates the voltages of FIG. 3 for the case in which the POR circuit releases the digital logic circuit from its reset state when VDD is below a minimum supply voltage for the non-volatile memory.
- FIG. 5 includes a timing diagram illustrating the operation of the POR circuit and the digital logic circuit for the case depicted in FIG. 4 .
- FIG. 6 illustrates the voltages of FIG. 3 for the case in which the POR circuit releases the digital logic circuit from its reset state when VDD is above the minimum supply voltage for the non-volatile memory.
- FIG. 7 includes a timing diagram illustrating the operation of the POR circuit and the digital logic circuit for the case depicted in FIG. 6 .
- FIG. 8 includes a timing diagram illustrating the operation of the POR circuit and the digital logic circuit during a fluctuation of the supply voltage.
- FIG. 9 shows an example implementation of the digital logic circuit of FIG. 1 .
- FIG. 1 shows an example of at least a portion of an integrated circuit (IC) 99 .
- IC 99 includes a power-on reset (POR) circuit 100 , a digital logic circuit 110 , and a non-volatile memory (NVM) 120 .
- the POR circuit 100 , digital logic circuit 110 , and NVM 120 are coupled to a supply voltage node (also referred to herein as a “terminal”) 101 (VDD) and to a common node 103 (VSS).
- the POR circuit 100 produces control signals RESETZ and RELOADZ, which are provided as inputs to the digital logic circuit 110 .
- the NVM 120 is coupled to the digital logic circuit 110 .
- the NVM 120 includes trim storage 122 in which one or more trim values can be stored.
- the trim values are retrieved by digital logic circuit 110 upon a power-on event and are used to configure the IC 99 (e.g., adjust a value of resistance, a value of capacitance, etc.).
- the signals between the digital logic circuit 110 and the NVM 120 include an NVM enable signal (NVM_EN), an address bus (ADDR), control bits (CTRL BITS), a data out bus (DATA OUT), and a data in bus (DATA IN).
- the digital logic circuit 110 can issue a read command (encoded in CTRL BITS) to the NVM 120 to trim data at an address specified by ADDR in order to read, for example, trim data stored in NVM 120 .
- the read data is returned by NVM 120 to the digital logic circuit 110 over DATA IN.
- the NVM 120 is maintained in a disabled state until NVM_EN is asserted (e.g., high).
- the VDD supply voltage increases from 0 V to its final steady-state level.
- the digital logic circuit 110 is not guaranteed to operate correctly until VDD reaches a minimum level consistent with operation of the digital logic circuit 110 (referred to herein as the “minimum digital logic circuit voltage”).
- the NVM 120 is not guaranteed to operate correctly until VDD reaches a minimum level consistent with operation of the NVM 120 (referred to herein as the “minimum NVM read voltage”).
- the minimum NVM read voltage may be different than the minimum digital logic circuit voltage. In the example described below, the minimum NVM read voltage is greater than the minimum digital logic circuit voltage.
- the IC 99 is rated to operate from a steady-state supply voltage between 1.55 V and 1.65 V, the minimum digital logic circuit voltage is 0.98 V, and the minimum NVM read voltage is 1.35 V. That is, in this example VDD needs to be at least 0.98 V for the digital logic circuit 110 to operate as intended and at least 1.35 V for the NVM 120 to accurately respond to read commands from the digital logic circuit 110 .
- the POR circuit 100 monitors the level of VDD as VDD ramps up from 0 V to its final steady-state level.
- VDD exceeds the minimum digital circuit voltage (e.g., 0.98 V in one example)
- the POR circuit 100 asserts RESETZ
- VDD exceeds the minimum NVM read voltage
- RELOADZ asserts RELOADZ.
- RESETZ and RELOADZ are initially logic low (e.g., 0 V) and assertion of those signals means that the signals are asserted to a logic high state.
- the digital logic circuit 110 is maintained in a reset state (idle) until RESETZ is forced high by the POR circuit 100 at which time digital logic circuit 110 is released from its reset state to begin operation.
- NVM_EN is asserted (e.g., high) approximately when RESETZ transitions from low to high.
- the digital logic circuit 110 then initiates a read transaction to the NVM 120 .
- the POR circuit 100 controls the assertion (low to high transition) of RELOADZ in a manner to ensure that VDD is above the minimum NVM read voltage for NVM 120 .
- FIG. 1 pertains to different levels of minimum required supply voltages for the digital logic circuit 110 and NVM 120 in IC 99 .
- the principles described herein pertain to power-on reset control of two or more circuits that have different minimum operating voltage ratings. That is, the scope of this disclosure is not limited to specifically NVMs and their use to trim an IC.
- the POR circuit 100 described herein is a relatively low area, low complexity circuit which is usable for handling small differences between the minimum IC supply voltage and the minimum supply voltage requirement of the various circuits within the IC (e.g., 0.98 V for the digital logic circuit 110 and 1.35 V for the NVM 120 ).
- FIG. 2 shows an example implementation of POR circuit 100 .
- POR circuit 100 includes a voltage divider 201 , a reference voltage generator 202 , and comparators 210 and 220 .
- the voltage divider 201 in this example is a resistor divider comprising resistors R 1 , R 2 , and R 3 .
- R 1 -R 3 are coupled in series between the supply voltage node 101 and the common node 103 . More than three resistors can be coupled in series between nodes 101 and 103 in other implementations.
- the node between R 1 and R 2 is labeled N 1 and the node between R 2 and R 3 is labeled N 2 .
- the voltage on N 1 (VN 1 ) is a fraction of the difference between VDD and VSS, specifically,
- VN ⁇ ⁇ 1 ( VDD - VSS ) * ( R ⁇ ⁇ 2 + R ⁇ ⁇ 3 ) R ⁇ ⁇ 1 + R ⁇ ⁇ 2 + R ⁇ ⁇ 3
- the voltage on N 2 (VN 2 ) also is a fraction of the difference between VDD and VSS,
- VN ⁇ ⁇ 2 ( VDD - VSS ) * ( R ⁇ ⁇ 3 ) R ⁇ ⁇ 1 + R ⁇ ⁇ 2 + R ⁇ ⁇ 3
- VN 1 is greater than VN 2 .
- Comparator 210 has a non-inverting (+) input and an inverting input ( ⁇ ).
- N 1 is coupled to the non-inverting input of comparator 210 .
- comparator 220 has a non-inverting input and an inverting input.
- N 2 is coupled to the non-inverting input of comparator 220 .
- the reference voltage generator 202 generates a reference voltage labeled VBG.
- the reference voltage generator 202 may comprise a bandgap voltage generator or any other suitable type of reference voltage generator. As a bandgap voltage generator, reference voltage generator 202 generates the output reference voltage VBG which is a fixed voltage that is generally not influenced by changes in temperature or VDD. VBG is coupled to the inverting inputs of both comparators 210 and 220 . The output of comparator 210 generates the control signal RESETZ and the output of comparator 220 generates the control signal RELOADZ.
- VN 1 less than VBG
- RESETZ With VN 1 less than VBG, RESETZ will be low.
- VN 2 With VN 2 less than VBG, RELOADZ will also be low.
- VDD will be low enough that both VN 1 and VN 2 will be less than VBG and both RESETZ and RELOADZ will be low.
- VDD eventually becomes high enough that VN 1 exceeds VBG.
- the comparator 210 forces RESETZ high.
- VDD continues to increase, eventually VN 2 also exceeds VBG thereby causing comparator 220 to force RELOADZ high.
- RELOADZ transitions from low to high after RESETZ transitions from low to high.
- FIG. 3 illustrates various voltages for the IC 99 of FIG. 1 .
- the minimum digital logic circuit voltage is illustrated at 310 .
- the minimum NVM read voltage is illustrated at 312
- the maximum supply voltage is illustrated at 314 .
- the maximum supply voltage is the maximum power supply voltage rating for the IC 99 .
- the voltage values in parentheses are example voltages and were mentioned above.
- the example voltage for the minimum digital logic circuit voltage 310 is 0.98 V.
- the example voltage for the minimum NVM read voltage 312 is 1.35 V.
- the example voltage for the maximum supply voltage 314 is 1.65 V.
- the IC 99 is rated to operate from a supply voltage VDD in the range shown at 315 , that is between voltage levels 324 and 314 .
- VDD supply voltage
- the trip point of comparator 210 for RESETZ is within the range illustrated as 311 between a lower level 316 and an upper level 318 . That is, the range of trip points for comparator 210 across a large sample of ICs 99 is between voltage levels 316 and 318 .
- the trip point of comparator 220 for RELOADZ is within the range illustrated as 313 between a lower level 320 and an upper level 322 . That is, the range of trip points for comparator 220 across a large sample of ICs 99 is between voltage levels 320 and 322 .
- comparators 210 and 220 are coupled to the same reference voltage generator 202 and because the comparators 210 , 220 are coupled to the same voltage divider 201 , the trip-point error in both RESETZ and RELOADZ will be correlated. That is, if RESETZ trips at a lower voltage of VDD, then RELOADZ will also trip at a lower voltage, and vice versa.
- the range 311 of VDD for the trip-point of comparator 210 to transition RESETZ from low to high, due to process variations means that, due to the process variations, some comparators 210 (in some instances of ICs 99 ) will trip when VDD exceeds a particular voltage that is below the minimum NVM read voltage 312 , while comparators 210 for other instances of IC 99 will trip when VDD exceeds a particular voltage that is above the minimum NVM read voltage 312 .
- FIG. 4 illustrates an example of a trip-point for comparator 210 for a given IC 99 being below the minimum NVM read voltage 312 as illustrated at 405 .
- NVM EN is asserted (low to high) by POR circuit 100 approximately when RESETZ is asserted, and thus when VDD is below the minimum NVM read voltage 312 .
- a read of NVM 120 will occur but the return data (e.g., trim values) are not guaranteed to be valid because VDD was too low (i.e., below the minimum NVM read voltage).
- a trip-point for comparator 210 being in a lower range 405 of range 311 also means that the trip-point for comparator 220 (RELOADZ) will also be in a corresponding lower range 407 of range 313 . That the RESETZ's and RELOADZ's trip-points are correlated in this way means that RELOADZ will trip after RESETZ trips and RELOADZ will transition from low to high when VDD is above the minimum NVM read voltage 312 but below the minimum valid IC supply voltage 324 .
- RESETZ trip-point range 405 and RELOADZ trip-point range 407 ensures that whenever RESETZ transitions from low to high, RESETZ will be below the minimum NVM read voltage 312 and it will be followed by a RELOADZ low to high transition before the IC supply voltage reaches its stable value.
- the POR circuit 100 asserting RELOADZ (which will occur when VDD is above the minimum NVM read voltage 312 ) also causes digital logic circuit 110 to again assert NVM EN to again initiate a read of NVM 120 . This time, the read of NVM 120 will occur when VDD is above the minimum NVM read voltage 312 and the return NVM read data will be valid.
- FIG. 5 shows a timing diagram illustrating the operation described above.
- VDD is shown starting at an initial (e.g., 0 V) voltage level at 501 .
- a power-on event begins at 502 at which time VDD begins to increase as shown toward its final steady-state level at 550 .
- VDD reaches the trip-point for comparator 210 which is above the minimum digital logic circuit voltage (but still below the minimum NVM read voltage) and the POR circuit 100 responds by asserting RESETZ at 512 .
- RESETZ transitions form low to high.
- the digital logic circuit 110 also asserts NVM EN at 514 . With NVM EN now being high, digital logic circuit 110 performs a read of NVM 120 at 530 .
- NVM EN becomes low again at 516 towards the end of the read transaction.
- the NVM EN signal is brought back to 0 (NVM disable state) once the NVM operation is completed in order to reduce power consumption by keeping the NVM disabled until such time when an NVM operation is needed.
- VDD As VDD continues to increase, VDD eventually reaches the trip-point for comparator 220 at 515 and RELOADZ is forced high as shown at 518 .
- the digital logic circuit 110 responds to assertion of RELOADZ by again forcing NVM EN high ( 520 ) and initiating a second read of NVM 120 at 540 . During this second read of NVM 120 , however, VDD is above the minimum NVM read voltage and the read returns valid data from NVM 120 to the digital logic circuit 110 .
- FIG. 6 illustrates an example of a trip-point for comparator 210 for a given IC 99 for VDD being above the minimum NVM read voltage 312 as illustrated at 505 , which is the upper portion of range 311 .
- the trip-point for comparator 220 occurs with VDD being in the upper portion 507 of range 313 due to the trip-points for comparators 210 and 220 being correlated as described above. This would mean that RELOADZ transitioning from low to high may or may not happen because a portion of RELOADZ trip-point range 507 is above the minimum valid IC supply voltage ( 324 ).
- FIG. 7 includes the timing diagram associated with FIG. 6 for the case in which a RELOADZ low to high transition is also present.
- VDD increases to the trip-point of comparator 210 at 710 thereby causing POR circuit 100 to transition RESETZ from low to high at 712 .
- the rising edge of RESETZ at 712 causes the digital logic circuit 110 to assert NVM EN at 714 and initiate a read of NVM 120 at 730 . Because VDD is above the minimum NVM read voltage during the read at 730 , the return data from the NVM 120 to the digital logic circuit is considered valid.
- FIGS. 4-7 illustrate that a first read of NVM 120 is performed upon the digital logic circuit 110 being released from its reset state, and then a second read of NVM is performed when RELOADZ is asserted high.
- the first read may or may not return valid data from NVM 120 (it depends on whether VDD is below or above the minimum NVM read voltage during the first read), but in case the first read is invalid, a second, RELOADZ-based valid read is assured.
- the use of the comparators 210 and 220 with their trip-points being correlated due to the use of the same reference voltage circuit 202 ensures that valid read data is returned from NVM 120 using a POR circuit 100 that is of relatively low area and low complexity.
- the POR circuit 100 facilitates a relatively small difference (e.g., 200 mV or less) between minimum valid IC supply voltage and minimum valid voltage for the functional blocks (e.g. digital logic circuit 110 and NVM 120 ) within the IC.
- FIG. 8 illustrates the operation of POR circuit 100 and the digital logic circuit 110 during a fluctuation in the voltage level of VDD within the valid IC supply voltage range 315 after the initial power-on event.
- VDD reaches the trip-point 810 corresponding to comparator 210 , which causes RESETZ to be asserted high at 812 .
- NVM EN is also asserted at 814 and a first read of NVM 120 is performed by the digital logic circuit 110 at 817 .
- Reference numeral illustrates 823 illustrates a subsequent fluctuation in VDD after the power-on event.
- VDD may dip below the trip-point of comparator 220 (as illustrated at 831 ).
- VDD may then increase and again reach the trip-point at 825 corresponding to comparator 220 .
- Comparator 220 responds by again asserting RELOADZ high at 828 .
- Digital logic circuit 110 precludes NVM EN from again being asserted high (as otherwise would have occurred at 830 ) and thus precludes another read of NVM 120 from being performed.
- FIG. 9 shows an example implementation of digital logic circuit 110 .
- the digital logic circuit 110 in this example is implemented as a combination of a wake-up state machine 910 and a reload state machine 920 .
- Each state machine can be implemented as a combination of logic gates (AND gates, OR gates, inverters, etc.), flip-flops, and/or other circuit components.
- the detailed circuit implementation of state machines 910 and 920 can be synthesized using a suitable circuit synthetization tool based on the functionality of the digital logic circuit 110 described herein.
- wake-up state machine 910 has three operational states 911 , 912 , and 913 .
- State 911 is the Idle state and the wake-up state machine 910 begins operation in the Idle state 911 upon RESETZ being asserted high.
- a flag, READ DONE is stored in, for example, a flip-flop (not shown) and maintained by the wake-up state machine 910 .
- the function of the READ DONE flag is to indicate when the NVM read operation post RESETZ low to high transition has happened.
- the reset (when RESETZ is low) value of the READ DONE flag is 0 indicating that the read operation post assertion of RESETZ has not yet been performed.
- State machine 910 checks the value of READ DONE and given it is 0, the state machine transitions from state 911 to state 912 .
- the wake-up state machine 910 sets NVM EN to a value of 1 (high) and performs a read of NVM 120 .
- the state machine 910 transitions from state 912 to state 913 in which the state machine 910 sets NVM EN to 0 and sets the flag READ DONE to 1.
- a state transition then occurs back to the Idle state 911 and state-machine 910 remains in state 911 as long as READ DONE equals 1.
- the reload state machine 920 has the four states 921 - 924 shown in the example of FIG. 9 .
- State 921 is the Idle state and the reload state machine 920 begins operation in the Idle state 921 when RESETZ is asserted high.
- a flag RELOAD DONE is stored in a flip-flop (not shown) and maintained by the reload state machine 920 .
- the function of RELOAD DONE is to indicate if an NVM read operation following the first low to high transition of RELOADZ has happened or not.
- the reset (when RESETZ is low) value of RELOAD DONE flag is 0 indicating that NVM read following the first RELOADZ low to high transition has not happened yet.
- RESETZ transitions from low to high the state machine 920 starts in state 921 with RELOAD DONE flag set to a value of 0. The state machine waits in state 921 until RELOADZ becomes 1.
- reload state machine 920 transitions from state 921 to state 922 in which the state machine 920 checks whether an NVM operation is on-going (e.g., whether NVM is busy) by checking the value of NVM EN. If NVM EN is 1 when the reload state machine 920 is in state 922 , the state machine will wait in state 922 until NVM EN becomes 0. Upon NVM EN becoming 0, state machine 920 transitions from state 922 to state 923 . In state 923 , the reload state machine 920 sets NVM EN to a value of 1 (high) and performs a read operation for NVM 120 .
- the state machine 920 Upon completion of the read of NVM 120 , the state machine 920 transitions from state 923 to state 924 . In state 924 , the RELOAD DONE is set to 1 and NVM EN is set to 0. Subsequently the reload state machine 920 transitions into the idle state 921 and remains in the idle state 921 until the RELOAD DONE is set back to 0 by RESETZ going low (i.e. de-assertion of power supply).
- Couple is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with the description of the present disclosure. For example, if device A generates a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.
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Abstract
An integrated circuit includes a power-on reset (POR) circuit and a digital logic circuit. The POR has first and second control outputs. The POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage node exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage. The digital logic circuit has a first control input coupled to the first control output of the POR circuit and has a second control input coupled to the second control output of the POR circuit. The digital logic circuit is configured to initiate a first read transaction responsive to assertion of the first control signal and to initiate a second read transaction responsive to assertion of the second control signal.
Description
- This continuation application claims priority to U.S. patent application Ser. No. 16/880,541, filed May 21, 2020, which application claims priority to U.S. Provisional Application No. 201941030672, filed Jul. 30, 2019, both of which are hereby incorporated herein by reference in their entirety.
- A power-on reset (POR) circuit causes a logic circuit to remain in a reset state following a power cycle until the power supply voltage has increased to a safe operating voltage, A logic circuit attempting to operate from a supply voltage below its pre-designated safe operating voltage may cause the logic circuit to operate in an unpredictable manner.
- In at least one example, an integrated circuit includes a power-on reset (POR) circuit and a digital logic circuit. The POR has first and second control outputs. The POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage terminal exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage. The digital logic circuit has a first control input coupled to the first control output of the POR circuit and has a second control input coupled to the second control output of the POR circuit. The digital logic circuit is configured to initiate a first read transaction responsive to assertion of the first control signal and to initiate a second read transaction responsive to assertion of the second control signal.
- For a detailed description of various examples, reference will now be made to the accompanying drawings in which:
-
FIG. 1 illustrates an example of at least a portion of an integrated circuit including a power-on reset (POR) circuit coupled to a digital logic circuit with the digital logic circuit coupled to non-volatile memory. -
FIG. 2 shows an example implementation of the POR circuit. -
FIG. 3 illustrates various voltages monitored by the POR circuit. -
FIG. 4 illustrates the voltages ofFIG. 3 for the case in which the POR circuit releases the digital logic circuit from its reset state when VDD is below a minimum supply voltage for the non-volatile memory. -
FIG. 5 includes a timing diagram illustrating the operation of the POR circuit and the digital logic circuit for the case depicted inFIG. 4 . -
FIG. 6 illustrates the voltages ofFIG. 3 for the case in which the POR circuit releases the digital logic circuit from its reset state when VDD is above the minimum supply voltage for the non-volatile memory. -
FIG. 7 includes a timing diagram illustrating the operation of the POR circuit and the digital logic circuit for the case depicted inFIG. 6 . -
FIG. 8 includes a timing diagram illustrating the operation of the POR circuit and the digital logic circuit during a fluctuation of the supply voltage. -
FIG. 9 shows an example implementation of the digital logic circuit ofFIG. 1 . -
FIG. 1 shows an example of at least a portion of an integrated circuit (IC) 99. In this example, IC 99 includes a power-on reset (POR)circuit 100, adigital logic circuit 110, and a non-volatile memory (NVM) 120. ThePOR circuit 100,digital logic circuit 110, andNVM 120 are coupled to a supply voltage node (also referred to herein as a “terminal”) 101 (VDD) and to a common node 103 (VSS). ThePOR circuit 100 produces control signals RESETZ and RELOADZ, which are provided as inputs to thedigital logic circuit 110. The NVM 120 is coupled to thedigital logic circuit 110. In the example IC 99 ofFIG. 1 , the NVM 120 includestrim storage 122 in which one or more trim values can be stored. The trim values are retrieved bydigital logic circuit 110 upon a power-on event and are used to configure the IC 99 (e.g., adjust a value of resistance, a value of capacitance, etc.). The signals between thedigital logic circuit 110 and theNVM 120 include an NVM enable signal (NVM_EN), an address bus (ADDR), control bits (CTRL BITS), a data out bus (DATA OUT), and a data in bus (DATA IN). Thedigital logic circuit 110 can issue a read command (encoded in CTRL BITS) to theNVM 120 to trim data at an address specified by ADDR in order to read, for example, trim data stored inNVM 120. The read data is returned by NVM 120 to thedigital logic circuit 110 over DATA IN. The NVM 120 is maintained in a disabled state until NVM_EN is asserted (e.g., high). - During a power-on event, the VDD supply voltage increases from 0 V to its final steady-state level. The
digital logic circuit 110 is not guaranteed to operate correctly until VDD reaches a minimum level consistent with operation of the digital logic circuit 110 (referred to herein as the “minimum digital logic circuit voltage”). Similarly, theNVM 120 is not guaranteed to operate correctly until VDD reaches a minimum level consistent with operation of the NVM 120 (referred to herein as the “minimum NVM read voltage”). The minimum NVM read voltage may be different than the minimum digital logic circuit voltage. In the example described below, the minimum NVM read voltage is greater than the minimum digital logic circuit voltage. In one example, theIC 99 is rated to operate from a steady-state supply voltage between 1.55 V and 1.65 V, the minimum digital logic circuit voltage is 0.98 V, and the minimum NVM read voltage is 1.35 V. That is, in this example VDD needs to be at least 0.98 V for thedigital logic circuit 110 to operate as intended and at least 1.35 V for theNVM 120 to accurately respond to read commands from thedigital logic circuit 110. - During a power-on event, the
POR circuit 100 monitors the level of VDD as VDD ramps up from 0 V to its final steady-state level. When VDD exceeds the minimum digital circuit voltage (e.g., 0.98 V in one example), thePOR circuit 100 asserts RESETZ, and when VDD exceeds the minimum NVM read voltage, thePOR circuit 100 asserts RELOADZ. In one example, RESETZ and RELOADZ are initially logic low (e.g., 0 V) and assertion of those signals means that the signals are asserted to a logic high state. Thedigital logic circuit 110 is maintained in a reset state (idle) until RESETZ is forced high by thePOR circuit 100 at which timedigital logic circuit 110 is released from its reset state to begin operation. One of the operations that thedigital logic circuit 110 performs is to assert NVM_EN to theNVM 120 to enable operation of the NVM. Thus, NVM_EN is asserted (e.g., high) approximately when RESETZ transitions from low to high. Thedigital logic circuit 110 then initiates a read transaction to theNVM 120. As described below, thePOR circuit 100 controls the assertion (low to high transition) of RELOADZ in a manner to ensure that VDD is above the minimum NVM read voltage forNVM 120. - The example of
FIG. 1 pertains to different levels of minimum required supply voltages for thedigital logic circuit 110 andNVM 120 inIC 99. However, the principles described herein pertain to power-on reset control of two or more circuits that have different minimum operating voltage ratings. That is, the scope of this disclosure is not limited to specifically NVMs and their use to trim an IC. - There is a general trend towards lower IC power supply voltages, and thus the difference between the minimum supply voltages of different circuits (e.g.,
digital logic circuit 110 and NVM 120) within an IC, as well as the IC's minimum valid supply voltage, also decreases. These decreases govern the design complexity and area of the POR circuit. One complicating factor is that the characteristics of a circuit vary with process technology. For example, any resistors used in the POR circuit will not have a resistance that is exactly the designed value. A comparator may have an offset. Further, if the POR circuit includes a reference voltage source (e.g., a bandgap voltage source), the reference voltage generated by the reference voltage source may deviate substantially from its designed, nominal value. These factors contribute to some POR circuit, for example, releasing the digital logic circuit from its reset state before VDD has actually reached the minimum digital logic circuit voltage. Similarly, the NVM may be released before its voltage is sufficiently high to ensure proper NVM operation. ThePOR circuit 100 described herein is a relatively low area, low complexity circuit which is usable for handling small differences between the minimum IC supply voltage and the minimum supply voltage requirement of the various circuits within the IC (e.g., 0.98 V for thedigital logic circuit 110 and 1.35 V for the NVM 120). -
FIG. 2 shows an example implementation ofPOR circuit 100. In this example,POR circuit 100 includes avoltage divider 201, areference voltage generator 202, andcomparators voltage divider 201 in this example is a resistor divider comprising resistors R1, R2, and R3. R1-R3 are coupled in series between thesupply voltage node 101 and thecommon node 103. More than three resistors can be coupled in series betweennodes -
- The voltage on N2 (VN2) also is a fraction of the difference between VDD and VSS,
-
- From the equations above, it can be seen that VN1 is greater than VN2.
-
Comparator 210 has a non-inverting (+) input and an inverting input (−). In the example ofFIG. 2 , N1 is coupled to the non-inverting input ofcomparator 210. Similarly,comparator 220 has a non-inverting input and an inverting input. N2 is coupled to the non-inverting input ofcomparator 220. - The
reference voltage generator 202 generates a reference voltage labeled VBG. Thereference voltage generator 202 may comprise a bandgap voltage generator or any other suitable type of reference voltage generator. As a bandgap voltage generator,reference voltage generator 202 generates the output reference voltage VBG which is a fixed voltage that is generally not influenced by changes in temperature or VDD. VBG is coupled to the inverting inputs of bothcomparators comparator 210 generates the control signal RESETZ and the output ofcomparator 220 generates the control signal RELOADZ. - With VN1 less than VBG, RESETZ will be low. Similarly, with VN2 less than VBG, RELOADZ will also be low. During a power-on event, initially VDD will be low enough that both VN1 and VN2 will be less than VBG and both RESETZ and RELOADZ will be low. As VDD increases, VDD eventually becomes high enough that VN1 exceeds VBG. As a result, the
comparator 210 forces RESETZ high. As VDD continues to increase, eventually VN2 also exceeds VBG thereby causingcomparator 220 to force RELOADZ high. As such, during a power-on event in which VDD increases from VSS to its final steady-state level, RELOADZ transitions from low to high after RESETZ transitions from low to high. -
FIG. 3 illustrates various voltages for theIC 99 ofFIG. 1 . The minimum digital logic circuit voltage is illustrated at 310. The minimum NVM read voltage is illustrated at 312, and the maximum supply voltage is illustrated at 314. The maximum supply voltage is the maximum power supply voltage rating for theIC 99. The voltage values in parentheses are example voltages and were mentioned above. The example voltage for the minimum digitallogic circuit voltage 310 is 0.98 V. The example voltage for the minimum NVM readvoltage 312 is 1.35 V. The example voltage for themaximum supply voltage 314 is 1.65 V. - The
IC 99 is rated to operate from a supply voltage VDD in the range shown at 315, that is betweenvoltage levels comparators comparator 210 for RESETZ is within the range illustrated as 311 between alower level 316 and anupper level 318. That is, the range of trip points forcomparator 210 across a large sample ofICs 99 is betweenvoltage levels comparator 220 for RELOADZ is within the range illustrated as 313 between alower level 320 and anupper level 322. That is, the range of trip points forcomparator 220 across a large sample ofICs 99 is betweenvoltage levels - Because
comparators reference voltage generator 202 and because thecomparators same voltage divider 201, the trip-point error in both RESETZ and RELOADZ will be correlated. That is, if RESETZ trips at a lower voltage of VDD, then RELOADZ will also trip at a lower voltage, and vice versa. - The
range 311 of VDD for the trip-point ofcomparator 210 to transition RESETZ from low to high, due to process variations, means that, due to the process variations, some comparators 210 (in some instances of ICs 99) will trip when VDD exceeds a particular voltage that is below the minimum NVM readvoltage 312, whilecomparators 210 for other instances ofIC 99 will trip when VDD exceeds a particular voltage that is above the minimum NVM readvoltage 312. -
FIG. 4 illustrates an example of a trip-point forcomparator 210 for a givenIC 99 being below the minimum NVM readvoltage 312 as illustrated at 405. As explained above, NVM EN is asserted (low to high) byPOR circuit 100 approximately when RESETZ is asserted, and thus when VDD is below the minimum NVM readvoltage 312. A read ofNVM 120 will occur but the return data (e.g., trim values) are not guaranteed to be valid because VDD was too low (i.e., below the minimum NVM read voltage). However, because RESETZ and RELOADZ are generated based on the samereference voltage generator 202, a trip-point for comparator 210 (RESETZ) being in alower range 405 ofrange 311 also means that the trip-point for comparator 220 (RELOADZ) will also be in a correspondinglower range 407 ofrange 313. That the RESETZ's and RELOADZ's trip-points are correlated in this way means that RELOADZ will trip after RESETZ trips and RELOADZ will transition from low to high when VDD is above the minimum NVM readvoltage 312 but below the minimum validIC supply voltage 324. This configuration of RESETZ trip-point range 405 and RELOADZ trip-point range 407 ensures that whenever RESETZ transitions from low to high, RESETZ will be below the minimum NVM readvoltage 312 and it will be followed by a RELOADZ low to high transition before the IC supply voltage reaches its stable value. ThePOR circuit 100 asserting RELOADZ (which will occur when VDD is above the minimum NVM read voltage 312) also causesdigital logic circuit 110 to again assert NVM EN to again initiate a read ofNVM 120. This time, the read ofNVM 120 will occur when VDD is above the minimum NVM readvoltage 312 and the return NVM read data will be valid. -
FIG. 5 shows a timing diagram illustrating the operation described above. VDD is shown starting at an initial (e.g., 0 V) voltage level at 501. A power-on event begins at 502 at which time VDD begins to increase as shown toward its final steady-state level at 550. At 510, VDD reaches the trip-point forcomparator 210 which is above the minimum digital logic circuit voltage (but still below the minimum NVM read voltage) and thePOR circuit 100 responds by asserting RESETZ at 512. As shown at 512, RESETZ transitions form low to high. Thedigital logic circuit 110 also asserts NVM EN at 514. With NVM EN now being high,digital logic circuit 110 performs a read ofNVM 120 at 530. However, because VDD is still below the minimum NVM read voltage duringread 530, the return data fromNVM 120 is considered invalid. NVM EN becomes low again at 516 towards the end of the read transaction. The NVM EN signal is brought back to 0 (NVM disable state) once the NVM operation is completed in order to reduce power consumption by keeping the NVM disabled until such time when an NVM operation is needed. - As VDD continues to increase, VDD eventually reaches the trip-point for
comparator 220 at 515 and RELOADZ is forced high as shown at 518. Thedigital logic circuit 110 responds to assertion of RELOADZ by again forcing NVM EN high (520) and initiating a second read ofNVM 120 at 540. During this second read ofNVM 120, however, VDD is above the minimum NVM read voltage and the read returns valid data fromNVM 120 to thedigital logic circuit 110. -
FIG. 6 illustrates an example of a trip-point forcomparator 210 for a givenIC 99 for VDD being above the minimum NVM readvoltage 312 as illustrated at 505, which is the upper portion ofrange 311. The trip-point forcomparator 220 occurs with VDD being in theupper portion 507 ofrange 313 due to the trip-points forcomparators point range 507 is above the minimum valid IC supply voltage (324). However, not having a RELOADZ low to high transition should not be a concern as the RESETZ trip-point is above the minimum NVM readvoltage 312 in which case the NVM read operation triggered by a low to high transition of RESETZ itself would result in a valid return of read data fromNVM 120. -
FIG. 7 includes the timing diagram associated withFIG. 6 for the case in which a RELOADZ low to high transition is also present. VDD increases to the trip-point ofcomparator 210 at 710 thereby causingPOR circuit 100 to transition RESETZ from low to high at 712. The rising edge of RESETZ at 712 causes thedigital logic circuit 110 to assert NVM EN at 714 and initiate a read ofNVM 120 at 730. Because VDD is above the minimum NVM read voltage during the read at 730, the return data from theNVM 120 to the digital logic circuit is considered valid. - As VDD continues to increase, it eventually reaches the trip-point for
comparator 220 and RELOADZ is asserted high bycomparator 220 at 718.Digital logic circuit 110 responds to RELOADZ being high by again asserting NVM EN high at 720 to initiate the second read ofNVM 120 at 740. The second read at 740 is redundant because the first read at 730 returned valid data, but the second read is not harmful. -
FIGS. 4-7 illustrate that a first read ofNVM 120 is performed upon thedigital logic circuit 110 being released from its reset state, and then a second read of NVM is performed when RELOADZ is asserted high. The first read may or may not return valid data from NVM 120 (it depends on whether VDD is below or above the minimum NVM read voltage during the first read), but in case the first read is invalid, a second, RELOADZ-based valid read is assured. Thus, the use of thecomparators reference voltage circuit 202 ensures that valid read data is returned fromNVM 120 using aPOR circuit 100 that is of relatively low area and low complexity. ThePOR circuit 100 facilitates a relatively small difference (e.g., 200 mV or less) between minimum valid IC supply voltage and minimum valid voltage for the functional blocks (e.g.digital logic circuit 110 and NVM 120) within the IC. -
FIG. 8 illustrates the operation ofPOR circuit 100 and thedigital logic circuit 110 during a fluctuation in the voltage level of VDD within the valid ICsupply voltage range 315 after the initial power-on event. As described above, during a power-on event, VDD reaches the trip-point 810 corresponding tocomparator 210, which causes RESETZ to be asserted high at 812. NVM EN is also asserted at 814 and a first read ofNVM 120 is performed by thedigital logic circuit 110 at 817. When VDD reaches the trip-point (815) corresponding to comparator 220 at 815, thePOR circuit 100 asserts RELOADZ high (818) thereby triggering thedigital logic circuit 110 to again assert NVM EN as shown at 816 and perform the second read at 819 of theNVM 120. At this point, the power-on event is complete. - Reference numeral illustrates 823 illustrates a subsequent fluctuation in VDD after the power-on event. VDD may dip below the trip-point of comparator 220 (as illustrated at 831). VDD may then increase and again reach the trip-point at 825 corresponding to
comparator 220.Comparator 220 responds by again asserting RELOADZ high at 828.Digital logic circuit 110, however, precludes NVM EN from again being asserted high (as otherwise would have occurred at 830) and thus precludes another read ofNVM 120 from being performed. -
FIG. 9 shows an example implementation ofdigital logic circuit 110. Thedigital logic circuit 110 in this example is implemented as a combination of a wake-upstate machine 910 and a reloadstate machine 920. Each state machine can be implemented as a combination of logic gates (AND gates, OR gates, inverters, etc.), flip-flops, and/or other circuit components. The detailed circuit implementation ofstate machines digital logic circuit 110 described herein. - In the example of
FIG. 9 , wake-upstate machine 910 has threeoperational states State 911 is the Idle state and the wake-upstate machine 910 begins operation in theIdle state 911 upon RESETZ being asserted high. A flag, READ DONE, is stored in, for example, a flip-flop (not shown) and maintained by the wake-upstate machine 910. The function of the READ DONE flag is to indicate when the NVM read operation post RESETZ low to high transition has happened. The reset (when RESETZ is low) value of the READ DONE flag is 0 indicating that the read operation post assertion of RESETZ has not yet been performed. When the RESETZ transitions from low to high, the state machine starts inIDLE state 911 with READ DONE flag set to 0.State machine 910 checks the value of READ DONE and given it is 0, the state machine transitions fromstate 911 tostate 912. Instate 912, the wake-upstate machine 910 sets NVM EN to a value of 1 (high) and performs a read ofNVM 120. Upon completion of the read ofNVM 120, thestate machine 910 transitions fromstate 912 tostate 913 in which thestate machine 910 sets NVM EN to 0 and sets the flag READ DONE to 1. A state transition then occurs back to theIdle state 911 and state-machine 910 remains instate 911 as long as READ DONE equals 1. - The reload
state machine 920 has the four states 921-924 shown in the example ofFIG. 9 .State 921 is the Idle state and the reloadstate machine 920 begins operation in theIdle state 921 when RESETZ is asserted high. A flag RELOAD DONE is stored in a flip-flop (not shown) and maintained by the reloadstate machine 920. The function of RELOAD DONE is to indicate if an NVM read operation following the first low to high transition of RELOADZ has happened or not. The reset (when RESETZ is low) value of RELOAD DONE flag is 0 indicating that NVM read following the first RELOADZ low to high transition has not happened yet. When RESETZ transitions from low to high, thestate machine 920 starts instate 921 with RELOAD DONE flag set to a value of 0. The state machine waits instate 921 until RELOADZ becomes 1. - Upon a RELOADZ transition from low-to-high, reload
state machine 920 transitions fromstate 921 tostate 922 in which thestate machine 920 checks whether an NVM operation is on-going (e.g., whether NVM is busy) by checking the value of NVM EN. If NVM EN is 1 when the reloadstate machine 920 is instate 922, the state machine will wait instate 922 until NVM EN becomes 0. Upon NVM EN becoming 0,state machine 920 transitions fromstate 922 tostate 923. Instate 923, the reloadstate machine 920 sets NVM EN to a value of 1 (high) and performs a read operation forNVM 120. Upon completion of the read ofNVM 120, thestate machine 920 transitions fromstate 923 tostate 924. Instate 924, the RELOAD DONE is set to 1 and NVM EN is set to 0. Subsequently the reloadstate machine 920 transitions into theidle state 921 and remains in theidle state 921 until the RELOAD DONE is set back to 0 by RESETZ going low (i.e. de-assertion of power supply). - The term “couple” is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with the description of the present disclosure. For example, if device A generates a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.
- Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.
Claims (12)
1. An integrated circuit (IC), comprising:
a power-on reset (POR) circuit coupled to a supply voltage terminal and having first and second control outputs, the POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage terminal exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage; and
a digital logic circuit having a first control input coupled to the first control output of the POR circuit and having a second control input coupled to the second control output of the POR circuit, the digital logic circuit is configured to initiate a first transaction responsive to assertion of the first control signal and to initiate a second transaction responsive to assertion of the second control signal.
2. The IC of claim 1 , wherein the second threshold voltage is greater than the first threshold voltage.
3. The IC of claim 2 , wherein the POR circuit includes first and second comparators, the first comparator having an output to produce the first control signal and the second comparator having an output to produce the second control signal.
4. The IC of claim 2 , wherein the POR circuit includes:
a voltage divider coupled to the supply voltage terminal and a common terminal and having a first voltage divider terminal and a second voltage divider terminal;
a first comparator coupled to the first voltage divider terminal, the first comparator having a comparator output to produce the first control signal; and
a second comparator coupled to the second voltage divider terminal, the second comparator having a comparator output to produce the second control signal.
5. The IC of claim 4 , further including a reference voltage generator coupled to the first and second comparators.
6. The IC of claim 5 , wherein
the first comparator has a noninverting input and an inverting input, the first voltage divider terminal is coupled to the noninverting input of the first comparator, and the reference voltage generator is coupled to the inverting input of the first comparator; and
the second comparator has a noninverting input and an inverting input, the second voltage divider terminal is coupled to the noninverting input of the second comparator, and the reference voltage generator is coupled to the inverting input of the second comparator.
7. The IC of claim 4 , wherein the voltage divider includes first, second, and third resistors coupled in series between the supply voltage terminal and the common terminal, the first voltage divider terminal is between the first and second resistors, and the second voltage divider terminal is between the second and third resistors.
8. The IC of claim 1 , wherein the digital logic circuit is configured to avoid initiating a subsequent transaction responsive to a subsequent assertion of the second control signal following a power-on event.
9. A circuit, comprising:
a voltage divider coupled between a supply voltage terminal and a common terminal and having a first voltage divider terminal and a second voltage divider terminal;
a reference voltage generator;
a first comparator coupled to the first voltage divider terminal and to the reference voltage generator, the first comparator having a comparator output to produce a first control signal; and
a second comparator coupled to the second voltage divider terminal and to the reference voltage generator, the second comparator having a comparator output to produce a second control signal.
10. The circuit of claim 9 , wherein the voltage divider includes first, second, and third resistors coupled in series between the supply voltage terminal and the common terminal, the first voltage divider terminal is between the first and second resistors, and the second voltage divider terminal is between the second and third resistors.
11. The circuit of claim 9 , wherein:
the first comparator has a noninverting input and an inverting input, the first voltage divider terminal is coupled to the noninverting input of the first comparator, and the reference voltage generator is coupled to the inverting input of the first comparator; and
the second comparator has a noninverting input and an inverting input, the second voltage divider terminal is coupled to the noninverting input of the second comparator, and the reference voltage generator is coupled to the inverting input of the second comparator.
12. The circuit of claim 9 , further including a digital logic circuit having a first control input and a second control input, the first control input is coupled to the comparator output of the first comparator and the second control input is coupled to the comparator output of the second comparator.
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US17/194,474 US20210194479A1 (en) | 2019-07-30 | 2021-03-08 | Power-on reset circuit |
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IN201941030672 | 2019-07-30 | ||
US16/880,541 US10972092B2 (en) | 2019-07-30 | 2020-05-21 | Power-on reset circuit |
US17/194,474 US20210194479A1 (en) | 2019-07-30 | 2021-03-08 | Power-on reset circuit |
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US7391665B1 (en) * | 2005-09-09 | 2008-06-24 | Altera Corporation | Process and temperature invariant power on reset circuit using a bandgap reference and a long delay chain |
US8823418B2 (en) * | 2009-09-17 | 2014-09-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Power on detection circuit |
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