US20210193835A1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

Info

Publication number
US20210193835A1
US20210193835A1 US17/193,830 US202117193830A US2021193835A1 US 20210193835 A1 US20210193835 A1 US 20210193835A1 US 202117193830 A US202117193830 A US 202117193830A US 2021193835 A1 US2021193835 A1 US 2021193835A1
Authority
US
United States
Prior art keywords
semiconductor layer
type
region
type impurity
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US17/193,830
Inventor
Takuo Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Original Assignee
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Electronic Devices and Storage Corp filed Critical Toshiba Corp
Priority to US17/193,830 priority Critical patent/US20210193835A1/en
Publication of US20210193835A1 publication Critical patent/US20210193835A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Definitions

  • Embodiments relate to a semiconductor device and a method for manufacturing the same.
  • MOSFET metal oxide semiconductor field effect transistor
  • FIG. 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment
  • FIG. 2 is a schematic plan view showing the semiconductor device according to the embodiment
  • FIGS. 3A to 4B are schematic cross-sectional views showing manufacturing processes of the semiconductor device according to the embodiment.
  • FIGS. 5A and 5B are schematic views showing a testing method of the semiconductor device according to the embodiment.
  • a semiconductor device includes a semiconductor body, a first electrode, a second electrode and a control electrode.
  • the first electrode partially contacts the semiconductor body.
  • the first electrode contacts the front surface of the semiconductor body.
  • the second electrode is provided on a side opposite to the first electrode with the semiconductor body interposed.
  • the control electrode is provided between the semiconductor body and the first electrode.
  • the semiconductor body includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type.
  • the first semiconductor layer and the second semiconductor layer are alternately arranged in a first direction along a front surface of the semiconductor body.
  • the semiconductor body further includes a third semiconductor layer of the second conductivity type and a fourth semiconductor layer of the first conductivity type.
  • the third semiconductor layer is provided between the second semiconductor layer and the first electrode.
  • the fourth semiconductor layer is selectively provided between the third semiconductor layer and the first electrode.
  • the first semiconductor layer includes a first low-concentration portion.
  • the first low-concentration portion has a first conductivity type impurity concentration lower than a first conductivity type impurity concentration in other portion of the first semiconductor layer.
  • the second semiconductor layer includes a second low-concentration portion.
  • the second low-concentration portion has a second conductivity type impurity concentration lower than a second conductivity type impurity concentration in other portion of the second semiconductor layer.
  • the second low-concentration portion is positioned between an end of the second semiconductor layer on a second electrode side and a boundary of the second semiconductor layer and the third semiconductor layer.
  • the first low-concentration portion is positioned at a level same as a level of the second low-concentration portion in a second direction directed toward the first electrode from the second electrode.
  • FIG. 1 is a schematic cross-sectional view showing a semiconductor device 1 according to an embodiment.
  • FIG. 2 is a schematic plan view showing the semiconductor device 1 according to the embodiment.
  • FIG. 1 is the schematic view showing cross-section taken along A-A line shown in FIG. 2 .
  • the semiconductor device 1 includes a semiconductor body 10 , a source electrode 20 , a drain electrode 30 and a gate electrode 40 .
  • the semiconductor body 10 is provided between the source electrode 20 and the drain electrode 30 .
  • the gate electrode 40 is provided between the semiconductor body 10 and the source electrode 20 .
  • the semiconductor device 1 is a so-called “vertical type MOSFET” in which electric current flows from the drain electrode 30 to the source electrode 20 .
  • the gate electrode 40 is electrically isolated from the semiconductor body 10 with a gate-insulating film 43 interposed.
  • the gate electrode 40 is electrically isolated from the source electrode 20 with an inter-layer insulating film 40 interposed.
  • the semiconductor body 10 includes an n-type semiconductor layer 11 and a p-type semiconductor layer 13 .
  • the n-type semiconductor layer 11 and the p-type semiconductor layer 13 are formed into a plate shape extending in the Y-direction and the Z-direction.
  • the n-type semiconductor layer 11 and the p-type semiconductor layer 13 are alternately arranged in a direction along the top surface of the semiconductor body 10 (e.g. in the X-direction).
  • the n-type semiconductor layer 11 includes a low-concentration portion 11 M.
  • the low-concentration portion 11 M includes an n-type impurity having a lower concentration than a concentration of an n-type impurity included in other portion of the n-type semiconductor layer 11 .
  • the p-type semiconductor layer 13 includes a low-concentration portion 13 M.
  • the low concentration portion 13 M includes a p-type impurity having a lower concentration than a concentration of a p-type impurity contained in other portion of the p-type semiconductor layer 13 .
  • the position (level) in the Z direction of the low concentration portion 11 M in the n type semiconductor layer 11 is the same as the position (level) in the Z direction of the low concentration portion 13 M in the p-type semiconductor layer 13 .
  • the n-type impurity concentration in the low density portion 11 M is, for example, 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 16 cm ⁇ 3 or less.
  • the n-type impurity concentration in the other portion of the n-type semiconductor layer 11 is 1 ⁇ 10 16 cm ⁇ 3 or more.
  • the p-type impurity concentration in the low concentration portion 13 M is, for example, 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 16 cm ⁇ 3 or less.
  • the p-type impurity concentration in the other portion of the p-type semiconductor layer 13 is 1 ⁇ 10 16 cm ⁇ 3 or more.
  • the semiconductor portion 10 further includes a p-type diffusion layer 15 , an n-type source layer 17 , a p-type contact layer 19 , and an n-type drain layer 35 .
  • the p-type diffusion layer 15 is provided between the p-type semiconductor layer 13 and the source electrode 20 .
  • the p-type diffusion layer 15 includes, for example, a p-type impurity having a higher concentration than a concentration of a p-type impurity in the p-type semiconductor layer 13 .
  • the p-type diffusion layer 15 is electrically connected to, for example, the p-type semiconductor layer 13 .
  • the n-type source layer 17 is selectively provided between the p-type diffusion layer 15 and the source electrode 20 .
  • the n-type source layer 17 includes, for example, an n-type impurity having a higher concentration than a concentration of an n-type impurity in the n-type semiconductor layer 11 .
  • the p-type contact layer 19 is selectively provided between the p-type diffusion layer 15 and the source electrode 20 .
  • the p-type contact layer 19 and the n-type source layer 17 are arranged along the top surface of the semiconductor portion 10 .
  • the source electrode 20 is provided so as to be electrically connected to a portion of the n-type source layer 17 and the p-type contact layer 19 .
  • the p-type contact layer 19 for example, includes a p-type impurity having a higher concentration than a concentration of a p-type impurity in the p-type diffusion layer 15 , and electrically connects the p-type diffusion layer 15 and the source electrode 20 .
  • the gate electrode 40 is positioned, for example, between the n-type semiconductor layer 11 and the source electrode 20 .
  • the gate electrode 40 is provided so as to face part of the n-type semiconductor layer 11 and the p-type diffusion layer 15 with the gate insulating film 43 interposed. That is, when the gate bias is applied, the gate electrode 40 is provided so that an n-type inversion layer is formed on the surface of the p-type diffusion layer 15 , and the n-type semiconductor layer 11 and the n-type source layer 17 are electrically conducted.
  • the n-type drain layer 35 is provided between the n-type semiconductor layer 11 and the drain electrode 30 and between the p-type semiconductor layer 13 and the drain electrode 30 .
  • the n-type drain layer 35 includes, for example, an n-type impurity having a higher concentration than the concentration of the n-type impurity in the n-type semiconductor layer 11 .
  • the n-type drain layer 35 is electrically connected to the drain electrode 30 , for example.
  • FIGS. 3A to 4B are schematic cross-sectional views sequentially showing the manufacturing process of the semiconductor device 1 .
  • a semiconductor layer 101 is formed on the semiconductor substrate SS.
  • the semiconductor substrate SS is, for example, an n-type silicon wafer.
  • the semiconductor layer 101 is, for example, a silicon layer epitaxially grown on the n-type silicon wafer.
  • the semiconductor layer 101 is, for example, a so-called undoped layer grown under the condition in which no impurity is added.
  • the semiconductor layer 101 includes, for example, an n-type impurity, or a p-type impurity, or both at the background level.
  • an n-type impurity and a p-type impurity are selectively ion-implanted into the semiconductor layer 101 using an implantation mask (not shown) to form an n-type implantation region NR and a p-type implantation region PR.
  • the amount of n-type impurity introduced into the n-type implantation region NR is controlled by the dose amount of the n-type impurity and the width LN of the n-type implantation region NR (the opening width of the implantation mask).
  • the amount of p-type impurity introduced into the p-type implantation region PR is controlled by the dose amount of the p-type impurity and the width LP of the p-type implantation region PR (the opening width of the implantation mask).
  • the n-type impurity introduced into the n-type implantation region NR is controlled, for example, to be the same amount as that of the p-type impurity introduced into the p-type implantation region PR.
  • a semiconductor layer 103 is formed on the semiconductor layer 101 .
  • the semiconductor layer 103 is, for example, a silicon layer and is an undoped layer to which no impurity is added.
  • an n-type impurity and a p-type impurity are selectively ion-implanted into the semiconductor layer 103 to form an n-type implantation region NR and a p-type implantation region PR.
  • the n-type implantation region NR of the semiconductor layer 103 is formed immediately above the n-type implantation region NR of the semiconductor layer 101 .
  • the p-type implantation region PR of the semiconductor layer 103 is formed immediately above the p-type implantation region PR of the semiconductor layer 101 .
  • the n-type impurity introduced into the n-type implantation region NR is controlled to be, for example, the same amount as that of the p-type impurity introduced into the p-type implantation region PR.
  • a semiconductor layer 105 is formed on the semiconductor layer 103 .
  • the semiconductor layer 105 is, for example, a silicon layer, and is an undoped layer to which no impurity is added.
  • an n-type impurity and a p-type impurity are selectively ion-implanted into the semiconductor layer 105 to form an n-type implantation region NR and a p-type implantation region PR.
  • the n-type implantation region NR of the semiconductor layer 105 is formed immediately above the n-type implantation region NR of the semiconductor layer 103 .
  • the p-type implantation region PR of the semiconductor layer 105 is formed immediately above the p-type implantation region PR of the semiconductor layer 103 .
  • the n-type impurity introduced into the n-type implantation region NR of the semiconductor layer 105 is controlled, for example, to be the same amount as that of the p-type impurity introduced in the p-type implantation region PR of the semiconductor layer 105 .
  • FIG. 4A is a schematic view showing a cross section of a stacked body 110 .
  • the stacked body 110 is formed by repeating the growth of an undoped semiconductor layer and the ion implantation of an n-type impurity and a p-type impurity.
  • the stacked body 110 includes semiconductor layers 101 , 103 , 105 , 107 , 109 , 111 , 113 , 115 , 117 and 119 stacked on a semiconductor substrate SS.
  • the n-type implantation region NR and the p-type implantation region PR are formed in each semiconductor layer except the semiconductor layer 119 . Neither the n-type impurity nor the p-type impurity is ion-implanted into the uppermost semiconductor layer 119 .
  • the semiconductor layer 119 is an undoped layer or an n-type layer in which an n-type impurity is doped during epitaxial growth so as to have the predetermined n-type impurity concentration.
  • the n-type implantation region NR and the p-type implantation region PR are formed so as to be arranged in the Z direction.
  • the n-type implantation region NR formed in the semiconductor layer 113 is formed to include the n-type impurity having a smaller amount than an amount of the n-type impurity in the n-type implantation region NR that is formed in the other semiconductor layer.
  • the p-type implantation region PR formed in the semiconductor layer 113 is formed so as to include the p-type impurity having a smaller amount than an amount of the p-type impurity in the p-type implantation region PR that is formed in the other semiconductor layer.
  • the amount of the n-type impurity introduced into the n-type implantation region NR formed in the semiconductor layer 113 is the same as the amount of the p-type impurity introduced into the p-type implantation region PR formed in the semiconductor layer 113 .
  • the amount of impurities at the background level in the semiconductor layer 113 is one or more orders of magnitude less than the amount of the ion-implanted n-type impurity or the ion-implanted p-type impurity.
  • the total amount of n-type impurities in the n-type implantation region NR is the same as the amount of the p-type impurity in the p-type implantation region PR
  • the total amount of n-type impurities is substantially the same as the total amount of p-type impurities in the n-type implantation region NR and the p-type implantation region PR that are adjacent to each other in the X-direction. That is, the total amount of n-type impurities is balanced with the total amount of p-type impurities.
  • the amount of n-type impurity in the n-type implantation region NR is substantially the same as the p-type impurity amount in the p-type implantation region PR.
  • the total amount of n-type impurities in the n-type implantation region NR and p-type implantation region PR adjacent to each other is balanced with the total amount of p-type impurities therein.
  • the n-type semiconductor layer 11 and the p-type semiconductor layer 13 are formed in the stacked body 110 .
  • the n-type semiconductor layer 11 and the p-type semiconductor layer 13 are formed by activating the ion-implanted n-type impurity and p-type impurity by heat treatment.
  • the semiconductor layers 101 to 119 are integrally shown as one semiconductor layer.
  • a low concentration portion 11 M is formed at a level corresponding to the position of the semiconductor layer 113 .
  • a low concentration portion 13 M is formed at a level corresponding to the position of the semiconductor layer 113 .
  • a p-type diffusion layer 15 , an n-type source layer 17 and a p-type contact layer 19 are formed in a region corresponding to the uppermost semiconductor layer 119 .
  • the semiconductor substrate SS is thinned to form an n-type drain region 35 .
  • the drain electrode 30 is formed to complete the semiconductor device 1 .
  • FIGS. 5A and 5B are schematic views showing a testing method of the semiconductor device 1 according to the embodiment.
  • FIG. 5A is a schematic view showing the test apparatus.
  • FIG. 5B is a time chart showing the drain voltage Vds, the electron current Id(e), the hole current Id(h), and the drain current Id.
  • a voltage is applied from the power supply VCL via the inductance L between the source electrode 20 and the drain electrode 30 of the semiconductor device 1 .
  • a gate bias VGF is applied to the gate electrode 40 of the semiconductor device 1 .
  • the gate bias VGF is a pulse voltage having a constant cycle, and performs the ON/OFF control in the semiconductor device 1 .
  • the drain voltage Vds applied between the source and drain varies corresponding to the period of the gate bias VGF.
  • the drain current Id also varies corresponding thereto.
  • the n-type inversion layer is induced at the interface between the gate insulating film 43 and the p-type diffusion layer 15 , and the n-type semiconductor layer 11 and the n-type source layer 17 are electrically conducted (see FIG. 1 ).
  • the gate bias falls below the threshold value and the semiconductor device 1 is turned off, the n-type inversion layer disappears and the electrical conduction is interrupted between the n-type semiconductor layer 11 and the n-type source layer 17 (see FIG. 1 ).
  • space charges remaining in the n-type semiconductor layer 11 are discharged to the source electrode 20 via the p-type diffusion layer 15 and discharged to the drain electrode 30 via the n-type drain layer 35 .
  • the n-type semiconductor layer 11 and the p-type semiconductor layer 13 are depleted, and high electric field is induced between the p-type diffusion layer 15 and the n-type drain layer 35 .
  • the electrons in the n-type semiconductor layer 11 are accelerated by the electric field, collide with the lattice atoms constituting the n-type semiconductor layer 11 , and ionize the lattice atoms. Thereby, new electron-hole pairs are generated.
  • the number of electrons and holes in the depletion layer increases as this process continues, and the avalanche current flows.
  • the electron current Id(e) and the hole current Id(h) may have the same phases, for example, in the case where the time required for the electrons generated by the impact-ionization to reach the n-type drain layer 35 coincides with the time required for the holes to reach the p-type diffusion layer 15 . In order to avoid this, for example, it is preferable to make the impact-ionization occur at a position in the n-type semiconductor layer 11 different from the position where the electron and hole generated by the impact-ionization simultaneously reach the n-type drain layer 35 and the p-type diffusion layer 15 , respectively.
  • the embodiment it is possible to suppress the impact-ionization by reducing the electric field in the low concentration portion 11 M provided in the n-type semiconductor layer 11 . Further, the charge balance in the n-type semiconductor layer 11 and the p-type semiconductor layer 13 is maintained by providing the low concentration portion 13 M in the p-type semiconductor layer 13 . Thereby, it is possible to make the n-type semiconductor layer 11 and the p-type semiconductor layer 13 being uniformly depleted, and prevent the electric field concentration in the vicinity of the low concentration portion 11 M and the low concentration portion 13 M. As a result, it is possible to reduce electrons and holes simultaneously reaching the n-type drain layer 35 and the p-type diffusion layer 15 , thereby avoiding the avalanche current oscillation.
  • distances Lh and Le is provided in the p-type semiconductor layer 13 .
  • the distance Lh is defined as a distance from the low-density portion 13 M to the p-type diffusion layer 15
  • the distance Le is defined as a distance from the low-density portion 13 M to the end 13 e of the p-type semiconductor layer 13 on the drain electrode side (See FIG. 1 ).
  • the mobility of electrons in silicon is greater than the mobility of holes in silicon.
  • the distance Le be three times the distance Lh.
  • the ratio of the electron mobility to the hole mobility is 1:0.6. Therefore, the ratio of the distance Le to the distance Lh is preferable to be set to 1:0.6. That is, it is more preferable that the ratio of the distance Le to the distance Lh is set to be the same as or substantially the same as the ratio of the electron mobility to the hole mobility.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor device includes a semiconductor body, first and second electrodes and a control electrode. The semiconductor body is positioned between the first and second electrodes. The control electrode is provided between the semiconductor body and the first electrode. The semiconductor body includes a first layer of a first conductivity-type and a second layer of a second conductivity-type alternately arranged along the first electrode. The first and second layers include first and second low-concentration portions, respectively. The first low-concentration portion has a first conductivity-type impurity concentration lower than that in other portion of the first layer. The second low-concentration portion has a second conductivity-type impurity concentration lower than that in other portion of the second layer. The first low-concentration portion is positioned at a level same as a level of the second low-concentration portion in a direction directed toward the first electrode from the second electrode.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of U.S. application Ser. No. 16/357,567, filed on Mar. 19, 2019, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-169710, filed on Sep. 11, 2018; the entire contents of which are incorporated herein by reference.
    • FIELD
  • Embodiments relate to a semiconductor device and a method for manufacturing the same.
    • BACKGROUND
  • In a case where a metal oxide semiconductor field effect transistor (MOSFET) acts as a switching device for controlling electric power, it is required to suppress oscillation of avalanche current that flows in the turn-off operation, and reduce electromagnetic interference (EMI).
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment;
  • FIG. 2 is a schematic plan view showing the semiconductor device according to the embodiment;
  • FIGS. 3A to 4B are schematic cross-sectional views showing manufacturing processes of the semiconductor device according to the embodiment; and
  • FIGS. 5A and 5B are schematic views showing a testing method of the semiconductor device according to the embodiment.
    •  DETAILED DESCRIPTION
  • According to one embodiment, a semiconductor device includes a semiconductor body, a first electrode, a second electrode and a control electrode. The first electrode partially contacts the semiconductor body. The first electrode contacts the front surface of the semiconductor body. The second electrode is provided on a side opposite to the first electrode with the semiconductor body interposed. The control electrode is provided between the semiconductor body and the first electrode. The semiconductor body includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The first semiconductor layer and the second semiconductor layer are alternately arranged in a first direction along a front surface of the semiconductor body. The semiconductor body further includes a third semiconductor layer of the second conductivity type and a fourth semiconductor layer of the first conductivity type. The third semiconductor layer is provided between the second semiconductor layer and the first electrode. The fourth semiconductor layer is selectively provided between the third semiconductor layer and the first electrode. The first semiconductor layer includes a first low-concentration portion. The first low-concentration portion has a first conductivity type impurity concentration lower than a first conductivity type impurity concentration in other portion of the first semiconductor layer. The second semiconductor layer includes a second low-concentration portion. The second low-concentration portion has a second conductivity type impurity concentration lower than a second conductivity type impurity concentration in other portion of the second semiconductor layer. The second low-concentration portion is positioned between an end of the second semiconductor layer on a second electrode side and a boundary of the second semiconductor layer and the third semiconductor layer. The first low-concentration portion is positioned at a level same as a level of the second low-concentration portion in a second direction directed toward the first electrode from the second electrode.
  • Embodiments will now be described with reference to the drawings. The same portions inside the drawings are marked with the same numerals; a detailed description is omitted as appropriate; and the different portions are described. The drawings are schematic or conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. The dimensions and/or the proportions may be illustrated differently between the drawings, even in the case where the same portion is illustrated.
  • There are cases where the dispositions of the components are described using the directions of XYZ axes shown in the drawings. The X-axis, the Y-axis, and the Z-axis are orthogonal to each other. Hereinbelow, the directions of the X-axis, the Y-axis, and the Z-axis are described as an X-direction, a Y-direction, and a Z-direction. Also, there are cases where the Z-direction is described as upward and the direction opposite to the Z-direction is described as downward.
  • FIG. 1 is a schematic cross-sectional view showing a semiconductor device 1 according to an embodiment. FIG. 2 is a schematic plan view showing the semiconductor device 1 according to the embodiment. FIG. 1 is the schematic view showing cross-section taken along A-A line shown in FIG. 2.
  • As shown in FIG. 1, the semiconductor device 1 includes a semiconductor body 10, a source electrode 20, a drain electrode 30 and a gate electrode 40. The semiconductor body 10 is provided between the source electrode 20 and the drain electrode 30. The gate electrode 40 is provided between the semiconductor body 10 and the source electrode 20. The semiconductor device 1 is a so-called “vertical type MOSFET” in which electric current flows from the drain electrode 30 to the source electrode 20.
  • The gate electrode 40 is electrically isolated from the semiconductor body 10 with a gate-insulating film 43 interposed. The gate electrode 40 is electrically isolated from the source electrode 20 with an inter-layer insulating film 40 interposed.
  • As shown in FIG. 1 and FIG. 2, the semiconductor body 10 includes an n-type semiconductor layer 11 and a p-type semiconductor layer 13. The n-type semiconductor layer 11 and the p-type semiconductor layer 13 are formed into a plate shape extending in the Y-direction and the Z-direction. The n-type semiconductor layer 11 and the p-type semiconductor layer 13 are alternately arranged in a direction along the top surface of the semiconductor body 10 (e.g. in the X-direction).
  • The n-type semiconductor layer 11 includes a low-concentration portion 11M. The low-concentration portion 11M includes an n-type impurity having a lower concentration than a concentration of an n-type impurity included in other portion of the n-type semiconductor layer 11. The p-type semiconductor layer 13 includes a low-concentration portion 13M. The low concentration portion 13M includes a p-type impurity having a lower concentration than a concentration of a p-type impurity contained in other portion of the p-type semiconductor layer 13. The position (level) in the Z direction of the low concentration portion 11M in the n type semiconductor layer 11 is the same as the position (level) in the Z direction of the low concentration portion 13M in the p-type semiconductor layer 13.
  • The n-type impurity concentration in the low density portion 11M is, for example, 1×1015 cm−3 or more and 1×1016 cm−3 or less. On the other hand, the n-type impurity concentration in the other portion of the n-type semiconductor layer 11 is 1×1016 cm−3 or more. Further, the p-type impurity concentration in the low concentration portion 13M is, for example, 1×1015 cm−3 or more and 1×1016 cm−3 or less. On the other hand, the p-type impurity concentration in the other portion of the p-type semiconductor layer 13 is 1×1016 cm−3 or more.
  • The semiconductor portion 10 further includes a p-type diffusion layer 15, an n-type source layer 17, a p-type contact layer 19, and an n-type drain layer 35.
  • The p-type diffusion layer 15 is provided between the p-type semiconductor layer 13 and the source electrode 20. The p-type diffusion layer 15 includes, for example, a p-type impurity having a higher concentration than a concentration of a p-type impurity in the p-type semiconductor layer 13. The p-type diffusion layer 15 is electrically connected to, for example, the p-type semiconductor layer 13.
  • The n-type source layer 17 is selectively provided between the p-type diffusion layer 15 and the source electrode 20. The n-type source layer 17 includes, for example, an n-type impurity having a higher concentration than a concentration of an n-type impurity in the n-type semiconductor layer 11.
  • The p-type contact layer 19 is selectively provided between the p-type diffusion layer 15 and the source electrode 20. The p-type contact layer 19 and the n-type source layer 17 are arranged along the top surface of the semiconductor portion 10. The source electrode 20 is provided so as to be electrically connected to a portion of the n-type source layer 17 and the p-type contact layer 19. The p-type contact layer 19, for example, includes a p-type impurity having a higher concentration than a concentration of a p-type impurity in the p-type diffusion layer 15, and electrically connects the p-type diffusion layer 15 and the source electrode 20.
  • The gate electrode 40 is positioned, for example, between the n-type semiconductor layer 11 and the source electrode 20. The gate electrode 40 is provided so as to face part of the n-type semiconductor layer 11 and the p-type diffusion layer 15 with the gate insulating film 43 interposed. That is, when the gate bias is applied, the gate electrode 40 is provided so that an n-type inversion layer is formed on the surface of the p-type diffusion layer 15, and the n-type semiconductor layer 11 and the n-type source layer 17 are electrically conducted.
  • The n-type drain layer 35 is provided between the n-type semiconductor layer 11 and the drain electrode 30 and between the p-type semiconductor layer 13 and the drain electrode 30. The n-type drain layer 35 includes, for example, an n-type impurity having a higher concentration than the concentration of the n-type impurity in the n-type semiconductor layer 11. The n-type drain layer 35 is electrically connected to the drain electrode 30, for example.
  • Next, a method of manufacturing the semiconductor device 1 according to the embodiment is described with reference to FIGS. 3A to 4B. FIGS. 3A to 4B are schematic cross-sectional views sequentially showing the manufacturing process of the semiconductor device 1.
  • As shown in FIG. 3A, a semiconductor layer 101 is formed on the semiconductor substrate SS. The semiconductor substrate SS is, for example, an n-type silicon wafer. The semiconductor layer 101 is, for example, a silicon layer epitaxially grown on the n-type silicon wafer. The semiconductor layer 101 is, for example, a so-called undoped layer grown under the condition in which no impurity is added. The semiconductor layer 101 includes, for example, an n-type impurity, or a p-type impurity, or both at the background level.
  • Subsequently, an n-type impurity and a p-type impurity are selectively ion-implanted into the semiconductor layer 101 using an implantation mask (not shown) to form an n-type implantation region NR and a p-type implantation region PR. The amount of n-type impurity introduced into the n-type implantation region NR is controlled by the dose amount of the n-type impurity and the width LN of the n-type implantation region NR (the opening width of the implantation mask). The amount of p-type impurity introduced into the p-type implantation region PR is controlled by the dose amount of the p-type impurity and the width LP of the p-type implantation region PR (the opening width of the implantation mask). The n-type impurity introduced into the n-type implantation region NR is controlled, for example, to be the same amount as that of the p-type impurity introduced into the p-type implantation region PR.
  • As shown in FIG. 3B, a semiconductor layer 103 is formed on the semiconductor layer 101. The semiconductor layer 103 is, for example, a silicon layer and is an undoped layer to which no impurity is added. Subsequently, an n-type impurity and a p-type impurity are selectively ion-implanted into the semiconductor layer 103 to form an n-type implantation region NR and a p-type implantation region PR. The n-type implantation region NR of the semiconductor layer 103 is formed immediately above the n-type implantation region NR of the semiconductor layer 101. The p-type implantation region PR of the semiconductor layer 103 is formed immediately above the p-type implantation region PR of the semiconductor layer 101. Also in this case, the n-type impurity introduced into the n-type implantation region NR is controlled to be, for example, the same amount as that of the p-type impurity introduced into the p-type implantation region PR.
  • As shown in FIG. 3C, a semiconductor layer 105 is formed on the semiconductor layer 103. The semiconductor layer 105 is, for example, a silicon layer, and is an undoped layer to which no impurity is added. Subsequently, an n-type impurity and a p-type impurity are selectively ion-implanted into the semiconductor layer 105 to form an n-type implantation region NR and a p-type implantation region PR. The n-type implantation region NR of the semiconductor layer 105 is formed immediately above the n-type implantation region NR of the semiconductor layer 103. The p-type implantation region PR of the semiconductor layer 105 is formed immediately above the p-type implantation region PR of the semiconductor layer 103. The n-type impurity introduced into the n-type implantation region NR of the semiconductor layer 105 is controlled, for example, to be the same amount as that of the p-type impurity introduced in the p-type implantation region PR of the semiconductor layer 105.
  • FIG. 4A is a schematic view showing a cross section of a stacked body 110. The stacked body 110 is formed by repeating the growth of an undoped semiconductor layer and the ion implantation of an n-type impurity and a p-type impurity. The stacked body 110 includes semiconductor layers 101, 103, 105, 107, 109, 111, 113, 115, 117 and 119 stacked on a semiconductor substrate SS.
  • The n-type implantation region NR and the p-type implantation region PR are formed in each semiconductor layer except the semiconductor layer 119. Neither the n-type impurity nor the p-type impurity is ion-implanted into the uppermost semiconductor layer 119. The semiconductor layer 119 is an undoped layer or an n-type layer in which an n-type impurity is doped during epitaxial growth so as to have the predetermined n-type impurity concentration.
  • As shown in FIG. 4A, the n-type implantation region NR and the p-type implantation region PR are formed so as to be arranged in the Z direction. The n-type implantation region NR formed in the semiconductor layer 113 is formed to include the n-type impurity having a smaller amount than an amount of the n-type impurity in the n-type implantation region NR that is formed in the other semiconductor layer. In addition, the p-type implantation region PR formed in the semiconductor layer 113 is formed so as to include the p-type impurity having a smaller amount than an amount of the p-type impurity in the p-type implantation region PR that is formed in the other semiconductor layer.
  • The amount of the n-type impurity introduced into the n-type implantation region NR formed in the semiconductor layer 113 is the same as the amount of the p-type impurity introduced into the p-type implantation region PR formed in the semiconductor layer 113. For example, the amount of impurities at the background level in the semiconductor layer 113 is one or more orders of magnitude less than the amount of the ion-implanted n-type impurity or the ion-implanted p-type impurity. Thus, in the semiconductor layer 113, when the amount of the n-type impurity in the n-type implantation region NR is the same as the amount of the p-type impurity in the p-type implantation region PR, the total amount of n-type impurities is substantially the same as the total amount of p-type impurities in the n-type implantation region NR and the p-type implantation region PR that are adjacent to each other in the X-direction. That is, the total amount of n-type impurities is balanced with the total amount of p-type impurities.
  • In each semiconductor layer excluding the semiconductor layers 113 and 119, the amount of n-type impurity in the n-type implantation region NR is substantially the same as the p-type impurity amount in the p-type implantation region PR. In other words, in each semiconductor layer excluding the semiconductor layers 113 and 119, the total amount of n-type impurities in the n-type implantation region NR and p-type implantation region PR adjacent to each other is balanced with the total amount of p-type impurities therein.
  • As shown in FIG. 4B, the n-type semiconductor layer 11 and the p-type semiconductor layer 13 are formed in the stacked body 110. The n-type semiconductor layer 11 and the p-type semiconductor layer 13 are formed by activating the ion-implanted n-type impurity and p-type impurity by heat treatment. In FIG. 4B, the semiconductor layers 101 to 119 are integrally shown as one semiconductor layer.
  • In the n-type semiconductor layer 11, a low concentration portion 11M is formed at a level corresponding to the position of the semiconductor layer 113. In the p-type semiconductor layer 13, a low concentration portion 13M is formed at a level corresponding to the position of the semiconductor layer 113.
  • Thereafter, a p-type diffusion layer 15, an n-type source layer 17 and a p-type contact layer 19 (see FIG. 1) are formed in a region corresponding to the uppermost semiconductor layer 119. Subsequently, after forming the gate electrode 40 and the source electrode 20, for example, the semiconductor substrate SS is thinned to form an n-type drain region 35. Further, the drain electrode 30 is formed to complete the semiconductor device 1.
  • FIGS. 5A and 5B are schematic views showing a testing method of the semiconductor device 1 according to the embodiment. FIG. 5A is a schematic view showing the test apparatus. FIG. 5B is a time chart showing the drain voltage Vds, the electron current Id(e), the hole current Id(h), and the drain current Id.
  • As shown in FIG. 5A, a voltage is applied from the power supply VCL via the inductance L between the source electrode 20 and the drain electrode 30 of the semiconductor device 1. A gate bias VGF is applied to the gate electrode 40 of the semiconductor device 1. For example, the gate bias VGF is a pulse voltage having a constant cycle, and performs the ON/OFF control in the semiconductor device 1.
  • As shown in FIG. 5B, the drain voltage Vds applied between the source and drain varies corresponding to the period of the gate bias VGF. The drain current Id also varies corresponding thereto.
  • For example, when the gate bias higher than the threshold voltage is applied to the gate electrode 40, the n-type inversion layer is induced at the interface between the gate insulating film 43 and the p-type diffusion layer 15, and the n-type semiconductor layer 11 and the n-type source layer 17 are electrically conducted (see FIG. 1). In contrast, when the gate bias falls below the threshold value and the semiconductor device 1 is turned off, the n-type inversion layer disappears and the electrical conduction is interrupted between the n-type semiconductor layer 11 and the n-type source layer 17 (see FIG. 1). At this time, space charges remaining in the n-type semiconductor layer 11 are discharged to the source electrode 20 via the p-type diffusion layer 15 and discharged to the drain electrode 30 via the n-type drain layer 35.
  • For example, when the semiconductor device 1 is turned off, the n-type semiconductor layer 11 and the p-type semiconductor layer 13 are depleted, and high electric field is induced between the p-type diffusion layer 15 and the n-type drain layer 35. For example, the electrons in the n-type semiconductor layer 11 are accelerated by the electric field, collide with the lattice atoms constituting the n-type semiconductor layer 11, and ionize the lattice atoms. Thereby, new electron-hole pairs are generated. The number of electrons and holes in the depletion layer increases as this process continues, and the avalanche current flows.
  • At this time, when the electron current Id(e) by the electrons discharged to the drain electrode 30 through the n-type drain layer 35 and the hole current Id(h) by the holes discharged to the source electrode 20 via the p-type diffusion layer 15 have phases that coincide with each other, the avalanche current resonance occurs and the excessive current flows. Thus, there may be a case where the semiconductor device 1 is destroyed. Even when the semiconductor device 1 is not destroyed, it is difficult to avoid EMI.
  • The electron current Id(e) and the hole current Id(h) may have the same phases, for example, in the case where the time required for the electrons generated by the impact-ionization to reach the n-type drain layer 35 coincides with the time required for the holes to reach the p-type diffusion layer 15. In order to avoid this, for example, it is preferable to make the impact-ionization occur at a position in the n-type semiconductor layer 11 different from the position where the electron and hole generated by the impact-ionization simultaneously reach the n-type drain layer 35 and the p-type diffusion layer 15, respectively.
  • In the embodiment, it is possible to suppress the impact-ionization by reducing the electric field in the low concentration portion 11M provided in the n-type semiconductor layer 11. Further, the charge balance in the n-type semiconductor layer 11 and the p-type semiconductor layer 13 is maintained by providing the low concentration portion 13M in the p-type semiconductor layer 13. Thereby, it is possible to make the n-type semiconductor layer 11 and the p-type semiconductor layer 13 being uniformly depleted, and prevent the electric field concentration in the vicinity of the low concentration portion 11 M and the low concentration portion 13 M. As a result, it is possible to reduce electrons and holes simultaneously reaching the n-type drain layer 35 and the p-type diffusion layer 15, thereby avoiding the avalanche current oscillation.
  • For example, distances Lh and Le is provided in the p-type semiconductor layer 13. The distance Lh is defined as a distance from the low-density portion 13 M to the p-type diffusion layer 15, and the distance Le is defined as a distance from the low-density portion 13M to the end 13 e of the p-type semiconductor layer 13 on the drain electrode side (See FIG. 1). For example, the mobility of electrons in silicon is greater than the mobility of holes in silicon. Thus, by making the distance Le longer than the distance Lh, it is possible to reduce the electric field at the position where electrons and holes are generated and simultaneously reach the n-type drain layer 35 and the p-type diffusion layer 15. Thereby, the avalanche current oscillation can be suppressed.
  • For example, in a low electric field region where the electron mobility in silicon does not reach the saturation value, the electron mobility is roughly three times the hole mobility. Therefore, it is preferable that the distance Le be three times the distance Lh. In the high electric field region where the electron mobility in silicon reaches the saturation value, the ratio of the electron mobility to the hole mobility is 1:0.6. Therefore, the ratio of the distance Le to the distance Lh is preferable to be set to 1:0.6. That is, it is more preferable that the ratio of the distance Le to the distance Lh is set to be the same as or substantially the same as the ratio of the electron mobility to the hole mobility.
  • While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.

Claims (5)

What is claimed is:
1. A method for manufacturing a semiconductor device, the method comprising:
selectively ion-implanting a first conductive type impurity into a first region of a first semiconductor layer, the first conductive type impurity having a first amount in the first region of the first semiconductor layer;
selectively ion-implanting a second conductive type impurity into a second region of the first semiconductor layer, the second conductive type impurity having the same amount in the second region of the first semiconductor layer as the first amount of the first conductive type impurity in the first region of the first semiconductor layer, the second region being adjacent in a first direction along a top surface of the first semiconductor layer;
forming a second semiconductor layer on the top surface of the first semiconductor layer;
selectively ion-implanting a first conductive type impurity into a first region of the second semiconductor layer, the first region of the second semiconductor layer being positioned above the first region of the first semiconductor layer, the first conductive type impurity having a second amount in the first region of the second semiconductor layer, the second amount being less than the first amount;
selectively ion-implanting a second conductive type impurity into a second region of the second semiconductor layer, the second region of the second semiconductor layer being positioned above the second region of the first semiconductor layer, the second conductive type impurity having the same amount in the second region of the second semiconductor layer as the second amount of the first conductive type impurity in the first region of the second semiconductor layer,
forming a third semiconductor layer on the second semiconductor layer;
selectively ion-implanting a first conductive type impurity into a first region of the third semiconductor layer, the first region of the third semiconductor layer being positioned above the first region of the second semiconductor layer, the first conductive type impurity having a third amount in the first region of the third semiconductor layer, the third amount being more than the second amount;
selectively ion-implanting a second conductive type impurity into a second region of the third semiconductor layer, the second region of the third semiconductor layer being positioned above the second region of the second semiconductor layer, the second conductive type impurity having the same amount in the second region of the third semiconductor layer as the third amount of the first conductive type impurity in the first region of the third semiconductor layer.
2. The method according claim 1, wherein
the first semiconductor layer is formed in a plurality, the plurality of first semiconductor layers being stacked in a second direction crossing the first direction, the plurality of first semiconductor layers each including the first region and the second region, the first region including the first conductive type impurity, the second region including the second conductive type impurity;
the second semiconductor layer being formed on an uppermost first semiconductor layer of the plurality of first semiconductor layer;
the third semiconductor layer is formed in a plurality, the plurality of third semiconductor layer being stacked in the second direction on the second semiconductor layer, the plurality of third semiconductor layers each including the first region and the second region, the first region including the first conductive type impurity, the second region including the second conductive type impurity; and
the first regions and the second regions are aligned respectively in the second direction.
3. The method according claim 2, wherein
the plurality of first semiconductor layers has a first stacked width in the second direction;
the plurality of second semiconductor layers has a second stacked width in the second direction; and
the first stacked width is wider than the second stacked width.
4. The method according claim 2, wherein
the plurality of first semiconductor layers has a first stacked width in the second direction;
the plurality of second semiconductor layers has a second stacked width in the second direction; and
a ratio of the second stacked width to the first stacked width is 1:3.
5. The method according claim 2, wherein
the plurality of first semiconductor layers has a first stacked width in the second direction;
the plurality of second semiconductor layers has a second stacked width in the second direction; and
a ratio of the second stacked width to the first stacked width is 0.6:3.
US17/193,830 2018-09-11 2021-03-05 Semiconductor device and method for manufacturing the same Abandoned US20210193835A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/193,830 US20210193835A1 (en) 2018-09-11 2021-03-05 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2018-169710 2018-09-11
JP2018169710A JP6833778B2 (en) 2018-09-11 2018-09-11 Semiconductor device
US16/357,567 US10971623B2 (en) 2018-09-11 2019-03-19 Semiconductor device and method for manufacturing the same
US17/193,830 US20210193835A1 (en) 2018-09-11 2021-03-05 Semiconductor device and method for manufacturing the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US16/357,567 Division US10971623B2 (en) 2018-09-11 2019-03-19 Semiconductor device and method for manufacturing the same

Publications (1)

Publication Number Publication Date
US20210193835A1 true US20210193835A1 (en) 2021-06-24

Family

ID=69718925

Family Applications (2)

Application Number Title Priority Date Filing Date
US16/357,567 Active US10971623B2 (en) 2018-09-11 2019-03-19 Semiconductor device and method for manufacturing the same
US17/193,830 Abandoned US20210193835A1 (en) 2018-09-11 2021-03-05 Semiconductor device and method for manufacturing the same

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US16/357,567 Active US10971623B2 (en) 2018-09-11 2019-03-19 Semiconductor device and method for manufacturing the same

Country Status (2)

Country Link
US (2) US10971623B2 (en)
JP (1) JP6833778B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11616123B2 (en) * 2021-02-12 2023-03-28 Alpha And Omega Semiconductor International Lp Enhancement on-state power semiconductor device characteristics utilizing new cell geometries

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4843843B2 (en) * 2000-10-20 2011-12-21 富士電機株式会社 Super junction semiconductor device
US6821824B2 (en) 2001-02-21 2004-11-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
DE102006061994B4 (en) 2006-12-21 2011-05-05 Infineon Technologies Austria Ag Charge compensation device with a drift path between two electrodes and method for producing the same
JP4564509B2 (en) 2007-04-05 2010-10-20 株式会社東芝 Power semiconductor device
JP2010045307A (en) 2008-08-18 2010-02-25 Toshiba Corp Semiconductor device for electric power
JP5863574B2 (en) * 2012-06-20 2016-02-16 株式会社東芝 Semiconductor device

Also Published As

Publication number Publication date
JP2020043231A (en) 2020-03-19
US20200083372A1 (en) 2020-03-12
US10971623B2 (en) 2021-04-06
JP6833778B2 (en) 2021-02-24

Similar Documents

Publication Publication Date Title
US6946705B2 (en) Lateral short-channel DMOS, method of manufacturing the same, and semiconductor device
US8247286B2 (en) Semiconductor device having transistor and method of manufacturing the same
CN113498544B (en) Silicon carbide semiconductor device and method for manufacturing same
JP6880669B2 (en) Silicon Carbide Semiconductor Device and Method for Manufacturing Silicon Carbide Semiconductor Device
CN101375402B (en) Transverse SOI semiconductor devices and manufacturing method thereof
US20080217684A1 (en) Semiconductor device and manufacturing method thereof and power supply apparatus using the same
US20130161740A1 (en) Lateral High-Voltage Transistor with Buried Resurf Layer and Associated Method for Manufacturing the Same
SE542607C2 (en) MOSFET in SiC with self-aligned lateral MOS channel
US10249717B2 (en) Semiconductor device and method for manufacturing the same
US9608057B2 (en) Semiconductor device and method for manufacturing semiconductor device
KR20060121983A (en) High voltage pmos transistor
CN113196500B (en) Semiconductor device and method for manufacturing the same
US20110073962A1 (en) Method and apparatus for forming a semiconductor gate
US20210193835A1 (en) Semiconductor device and method for manufacturing the same
US8686500B2 (en) Double diffused metal oxide semiconductor device and manufacturing method thereof
KR102424768B1 (en) P-type LATERAL DOUBLE DIFFUSED MOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
US20200083320A1 (en) Semiconductor device
US10957768B1 (en) Silicon carbide device with an implantation tail compensation region
JP2011211078A (en) Semiconductor device and method of manufacturing the same
US20160071940A1 (en) Semiconductor device
CN111969060B (en) Semiconductor device and manufacturing method thereof
CN111463284A (en) N-type FET and method of manufacturing the same
KR20130073776A (en) Ldmos transistor device and preparing method of the same
US20170040414A1 (en) Semiconductor device
KR102359373B1 (en) Method of fabricating a high voltage semiconductor device

Legal Events

Date Code Title Description
STPP Information on status: patent application and granting procedure in general

Free format text: APPLICATION DISPATCHED FROM PREEXAM, NOT YET DOCKETED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION