US20210183695A1 - Method for fabricating a semiconductor device - Google Patents

Method for fabricating a semiconductor device Download PDF

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Publication number
US20210183695A1
US20210183695A1 US16/712,203 US201916712203A US2021183695A1 US 20210183695 A1 US20210183695 A1 US 20210183695A1 US 201916712203 A US201916712203 A US 201916712203A US 2021183695 A1 US2021183695 A1 US 2021183695A1
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Prior art keywords
etch stop
trench
dielectric layer
partial
top plate
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US16/712,203
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US11049764B1 (en
Inventor
Jung-Che Chang
Bao-Tzeng Huang
Yu-Hong Huang
Siou-Cyun LIN
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United Microelectronics Corp
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United Microelectronics Corp
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Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG, JUNG-CHE, HUANG, BAO-TZENG, HUANG, Yu-hong, LIN, SIOU-CYUN
Publication of US20210183695A1 publication Critical patent/US20210183695A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors

Definitions

  • the invention relates in general to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a semiconductor device including a semiconductor element.
  • a process for fabricating interconnections in the semiconductor device is quite critical.
  • a dual damascene process is one of methods for providing interconnections to connect the numerous layers of metallization in the semiconductor device.
  • a via may be formed first, and then a trench connected to the via may be formed.
  • a metal layer below the via may be damaged simultaneously.
  • GFP gap fill plug
  • the invention is directed to a method for fabricating a semiconductor device.
  • a first partial via corresponding to a bottom metal is formed and separated from the bottom metal by a first dielectric layer
  • a second partial via corresponding to a top plate in the semiconductor element is formed and separated from the top plate by an etch stop pad disposed on the top plate.
  • the first partial via is not directly connected to the bottom metal
  • the second partial via is not directly connected to the top plate, either.
  • the first dielectric layer can protect the bottom metal from being damaged
  • the etch stop pad can protect the top plate from being damaged. In this way, a gap fill plug (GFP) process can be omitted, and the cost can be reduced.
  • GFP gap fill plug
  • a method for fabricating a semiconductor device comprises: providing a substrate having a top surface; forming a bottom metal embedded in the substrate; forming a first etch stop layer, a first dielectric layer, a second etch stop layer and a second dielectric layer sequentially stacked on the top surface of the substrate; forming a semiconductor element disposed on the first etch stop layer, wherein the semiconductor element comprises a top plate and an etch stop pad disposed on the top plate; performing a first etching process to form a first partial via and a second partial via penetrating the second dielectric layer, the second etch stop layer and a portion of the first dielectric layer, wherein the first partial via is separated from the bottom metal by the first dielectric layer, and the second partial via is separated from the top plate by the etch stop pad.
  • FIGS. 1-5 are cross-sectional views showing a process for fabricating a semiconductor device according to an embodiment of the invention.
  • FIG. 6 is a cross-sectional view showing a semiconductor device according to another embodiment of the invention.
  • an improved method for fabricating a semiconductor device is provided.
  • a first partial via and a second partial via are formed.
  • a first dielectric layer disposed below the first partial via can protect the bottom metal from being damaged
  • the etch stop pad disposed below the second partial via can protect the top plate from being damaged. Therefore, the remained first dielectric layer and the remained etch stop pad can replace the gap fill plug (GFP) process, and the cost can be reduced, the semiconductor device having an excellent electrical property (such as having good quality of interconnections) can be formed.
  • GFP gap fill plug
  • a preliminary structure 10 ′ is provided.
  • the preliminary structure 10 ′ may be formed in the following steps. Firstly, a substrate 100 is provided. A bottom metal BM is embedded in the substrate 100 . Then, a first etch stop layer 110 , a first dielectric layer 112 , a second etch stop layer 114 and a second dielectric layer 116 are sequentially stacked on a top surface 100 a of the substrate 100 . A semiconductor element 120 is disposed on the first etch stop layer 110 and is covered by the first dielectric layer 112 .
  • the semiconductor element 120 may be a resistor, a capacitor or other suitable semiconductor element.
  • the semiconductor element 120 is a capacitor, but the present invention is no limited thereto.
  • the semiconductor element 120 includes a bottom plate 128 , a top plate 124 disposed on the bottom plate 128 , a dielectric film 126 disposed between the top plate 124 and the bottom plate 128 , and an etch stop pad 122 disposed on the top plate 124 .
  • the bottom plate 128 may have a width larger than that of the top plate 124 in a direction parallel to the top surface 100 a of the substrate 100 , but the present invention is not limited thereto.
  • a protruding portion 128 p of the bottom plate 128 may be non-overlapped with the top plate 124 in the normal direction N of the top surface.
  • the bottom metal BM and the semiconductor element 120 may be non-overlapping in a normal direction N of the top surface 100 a of the substrate 100 , but the present invention is not limited thereto.
  • the substrate 100 may include silicon, germanium or other suitable material.
  • the substrate 100 may include an epitaxial layer, doped regions, isolation features or other suitable structures.
  • the first etch stop layer 110 and the second etch stop layer 114 may include nitride or other suitable material.
  • the first dielectric layer 112 and the second dielectric layer 116 may include oxide or other suitable material.
  • the first etch stop layer 110 and the second etch stop layer 114 may be SiN or SiON, and the first dielectric layer 112 and the second dielectric layer 116 may be SiO 2 .
  • a first etching process is performed to form a first partial via 1302 , a second partial via 1304 and a third partial via 1306 penetrating the second dielectric layer 116 , the second etch stop layer 114 and a portion of the first dielectric layer 112 .
  • the first partial via 1302 , the second partial vial 304 and the third partial via 1306 may have a same depth.
  • the first partial via 1302 may be overlapped with the bottom metal BM in the normal direction N of the top surface 100 a of the substrate 100 .
  • the second partial via 1304 may be overlapped with the top plate 124 in the normal direction N of the top surface 100 a of the substrate 100 .
  • the third partial via 1306 may be overlapped with the bottom plate 128 (such as the protruding portion 128 p ) in the normal direction N of the top surface 100 a of the substrate 100 .
  • the first partial via 1302 is separated from the bottom metal BM by the first etch stop layer 110 and the first dielectric layer 112 .
  • the second partial via 1304 is separated from the top plate 124 by the etch stop pad 122 .
  • the third partial via 1306 is separated from the bottom plate 128 by the first dielectric layer 112 .
  • the second partial via 1304 is separated from the top plate 124 by both of the etch stop pad 122 and a portion of the first dielectric layer 112 .
  • a second etching process is performed to transfer the first partial via 1302 into a first trench 1312 a and a first extending via 1312 b connected to the first trench 1312 a, transfer the second partial via 1304 into a second trench 1314 a and a second extending via 1314 b connected to the second trench 1314 a, and transfer the third partial via 1306 into a third trench 1316 a and a third extending via 1316 b connected to the third trench 1316 a.
  • the first trench 1312 a, the second trench 1314 a and the third trench 1316 b may have a width in a direction parallel to the top surface 100 a greater than that of the first extending via 1312 b, the second extending via 1314 b and the third extending via 1316 b, respectively.
  • the bottom metal BM, the bottom plate 128 and the top plate 124 can be protected by the remained first dielectric layer 112 and the remained etch stop pad 122 during the second etching process.
  • the second etching process has a first etching rate to the first dielectric layer 112 and a second etching rate to the etch stop pad 122 , and the first etching rate is greater than the second etching rate. That is, each of the first extending via 1312 b and the third extending via 1316 b may have a depth greater than that of the second extending via 1314 b. The second extending via 1314 b may be separated from the top plate 124 by a remaining portion of the etch stop pad 122 .
  • a punch through process is performed to extend the first extending via 1312 b to become a first penetrating via 1312 c connected to the bottom metal BM, extend the second extending via 1314 b to become a second penetrating via 1314 c connected to the top plate 124 , and extend the third extending via 1316 b to become a third penetrating via 1316 c connected to the bottom plate 128 .
  • the bottom metal BM is exposed from the first trench 1312 a and the first penetrating via 1312 c
  • the top plate 124 is exposed from the second trench 1314 a and the second penetrating via 1314 c
  • the bottom plate 128 is exposed from the third trench 1316 a and the third penetrating via 1316 c.
  • a deposition process is performed to fill a conductive material into the first trench 1312 a, the first penetrating via 1312 c, the second trench 1314 a, the second penetrating via 1314 c, the third trench 1316 a, and the third penetrating via 1316 c.
  • the conductive material may include tungsten, copper or other suitable conductive materials.
  • a first interconnection 1322 electrically connected to the bottom metal BM, a second interconnection 1324 electrically connected to the top plate 124 , and a third interconnection electrically connected to the bottom plate 128 are formed, and the semiconductor device 10 including the semiconductor element 120 is formed.
  • FIG. 6 is a cross-sectional view showing a semiconductor device 20 according to another embodiment of the invention.
  • the semiconductor device 20 is similar to the semiconductor device 10 , the difference is in that the semiconductor element 220 includes the etch stop pad 222 and the top plate 224 , but not include the bottom plate.
  • the semiconductor device 20 includes a substrate 100 ; a bottom metal BM embedded in the substrate 100 ; a first etch stop layer 110 , a first dielectric layer 212 , a second etch stop layer 214 and a second dielectric layer 216 sequentially stacked on a top surface 100 a of the substrate 100 ; a semiconductor element 220 disposed on the first etch stop layer 110 , wherein the semiconductor element 220 includes a top plate 224 and an etch stop pad 222 disposed on the top plate 224 ; a first interconnection 2322 electrically connected to the bottom metal BM; and a second interconnection 2324 electrically connected to the top plate 224 .
  • the semiconductor element 220 may be a resistor.
  • the methods for fabricating the first interconnection 2322 and the second interconnection 2324 are similar to that of the first interconnection 1322 and the second interconnection 1324 , respectively, and the repetitive description is omitted herein.
  • a method for fabricating a semiconductor device comprises: providing a substrate having a top surface; forming a bottom metal embedded in the substrate; forming a first etch stop layer, a first dielectric layer, a second etch stop layer and a second dielectric layer sequentially stacked on the top surface of the substrate; forming a semiconductor element disposed on the first etch stop layer, wherein the semiconductor element comprises a top plate and an etch stop pad disposed on the top plate; performing a first etching process to form a first partial via and a second partial via penetrating the second dielectric layer, the second etch stop layer and a portion of the first dielectric layer, wherein the first partial via is separated from the bottom metal by the first dielectric layer, and the second partial via is separated from the top plate by the etch stop pad.
  • the semiconductor device including the semiconductor element can be made by a simple and cost saving process, and can have an excellent electrical property, such as having good quality of interconnections.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for fabricating a semiconductor device comprises: providing a substrate having a top surface; forming a bottom metal embedded in the substrate; forming a first etch stop layer, a first dielectric layer, a second etch stop layer and a second dielectric layer sequentially stacked on the top surface of the substrate; forming a semiconductor element disposed on the first etch stop layer, wherein the semiconductor element comprises a top plate and an etch stop pad disposed on the top plate; performing a first etching process to form a first partial via and a second partial via penetrating the second dielectric layer, the second etch stop layer and a portion of the first dielectric layer, wherein the first partial via is separated from the bottom metal by the first dielectric layer, and the second partial via is separated from the top plate by the etch stop pad.

Description

    BACKGROUND OF THE INVENTION Field of the Invention
  • The invention relates in general to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a semiconductor device including a semiconductor element.
    • Description of the Related Art
  • With a trend toward scaling down the size of the semiconductor device, a process for fabricating interconnections in the semiconductor device is quite critical. For example, a dual damascene process is one of methods for providing interconnections to connect the numerous layers of metallization in the semiconductor device.
  • In the conventional dual damascene process, a via may be formed first, and then a trench connected to the via may be formed. However, if an etching process for forming the trench is not well-controlled, a metal layer below the via may be damaged simultaneously. Although a gap fill plug (GFP) process can be used to provide a resist layer in the via for protecting the metal layer below the via during forming the trench, the additional step will increase the cost and the time.
  • Therefore, there is a need for developing an improved method for fabricating interconnections in the semiconductor device.
    • SUMMARY OF THE INVENTION
  • The invention is directed to a method for fabricating a semiconductor device. In the present application, during fabricating a semiconductor device including a semiconductor element, a first partial via corresponding to a bottom metal is formed and separated from the bottom metal by a first dielectric layer, and a second partial via corresponding to a top plate in the semiconductor element is formed and separated from the top plate by an etch stop pad disposed on the top plate. In other words, the first partial via is not directly connected to the bottom metal and the second partial via is not directly connected to the top plate, either. Thus, in the following step of forming trenches connected to the first partial via and the second partial via, the first dielectric layer can protect the bottom metal from being damaged, and the etch stop pad can protect the top plate from being damaged. In this way, a gap fill plug (GFP) process can be omitted, and the cost can be reduced.
  • According to an aspect of the present invention, a method for fabricating a semiconductor device is provided. The method comprises: providing a substrate having a top surface; forming a bottom metal embedded in the substrate; forming a first etch stop layer, a first dielectric layer, a second etch stop layer and a second dielectric layer sequentially stacked on the top surface of the substrate; forming a semiconductor element disposed on the first etch stop layer, wherein the semiconductor element comprises a top plate and an etch stop pad disposed on the top plate; performing a first etching process to form a first partial via and a second partial via penetrating the second dielectric layer, the second etch stop layer and a portion of the first dielectric layer, wherein the first partial via is separated from the bottom metal by the first dielectric layer, and the second partial via is separated from the top plate by the etch stop pad.
  • The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1-5 are cross-sectional views showing a process for fabricating a semiconductor device according to an embodiment of the invention.
  • FIG. 6 is a cross-sectional view showing a semiconductor device according to another embodiment of the invention.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • Use of ordinal terms such as “first”, “second”, “third”, etc., in the specification and claims to modify an element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having the same name (but for use of the ordinal term) to distinguish the claim elements.
  • The present specification provides various embodiments to illustrate the technical features of various embodiments of the present invention. The arrangement of the components in the embodiments is for illustrative purposes and is not intended to limit the invention.
  • In the present application, an improved method for fabricating a semiconductor device is provided. In particular, during fabricating a semiconductor device including a semiconductor element, a first partial via and a second partial via are formed. Thus, in the following step of forming trenches connected to the first partial via and the second partial via, a first dielectric layer disposed below the first partial via can protect the bottom metal from being damaged, and the etch stop pad disposed below the second partial via can protect the top plate from being damaged. Therefore, the remained first dielectric layer and the remained etch stop pad can replace the gap fill plug (GFP) process, and the cost can be reduced, the semiconductor device having an excellent electrical property (such as having good quality of interconnections) can be formed.
  • Referring to FIG. 1, a preliminary structure 10′ is provided. The preliminary structure 10′ may be formed in the following steps. Firstly, a substrate 100 is provided. A bottom metal BM is embedded in the substrate 100. Then, a first etch stop layer 110, a first dielectric layer 112, a second etch stop layer 114 and a second dielectric layer 116 are sequentially stacked on a top surface 100 a of the substrate 100. A semiconductor element 120 is disposed on the first etch stop layer 110 and is covered by the first dielectric layer 112.
  • In some embodiments, the semiconductor element 120 may be a resistor, a capacitor or other suitable semiconductor element. In the present embodiment, the semiconductor element 120 is a capacitor, but the present invention is no limited thereto.
  • In the present embodiment, the semiconductor element 120 includes a bottom plate 128, a top plate 124 disposed on the bottom plate 128, a dielectric film 126 disposed between the top plate 124 and the bottom plate 128, and an etch stop pad 122 disposed on the top plate 124. In some embodiments, the bottom plate 128 may have a width larger than that of the top plate 124 in a direction parallel to the top surface 100 a of the substrate 100, but the present invention is not limited thereto. A protruding portion 128 p of the bottom plate 128 may be non-overlapped with the top plate 124 in the normal direction N of the top surface.
  • In the present embodiment, the bottom metal BM and the semiconductor element 120 may be non-overlapping in a normal direction N of the top surface 100 a of the substrate 100, but the present invention is not limited thereto.
  • In some embodiments, the substrate 100 may include silicon, germanium or other suitable material. The substrate 100 may include an epitaxial layer, doped regions, isolation features or other suitable structures. The first etch stop layer 110 and the second etch stop layer 114 may include nitride or other suitable material. The first dielectric layer 112 and the second dielectric layer 116 may include oxide or other suitable material. For example, the first etch stop layer 110 and the second etch stop layer 114 may be SiN or SiON, and the first dielectric layer 112 and the second dielectric layer 116 may be SiO2.
  • Referring to FIG. 2, a first etching process is performed to form a first partial via 1302, a second partial via 1304 and a third partial via 1306 penetrating the second dielectric layer 116, the second etch stop layer 114 and a portion of the first dielectric layer 112. The first partial via 1302, the second partial vial 304 and the third partial via 1306 may have a same depth. The first partial via 1302 may be overlapped with the bottom metal BM in the normal direction N of the top surface 100 a of the substrate 100. The second partial via 1304 may be overlapped with the top plate 124 in the normal direction N of the top surface 100 a of the substrate 100. The third partial via 1306 may be overlapped with the bottom plate 128 (such as the protruding portion 128 p) in the normal direction N of the top surface 100 a of the substrate 100.
  • More specifically, the first partial via 1302 is separated from the bottom metal BM by the first etch stop layer 110 and the first dielectric layer 112. The second partial via 1304 is separated from the top plate 124 by the etch stop pad 122. The third partial via 1306 is separated from the bottom plate 128 by the first dielectric layer 112. In some embodiments, the second partial via 1304 is separated from the top plate 124 by both of the etch stop pad 122 and a portion of the first dielectric layer 112.
  • Referring to FIG. 3, a second etching process is performed to transfer the first partial via 1302 into a first trench 1312 a and a first extending via 1312 b connected to the first trench 1312 a, transfer the second partial via 1304 into a second trench 1314 a and a second extending via 1314 b connected to the second trench 1314 a, and transfer the third partial via 1306 into a third trench 1316 a and a third extending via 1316 b connected to the third trench 1316 a. The first trench 1312 a, the second trench 1314 a and the third trench 1316 b may have a width in a direction parallel to the top surface 100 a greater than that of the first extending via 1312 b, the second extending via 1314 b and the third extending via 1316 b, respectively.
  • Since the first dielectric layer 112 is disposed below the first partial via 1302 and the third partial via 1306, and the etch stop pad 122 is disposed below the second partial via 1304, the bottom metal BM, the bottom plate 128 and the top plate 124 can be protected by the remained first dielectric layer 112 and the remained etch stop pad 122 during the second etching process.
  • In some embodiments, the second etching process has a first etching rate to the first dielectric layer 112 and a second etching rate to the etch stop pad 122, and the first etching rate is greater than the second etching rate. That is, each of the first extending via 1312 b and the third extending via 1316 b may have a depth greater than that of the second extending via 1314 b. The second extending via 1314 b may be separated from the top plate 124 by a remaining portion of the etch stop pad 122.
  • Referring to FIG. 4, a punch through process is performed to extend the first extending via 1312 b to become a first penetrating via 1312 c connected to the bottom metal BM, extend the second extending via 1314 b to become a second penetrating via 1314 c connected to the top plate 124, and extend the third extending via 1316 b to become a third penetrating via 1316 c connected to the bottom plate 128. In other words, the bottom metal BM is exposed from the first trench 1312 a and the first penetrating via 1312 c, the top plate 124 is exposed from the second trench 1314 a and the second penetrating via 1314 c, and the bottom plate 128 is exposed from the third trench 1316 a and the third penetrating via 1316 c.
  • Referring to FIG. 5, a deposition process is performed to fill a conductive material into the first trench 1312 a, the first penetrating via 1312 c, the second trench 1314 a, the second penetrating via 1314 c, the third trench 1316 a, and the third penetrating via 1316 c. The conductive material may include tungsten, copper or other suitable conductive materials. In this way, a first interconnection 1322 electrically connected to the bottom metal BM, a second interconnection 1324 electrically connected to the top plate 124, and a third interconnection electrically connected to the bottom plate 128 are formed, and the semiconductor device 10 including the semiconductor element 120 is formed.
  • FIG. 6 is a cross-sectional view showing a semiconductor device 20 according to another embodiment of the invention. The semiconductor device 20 is similar to the semiconductor device 10, the difference is in that the semiconductor element 220 includes the etch stop pad 222 and the top plate 224, but not include the bottom plate.
  • The semiconductor device 20 includes a substrate 100; a bottom metal BM embedded in the substrate 100; a first etch stop layer 110, a first dielectric layer 212, a second etch stop layer 214 and a second dielectric layer 216 sequentially stacked on a top surface 100 a of the substrate 100; a semiconductor element 220 disposed on the first etch stop layer 110, wherein the semiconductor element 220 includes a top plate 224 and an etch stop pad 222 disposed on the top plate 224; a first interconnection 2322 electrically connected to the bottom metal BM; and a second interconnection 2324 electrically connected to the top plate 224. In the present embodiment, the semiconductor element 220 may be a resistor.
  • The methods for fabricating the first interconnection 2322 and the second interconnection 2324 are similar to that of the first interconnection 1322 and the second interconnection 1324, respectively, and the repetitive description is omitted herein.
  • According to an embodiment of present application, a method for fabricating a semiconductor device is provided. The method comprises: providing a substrate having a top surface; forming a bottom metal embedded in the substrate; forming a first etch stop layer, a first dielectric layer, a second etch stop layer and a second dielectric layer sequentially stacked on the top surface of the substrate; forming a semiconductor element disposed on the first etch stop layer, wherein the semiconductor element comprises a top plate and an etch stop pad disposed on the top plate; performing a first etching process to form a first partial via and a second partial via penetrating the second dielectric layer, the second etch stop layer and a portion of the first dielectric layer, wherein the first partial via is separated from the bottom metal by the first dielectric layer, and the second partial via is separated from the top plate by the etch stop pad.
  • Since a first partial via corresponding to a bottom metal is formed and separated from the bottom metal by a first dielectric layer, and a second partial via corresponding to a top plate in the semiconductor element is formed and separated from the top plate by an etch stop pad disposed on the top plate, the first dielectric layer can protect the bottom metal from being damaged, and the etch stop pad can protect the top plate from being damaged during the following etching process (such as the second etching process). Further, the remained first dielectric layer and the remained etch stop pad can replace the gap fill plug process, and the cost can be reduced. Therefore, in the present application, the semiconductor device including the semiconductor element can be made by a simple and cost saving process, and can have an excellent electrical property, such as having good quality of interconnections.
  • While the invention has been described by way of example and in terms of the preferred embodiment(s), it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

Claims (10)

1. A method for fabricating a semiconductor device comprising:
providing a substrate having a top surface;
forming a bottom metal embedded in the substrate;
forming a first etch stop layer, a first dielectric layer, a second etch stop layer and a second dielectric layer sequentially stacked on the top surface of the substrate;
forming a semiconductor element disposed on the first etch stop layer, wherein the semiconductor element comprises a top plate and an etch stop pad disposed on the top plate; and
performing a first etching process to form a first partial via and a second partial via penetrating the second dielectric layer, the second etch stop layer and a portion of the first dielectric layer, wherein the first partial via is separated from the bottom metal by the first dielectric layer, and the second partial via is separated from the top plate by the etch stop pad;
wherein the first partial via and the second partial via have a same depth.
2. The method according to claim 1, further comprising:
performing a second etching process to transfer the first partial via into a first trench and a first extending via connected to the first trench and transfer the second partial via into a second trench and a second extending via connected to the second trench, wherein the second etching process has a first etching rate to the first dielectric layer and a second etching rate to the etch stop pad, and the first etching rate is greater than the second etching rate.
3. The method according to claim 2, further comprising:
performing a punch through process to extend the first extending via to become a first penetrating via connected to the bottom metal and to extend the second extending via to become a second penetrating via connected to the top plate; and
filling a conductive material into the first trench, the first penetrating via, the second trench and the second penetrating via.
4. The method according to claim 2, wherein a depth of the first extending via is greater than a depth of the second extending via.
5. The method according to claim 2, wherein the second extending via is separated from the top plate by a remaining portion of the etch stop pad.
6. The method according to claim 1, wherein the first partial via is overlapped with the bottom metal and the second partial via is overlapped with the top plate in a normal direction of the top surface of the substrate.
7. The method according to claim 1, wherein the semiconductor element further comprises a bottom plate disposed on the first etch stop layer and a dielectric film disposed between the top plate and the bottom plate.
8. The method according to claim 1, further comprising:
forming a third partial via penetrating the second dielectric layer, the second etch stop layer and a portion of the first dielectric layer by the first etching process; and
performing a second etching process to transfer the first partial via into a first trench and a first extending via connected to the first trench, transfer the second partial via into a second trench and a second extending via connected to the second trench, and transfer the third partial via into a third trench and a third extending via connected to the third trench;
wherein the second etching process has a first etching rate to the first dielectric layer and a second etching rate to the etch stop pad, and the first etching rate is greater than the second etching rate.
9. The method according to claim 8, further comprising:
performing a punch through process to extend the first extending via to become a first penetrating via connected to the bottom metal, to extend the second extending via to become a second penetrating via connected to the top plate, and to extend the third extending via to become a third penetrating via connected to the bottom plate; and
filling a conductive material into the first trench, the first penetrating via, the second trench, the second penetrating via, the third trench and the third penetrating via.
10. The method according to claim 1, wherein the semiconductor element is a resistor or a capacitor.
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