US20210135271A1 - Method of fabricating porous wafer battery - Google Patents

Method of fabricating porous wafer battery Download PDF

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Publication number
US20210135271A1
US20210135271A1 US17/087,617 US202017087617A US2021135271A1 US 20210135271 A1 US20210135271 A1 US 20210135271A1 US 202017087617 A US202017087617 A US 202017087617A US 2021135271 A1 US2021135271 A1 US 2021135271A1
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Prior art keywords
applying
pores
wafer
silicon wafer
doped region
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US17/087,617
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Gerard Christopher D'Couto
Ljubisa Ristic
Slobodan Petrovic
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XNRGI Inc
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XNRGI Inc
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Priority to US17/087,617 priority Critical patent/US20210135271A1/en
Assigned to XNRGI, INC. reassignment XNRGI, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: D'COUTO, GERARD CHRISTOPHER
Publication of US20210135271A1 publication Critical patent/US20210135271A1/en
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Definitions

  • This invention relates generally to a method of fabricating a porous wafer battery. More particularly, the present invention relates to a porous wafer battery made by a semiconductor manufacturing process or a Micro-Electro Mechanical Systems (MEMS) manufacturing process.
  • MEMS Micro-Electro Mechanical Systems
  • a battery stack contains a plurality of single cell batteries is formed.
  • a battery may be made by one or more wafers. Each wafer has one or more pores. Each pore may include an anode and cathode and form a single battery. Then, the single batteries are stacked. Each wafer may include many cells or batteries.
  • each wafer does not need an individual package. Wafers can be stacked together to form a larger battery. It facilitates efficiency in production, space reduction, and cost reduction.
  • a plurality of wafers may be stacked in a housing.
  • the housing can be a solid housing.
  • the housing may include tabs, slots or grooves for holding the wafers in place.
  • the housing may also include electrical connectors to transmit current to and from the wafers to an external device or destinations.
  • Liquid or gas may be within the housing. Liquid or heat facilitates heat dissipation so as to reduce the temperature of the wafers. Other wafers including cooling or heating elements may be included in the housing.
  • a method of fabricating a porous wafer battery comprises the steps of providing a silicon wafer; forming a P+ doped region; patterning a mask; applying an etching process; removing the mask; applying a first metallization process; applying a second metallization process; applying a passivation process; and applying a back-end metallization process.
  • a P+ doped region is introduced in the wafer.
  • the P+ doped region can serve as an etch stop.
  • the P+ doped region may also act as a good Ohmic contact for the back-end metallization.
  • FIG. 1 is a flowchart of a process to develop a porous wafer battery in examples of the present disclosure.
  • FIGS. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, and 2J show the steps of the process to fabricate a porous wafer battery in examples of the present disclosure.
  • FIG. 3 is a cross-sectional plot, along BB′ of FIG. 4 , of a wafer with inclined side walls of a plurality of pores in examples of the present disclosure.
  • FIG. 4 is a front view of a porous wafer in examples of the present disclosure.
  • FIG. 1 is a flowchart of a process 100 to develop a porous wafer battery in examples of the present disclosure.
  • the process 100 may start from block 102 .
  • FIGS. 2A-2J show the cross sections, along AA′ of FIG. 4 , of the corresponding steps.
  • a wafer 200 is provided.
  • the wafer 200 is a silicon wafer.
  • the wafer 200 comprises a (110) surface orientation.
  • the wafer 200 comprises a (100) surface orientation.
  • the wafer 200 comprises a first side 202 (first surface) and a second side 204 (second surface).
  • the wafer 200 is P doped.
  • a diameter of the wafer 200 is 4 inches.
  • a diameter of the wafer 200 is 6 inches.
  • a diameter of the wafer 200 is 8 inches.
  • a diameter of the wafer 200 is 12 inches.
  • a diameter of the wafer 200 is 18 inches.
  • Block 102 may be followed by block 104 .
  • a P+ doped region 212 having a predetermined thickness is formed.
  • P+ type dopant is implanted from the first side 202 of the wafer 200 .
  • the predetermined thickness 213 of the P+ doped region 212 is in a range from 10% of a thickness 211 of the wafer 200 to 33.3% of the thickness 211 of the wafer 200 .
  • the predetermined thickness 213 of the P+ doped region 212 is in a range from 10 microns to 300 microns.
  • the lower limit of the predetermined thickness 213 is to maintain required strength of the bottom surface 223 of the plurality of pores 232 .
  • the upper limit of the predetermined thickness 213 is to maintain required depth of the plurality of pores 232 .
  • Block 104 may be followed by block 106 .
  • a mask 222 is patterned on the second side 204 of the wafer 200 .
  • Wafer 200 is flipped to allow processing on the second side 204 .
  • Horizontal sizes of a plurality of pores 232 of FIG. 2D are determined by the pattern of the mask 222 .
  • Block 106 may be followed by block 108 .
  • an etching process is performed.
  • a plurality of pores 232 are formed.
  • the etching process is a wet (anisotropic) etching using one of standard etchants such as KOH, EDP (Ethylenediamine Pyrocatechol), CsOH, NaOH, or N 2 H 4 —H 2 O (Hydrazine).
  • An inclination angle 338 (inclined from the bottom surface 333 of the plurality of pores 332 ) of FIG. 3 of the plurality of side walls 331 of each of the plurality of pores 332 is in a range from 54 degrees to 55 degrees (including tolerance for 54.7 degrees).
  • wet etching may be followed by a laser damaging process of block 112 to adjust inclination angle 338 .
  • the etching process is a deep reactive-ion etching process.
  • Side walls 231 of the plurality of pores 232 are perpendicular to the bottom surfaces 233 of the plurality of pores 232 .
  • An etch rate of highly doped p+ silicon is about 1000 times lower than the etch rate of p ⁇ type silicon. Therefore, the P+ doped region 212 can serve as an etch stop.
  • the P+ doped region 212 define the bottom surfaces of the plurality of pores 232 and define the depth of the plurality of pores 232 .
  • P+ doped region 212 may also act as a good Ohmic contact for the back-end metallization.
  • Block 108 may be followed by block 110 .
  • a bottom surface 233 of each of the plurality of pores 232 is flat and is of a rectangular shape.
  • the plurality of pores 232 are not through holes.
  • the plurality of pores 232 are through holes (a special example that P+ doped region 212 of block 104 is not formed).
  • Block 110 referring now to FIG. 2E , the mask 222 of FIG. 2D is removed. Surfaces 241 are exposed. Block 110 may be followed by optional block 112 or block 114 .
  • the laser damaging process can also adjust a respective inclination angle 338 of FIG. 3 of the plurality of side walls 331 of each of the plurality of pores 332 .
  • the inclination angle 338 is adjusted to 90 degrees.
  • the inclination angle 338 is adjusted to a range from 65 degrees to 75 degrees.
  • the lower limit of the inclination angle 338 is to maintain required pitch of the plurality of pores 332 .
  • the upper limit of the inclination angle 338 is to increase metallization efficiency on side walls 331 of the plurality of pores 332 .
  • Block 112 may be followed by block 114 .
  • a first respective metal section 257 of a first plurality of metal sections 256 covers a plurality of respective side walls 231 and a respective bottom surface 233 of each of the plurality of pores 232 .
  • a thickness of the first plurality of metal sections 256 is in a range from 20 microns to 200 microns.
  • the first respective metal section 257 is of a letter U shape.
  • the first respective metal section 257 is made of nickel.
  • the first respective metal section 257 is made of titanium nitride, silicates, or silicon carbide.
  • Block 114 may be followed by block 116 .
  • a second respective metal section 267 of a second plurality of metal sections 266 covers the first respective metal section 257 .
  • a thickness of the second plurality of metal sections 266 is in a range from 20 microns to 200 microns.
  • the second respective metal section 267 is of a letter U shape.
  • the second respective metal section 267 is made of copper.
  • the second respective metal section 267 is made of titanium nitride, silicates, silicon carbide.
  • Block 116 may be followed by block 118 .
  • a passivation process is applied.
  • a plurality of passivation sections 276 are formed. Advantages of the plurality of passivation sections 276 are to prevent lithium reduction and to reduce dendrite growth.
  • a thickness of the plurality of passivation sections 276 is in a range from 20 microns to 200 microns.
  • each passivation section 277 of the plurality of passivation sections 276 is of a letter U shape. Letter U shape passivation section provides better insulation than flat passivation section.
  • a first leg 271 of the letter U shape is directly attached to the second respective metal section of a first selected pore 291 of the plurality of pores.
  • a second leg 272 of the letter U shape is directly attached to the second respective metal section of a second selected pore 292 of the plurality of pores.
  • the first selected pore 291 is different from the second selected pore 292 .
  • Block 118 may be followed by block 120 .
  • Block 120 referring now to FIG. 2J , a back-end metallization process is applied.
  • a back-end metal layer 289 is formed and is directly attached to the P+ doped region 212 .
  • Back-end metal layer 289 may serve as an electrical contact pad. Therefore, one electrode of the pores battery is formed.
  • Block 120 may be followed by optional block 122 .
  • a back-end annealing process is applied to the back-end metal layer 289 .
  • the wafer may be processed from one side of the wafer through ion implantation of boron followed by a p+ diffusion similar to a source and a drain of a metal-oxide-semiconductor (MOS) transistor.
  • MOS metal-oxide-semiconductor
  • the wafer may be p+, p ⁇ , n+, or n ⁇ doped.
  • inclination angles of side walls of the plurality of pores may be changed by using different etching rates and by different crystallographic orientations.
  • the present disclosure is to fabricate a porous wafer battery. Therefore, the plurality of pores will not be filled with control gate materials used in a metal-oxide-semiconductor field-effect transistor (MOSFET). The plurality of pores will not be filled with overmold encapsulation material used in a conventional semiconductor device. In one example, the plurality of pores are filled with lithium ions. In examples of the present disclosure, no singulation process is applied to the silicon wafer to separate a first portion of the plurality of pores from a second portion of the plurality of pores.
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • FIG. 4 is a front view of a porous wafer 400 in examples of the present disclosure.
  • the plurality of pores 432 are symmetric with respect to a center 431 of the wafer 400 .
  • the plurality of pores 432 are symmetric with respect to X-axis.
  • the plurality of pores 432 are symmetric with respect to Y-axis.
  • the plurality of pores 432 are of rectangular shapes.
  • the plurality of pores 432 are of square shapes.
  • the plurality of pores 432 are of circular shapes.
  • each pore of the plurality of pores of a single wafer made by the process of FIG. 1 contains a respective anode and a respective cathode. Therefore, the single wafer, by itself, is a porous wafer battery.
  • a first wafer made by the process of FIG. 1 is integrated with a second wafer made by the process of FIG. 1 .
  • the first wafer is anode (the plurality of pores 232 of the first wafer contain lithium) and the second wafer is cathode (the plurality of pores 232 of the second wafer contain manganese dioxide, LiCoO 2 , or LiMn 2 O 4 ).
  • the first wafer is parallel to the second wafer.
  • An optional electrolyte separator is between the first wafer and the second wafer. A centerline of the first wafer is aligned with a centerline of the second wafer.
  • the plurality of passivation sections 276 of the first wafer is closer to the plurality of passivation sections 276 of the second wafer than the back-end metal layer 289 of the second wafer.
  • the plurality of passivation sections 276 of the second wafer is closer to the plurality of passivation sections 276 of the first wafer than the back-end metal layer 289 of the first wafer (Similar to the arrangement of FIG. 1 of provisional patent application 62/930,016).
  • the first wafer and the second wafer are enclosed by a housing (Similar to the arrangement of FIG. 1B of provisional patent application 62/930,019).

Abstract

A method of fabricating a porous wafer battery comprises the steps of providing a silicon wafer; forming a P+ doped region; patterning a mask; applying an etching process; removing the mask; applying a first metallization process; applying a second metallization process; applying a passivation process; and applying a back-end metallization process. A P+ doped region is introduced in the wafer. The P+ doped region can serve as an etch stop. The P+ doped region may also act as a good Ohmic contact for the back-end metallization.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This patent application claims benefit of provisional patent applications 62/930,016, 62/930,018, 62/930,019, 62/930,020, and 62/930,021 because of a common inventor, Slobodan Petrovic. The disclosures made in the provisional patent applications 62/930,016, 62/930,018, 62/930,019, 62/930,020, and 62/930,021 are hereby incorporated by reference.
    • FIELD OF THE INVENTION
  • This invention relates generally to a method of fabricating a porous wafer battery. More particularly, the present invention relates to a porous wafer battery made by a semiconductor manufacturing process or a Micro-Electro Mechanical Systems (MEMS) manufacturing process.
    • BACKGROUND OF THE INVENTION
  • Applications for vehicles or stationary apparatus require large size batteries. Currently, the industry standard for large size battery is to take standardized or proprietary small scale batteries and package them together to form a large size battery. For example, hundreds or thousands of 18650-type batteries are packaged together to form a large size battery. It is inefficient because each cell requires casing, packaging or housing. Thus, it lowers the energy density of the stack. It also induces problems for cooling, longevity and maintenance, and replacement. Some current players in the industry, Panasonic and Tesla, tried to introduce the 2170-type cell. 2170-type is larger than 18650-type. The large number of individually packaging cells requires packaging with complex heat distribution capability and interconnections between the cells.
  • Other manufacturers also introduced larger cells including cells as large as 20 Ah, in a pouch cell package. It results in packing a large number of pouch cells stacked next to one another or in strings on top of one another. It is still inefficient and faces many challenges due to non-uniform current distribution, sensitivity of welded contact tabs and excessive heat generation issue. Those batteries are also expensive because each 20 Ah cell has a pouch package. In large scale manufacturing, it still does not realize a true cost effective package and application.
  • Therefore, there is a need for a high-power density, high current and low cost battery stack facilitating efficiently scaling the size of the battery.
    • SUMMARY OF THE INVENTION
  • The present disclosure does not require special packing used in current large-size battery industry. A battery stack contains a plurality of single cell batteries is formed.
  • A battery may be made by one or more wafers. Each wafer has one or more pores. Each pore may include an anode and cathode and form a single battery. Then, the single batteries are stacked. Each wafer may include many cells or batteries.
  • In one example, each wafer does not need an individual package. Wafers can be stacked together to form a larger battery. It facilitates efficiency in production, space reduction, and cost reduction.
  • A plurality of wafers may be stacked in a housing. The housing can be a solid housing. The housing may include tabs, slots or grooves for holding the wafers in place. The housing may also include electrical connectors to transmit current to and from the wafers to an external device or destinations.
  • Liquid or gas may be within the housing. Liquid or heat facilitates heat dissipation so as to reduce the temperature of the wafers. Other wafers including cooling or heating elements may be included in the housing.
  • A method of fabricating a porous wafer battery is disclosed. The method comprises the steps of providing a silicon wafer; forming a P+ doped region; patterning a mask; applying an etching process; removing the mask; applying a first metallization process; applying a second metallization process; applying a passivation process; and applying a back-end metallization process.
  • A P+ doped region is introduced in the wafer. The P+ doped region can serve as an etch stop. The P+ doped region may also act as a good Ohmic contact for the back-end metallization.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a flowchart of a process to develop a porous wafer battery in examples of the present disclosure.
  • FIGS. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, and 2J show the steps of the process to fabricate a porous wafer battery in examples of the present disclosure.
  • FIG. 3 is a cross-sectional plot, along BB′ of FIG. 4, of a wafer with inclined side walls of a plurality of pores in examples of the present disclosure.
  • FIG. 4 is a front view of a porous wafer in examples of the present disclosure.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 1 is a flowchart of a process 100 to develop a porous wafer battery in examples of the present disclosure. The process 100 may start from block 102. FIGS. 2A-2J show the cross sections, along AA′ of FIG. 4, of the corresponding steps.
  • In block 102, referring now to FIG. 2A, a wafer 200 is provided. In examples of the present disclosure, the wafer 200 is a silicon wafer. In one example, the wafer 200 comprises a (110) surface orientation. In another example, the wafer 200 comprises a (100) surface orientation. The wafer 200 comprises a first side 202 (first surface) and a second side 204 (second surface). In examples of the present disclosure, the wafer 200 is P doped. In one example, a diameter of the wafer 200 is 4 inches. In another example, a diameter of the wafer 200 is 6 inches. In still another example, a diameter of the wafer 200 is 8 inches. In yet another example, a diameter of the wafer 200 is 12 inches. In yet still another example, a diameter of the wafer 200 is 18 inches. Block 102 may be followed by block 104.
  • In block 104, referring now to FIG. 2B, a P+ doped region 212 having a predetermined thickness is formed. P+ type dopant is implanted from the first side 202 of the wafer 200. In one example, the predetermined thickness 213 of the P+ doped region 212 is in a range from 10% of a thickness 211 of the wafer 200 to 33.3% of the thickness 211 of the wafer 200. In another example, the predetermined thickness 213 of the P+ doped region 212 is in a range from 10 microns to 300 microns. The lower limit of the predetermined thickness 213 is to maintain required strength of the bottom surface 223 of the plurality of pores 232. The upper limit of the predetermined thickness 213 is to maintain required depth of the plurality of pores 232. Block 104 may be followed by block 106.
  • In block 106, referring now to FIG. 2C, a mask 222 is patterned on the second side 204 of the wafer 200. Wafer 200 is flipped to allow processing on the second side 204. Horizontal sizes of a plurality of pores 232 of FIG. 2D are determined by the pattern of the mask 222. Block 106 may be followed by block 108.
  • In block 108, referring now to FIG. 2D, an etching process is performed. A plurality of pores 232 are formed. In one example, the etching process is a wet (anisotropic) etching using one of standard etchants such as KOH, EDP (Ethylenediamine Pyrocatechol), CsOH, NaOH, or N2H4—H2O (Hydrazine). An inclination angle 338 (inclined from the bottom surface 333 of the plurality of pores 332) of FIG. 3 of the plurality of side walls 331 of each of the plurality of pores 332 is in a range from 54 degrees to 55 degrees (including tolerance for 54.7 degrees). Wet etching may be followed by a laser damaging process of block 112 to adjust inclination angle 338. In another example, the etching process is a deep reactive-ion etching process. Side walls 231 of the plurality of pores 232 are perpendicular to the bottom surfaces 233 of the plurality of pores 232.
  • An etch rate of highly doped p+ silicon is about 1000 times lower than the etch rate of p− type silicon. Therefore, the P+ doped region 212 can serve as an etch stop. The P+ doped region 212 define the bottom surfaces of the plurality of pores 232 and define the depth of the plurality of pores 232. P+ doped region 212 may also act as a good Ohmic contact for the back-end metallization. Block 108 may be followed by block 110.
  • In examples of the present disclosure, a bottom surface 233 of each of the plurality of pores 232 is flat and is of a rectangular shape. In one example, the plurality of pores 232 are not through holes. In another example, the plurality of pores 232 are through holes (a special example that P+ doped region 212 of block 104 is not formed).
  • In block 110, referring now to FIG. 2E, the mask 222 of FIG. 2D is removed. Surfaces 241 are exposed. Block 110 may be followed by optional block 112 or block 114.
  • In block 112, referring now to FIG. 2F, debris 244 will be removed. The laser damaging process can also adjust a respective inclination angle 338 of FIG. 3 of the plurality of side walls 331 of each of the plurality of pores 332. In one example, the inclination angle 338 is adjusted to 90 degrees. In another example, the inclination angle 338 is adjusted to a range from 65 degrees to 75 degrees. The lower limit of the inclination angle 338 is to maintain required pitch of the plurality of pores 332. The upper limit of the inclination angle 338 is to increase metallization efficiency on side walls 331 of the plurality of pores 332. Block 112 may be followed by block 114.
  • In block 114, referring now to FIG. 2G, a first metallization process is applied. A first respective metal section 257 of a first plurality of metal sections 256 covers a plurality of respective side walls 231 and a respective bottom surface 233 of each of the plurality of pores 232. In examples of the present disclosure, a thickness of the first plurality of metal sections 256 is in a range from 20 microns to 200 microns. In examples of the present disclosure, the first respective metal section 257 is of a letter U shape. In one example, the first respective metal section 257 is made of nickel. In another example, the first respective metal section 257 is made of titanium nitride, silicates, or silicon carbide. Block 114 may be followed by block 116.
  • In block 116, referring now to FIG. 2H, a second metallization process is applied. A second respective metal section 267 of a second plurality of metal sections 266 covers the first respective metal section 257. In examples of the present disclosure, a thickness of the second plurality of metal sections 266 is in a range from 20 microns to 200 microns. In examples of the present disclosure, the second respective metal section 267 is of a letter U shape. In one example, the second respective metal section 267 is made of copper. In another example, the second respective metal section 267 is made of titanium nitride, silicates, silicon carbide. Block 116 may be followed by block 118.
  • In block 118, referring now to FIG. 2I, a passivation process is applied. A plurality of passivation sections 276 are formed. Advantages of the plurality of passivation sections 276 are to prevent lithium reduction and to reduce dendrite growth. In examples of the present disclosure, a thickness of the plurality of passivation sections 276 is in a range from 20 microns to 200 microns. In examples of the present disclosure, each passivation section 277 of the plurality of passivation sections 276 is of a letter U shape. Letter U shape passivation section provides better insulation than flat passivation section. A first leg 271 of the letter U shape is directly attached to the second respective metal section of a first selected pore 291 of the plurality of pores. A second leg 272 of the letter U shape is directly attached to the second respective metal section of a second selected pore 292 of the plurality of pores. The first selected pore 291 is different from the second selected pore 292. Block 118 may be followed by block 120.
  • In block 120, referring now to FIG. 2J, a back-end metallization process is applied. A back-end metal layer 289 is formed and is directly attached to the P+ doped region 212. Back-end metal layer 289 may serve as an electrical contact pad. Therefore, one electrode of the pores battery is formed. Block 120 may be followed by optional block 122.
  • In optional block 122 (shown in dashed lines), still referring now to FIG. 2J, a back-end annealing process is applied to the back-end metal layer 289.
  • In examples of the present disclosure, the wafer may be processed from one side of the wafer through ion implantation of boron followed by a p+ diffusion similar to a source and a drain of a metal-oxide-semiconductor (MOS) transistor.
  • In examples of the present disclosure, the wafer may be p+, p−, n+, or n− doped.
  • In examples of the present disclosure, inclination angles of side walls of the plurality of pores may be changed by using different etching rates and by different crystallographic orientations.
  • The present disclosure is to fabricate a porous wafer battery. Therefore, the plurality of pores will not be filled with control gate materials used in a metal-oxide-semiconductor field-effect transistor (MOSFET). The plurality of pores will not be filled with overmold encapsulation material used in a conventional semiconductor device. In one example, the plurality of pores are filled with lithium ions. In examples of the present disclosure, no singulation process is applied to the silicon wafer to separate a first portion of the plurality of pores from a second portion of the plurality of pores.
  • FIG. 4 is a front view of a porous wafer 400 in examples of the present disclosure. In examples of the present disclosure, the plurality of pores 432 are symmetric with respect to a center 431 of the wafer 400. The plurality of pores 432 are symmetric with respect to X-axis. The plurality of pores 432 are symmetric with respect to Y-axis. In one example, the plurality of pores 432 are of rectangular shapes. In another example, the plurality of pores 432 are of square shapes. In still another example, the plurality of pores 432 are of circular shapes.
  • In examples of the present disclosure, each pore of the plurality of pores of a single wafer made by the process of FIG. 1 contains a respective anode and a respective cathode. Therefore, the single wafer, by itself, is a porous wafer battery.
  • In examples of the present disclosure, a first wafer made by the process of FIG. 1 is integrated with a second wafer made by the process of FIG. 1. In one example, the first wafer is anode (the plurality of pores 232 of the first wafer contain lithium) and the second wafer is cathode (the plurality of pores 232 of the second wafer contain manganese dioxide, LiCoO2, or LiMn2O4). The first wafer is parallel to the second wafer. An optional electrolyte separator is between the first wafer and the second wafer. A centerline of the first wafer is aligned with a centerline of the second wafer. The plurality of passivation sections 276 of the first wafer is closer to the plurality of passivation sections 276 of the second wafer than the back-end metal layer 289 of the second wafer. The plurality of passivation sections 276 of the second wafer is closer to the plurality of passivation sections 276 of the first wafer than the back-end metal layer 289 of the first wafer (Similar to the arrangement of FIG. 1 of provisional patent application 62/930,016). In examples of the present disclosure, the first wafer and the second wafer are enclosed by a housing (Similar to the arrangement of FIG. 1B of provisional patent application 62/930,019).
  • Those of ordinary skill in the art may recognize that modifications of the embodiments disclosed herein are possible. For example, a number of the plurality of pores may vary. Other modifications may occur to those of ordinary skill in this art, and all such modifications are deemed to fall within the purview of the present invention, as defined by the claims.

Claims (15)

1. A method of fabricating a porous wafer battery, the method comprising the steps of:
providing a silicon wafer comprising
a first side; and
a second side opposite the first side;
implanting P+ type dopant from the first side of the silicon wafer forming a P+ doped region having a predetermined thickness;
patterning a mask on the second side of the silicon wafer;
applying an etching process forming a plurality of pores on the second side of the silicon wafer;
removing the mask;
applying a first metallization process so that a first respective metal section of a first plurality of metal sections covers a plurality of respective side walls and a respective bottom surface of each of the plurality of pores;
applying a second metallization process so that a second respective metal section of a second plurality of metal sections covers the first respective metal section;
applying a passivation process forming a plurality of passivation sections; and
applying a back-end metallization process so that a back-end metal layer is formed and is directly attached to the P+ doped region.
2. The method of claim 1 further comprising, after the step of applying the etching process, applying a laser damaging process removing debris.
3. The method of claim 1 further comprising, after the step of applying the etching process, applying a laser damaging process adjusting a respective inclination angle of the plurality of side walls of each of the plurality of pores.
4. The method of claim 3, wherein the respective inclination angle is in a range from sixty-five degrees to seventy-five degrees.
5. The method of claim 1 further comprising, after the step of applying the back-end metallization process, applying a back-end annealing process.
6. The method of claim 1, wherein the predetermined thickness of the P+ doped region is in a range from one-tenth of a thickness of the silicon wafer to one-third of the thickness of the silicon wafer.
7. The method of claim 1, wherein the predetermined thickness of the P+ doped region is in a range from ten microns to three-hundred microns.
8. The method of claim 1, wherein the silicon wafer comprises a (110) surface orientation.
9. The method of claim 1, wherein the silicon wafer comprises a (100) surface orientation; and wherein a respective inclination angle of the plurality of side walls of each of the plurality of pores is in a range from fifty-four degrees to fifty-five degrees.
10. The method of claim 1, wherein each of the plurality of passivation sections is of a letter U shape.
11. The method of claim 10, wherein a first leg of the letter U shape is directly attached to the second respective metal section of a first selected pore of the plurality of pores; wherein a second leg of the letter U shape is directly attached to the second respective metal section of a second selected pore of the plurality of pores; and wherein the first selected pore is different from the second selected pore.
12. The method of claim 1, wherein the respective bottom surface of each of the plurality of pores is flat and is of a rectangular shape.
13. The method of claim 1, wherein first plurality of metal sections are made of nickel; and wherein the second plurality of metal sections are made of copper.
14. The method of claim 1, wherein the etching process is a wet etching process.
15. The method of claim 1, wherein the etching process is a deep reactive-ion etching process.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11342625B2 (en) * 2019-11-04 2022-05-24 Xnrgi, Inc. Method of fabricating and method of using porous wafer battery

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4468852A (en) * 1982-04-08 1984-09-04 Sgs-Ates Componenti Elettronici S.P.A. Process for making CMOS field-effect transistors with self-aligned guard rings utilizing special masking and ion implantation
US20090023275A1 (en) * 2007-07-20 2009-01-22 Stmicroelectronics Crolles 2 Sas Method for forming silicon wells of different crystallographic orientations
US20160379936A1 (en) * 2014-02-28 2016-12-29 Lfoundry S.R.L. Method of fabricating a semiconductor device and semiconductor product

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6197450B1 (en) * 1998-10-22 2001-03-06 Ramot University Authority For Applied Research & Industrial Development Ltd. Micro electrochemical energy storage cells
US6432577B1 (en) * 2000-06-29 2002-08-13 Sandia Corporation Apparatus and method for fabricating a microbattery
US20030042587A1 (en) 2001-08-31 2003-03-06 Tsung-Jen Lee IC packaging and manufacturing methods
US20060032046A1 (en) * 2002-10-17 2006-02-16 Menachem Nathan Thin-film cathode for 3-dimensional microbattery and method for preparing such cathode
CA2432397A1 (en) * 2003-06-25 2004-12-25 Hydro-Quebec Procedure for preparing an electrode from porous silicon, the electrode so obtained, and an electrochemical system containing at least one such electrode
US7295029B2 (en) * 2005-03-24 2007-11-13 Memsic, Inc. Chip-scale package for integrated circuits
EP2913881A1 (en) * 2007-08-21 2015-09-02 A123 Systems LLC Electrochemical cell
JPWO2010053173A1 (en) 2008-11-10 2012-04-05 株式会社Kelk Semiconductor wafer temperature control apparatus and temperature control method
US20100291431A1 (en) * 2009-05-13 2010-11-18 Front Edge Technology, Inc. Thin film battery with protective packaging
EP2660899B1 (en) * 2010-12-28 2018-08-29 LG Chem, Ltd. Battery module storage device, and electric power storage system having same
US9368429B2 (en) * 2011-10-25 2016-06-14 Intel Corporation Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips
FR2982082B1 (en) * 2011-11-02 2013-11-22 Fabien Gaben PROCESS FOR PRODUCING THIN-FILT THIN-FILTER BATTERIES
US9876200B2 (en) * 2015-08-07 2018-01-23 International Business Machines Corporation All-silicon hermetic package and processing for narrow, low-profile microbatteries
US10079375B2 (en) * 2015-12-30 2018-09-18 International Business Machines Corporation Dual seal microbattery and method of making
WO2018175423A1 (en) * 2017-03-20 2018-09-27 Millibatt, Inc. Battery system and production method
US10505160B2 (en) * 2017-06-26 2019-12-10 International Business Machines Corporation Micro-battery using glass package
US11233288B2 (en) * 2018-07-11 2022-01-25 International Business Machines Corporation Silicon substrate containing integrated porous silicon electrodes for energy storage devices
US10833301B2 (en) * 2019-01-02 2020-11-10 International Business Machines Corporation Through silicon via energy storage devices
US20210135311A1 (en) * 2019-11-04 2021-05-06 Xnrgi, Inc. Battery package containing porous wafer battery

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4468852A (en) * 1982-04-08 1984-09-04 Sgs-Ates Componenti Elettronici S.P.A. Process for making CMOS field-effect transistors with self-aligned guard rings utilizing special masking and ion implantation
US20090023275A1 (en) * 2007-07-20 2009-01-22 Stmicroelectronics Crolles 2 Sas Method for forming silicon wells of different crystallographic orientations
US20160379936A1 (en) * 2014-02-28 2016-12-29 Lfoundry S.R.L. Method of fabricating a semiconductor device and semiconductor product

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Doolittle, Alan, "Ion Implantation", no date *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11342625B2 (en) * 2019-11-04 2022-05-24 Xnrgi, Inc. Method of fabricating and method of using porous wafer battery

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