US20210135231A1 - Porous two-wafer battery - Google Patents
Porous two-wafer battery Download PDFInfo
- Publication number
- US20210135231A1 US20210135231A1 US17/087,575 US202017087575A US2021135231A1 US 20210135231 A1 US20210135231 A1 US 20210135231A1 US 202017087575 A US202017087575 A US 202017087575A US 2021135231 A1 US2021135231 A1 US 2021135231A1
- Authority
- US
- United States
- Prior art keywords
- wafer
- pores
- porous
- battery
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000011148 porous material Substances 0.000 claims abstract description 72
- 238000002161 passivation Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000003792 electrolyte Substances 0.000 claims description 6
- 239000002210 silicon-based material Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 4
- 229910004541 SiN Inorganic materials 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 150000004760 silicates Chemical class 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 210000001787 dendrite Anatomy 0.000 description 14
- 229910052744 lithium Inorganic materials 0.000 description 12
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 11
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 229910021426 porous silicon Inorganic materials 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910015027 LiAsF4 Inorganic materials 0.000 description 1
- 229910032387 LiCoO2 Inorganic materials 0.000 description 1
- 229910010942 LiFP6 Inorganic materials 0.000 description 1
- 229910001290 LiPF6 Inorganic materials 0.000 description 1
- 229910002097 Lithium manganese(III,IV) oxide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229920001400 block copolymer Polymers 0.000 description 1
- 239000010406 cathode material Substances 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 229910021525 ceramic electrolyte Inorganic materials 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 150000002148 esters Chemical class 0.000 description 1
- 150000002170 ethers Chemical class 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005470 impregnation Methods 0.000 description 1
- 239000002608 ionic liquid Substances 0.000 description 1
- 229920000554 ionomer Polymers 0.000 description 1
- 229910003473 lithium bis(trifluoromethanesulfonyl)imide Inorganic materials 0.000 description 1
- 229910001416 lithium ion Inorganic materials 0.000 description 1
- MHCFAGZWMAWTNR-UHFFFAOYSA-M lithium perchlorate Chemical compound [Li+].[O-]Cl(=O)(=O)=O MHCFAGZWMAWTNR-UHFFFAOYSA-M 0.000 description 1
- 229910001486 lithium perchlorate Inorganic materials 0.000 description 1
- 229910001496 lithium tetrafluoroborate Inorganic materials 0.000 description 1
- QSZMZKBZAYQGRS-UHFFFAOYSA-N lithium;bis(trifluoromethylsulfonyl)azanide Chemical compound [Li+].FC(F)(F)S(=O)(=O)[N-]S(=O)(=O)C(F)(F)F QSZMZKBZAYQGRS-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 238000007086 side reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007784 solid electrolyte Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M50/00—Constructional details or processes of manufacture of the non-active parts of electrochemical cells other than fuel cells, e.g. hybrid cells
- H01M50/20—Mountings; Secondary casings or frames; Racks, modules or packs; Suspension devices; Shock absorbers; Transport or carrying devices; Holders
- H01M50/204—Racks, modules or packs for multiple batteries or multiple cells
- H01M50/207—Racks, modules or packs for multiple batteries or multiple cells characterised by their shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
- H01M10/4257—Smart batteries, e.g. electronic circuits inside the housing of the cells or batteries
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/04—Construction or manufacture in general
- H01M10/0436—Small-sized flat cells or batteries for portable equipment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/04—Construction or manufacture in general
- H01M10/0477—Construction or manufacture in general with circular plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/05—Accumulators with non-aqueous electrolyte
- H01M10/052—Li-accumulators
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/05—Accumulators with non-aqueous electrolyte
- H01M10/058—Construction or manufacture
- H01M10/0585—Construction or manufacture of accumulators having only flat construction elements, i.e. flat positive electrodes, flat negative electrodes and flat separators
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/60—Heating or cooling; Temperature control
- H01M10/61—Types of temperature control
- H01M10/613—Cooling or keeping cold
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/60—Heating or cooling; Temperature control
- H01M10/61—Types of temperature control
- H01M10/615—Heating or keeping warm
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M4/00—Electrodes
- H01M4/02—Electrodes composed of, or comprising, active material
- H01M4/13—Electrodes for accumulators with non-aqueous electrolyte, e.g. for lithium-accumulators; Processes of manufacture thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M4/00—Electrodes
- H01M4/02—Electrodes composed of, or comprising, active material
- H01M4/62—Selection of inactive substances as ingredients for active masses, e.g. binders, fillers
- H01M4/624—Electric conductive fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M4/00—Electrodes
- H01M4/02—Electrodes composed of, or comprising, active material
- H01M4/62—Selection of inactive substances as ingredients for active masses, e.g. binders, fillers
- H01M4/628—Inhibitors, e.g. gassing inhibitors, corrosion inhibitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
- H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
- H01L2021/60097—Applying energy, e.g. for the soldering or alloying process
- H01L2021/60135—Applying energy, e.g. for the soldering or alloying process using convection, e.g. reflow oven
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M4/00—Electrodes
- H01M4/02—Electrodes composed of, or comprising, active material
- H01M2004/021—Physical characteristics, e.g. porosity, surface area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/04—Construction or manufacture in general
- H01M2010/0495—Nanobatteries
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
- H01M2010/4271—Battery management systems including electronic circuits, e.g. control of current or voltage to keep battery in healthy state, cell balancing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- This invention relates generally to a porous two-wafer battery. More particularly, the present invention relates to a porous silicon two-wafer, lithium battery.
- Li metal dendritic growth is one of the most serious problems affecting the safety and functionality of lithium-based batteries.
- Dendrites are fractal deposits of various shapes such as needle-like, snowflake-like, tree-like, bush-like, moss-like, and whisker- like structures.
- Li metal (and Li-ion) anodes lithium does not form a flat, homogeneous layer on the anode, but instead dendrites that can be needle-like or branched.
- Factors affecting Li dendrite growth at the anode are current density, electrolyte composition and concentration, and solid-electrolyte-interphase layer (SEI).
- the dendrites growth are not dominated by the direction of the electric field.
- the lithium dendrites In a configuration with two planar-type electrodes, the lithium dendrites inevitably grow towards the other electrode, penetrating thereby through the separator and causing short upon reaching the conductive surface of the opposite electrode.
- the methods above may suppress dendrite growth. But, it also introduce additional problems such as increased side reaction and modified cycling characteristics.
- lithium dendrite may result in electrical short. It can lead to battery heating up, catching fire, or exploding.
- a porous two-wafer battery comprises a first wafer and a second wafer.
- Each of the first wafer and the second wafer comprises a substrate, a conductive layer, and a passivation layer.
- the first wafer is parallel to the second wafer.
- the passivation layer of the first wafer is closer to the passivation layer of the second wafer.
- the first wafer serves as an anode and the second wafer serves as a cathode.
- the substrate comprises a plurality of pores and a P+ doped region.
- the plurality of pores are symmetric with respect to a respective center of each of the first wafer and the second wafer.
- An adhesion promotion layer is between the conductive layer and a respective side wall of the plurality of pores.
- FIG. 1 is a side view of a porous two-wafer battery in examples of the present disclosure.
- FIG. 2 is a front view of a wafer of a porous two-wafer battery in examples of the present disclosure.
- FIG. 3 is a side view of another porous two-wafer battery in examples of the present disclosure.
- FIG. 4 is a cross-sectional plot along AA′ of the wafer of FIG. 2 in examples of the present disclosure.
- FIG. 1 is a side view of a porous two-wafer battery 100 in examples of the present disclosure.
- the porous two-wafer battery 100 comprises a first wafer 120 , a second wafer 160 , and an optional electrolyte separator 110 (shown in dashed lines) between a front side 131 of the first wafer 120 and a front side 171 of the second wafer 160 .
- FIG. 2 is a front view of the first wafer 120 of the porous two-wafer battery 100 in examples of the present disclosure.
- the first wafer 120 comprises a first substrate 122 .
- the first substrate 122 comprises a plurality of pores 140 (shown in dashed lines because of the side view).
- the second wafer 160 comprises a second substrate 162 .
- the second substrate 162 comprises a plurality of pores 180 (shown in dashed lines because of the side view).
- the plurality of pores 140 and the plurality of pores 180 are of rectangular shapes. In another example, the plurality of pores 140 and the plurality of pores 180 are of square shapes. In still another example, the plurality of pores 140 and the plurality of pores 180 are of circular shapes.
- a diameter of the plurality of pores 140 and the plurality of pores 180 is in a range from 1 micron to 100 microns. In examples of the present disclosure, a diameter and a pitch of the plurality of pores 140 and the plurality of pores 180 is 20 microns and 22 microns respectively.
- a diameter of the first wafer 120 is 4 inches. In another example, a diameter of the first wafer 120 is 6 inches. In still another example, a diameter of the first wafer 120 is 8 inches. In yet another example, a diameter of the first wafer 120 is 12 inches.
- the capacity (charge) of the first wafer 120 is 60 Ah. In yet still another example, a diameter of the first wafer 120 is 18 inches. In examples of the present disclosure, the capacity (charge) of the first wafer 120 is in a range from 1 Ah to 100 Ah. A thickness of the first wafer is in a range from 100 microns to 750 microns.
- the first wafer 120 is parallel to the second wafer 160 .
- the front side 131 of the first wafer 120 is closer to the front side 171 of the second wafer 160 than a back side 173 of the second wafer 160 .
- the front side 171 of the second wafer 160 is closer to the front side 131 of the first wafer 120 than a back side 133 of the first wafer 120 .
- the first substrate 122 of the first wafer 120 is made of a silicon material.
- the second substrate 162 of the second wafer 160 is made of the silicon material.
- the first plurality of pores 140 are symmetric with respect to a center 231 of the first wafer 120 .
- the second plurality of pores 180 are symmetric with respect to a center of the second wafer 160 .
- the first plurality of pores 140 are symmetric with respect to X-axis.
- the first plurality of pores 140 are symmetric with respect to Y-axis.
- the second plurality of pores 180 are symmetric with respect to X-axis.
- the second plurality of pores 180 are symmetric with respect to Y-axis.
- a centerline 130 of the first wafer 120 is aligned with a centerline 170 of the second wafer 160 .
- the porous two-wafer battery 100 may include hundreds or thousands of cathode or anode pores.
- the first wafer 120 serves as an anode and the second wafer 160 serves as a cathode.
- FIG. 3 is a side view of a porous two-wafer battery 300 in examples of the present disclosure.
- the porous two-wafer battery 300 comprises a first wafer 320 and a second wafer 360 .
- the first wafer 320 comprises a first substrate 322 and a first passivation layer 345 on a front side 331 of the first wafer 320 .
- the first substrate 322 comprises a first plurality of pores 340 (shown in dashed lines because of the side view).
- the second wafer 360 comprises a second substrate 362 and a second passivation layer 385 on a front side 371 of the second wafer 360 .
- the second substrate 362 comprises a second plurality of pores 380 (shown in dashed lines because of the side view).
- the first passivation layer 345 and the second passivation layer 385 are made of a material selected from the group consisting of Ta2O5, HfO2, and SiN.
- a thickness of each of the first passivation layer 345 and the second passivation layer 385 is in a range from 30 microns to 100 microns.
- the first wafer 320 is parallel to the second wafer 360 .
- the first substrate 322 of the first wafer 320 is made of a silicon material.
- the second substrate 362 of the second wafer 360 is made of the silicon material.
- the first plurality of pores 340 are symmetric with respect to a center of the first wafer 320 .
- the second plurality of pores 380 are symmetric with respect to a center of the second wafer 360 .
- the first passivation layer 345 directly contacts the second passivation layer 385 .
- a centerline 330 of the first wafer 320 offsets from a centerline 370 of the second wafer 360 by a pre-determined distance 351 .
- the pre-determined distance 351 is in a range from 10% of a width 353 of a selected pore of the first plurality of pores 340 to 50% of the width 353 of the selected pore of the first plurality of pores 340 .
- the first wafer 320 serves as an anode and the second wafer 360 serves as a cathode.
- FIG. 4 is a cross-sectional plot along AA′ of the first wafer 120 of FIG. 2 in examples of the present disclosure.
- the second wafer 160 has similar structure as the first wafer 120 .
- the first wafer 120 comprises a first substrate 122 , a first conductive layer 430 on a respective side wall 442 of each of the first plurality of pores 140 , and a first passivation layer 476 on a front side of the first wafer 120 .
- the first substrate 122 comprises a plurality of pores 140 and a P+ doped region 123 .
- the first conductive layer 430 provides electrical conductivity and serves as a reactive surface for battery reactions.
- the silicon substrate may not in contact with lithium.
- the first passivation layer 476 prevents lithium reduction and prevents dendrite growth.
- the first passivation layer 476 comprises a first plurality of passivation sections 477 .
- Each of the first plurality of passivation sections 477 is of a first letter U shape.
- a first leg 471 of the first letter U shape is directly attached to the first conductive layer 430 of a first selected pore 491 of the first plurality of pores 140 .
- a second leg 472 of the first letter U shape is directly attached to the first conductive layer 430 of a second selected pore 492 of the first plurality of pores 140 .
- a length of the first leg 471 and a length of the second leg 472 is in a range from 20 microns to 50 microns.
- the first conductive layer 430 is made of a material selected from the group consisting of titanium nitride, silicates, silicon carbide, copper, and nickel.
- the first passivation layer 476 is made of a material selected from the group consisting of Ta2O5, HfO2, and SiN.
- the first conductive layer 430 may be formed by impregnation or deposition.
- An entirety of the first conductive layer 430 is in the inner portion of the first plurality of pores 140 . There is no direct path for electrical short. In addition, there is no SEI layer that would initiate the dendrite growth. Furthermore, there are no edge effects of protrusion.
- a first adhesion promotion layer 447 is between the first conductive layer 430 and the respective side wall 442 of each of the first plurality of pores 140 .
- a thickness of the first conductive layer 430 is in a range from 30 microns to 200 microns. In another example, a thickness of the first conductive layer 430 is in a range from 100 microns to 150 microns. In one example, a thickness of the adhesion promotion layer 447 is in a range from 20 microns to 200 microns.
- each of a porous silicon anode and a porous silicon cathode comprises 20 ⁇ m pore dimension, 22 ⁇ m pitch, 350 ⁇ m electrode thickness; TiN coating (100 ⁇ m), Ta2O5 dielectric coating on the inner surface (50 ⁇ m).
- the cathode material is LiCoO 2 or LiMn 2 O 4 .
- the electrolyte is 1 M LiFP6 in CE/DE.
- the battery is held in a pouch-type cell including rigid or semi-rigid containers.
- Another conductive layer may be added on top of the first conductive layer 430 to further improve conductivity.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Secondary Cells (AREA)
- Weting (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Battery Electrode And Active Subsutance (AREA)
- Battery Mounting, Suspending (AREA)
Abstract
A porous two-wafer battery comprises a first wafer and a second wafer. Each of the first wafer and the second wafer comprises a substrate, a conductive layer, and a passivation layer. The first wafer is parallel to the second wafer. The passivation layer of the first wafer is closer to the passivation layer of the second wafer. The first wafer serves as an anode and the second wafer serves as a cathode. The substrate comprises a plurality of pores and a P+ doped region. The plurality of pores are symmetric with respect to a respective center of each of the first wafer and the second wafer. An adhesion promotion layer is between the conductive layer and a respective side wall of the plurality of pores.
Description
- This patent application claims benefit of provisional patent applications 62/930,016, 62/930,018, 62/930,019, 62/930,020, and 62/930,021 because of a common inventor, Slobodan Petrovic. The disclosures made in the provisional patent applications 62/930,016, 62/930,018, 62/930,019, 62/930,020, and 62/930,021 are hereby incorporated by reference.
- This invention relates generally to a porous two-wafer battery. More particularly, the present invention relates to a porous silicon two-wafer, lithium battery.
- For lithium batteries, lithium metal dendritic growth is one of the most serious problems affecting the safety and functionality of lithium-based batteries. Dendrites are fractal deposits of various shapes such as needle-like, snowflake-like, tree-like, bush-like, moss-like, and whisker- like structures. During charging in Li metal (and Li-ion) anodes, lithium does not form a flat, homogeneous layer on the anode, but instead dendrites that can be needle-like or branched. Factors affecting Li dendrite growth at the anode are current density, electrolyte composition and concentration, and solid-electrolyte-interphase layer (SEI). Dendrites grow in a non-linear fashion and in apparently random motion of the tips of the lithium. The dendrites growth are not dominated by the direction of the electric field. In a configuration with two planar-type electrodes, the lithium dendrites inevitably grow towards the other electrode, penetrating thereby through the separator and causing short upon reaching the conductive surface of the opposite electrode.
- Methods using polymers, block copolymers, ionomers, HF, metal ions with a higher reduction potential than Li such as Sn4+, Sn2+, Al3+, In3+, Ga3+ and Bi3+, oligomers, ionic liquids to possibly suppress the dendrites growth are reported in the battery industry. Other methods include use of solid electrolyte, ceramic electrolyte, and self-healing electrostatic shield, e.g., Cs+.
- Variations of the formulations of electrolyte have also been reported. It includes modifications of the electrolyte salts: LiClO4, LiPF6, LiAsF4 and LiBF4, addition of ethers (DME and DEE), esters (PC, EC, DMC and DEC), EC/DMC and PC/DMC mixture with LiTFSI demonstrated to promote delayed dendrite formation.
- The methods above may suppress dendrite growth. But, it also introduce additional problems such as increased side reaction and modified cycling characteristics.
- The growth of lithium dendrite may result in electrical short. It can lead to battery heating up, catching fire, or exploding.
- Therefore, it is required for suppressing the growth of lithium dendrite especially for a high-power density, high current, low cost battery. It is possible to completely eliminate dendrite growth by placing the reaction of lithium reduction away from the surface of electrode and inside the pore of porous silicon. It is also possible to provide a structure that allows for high-power density and high current abilities.
- A porous two-wafer battery comprises a first wafer and a second wafer. Each of the first wafer and the second wafer comprises a substrate, a conductive layer, and a passivation layer. The first wafer is parallel to the second wafer. The passivation layer of the first wafer is closer to the passivation layer of the second wafer. The first wafer serves as an anode and the second wafer serves as a cathode.
- The substrate comprises a plurality of pores and a P+ doped region. The plurality of pores are symmetric with respect to a respective center of each of the first wafer and the second wafer. An adhesion promotion layer is between the conductive layer and a respective side wall of the plurality of pores.
-
FIG. 1 is a side view of a porous two-wafer battery in examples of the present disclosure. -
FIG. 2 is a front view of a wafer of a porous two-wafer battery in examples of the present disclosure. -
FIG. 3 is a side view of another porous two-wafer battery in examples of the present disclosure. -
FIG. 4 is a cross-sectional plot along AA′ of the wafer ofFIG. 2 in examples of the present disclosure. -
FIG. 1 is a side view of a porous two-wafer battery 100 in examples of the present disclosure. The porous two-wafer battery 100 comprises afirst wafer 120, asecond wafer 160, and an optional electrolyte separator 110 (shown in dashed lines) between afront side 131 of thefirst wafer 120 and afront side 171 of thesecond wafer 160.FIG. 2 is a front view of thefirst wafer 120 of the porous two-wafer battery 100 in examples of the present disclosure. Thefirst wafer 120 comprises afirst substrate 122. Thefirst substrate 122 comprises a plurality of pores 140 (shown in dashed lines because of the side view). Thesecond wafer 160 comprises asecond substrate 162. Thesecond substrate 162 comprises a plurality of pores 180 (shown in dashed lines because of the side view). - In one example, the plurality of
pores 140 and the plurality ofpores 180 are of rectangular shapes. In another example, the plurality ofpores 140 and the plurality ofpores 180 are of square shapes. In still another example, the plurality ofpores 140 and the plurality ofpores 180 are of circular shapes. A diameter of the plurality ofpores 140 and the plurality ofpores 180 is in a range from 1 micron to 100 microns. In examples of the present disclosure, a diameter and a pitch of the plurality ofpores 140 and the plurality ofpores 180 is 20 microns and 22 microns respectively. - In one example, a diameter of the
first wafer 120 is 4 inches. In another example, a diameter of thefirst wafer 120 is 6 inches. In still another example, a diameter of thefirst wafer 120 is 8 inches. In yet another example, a diameter of thefirst wafer 120 is 12 inches. The capacity (charge) of thefirst wafer 120 is 60 Ah. In yet still another example, a diameter of thefirst wafer 120 is 18 inches. In examples of the present disclosure, the capacity (charge) of thefirst wafer 120 is in a range from 1 Ah to 100 Ah. A thickness of the first wafer is in a range from 100 microns to 750 microns. - In examples of the present disclosure, the
first wafer 120 is parallel to thesecond wafer 160. Thefront side 131 of thefirst wafer 120 is closer to thefront side 171 of thesecond wafer 160 than aback side 173 of thesecond wafer 160. Thefront side 171 of thesecond wafer 160 is closer to thefront side 131 of thefirst wafer 120 than aback side 133 of thefirst wafer 120. - In examples of the present disclosure, the
first substrate 122 of thefirst wafer 120 is made of a silicon material. Thesecond substrate 162 of thesecond wafer 160 is made of the silicon material. - In examples of the present disclosure, the first plurality of
pores 140 are symmetric with respect to acenter 231 of thefirst wafer 120. The second plurality ofpores 180 are symmetric with respect to a center of thesecond wafer 160. The first plurality ofpores 140 are symmetric with respect to X-axis. The first plurality ofpores 140 are symmetric with respect to Y-axis. The second plurality ofpores 180 are symmetric with respect to X-axis. The second plurality ofpores 180 are symmetric with respect to Y-axis. - In examples of the present disclosure, a
centerline 130 of thefirst wafer 120 is aligned with acenterline 170 of thesecond wafer 160. The porous two-wafer battery 100 may include hundreds or thousands of cathode or anode pores. - In examples of the present disclosure, the
first wafer 120 serves as an anode and thesecond wafer 160 serves as a cathode. -
FIG. 3 is a side view of a porous two-wafer battery 300 in examples of the present disclosure. The porous two-wafer battery 300 comprises afirst wafer 320 and asecond wafer 360. Thefirst wafer 320 comprises afirst substrate 322 and afirst passivation layer 345 on afront side 331 of thefirst wafer 320. Thefirst substrate 322 comprises a first plurality of pores 340 (shown in dashed lines because of the side view). Thesecond wafer 360 comprises asecond substrate 362 and asecond passivation layer 385 on afront side 371 of thesecond wafer 360. Thesecond substrate 362 comprises a second plurality of pores 380 (shown in dashed lines because of the side view). - In examples of the present disclosure, the
first passivation layer 345 and thesecond passivation layer 385 are made of a material selected from the group consisting of Ta2O5, HfO2, and SiN. A thickness of each of thefirst passivation layer 345 and thesecond passivation layer 385 is in a range from 30 microns to 100 microns. - In examples of the present disclosure, the
first wafer 320 is parallel to thesecond wafer 360. In examples of the present disclosure, thefirst substrate 322 of thefirst wafer 320 is made of a silicon material. Thesecond substrate 362 of thesecond wafer 360 is made of the silicon material. - In examples of the present disclosure, the first plurality of
pores 340 are symmetric with respect to a center of thefirst wafer 320. The second plurality ofpores 380 are symmetric with respect to a center of thesecond wafer 360. - In examples of the present disclosure, the
first passivation layer 345 directly contacts thesecond passivation layer 385. Acenterline 330 of thefirst wafer 320 offsets from acenterline 370 of thesecond wafer 360 by apre-determined distance 351. In examples of the present disclosure, thepre-determined distance 351 is in a range from 10% of awidth 353 of a selected pore of the first plurality ofpores 340 to 50% of thewidth 353 of the selected pore of the first plurality ofpores 340. - In examples of the present disclosure, the
first wafer 320 serves as an anode and thesecond wafer 360 serves as a cathode. -
FIG. 4 is a cross-sectional plot along AA′ of thefirst wafer 120 ofFIG. 2 in examples of the present disclosure. Thesecond wafer 160 has similar structure as thefirst wafer 120. Thefirst wafer 120 comprises afirst substrate 122, a firstconductive layer 430 on arespective side wall 442 of each of the first plurality ofpores 140, and afirst passivation layer 476 on a front side of thefirst wafer 120. Thefirst substrate 122 comprises a plurality ofpores 140 and a P+ dopedregion 123. - The first
conductive layer 430 provides electrical conductivity and serves as a reactive surface for battery reactions. The silicon substrate may not in contact with lithium. Thefirst passivation layer 476 prevents lithium reduction and prevents dendrite growth. - In examples of the present disclosure, the
first passivation layer 476 comprises a first plurality ofpassivation sections 477. Each of the first plurality ofpassivation sections 477 is of a first letter U shape. Afirst leg 471 of the first letter U shape is directly attached to the firstconductive layer 430 of a firstselected pore 491 of the first plurality ofpores 140. Asecond leg 472 of the first letter U shape is directly attached to the firstconductive layer 430 of a secondselected pore 492 of the first plurality ofpores 140. A length of thefirst leg 471 and a length of thesecond leg 472 is in a range from 20 microns to 50 microns. - In examples of the present disclosure, the first
conductive layer 430 is made of a material selected from the group consisting of titanium nitride, silicates, silicon carbide, copper, and nickel. Thefirst passivation layer 476 is made of a material selected from the group consisting of Ta2O5, HfO2, and SiN. The firstconductive layer 430 may be formed by impregnation or deposition. - An entirety of the first
conductive layer 430 is in the inner portion of the first plurality ofpores 140. There is no direct path for electrical short. In addition, there is no SEI layer that would initiate the dendrite growth. Furthermore, there are no edge effects of protrusion. - In examples of the present disclosure, a first
adhesion promotion layer 447 is between the firstconductive layer 430 and therespective side wall 442 of each of the first plurality ofpores 140. - In one example, a thickness of the first
conductive layer 430 is in a range from 30 microns to 200 microns. In another example, a thickness of the firstconductive layer 430 is in a range from 100 microns to 150 microns. In one example, a thickness of theadhesion promotion layer 447 is in a range from 20 microns to 200 microns. - In examples of the present disclosure, each of a porous silicon anode and a porous silicon cathode comprises 20 μm pore dimension, 22 μm pitch, 350 μm electrode thickness; TiN coating (100 μm), Ta2O5 dielectric coating on the inner surface (50 μm). The cathode material is LiCoO2 or LiMn2O4. The electrolyte is 1 M LiFP6 in CE/DE.
- In examples of the present disclosure, the battery is held in a pouch-type cell including rigid or semi-rigid containers. Another conductive layer may be added on top of the first
conductive layer 430 to further improve conductivity. - Those of ordinary skill in the art may recognize that modifications of the embodiments disclosed herein are possible. For example, a number of the first plurality of pores may vary. Other modifications may occur to those of ordinary skill in this art, and all such modifications are deemed to fall within the purview of the present invention, as defined by the claims.
Claims (14)
1. A porous two-wafer battery comprising
a first wafer comprising
a first substrate comprising
a first plurality of pores;
a first conductive layer on a respective side wall of each of the first plurality of pores; and
a first passivation layer on a front side of the first wafer; and
a second wafer comprising
a second substrate comprising
a second plurality of pores;
a second conductive layer on a respective side wall of each of the second plurality of pores; and
a second passivation layer on a front side of the second wafer;
wherein the first wafer is parallel to the second wafer;
wherein the front side of the first wafer is closer to the front side of the second wafer than a back side of the second wafer; and
wherein the front side of the second wafer is closer to the front side of the first wafer than a back side of the first wafer.
2. The porous two-wafer battery of claim 1 , wherein the first substrate of the first wafer is made of a silicon material; and wherein the second substrate of the second wafer is made of the silicon material.
3. The porous two-wafer battery of claim 1 , wherein an electrolyte separator is between the front side of the first wafer and the front side of the second wafer.
4. The porous two-wafer battery of claim 1 , wherein the first passivation layer comprises a first plurality of passivation sections;
wherein each of the first plurality of passivation sections is of a first letter U shape;
wherein the second passivation layer comprises a second plurality of passivation sections; and
wherein each of the second plurality of passivation sections is of a second letter U shape.
5. The porous two-wafer battery of claim 4 , wherein a first leg of the first letter U shape is directly attached to the first conductive layer of a first selected pore of the first plurality of pores;
wherein a second leg of the first letter U shape is directly attached to the first conductive layer of a second selected pore of the first plurality of pores;
wherein the first selected pore of the first plurality of pores is different from the second selected pore of the first plurality of pores;
wherein a first leg of the second letter U shape is directly attached to the first conductive layer of a first selected pore of the second plurality of pores;
wherein a second leg of the second letter U shape is directly attached to the first conductive layer of a second selected pore of the second plurality of pores; and
wherein the first selected pore of the second plurality of pores is different from the second selected pore of the second plurality of pores.
6. The porous two-wafer battery of claim 1 , wherein the first plurality of pores are symmetric with respect to a center of the first wafer; and wherein the second plurality of pores are symmetric with respect to a center of the second wafer.
7. The porous two-wafer battery of claim 6 , wherein a centerline of the first wafer is aligned with a centerline of the second wafer.
8. The porous two-wafer battery of claim 6 , wherein the first passivation layer directly contacts the second passivation layer.
9. The porous two-wafer battery of claim 8 , wherein a centerline of the first wafer offsets from a centerline of the second wafer by a range from ten percent of a width of a selected pore of the first plurality of pores to fifty percent of the width of the selected pore of the first plurality of pores.
10. The porous two-wafer battery of claim 1 , wherein a first adhesion promotion layer is between the first conductive layer and the respective side wall of each of the first plurality of pores; and wherein a second adhesion promotion layer is between the second conductive layer and the respective side wall of each of the second plurality of pores.
11. The porous two-wafer battery of claim 1 , wherein the first wafer serves as an anode and the second wafer serves as a cathode.
12. The porous two-wafer battery of claim 1 , wherein the first conductive layer and the second conductive layer are made of a material selected from the group consisting of titanium nitride, silicates, silicon carbide, copper, and nickel.
13. The porous two-wafer battery of claim 1 , wherein the first passivation layer and the second passivation layer are made of a material selected from the group consisting of Ta2O5, HfO2, and SiN.
14. The porous two-wafer battery of claim 1 , wherein the first substrate further comprises a first P+ doped region; and wherein the second substrate further comprises a second P+ doped region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/087,575 US20210135231A1 (en) | 2019-11-04 | 2020-11-02 | Porous two-wafer battery |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201962930021P | 2019-11-04 | 2019-11-04 | |
US201962930020P | 2019-11-04 | 2019-11-04 | |
US201962930019P | 2019-11-04 | 2019-11-04 | |
US201962930016P | 2019-11-04 | 2019-11-04 | |
US201962930018P | 2019-11-04 | 2019-11-04 | |
US17/087,575 US20210135231A1 (en) | 2019-11-04 | 2020-11-02 | Porous two-wafer battery |
Publications (1)
Publication Number | Publication Date |
---|---|
US20210135231A1 true US20210135231A1 (en) | 2021-05-06 |
Family
ID=75686355
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/087,600 Pending US20210135003A1 (en) | 2019-11-04 | 2020-11-02 | Single-chip containing porous-wafer battery and device and method of making the same |
US17/087,607 Active 2041-02-04 US11342625B2 (en) | 2019-11-04 | 2020-11-02 | Method of fabricating and method of using porous wafer battery |
US17/087,617 Abandoned US20210135271A1 (en) | 2019-11-04 | 2020-11-02 | Method of fabricating porous wafer battery |
US17/087,604 Abandoned US20210135311A1 (en) | 2019-11-04 | 2020-11-02 | Battery package containing porous wafer battery |
US17/087,575 Abandoned US20210135231A1 (en) | 2019-11-04 | 2020-11-02 | Porous two-wafer battery |
Family Applications Before (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/087,600 Pending US20210135003A1 (en) | 2019-11-04 | 2020-11-02 | Single-chip containing porous-wafer battery and device and method of making the same |
US17/087,607 Active 2041-02-04 US11342625B2 (en) | 2019-11-04 | 2020-11-02 | Method of fabricating and method of using porous wafer battery |
US17/087,617 Abandoned US20210135271A1 (en) | 2019-11-04 | 2020-11-02 | Method of fabricating porous wafer battery |
US17/087,604 Abandoned US20210135311A1 (en) | 2019-11-04 | 2020-11-02 | Battery package containing porous wafer battery |
Country Status (1)
Country | Link |
---|---|
US (5) | US20210135003A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20210135003A1 (en) * | 2019-11-04 | 2021-05-06 | Xnrgi, Inc. | Single-chip containing porous-wafer battery and device and method of making the same |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6432577B1 (en) * | 2000-06-29 | 2002-08-13 | Sandia Corporation | Apparatus and method for fabricating a microbattery |
US20170040580A1 (en) * | 2015-08-07 | 2017-02-09 | International Business Machines Corporation | All-silicon hermetic package and processing for narrow, low-profile microbatteries |
US20170194607A1 (en) * | 2015-12-30 | 2017-07-06 | International Business Machines Corporation | Dual seal microbattery and method of making |
US20180375067A1 (en) * | 2017-06-26 | 2018-12-27 | International Business Machines Corporation | Micro-battery using glass package |
US20200020895A1 (en) * | 2018-07-11 | 2020-01-16 | International Business Machines Corporation | Silicon substrate containing integrated porous silicon electrodes for energy storage devices |
US20200403268A1 (en) * | 2017-03-20 | 2020-12-24 | Millibatt, Inc. | Battery system and production method |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1210872B (en) * | 1982-04-08 | 1989-09-29 | Ates Componenti Elettron | PROCESS FOR THE MANUFACTURE OF COMPLEMENTARY MOS TRANSISTORS IN HIGH DENSITY INTEGRATED CIRCUITS FOR HIGH VOLTAGES. |
US6197450B1 (en) * | 1998-10-22 | 2001-03-06 | Ramot University Authority For Applied Research & Industrial Development Ltd. | Micro electrochemical energy storage cells |
US20030042587A1 (en) | 2001-08-31 | 2003-03-06 | Tsung-Jen Lee | IC packaging and manufacturing methods |
AU2003301357A1 (en) * | 2002-10-17 | 2004-05-04 | Tel-Aviv University Future Technology Development L.P. | Thin-film cathode for 3-dimensional microbattery and method for preparing such cathode |
CA2432397A1 (en) * | 2003-06-25 | 2004-12-25 | Hydro-Quebec | Procedure for preparing an electrode from porous silicon, the electrode so obtained, and an electrochemical system containing at least one such electrode |
US7295029B2 (en) * | 2005-03-24 | 2007-11-13 | Memsic, Inc. | Chip-scale package for integrated circuits |
US7776679B2 (en) * | 2007-07-20 | 2010-08-17 | Stmicroelectronics Crolles 2 Sas | Method for forming silicon wells of different crystallographic orientations |
KR101590339B1 (en) * | 2007-08-21 | 2016-02-01 | 에이일이삼 시스템즈 인코포레이티드 | Separator for electrochemical cell and method for its manufacture |
US8600543B2 (en) | 2008-11-10 | 2013-12-03 | Kelk Ltd. | Apparatus and method for controlling temperature of semiconductor wafers |
US20100291431A1 (en) * | 2009-05-13 | 2010-11-18 | Front Edge Technology, Inc. | Thin film battery with protective packaging |
WO2012091459A2 (en) * | 2010-12-28 | 2012-07-05 | 주식회사 엘지화학 | Battery module storage device, battery module temperature adjustment device, and electric power storage system having same |
US9368429B2 (en) * | 2011-10-25 | 2016-06-14 | Intel Corporation | Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips |
FR2982082B1 (en) * | 2011-11-02 | 2013-11-22 | Fabien Gaben | PROCESS FOR PRODUCING THIN-FILT THIN-FILTER BATTERIES |
EP3422415B1 (en) * | 2014-02-28 | 2023-08-02 | LFoundry S.r.l. | Semiconductor device comprising a laterally diffused mos transistor |
US10833301B2 (en) * | 2019-01-02 | 2020-11-10 | International Business Machines Corporation | Through silicon via energy storage devices |
US20210135003A1 (en) * | 2019-11-04 | 2021-05-06 | Xnrgi, Inc. | Single-chip containing porous-wafer battery and device and method of making the same |
-
2020
- 2020-11-02 US US17/087,600 patent/US20210135003A1/en active Pending
- 2020-11-02 US US17/087,607 patent/US11342625B2/en active Active
- 2020-11-02 US US17/087,617 patent/US20210135271A1/en not_active Abandoned
- 2020-11-02 US US17/087,604 patent/US20210135311A1/en not_active Abandoned
- 2020-11-02 US US17/087,575 patent/US20210135231A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6432577B1 (en) * | 2000-06-29 | 2002-08-13 | Sandia Corporation | Apparatus and method for fabricating a microbattery |
US20170040580A1 (en) * | 2015-08-07 | 2017-02-09 | International Business Machines Corporation | All-silicon hermetic package and processing for narrow, low-profile microbatteries |
US20170194607A1 (en) * | 2015-12-30 | 2017-07-06 | International Business Machines Corporation | Dual seal microbattery and method of making |
US20200403268A1 (en) * | 2017-03-20 | 2020-12-24 | Millibatt, Inc. | Battery system and production method |
US20180375067A1 (en) * | 2017-06-26 | 2018-12-27 | International Business Machines Corporation | Micro-battery using glass package |
US20200020895A1 (en) * | 2018-07-11 | 2020-01-16 | International Business Machines Corporation | Silicon substrate containing integrated porous silicon electrodes for energy storage devices |
Also Published As
Publication number | Publication date |
---|---|
US20210135311A1 (en) | 2021-05-06 |
US20210135271A1 (en) | 2021-05-06 |
US20210134608A1 (en) | 2021-05-06 |
US20210135003A1 (en) | 2021-05-06 |
US11342625B2 (en) | 2022-05-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102603481B1 (en) | High salt concentration electrolyte for rechargeable lithium batteries | |
US10553899B2 (en) | Battery including a polyether-based organic solid electrolyte | |
US20160172682A1 (en) | Method for producing an electrode for a lithium-ion battery | |
CN111712949B (en) | Lithium electrode and lithium secondary battery comprising same | |
JP5151329B2 (en) | Positive electrode body and lithium secondary battery using the same | |
KR20200018902A (en) | A negative electrode for a lithium secondary battery formed with a ferroelectric polymer protective layer, method for preparing the same, and a lithium secondary battery including the negative electrode | |
US11158882B2 (en) | Lithum metal battery | |
KR20140058928A (en) | The non-aqueous and high-capacity lithium secondary battery | |
US20210135231A1 (en) | Porous two-wafer battery | |
CN100470918C (en) | Battery and manufacturing method thereof | |
KR20160053708A (en) | Electrode for rechargeable lithium battery and rechargeable lithium battery including the same | |
US9564658B2 (en) | Lithium-ion secondary battery and electrolyte thereof | |
CN114530670A (en) | Battery cell structure and secondary battery | |
Wild | Anode–electrolyte interface | |
KR102566944B1 (en) | Structure for Manufacturing Lithium Electrode and Method for Preparing Structure for Manufacturing Lithium Electrode | |
US20240213460A1 (en) | Lithium metal anode protective layer and method of depositing same on lithium metal anode | |
JP2018160349A (en) | Electric storage device | |
KR102448073B1 (en) | Porous polymer membrane coated oxide semiconductor, lithium-sulfur battery including the same as a negative electrode and method for preparing lithium-sulfur battery | |
KR20180023688A (en) | Secondary Battery Comprising Electrode Having Thin Electrode Active Material Layer | |
KR20220097821A (en) | Lithium metal anode for Lithium batteries | |
CN118281162A (en) | Lithium metal negative electrode, method for manufacturing same, and lithium metal battery | |
WO2021226180A9 (en) | Inhibition of lithium dendrite growth using ultra-thin sub-nanometer porous carbon nanomembrane in conventional and solid-state lithium-ion batteries | |
KR20230138935A (en) | High capacity and high reversible anode for lithium secondary batteries, manufacturing method for the same, and lithium secondary batteries including the same | |
KR20240006382A (en) | Electrode assembly and method of preparing thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: XNRGI, INC., WASHINGTON Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:D'COUTO, GERARD CHRISTOPHER;REEL/FRAME:054247/0977 Effective date: 20201102 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: APPLICATION DISPATCHED FROM PREEXAM, NOT YET DOCKETED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |