US20210105893A1 - Circuit board - Google Patents
Circuit board Download PDFInfo
- Publication number
- US20210105893A1 US20210105893A1 US17/125,475 US202017125475A US2021105893A1 US 20210105893 A1 US20210105893 A1 US 20210105893A1 US 202017125475 A US202017125475 A US 202017125475A US 2021105893 A1 US2021105893 A1 US 2021105893A1
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- United States
- Prior art keywords
- pin row
- pin
- signal
- circuit board
- signal vias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
- H01R13/6461—Means for preventing cross-talk
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/114—Pad being close to via, but not surrounding the via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0228—Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09236—Parallel layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09409—Multiple rows of pads, lands, terminals or dummy patterns; Multiple rows of mounted components
Definitions
- the invention relates to a circuit board. More particularly, the invention relates to a circuit board capable of improving signal quality.
- a plurality of signal vias are disposed on a printed circuit board to enable signal transmission among the elements of the printed circuit board through signal traces of each of the layers of the printed circuit board as well as the corresponding signal vias.
- the invention provides a circuit board in which a plurality of signal vias of at least one pin row of the circuit board are alternately disposed at different sides of the at least one pin row to prevent the signal vias from being disposed too close to each other for increasing signal quality of the at least one pin row.
- a circuit board in an embodiment of the invention, includes a first pin row, a second pin row, and a plurality of signal vias.
- the first pin row has a first side and a second side, wherein the first side of the first pin row and the second side of the first pin row are opposite to each other.
- the second pin row has a first side and a second side, wherein the first side of the second pin row and the second side of the second pin row are opposite to each other, and one of the first side and the second side of the second pin row is adjacent to one of the first side and the second side of the first pin row.
- a plurality of traces of the circuit board are electrically connected to a plurality of pins of the first pin row and a plurality of pins of the second pin row respectively through the signal vias.
- Three consecutive signal vias of the signal vias are sequentially disposed at the first side of the first pin row, the first side of the second pin row, and the second side of the first pin row.
- the circuit board further includes a third pin row.
- the third pin row has a first side and a second side.
- the first side of the third pin row and the second side of the third pin row are opposite to each other, and one of the first side and the second side of the third pin row is adjacent to one of the first side and the second side of the second pin row.
- Four consecutive signal vias of the signal vias are sequentially disposed at the first side of the first pin row, the first side of the second pin row, the first side of the third pin row, and the second side of the first pin row.
- a circuit board includes N pin rows and a plurality of signal vias.
- Each of the N pin rows has a first side and a second side. The first side and the second side of each of the N pin rows are opposite to each other.
- One of the first side and the second side of a Jth pin row of the N pin rows is adjacent to one of the first side and the second side of a J ⁇ 1th pin row of the N pin rows, wherein N is an integer greater than or equal to 3.
- a plurality of traces of the circuit board are electrically connected to a plurality of pins of the N pin row respectively through the signal vias.
- the signal vias of the at least one pin row of the circuit board are alternately disposed at two opposite sides of the at least one pin row. In this way, the signal vias are prevented from being located too close to each other, and therefore, signal quality of the at least one pin row of the circuit board is increased.
- FIG. 1 is a schematic diagram illustrating implementation of a circuit board according to an embodiment of the invention.
- FIG. 2 is a schematic diagram illustrating implementation of a circuit board according to another embodiment of the invention.
- FIG. 3A to FIG. 3D are schematic diagrams illustrating implementation of circuit boards according to still another embodiment of the invention.
- FIG. 4 is a schematic diagram illustrating implementation of a circuit board according to still another embodiment of the invention.
- FIG. 5 is a schematic diagram illustrating implementation of a circuit board according to still another embodiment of the invention.
- FIG. 6 is a schematic chart of a crosstalk interference value of at least one pin row of a circuit board.
- FIG. 7 is a schematic chart of a signal-to-noise ratio of at least one pin row of a circuit board.
- FIG. 1 is a schematic diagram illustrating implementation of a circuit board according to an embodiment of the invention.
- a circuit board 100 includes a first pin row 110 and a plurality of signal vias 180 .
- the first pin row 110 may be, for example, a single row of pins of a surface-mount technology (SMT) connector, which should however not be construed as limitations to the invention.
- the first pin row 110 has a plurality of pins 112 sequentially arranged, and each of the signal vias 180 is adjacent to a corresponding one of the pins 112 .
- a plurality of traces 170 of the circuit board 100 may be electrically connected to the pins 112 of the first pin row 110 respectively through the signal vias 180 .
- a signal via H 1 is adjacent to a pin A 1 of the first pin row 110 , and a first trace of the circuit board 100 may be electrically connected to the pin A 1 through the signal via H 1 ;
- a signal via H 2 is adjacent to a pin A 2 of the first pin row 110 , and a second trace of the circuit board 100 may be electrically connected to the pin A 2 through the signal via H 2 ;
- a signal via H 3 is adjacent to a pin A 3 of the first pin row 110 , and a third trace of the circuit board 100 may be electrically connected to the pin A 3 through the signal via H 3 .
- the invention should not be construed as limited thereto. In fact, whether the signal via corresponding to each of the pins of the first pin row 110 is required to be disposed depends on actual applications or design requirements.
- the first pin row 110 includes a first side S 11 and a second side S 12 , wherein the first side S 11 and the second side S 12 are opposite to each other.
- the three consecutive signal vias H 1 , H 2 , and H 3 of the signal vias 180 are sequentially disposed at the first side S 11 of the first pin row 110 , the second side S 12 of the first pin row 110 , and the first side S 11 of the first pin row 110 .
- Alternate arrangement of the signal vias H 1 , H 2 , and H 3 as shown by the dashed arrows in FIG. 1 is thereby formed.
- the signal vias H 1 , H 2 , and H 3 are prevented from being disposed together at the same side (e.g., the first side S 11 ) of the first pin row 110 .
- the signal vias H 1 , H 2 , and H 3 are prevented from being located too close to each other, and that crosstalk interference is prevented from being generated. Signal quality of the signal vias H 1 , H 2 , and H 3 of the circuit board 100 is thereby increased.
- the signal vias 180 of FIG. 1 may include a differential signal pair via (e.g. signal vias H 5 and H 6 ), wherein a differential signal pair trace (e.g. traces 170 A and 170 B) of the circuit board 100 may be electrically connected to a differential signal pair pin (e.g. pins 112 A and 112 B) of the first pin row 110 through the differential signal pair via.
- the differential signal pair via is disposed at a same side of the first pin row 110 .
- the signal vias 180 of FIG. 1 may include at least two consecutive grounding vias (not shown), wherein the at least two consecutive grounding vias are both disposed at a same side of the first pin row 110 .
- the circuit board 100 of FIG. 1 may further include a plurality of grounding vias 190 , wherein the grounding vias 190 may be distributed around the signal vias 180 for increasing signal quality of the signal vias 180 .
- FIG. 2 is a schematic diagram illustrating implementation of a circuit board according to another embodiment of the invention.
- a circuit board 200 of FIG. 2 may also include the first pin row 110 and the signal vias 180 , wherein the first pin row 110 has the pins 112 sequentially arranged.
- the plurality of traces 170 of the circuit board 200 may be electrically connected to the pins 112 of the first pin row 110 respectively through the signal vias 180 .
- whether the signal via corresponding to each of the pins of the pins 112 in FIG. 2 is required to be disposed depends on actual applications or design requirements.
- the four consecutive signal vias H 1 to H 4 of the signal vias 180 in FIG. 2 are electrically connected to the pins A 1 to A 4 respectively and are sequentially disposed at the first side S 11 of the first pin row 110 , the second side S 12 of the first pin row 110 , the first side S 11 of the first pin row 110 , and the second side S 12 of the first pin row 110 .
- Alternate arrangement of the signal vias H 1 to H 4 as shown by the dashed arrows in FIG. 2 is thereby formed.
- the signal vias H 1 to H 4 in FIG. 2 are prevented from being disposed together at the same side of the first pin row 110 .
- the signal vias H 1 to H 4 are prevented from being located too close to each other, and that crosstalk interference is prevented from being generated.
- Signal quality of the signal vias H 1 to H 4 of the circuit board 200 is thereby increased.
- other implementation details of the circuit board 200 of FIG. 2 may be referred to the related description of the circuit board 100 of FIG. 1 , and a relevant description thereof is thus omitted.
- five (or more) consecutive signal vias of the signal vias 180 may similarly be disposed sequentially at the first side S 11 of the first pin row 110 and the second side S 12 of the first pin row 110 in cycles by a designer. That is, the five or more signal vias of the signal vias 180 may be sequentially disposed at different sides of the first pin row 110 for improving signal quality of the circuit board. Thus, details are not repeated hereinafter.
- FIG. 3A is a schematic diagram illustrating implementation of a circuit board according to still another embodiment of the invention.
- a circuit board 300 A may include a first pin row 310 , a second pin row 320 , and a plurality of signal vias 380 .
- the first pin row 310 and the second pin row 320 may be, for example, double rows of pins of a surface-mount technology connector, which should however not be construed as limitations to the invention.
- the first pin row 310 has a plurality of pins 312 sequentially arranged, and the second pin row 320 has a plurality of pins 322 sequentially arranged.
- each of the signal vias 380 is adjacent to a corresponding one pin of the pins 312 and 322 .
- a plurality of traces 370 of the circuit board 300 A may be electrically connected to the pins 312 of the first pin row 310 and the pins 322 of the second pin row 320 respectively through the signal vias 380 .
- the signal via H 1 is adjacent to a pin B 1 of the first pin row 310 , and a first trace of the circuit board 300 A may be electrically connected to the pin B 1 of the first pin row 310 through the signal via H 1 ;
- the signal via H 2 is adjacent to a pin B 2 of the second pin row 320 , and a second trace of the circuit board 300 A may be electrically connected to the pin B 2 of the second pin row 320 through the signal via H 2 ;
- the signal via H 3 is adjacent to a pin B 3 of the first pin row 310 , and a third trace of the circuit board 300 A may be electrically connected to the pin B 3 of the first pin row 310 through the signal via H 3 .
- the invention should not be construed as limited thereto. In fact, whether the signal via corresponding to each of the pins in the first pin row 310 and the second pin row 320 is required to be disposed depends on actual applications or design requirements.
- the first pin row 310 includes a first side S 11 and a second side S 12 , wherein the first side S 11 and the second side S 12 are opposite to each other.
- the second pin row 320 has a first side S 21 and a second side S 22 , wherein the first side S 21 and the second side S 22 are opposite to each other, and the second side S 22 of the second pin row 320 is adjacent to the first side S 11 of the first pin row 310 .
- the three consecutive signal vias H 1 , H 2 , and H 3 of the signal vias 380 are sequentially disposed at the first side S 11 of the first pin row 310 , the first side S 21 of the second pin row 320 , and the second side S 12 of the first pin row 310 .
- FIG. 3B is a schematic diagram illustrating implementation of a circuit board according to still another embodiment of the invention.
- a circuit board 300 B may include a first pin row 310 , a second pin row 320 , and a plurality of signal vias 380 .
- the first pin row 310 has a plurality of pins 312 sequentially arranged
- the second pin row 320 has a plurality of pins 322 sequentially arranged.
- each of the signal vias 380 is adjacent to a corresponding one pin of the pins 312 and 322 .
- a plurality of traces 370 of the circuit board 300 B may be electrically connected to the pins 312 of the first pin row 310 and the pins 322 of the second pin row 320 respectively through the signal vias 380 .
- the signal via H 1 is adjacent to a pin C 1 of the first pin row 310
- a first trace of the circuit board 300 B may be electrically connected to the pin C 1 of the first pin row 310 through the signal via H 1
- the signal via H 2 is adjacent to a pin C 2 of the second pin row 320
- a second trace of the circuit board 300 B may be electrically connected to the pin C 2 of the second pin row 320 through the signal via H 2
- the signal via H 3 is adjacent to a pin C 3 of the first pin row 310
- a third trace of the circuit board 300 B may be electrically connected to the pin C 3 of the first pin row 310 through the signal via H 3 .
- the invention should not be construed as limited thereto. In fact, whether the signal
- the first pin row 310 includes a first side S 11 and a second side S 12 , wherein the first side S 11 and the second side S 12 are opposite to each other.
- the second pin row 320 includes a first side S 21 and a second side S 22 , wherein the first side S 21 and the second side S 22 are opposite to each other, and the second side S 22 of the second pin row 320 is adjacent to the first side S 11 of the first pin row 310 .
- the three consecutive signal vias H 1 , H 2 , and H 3 of the signal vias 380 are sequentially disposed at the first side S 11 of the first pin row 310 , the first side S 21 of the second pin row 320 , and the second side S 12 of the first pin row 310 .
- FIG. 3C is a schematic diagram illustrating implementation of a circuit board according to still another embodiment of the invention.
- a circuit board 300 C may include a first pin row 310 , a second pin row 320 , and a plurality of signal vias 380 .
- the first pin row 310 has a plurality of pins 312 sequentially arranged
- the second pin row 320 has a plurality of pins 322 sequentially arranged.
- each of the signal vias 380 is adjacent to a corresponding one pin of the pins 312 and 322 .
- a plurality of traces 370 of the circuit board 300 C may be electrically connected to the pins 312 of the first pin row 310 and the pins 322 of the second pin row 320 respectively through the signal vias 380 .
- the signal via H 1 is adjacent to a pin D 1 of the first pin row 310
- a first trace of the circuit board 300 C may be electrically connected to the pin D 1 of the first pin row 310 through the signal via H 1
- the signal via H 2 is adjacent to a pin D 2 of the second pin row 320
- a second trace of the circuit board 300 C may be electrically connected to the pin D 2 of the second pin row 320 through the signal via H 2
- the signal via H 3 is adjacent to a pin D 3 of the first pin row 310
- a third trace of the circuit board 300 C may be electrically connected to the pin D 3 of the first pin row 310 through the signal via H 3 .
- the invention should not be construed as limited thereto. In fact, whether the signal
- the first pin row 310 includes a first side S 11 and a second side S 12 , wherein the first side S 11 and the second side S 12 are opposite to each other.
- the second pin row 320 includes a first side S 21 and a second side S 22 , wherein the first side S 21 and the second side S 22 are opposite to each other, and the first side S 21 of the second pin row 320 is adjacent to the second side S 12 of the first pin row 310 .
- the three consecutive signal vias H 1 , H 2 , and H 3 of the signal vias 380 are sequentially disposed at the first side S 11 of the first pin row 310 , the first side S 21 of the second pin row 320 , and the second side S 12 of the first pin row 310 .
- FIG. 3D is a schematic diagram illustrating implementation of a circuit board according to still another embodiment of the invention.
- a circuit board 300 D may include a first pin row 310 , a second pin row 320 , and a plurality of signal vias 380 .
- the first pin row 310 has a plurality of pins 312 sequentially arranged
- the second pin row 320 has a plurality of pins 322 sequentially arranged.
- each of the signal vias 380 is adjacent to a corresponding one pin of the pins 312 and 322 .
- a plurality of traces 370 of the circuit board 300 D may be electrically connected to the pins 312 of the first pin row 310 and the pins 322 of the second pin row 320 respectively through the signal vias 380 .
- a signal via H 1 is adjacent to a pin E 1 of the first pin row 310
- a first trace of the circuit board 300 D may be electrically connected to the pin E 1 of the first pin row 310 through the signal via H 1
- a signal via H 2 is adjacent to a pin E 2 of the second pin row 320
- a second trace of the circuit board 300 D may be electrically connected to the pin E 2 of the second pin row 320 through the signal via H 2
- a signal via H 3 is adjacent to a pin E 3 of the first pin row 310
- a third trace of the circuit board 300 D may be electrically connected to the pin E 3 of the first pin row 310 through the signal via H 3 .
- the first pin row 310 includes a first side S 11 and a second side S 12 , wherein the first side S 11 and the second side S 12 are opposite to each other.
- the second pin row 320 includes a first side S 21 and a second side S 22 , wherein the first side S 21 and the second side S 22 are opposite to each other, and the first side S 21 of the second pin row 320 is adjacent to the second side S 12 of the first pin row 310 .
- the three consecutive signal vias H 1 , H 2 , and H 3 of the signal vias 380 are sequentially disposed at the first side S 11 of the first pin row 310 , the first side S 21 of the second pin row 320 , and the second side S 12 of the first pin row 310 .
- the signal vias 380 of each of the circuit boards 300 A to 300 D of FIG. 3A to FIG. 3D may include a differential signal pair via (e.g. signal vias H 5 and H 6 ).
- a differential signal pair trace (e.g. traces 370 A and 370 B) of each of the circuit boards 300 A to 300 D may be electrically connected to a differential signal pair pin (e.g. pins 312 A and 312 B in FIG. 3A ) of the first pin row 310 or a differential signal pair pin (e.g. pins 322 A and 322 B in FIG. 3C ) of the second pin row 320 through the differential signal pair via.
- the differential signal pair vias are disposed at the same side of the first pin row 310 or the same side of the second pin row 320 .
- the signal vias 380 of each of the circuit boards 300 A to 300 D of FIG. 3A to FIG. 3D may include at least two consecutive grounding vias (not shown).
- the at least two consecutive grounding vias are both disposed at the same side of the first pin row 310 or the same side of the second pin row 320 .
- each of the circuit boards 300 A to 300 D of FIG. 3A to FIG. 3D may further include a plurality of grounding vias (not shown).
- the grounding vias may be distributed around the signal vias 380 so as to increase signal quality of the signal vias 380 .
- FIG. 4 is a schematic diagram illustrating implementation of a circuit board according to still another embodiment of the invention.
- a circuit board 400 of FIG. 4 may similarly include the first pin row 310 , the second pin row 320 , and the signal vias 380 .
- the electrical connection relationship between the first pin row 310 and the second pin row 320 and the signal vias 380 can be referred to and inferred from related description of FIG. 3A , and thus is not repeated hereinafter.
- the four consecutive signal vias H 1 to H 4 of the signal vias 380 in FIG. 4 are sequentially disposed at the first side S 11 of the first pin row 310 , the first side S 21 of the second pin row 320 , the second side S 12 of the first pin row 310 , and the second side S 22 of the second pin row 320 .
- the five or more consecutive signal vias of the signal vias 380 may sequentially be disposed at the first side S 11 of the first pin row 310 , the first side S 21 of the second pin row 320 , the second side S 12 of the first pin row 310 , and the second side S 22 of the second pin row 320 in cycles by the designer for improving signal quality of the circuit board.
- Description of a circuit board with a number of pin rows greater than or equal to three is provided as follows.
- a circuit board may include N pin rows and a plurality of signal vias, wherein N is an integer greater than or equal to 3.
- Each of the N pin rows includes a first side and a second side. The first side and the second side of each of the N pin rows are opposite to each other.
- One of the first side and the second side of a Jth pin row of the N pin rows is adjacent to one of the first side and the second side of a J ⁇ 1th pin row of the N pin rows.
- a plurality of traces of the circuit board may be electrically connected to a plurality of pins of the N pin rows respectively through the signal vias.
- FIG. 5 is a schematic diagram illustrating implementation of a circuit board according to still another embodiment of the invention.
- a circuit board 500 may include a first pin row 510 , a second pin row 520 , a third pin row 530 , and a plurality of signal vias 580 .
- the first pin row 510 , the second pin row 520 , and the third pin row 530 may be, for example, three rows of pins of a surface-mount technology connector, which should however not be construed as limitations to the invention.
- the first pin row 510 has a plurality of pins 512 sequentially arranged
- the second pin row 520 has a plurality of pins 522 sequentially arranged
- the third pin row 530 has a plurality of pins 532 sequentially arranged.
- Each of the signal vias 580 is adjacent to a corresponding one pin of the pins 512 , 522 , and 532 .
- a plurality of traces 570 of the circuit board 500 may be electrically connected to the pins 512 of the first pin row 510 , the pins 522 of the second pin row 520 , and the pins 532 of the third pin row 530 respectively through the signal vias 580 .
- the signal via H 1 is adjacent to a pin F 1 of the first pin row 510 , and a first trace of the circuit board 500 may be electrically connected to the pin F 1 of the first pin row 510 through the signal via H 1 ;
- the signal via H 2 is adjacent to a pin F 2 of the second pin row 520 , and a second trace of the circuit board 500 may be electrically connected to the pin F 2 of the second pin row 520 through the signal via H 2 ;
- the signal via H 3 is adjacent to a pin F 3 of the third pin row 530 , and a third trace of the circuit board 500 may be electrically connected to the pin F 3 of the third pin row 530 through the signal via H 3 ;
- the signal via H 4 is adjacent to a pin F 4 of the first pin row 510 , and a fourth trace of the circuit board 500 may be electrically connected to the pin F 4 of the first pin row 510 through the signal via H 4 .
- the first pin row 510 includes a first side S 11 and a second side S 12 , wherein the first side S 11 and the second side S 12 are opposite to each other.
- the second pin row 520 includes a first side S 21 and a second side S 22 , wherein the first side S 21 and the second side S 22 are opposite to each other, and the second side S 22 of the second pin row 520 is adjacent to the first side S 11 of the first pin row 510 .
- the third pin row 530 has a first side S 31 and a second side S 32 , wherein the first side S 31 and the second side S 32 are opposite to each other, and the second side S 32 of the third pin row 530 is adjacent to the first side S 21 of the second pin row 520 .
- the four consecutive signal vias H 1 , H 2 , H 3 , and H 4 of the signal vias 580 are sequentially disposed at the first side S 11 of the first pin row 510 , the first side S 21 of the second pin row 520 , the first side S 31 of the third pin row 530 , and the second side S 12 of the first pin row 510 .
- Alternate arrangement of the signal vias H 1 , H 2 , H 3 , and H 4 as shown by the dashed arrows in FIG. 5 is thereby formed. In this way, the signal vias H 1 , H 2 , H 3 and H 4 are prevented from being located too close to each other, and crosstalk interference is thus prevented from being generated. Signal quality of the signal vias H 1 , H 2 , H 3 , and H 4 of the circuit board 500 is thereby increased.
- five or more consecutive signal vias of the signal vias 580 may be sequentially disposed at the first side S 11 of the first pin row 510 , the first side S 21 of the second pin row 520 , the first side S 31 of the third pin row 530 , the second side S 12 of the first pin row 510 , the second side S 22 of the second pin row 520 , and the second side S 32 of the third pin row 530 in cycles by the designer for improving signal quality of the circuit board 500 .
- details are not repeated hereinafter.
- the signal vias 580 of the circuit board 500 are disposed, enough teaching, suggestion, and implementation illustration may be obtained from the above embodiments of FIG. 1 to FIG. 4 , and that detailed descriptions are not further provided hereinafter.
- FIG. 6 is a schematic chart of a crosstalk interference value of at least one pin row of a circuit board.
- the horizontal axis represents numbering of pins in the at least one pin row
- the vertical axis represents a crosstalk interference value of each of the pins measured.
- the measured crosstalk interference value that the signal vias are disposed at a same side of the at least one pin row is labeled as 610 .
- the measured crosstalk interference value that the signal vias are disposed at different sides of the at least one pin row is labeled as 620 .
- FIG. 7 is a schematic chart of a signal-to-noise ratio of at least one pin row of a circuit board. In FIG.
- the horizontal axis represents numbering of pins in the at least one pin row
- the vertical axis represents the signal-to-noise ratio of each of the pins.
- the measured signal-to-noise ratio that the signal vias are disposed at a same side of the at least one pin row is labeled as 710 .
- the measure signal-to-noise ratio that the signal vias are disposed at two opposite sides of the at least one pin row is labeled as 720 .
- the signal vias of the at least one pin row of the circuit board are alternately disposed at two opposite sides of the at least one pin row. In this way, the signal vias are prevented from being located too close to each other, and therefore, signal quality of the circuit board is increased.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structure Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
Abstract
Description
- This application is a divisional application of and claims the priority benefit of U.S. application Ser. No. 16/601,342, filed on Oct. 14, 2019, now allowed. The prior U.S. application Ser. No. 16/601,342 is a divisional application of and claims the priority benefit of U.S. application Ser. No. 16/022,532, filed on Jun. 28, 2018, now abandoned, which claims the priority benefit of Taiwan application serial no. 106128590, filed on Aug. 23, 2017. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
- The invention relates to a circuit board. More particularly, the invention relates to a circuit board capable of improving signal quality.
- Generally, a plurality of signal vias are disposed on a printed circuit board to enable signal transmission among the elements of the printed circuit board through signal traces of each of the layers of the printed circuit board as well as the corresponding signal vias. In the current printed circuit board design, how the signal traces can be laid out more conveniently determines the positions in which the signal vias are disposed most of the time. In this way, however, distances between the signal vias may be too close to each other. When the signal vias are disposed too close to each other, greater crosstalk interference is generated, and signal quality of the circuit board is thus affected.
- The invention provides a circuit board in which a plurality of signal vias of at least one pin row of the circuit board are alternately disposed at different sides of the at least one pin row to prevent the signal vias from being disposed too close to each other for increasing signal quality of the at least one pin row.
- In an embodiment of the invention, a circuit board includes a first pin row, a second pin row, and a plurality of signal vias. The first pin row has a first side and a second side, wherein the first side of the first pin row and the second side of the first pin row are opposite to each other. The second pin row has a first side and a second side, wherein the first side of the second pin row and the second side of the second pin row are opposite to each other, and one of the first side and the second side of the second pin row is adjacent to one of the first side and the second side of the first pin row. A plurality of traces of the circuit board are electrically connected to a plurality of pins of the first pin row and a plurality of pins of the second pin row respectively through the signal vias. Three consecutive signal vias of the signal vias are sequentially disposed at the first side of the first pin row, the first side of the second pin row, and the second side of the first pin row.
- In an embodiment of the invention, the circuit board further includes a third pin row. The third pin row has a first side and a second side. The first side of the third pin row and the second side of the third pin row are opposite to each other, and one of the first side and the second side of the third pin row is adjacent to one of the first side and the second side of the second pin row. Four consecutive signal vias of the signal vias are sequentially disposed at the first side of the first pin row, the first side of the second pin row, the first side of the third pin row, and the second side of the first pin row.
- In an embodiment of the invention, a circuit board includes N pin rows and a plurality of signal vias. Each of the N pin rows has a first side and a second side. The first side and the second side of each of the N pin rows are opposite to each other. One of the first side and the second side of a Jth pin row of the N pin rows is adjacent to one of the first side and the second side of a J−1th pin row of the N pin rows, wherein N is an integer greater than or equal to 3. A plurality of traces of the circuit board are electrically connected to a plurality of pins of the N pin row respectively through the signal vias. M consecutive signal vias of the signal vias are sequentially disposed at the first side of each of the N pin rows and the second side of a first pin row of the N pin rows, wherein M=N+1.
- To sum up, in the circuit board provided by the embodiments of the invention, the signal vias of the at least one pin row of the circuit board are alternately disposed at two opposite sides of the at least one pin row. In this way, the signal vias are prevented from being located too close to each other, and therefore, signal quality of the at least one pin row of the circuit board is increased.
- To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
- The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
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FIG. 1 is a schematic diagram illustrating implementation of a circuit board according to an embodiment of the invention. -
FIG. 2 is a schematic diagram illustrating implementation of a circuit board according to another embodiment of the invention. -
FIG. 3A toFIG. 3D are schematic diagrams illustrating implementation of circuit boards according to still another embodiment of the invention. -
FIG. 4 is a schematic diagram illustrating implementation of a circuit board according to still another embodiment of the invention. -
FIG. 5 is a schematic diagram illustrating implementation of a circuit board according to still another embodiment of the invention. -
FIG. 6 is a schematic chart of a crosstalk interference value of at least one pin row of a circuit board. -
FIG. 7 is a schematic chart of a signal-to-noise ratio of at least one pin row of a circuit board. - In order to make the invention more comprehensible, several embodiments are described below as examples of implementation of the invention. In addition, wherever possible, identical or similar reference numerals stand for identical or similar elements/components in the drawings and the embodiments.
- With reference to
FIG. 1 ,FIG. 1 is a schematic diagram illustrating implementation of a circuit board according to an embodiment of the invention. Acircuit board 100 includes afirst pin row 110 and a plurality ofsignal vias 180. In an embodiment of the invention, thefirst pin row 110 may be, for example, a single row of pins of a surface-mount technology (SMT) connector, which should however not be construed as limitations to the invention. Thefirst pin row 110 has a plurality ofpins 112 sequentially arranged, and each of thesignal vias 180 is adjacent to a corresponding one of thepins 112. A plurality oftraces 170 of thecircuit board 100 may be electrically connected to thepins 112 of thefirst pin row 110 respectively through thesignal vias 180. For instance, a signal via H1 is adjacent to a pin A1 of thefirst pin row 110, and a first trace of thecircuit board 100 may be electrically connected to the pin A1 through the signal via H1; a signal via H2 is adjacent to a pin A2 of thefirst pin row 110, and a second trace of thecircuit board 100 may be electrically connected to the pin A2 through the signal via H2; a signal via H3 is adjacent to a pin A3 of thefirst pin row 110, and a third trace of thecircuit board 100 may be electrically connected to the pin A3 through the signal via H3. Nevertheless, the invention should not be construed as limited thereto. In fact, whether the signal via corresponding to each of the pins of thefirst pin row 110 is required to be disposed depends on actual applications or design requirements. - In addition, the
first pin row 110 includes a first side S11 and a second side S12, wherein the first side S11 and the second side S12 are opposite to each other. Particularly, the three consecutive signal vias H1, H2, and H3 of thesignal vias 180 are sequentially disposed at the first side S11 of thefirst pin row 110, the second side S12 of thefirst pin row 110, and the first side S11 of thefirst pin row 110. Alternate arrangement of the signal vias H1, H2, and H3 as shown by the dashed arrows inFIG. 1 is thereby formed. In this way, the signal vias H1, H2, and H3 are prevented from being disposed together at the same side (e.g., the first side S11) of thefirst pin row 110. As such, the signal vias H1, H2, and H3 are prevented from being located too close to each other, and that crosstalk interference is prevented from being generated. Signal quality of the signal vias H1, H2, and H3 of thecircuit board 100 is thereby increased. - In an embodiment of the invention, the signal vias 180 of
FIG. 1 may include a differential signal pair via (e.g. signal vias H5 and H6), wherein a differential signal pair trace (e.g. traces 170A and 170B) of thecircuit board 100 may be electrically connected to a differential signal pair pin (e.g. pins 112A and 112B) of thefirst pin row 110 through the differential signal pair via. The differential signal pair via is disposed at a same side of thefirst pin row 110. - In an embodiment of the invention, the signal vias 180 of
FIG. 1 may include at least two consecutive grounding vias (not shown), wherein the at least two consecutive grounding vias are both disposed at a same side of thefirst pin row 110. - In an embodiment of the invention, the
circuit board 100 ofFIG. 1 may further include a plurality ofgrounding vias 190, wherein the grounding vias 190 may be distributed around the signal vias 180 for increasing signal quality of thesignal vias 180. -
FIG. 2 is a schematic diagram illustrating implementation of a circuit board according to another embodiment of the invention. With reference toFIG. 1 andFIG. 2 together, acircuit board 200 ofFIG. 2 may also include thefirst pin row 110 and thesignal vias 180, wherein thefirst pin row 110 has thepins 112 sequentially arranged. The plurality oftraces 170 of thecircuit board 200 may be electrically connected to thepins 112 of thefirst pin row 110 respectively through thesignal vias 180. Similarly, whether the signal via corresponding to each of the pins of thepins 112 inFIG. 2 is required to be disposed depends on actual applications or design requirements. - Comparing to the three consecutive signal vias H1, H2, and H3 in
FIG. 1 which are electrically connected to the pins A1, A2, and A3 respectively and are sequentially disposed at the first side S11 of thefirst pin row 110, the second side S12 of thefirst pin row 110, and the first side S11 of thefirst pin row 110, the four consecutive signal vias H1 to H4 of the signal vias 180 inFIG. 2 are electrically connected to the pins A1 to A4 respectively and are sequentially disposed at the first side S11 of thefirst pin row 110, the second side S12 of thefirst pin row 110, the first side S11 of thefirst pin row 110, and the second side S12 of thefirst pin row 110. Alternate arrangement of the signal vias H1 to H4 as shown by the dashed arrows inFIG. 2 is thereby formed. In this way, the signal vias H1 to H4 inFIG. 2 are prevented from being disposed together at the same side of thefirst pin row 110. As such, the signal vias H1 to H4 are prevented from being located too close to each other, and that crosstalk interference is prevented from being generated. Signal quality of the signal vias H1 to H4 of thecircuit board 200 is thereby increased. In addition, other implementation details of thecircuit board 200 ofFIG. 2 may be referred to the related description of thecircuit board 100 ofFIG. 1 , and a relevant description thereof is thus omitted. - It should be understood that five (or more) consecutive signal vias of the
signal vias 180 may similarly be disposed sequentially at the first side S11 of thefirst pin row 110 and the second side S12 of thefirst pin row 110 in cycles by a designer. That is, the five or more signal vias of thesignal vias 180 may be sequentially disposed at different sides of thefirst pin row 110 for improving signal quality of the circuit board. Thus, details are not repeated hereinafter. -
FIG. 3A is a schematic diagram illustrating implementation of a circuit board according to still another embodiment of the invention. As shown inFIG. 3A , acircuit board 300A may include afirst pin row 310, asecond pin row 320, and a plurality ofsignal vias 380. In an embodiment of the invention, thefirst pin row 310 and thesecond pin row 320 may be, for example, double rows of pins of a surface-mount technology connector, which should however not be construed as limitations to the invention. Thefirst pin row 310 has a plurality ofpins 312 sequentially arranged, and thesecond pin row 320 has a plurality ofpins 322 sequentially arranged. Moreover, each of thesignal vias 380 is adjacent to a corresponding one pin of thepins traces 370 of thecircuit board 300A may be electrically connected to thepins 312 of thefirst pin row 310 and thepins 322 of thesecond pin row 320 respectively through thesignal vias 380. For instance, the signal via H1 is adjacent to a pin B1 of thefirst pin row 310, and a first trace of thecircuit board 300A may be electrically connected to the pin B1 of thefirst pin row 310 through the signal via H1; the signal via H2 is adjacent to a pin B2 of thesecond pin row 320, and a second trace of thecircuit board 300A may be electrically connected to the pin B2 of thesecond pin row 320 through the signal via H2; the signal via H3 is adjacent to a pin B3 of thefirst pin row 310, and a third trace of thecircuit board 300A may be electrically connected to the pin B3 of thefirst pin row 310 through the signal via H3. Nevertheless, the invention should not be construed as limited thereto. In fact, whether the signal via corresponding to each of the pins in thefirst pin row 310 and thesecond pin row 320 is required to be disposed depends on actual applications or design requirements. - The
first pin row 310 includes a first side S11 and a second side S12, wherein the first side S11 and the second side S12 are opposite to each other. Thesecond pin row 320 has a first side S21 and a second side S22, wherein the first side S21 and the second side S22 are opposite to each other, and the second side S22 of thesecond pin row 320 is adjacent to the first side S11 of thefirst pin row 310. The three consecutive signal vias H1, H2, and H3 of thesignal vias 380 are sequentially disposed at the first side S11 of thefirst pin row 310, the first side S21 of thesecond pin row 320, and the second side S12 of thefirst pin row 310. Alternate arrangement of the signal vias H1, H2, and H3 as shown by the dashed arrows inFIG. 3A is thereby formed. In this way, the signal vias H1, H2, and H3 are prevented from being located too close to each other, and that crosstalk interference is prevented from being generated. Signal quality of the signal vias H1, H2, and H3 of thecircuit board 300A is thereby increased. -
FIG. 3B is a schematic diagram illustrating implementation of a circuit board according to still another embodiment of the invention. As shown inFIG. 3B , acircuit board 300B may include afirst pin row 310, asecond pin row 320, and a plurality ofsignal vias 380. Thefirst pin row 310 has a plurality ofpins 312 sequentially arranged, and thesecond pin row 320 has a plurality ofpins 322 sequentially arranged. Moreover, each of thesignal vias 380 is adjacent to a corresponding one pin of thepins traces 370 of thecircuit board 300B may be electrically connected to thepins 312 of thefirst pin row 310 and thepins 322 of thesecond pin row 320 respectively through thesignal vias 380. For instance, the signal via H1 is adjacent to a pin C1 of thefirst pin row 310, and a first trace of thecircuit board 300B may be electrically connected to the pin C1 of thefirst pin row 310 through the signal via H1; the signal via H2 is adjacent to a pin C2 of thesecond pin row 320, and a second trace of thecircuit board 300B may be electrically connected to the pin C2 of thesecond pin row 320 through the signal via H2; the signal via H3 is adjacent to a pin C3 of thefirst pin row 310, and a third trace of thecircuit board 300B may be electrically connected to the pin C3 of thefirst pin row 310 through the signal via H3. Nevertheless, the invention should not be construed as limited thereto. In fact, whether the signal via corresponding to each of the pins of thefirst pin row 310 and thesecond pin row 320 is required to be disposed depends on actual applications or design requirements. - The
first pin row 310 includes a first side S11 and a second side S12, wherein the first side S11 and the second side S12 are opposite to each other. Thesecond pin row 320 includes a first side S21 and a second side S22, wherein the first side S21 and the second side S22 are opposite to each other, and the second side S22 of thesecond pin row 320 is adjacent to the first side S11 of thefirst pin row 310. The three consecutive signal vias H1, H2, and H3 of thesignal vias 380 are sequentially disposed at the first side S11 of thefirst pin row 310, the first side S21 of thesecond pin row 320, and the second side S12 of thefirst pin row 310. Alternate arrangement of the signal vias H1, H2, and H3 as shown by the dashed arrows inFIG. 3B is thereby formed. In this way, the signal vias H1, H2, and H3 are prevented from being located too close to each other, and that crosstalk interference is prevented from being generated. Signal quality of the signal vias H1, H2, and H3 of thecircuit board 300B is thereby increased. -
FIG. 3C is a schematic diagram illustrating implementation of a circuit board according to still another embodiment of the invention. As shown inFIG. 3C , acircuit board 300C may include afirst pin row 310, asecond pin row 320, and a plurality ofsignal vias 380. Thefirst pin row 310 has a plurality ofpins 312 sequentially arranged, and thesecond pin row 320 has a plurality ofpins 322 sequentially arranged. Moreover, each of thesignal vias 380 is adjacent to a corresponding one pin of thepins traces 370 of thecircuit board 300C may be electrically connected to thepins 312 of thefirst pin row 310 and thepins 322 of thesecond pin row 320 respectively through thesignal vias 380. For instance, the signal via H1 is adjacent to a pin D1 of thefirst pin row 310, and a first trace of thecircuit board 300C may be electrically connected to the pin D1 of thefirst pin row 310 through the signal via H1; the signal via H2 is adjacent to a pin D2 of thesecond pin row 320, and a second trace of thecircuit board 300C may be electrically connected to the pin D2 of thesecond pin row 320 through the signal via H2; the signal via H3 is adjacent to a pin D3 of thefirst pin row 310, and a third trace of thecircuit board 300C may be electrically connected to the pin D3 of thefirst pin row 310 through the signal via H3. Nevertheless, the invention should not be construed as limited thereto. In fact, whether the signal via corresponding to each of the pins of thefirst pin row 310 and thesecond pin row 320 is required to be disposed depends on actual applications or design requirements. - The
first pin row 310 includes a first side S11 and a second side S12, wherein the first side S11 and the second side S12 are opposite to each other. Thesecond pin row 320 includes a first side S21 and a second side S22, wherein the first side S21 and the second side S22 are opposite to each other, and the first side S21 of thesecond pin row 320 is adjacent to the second side S12 of thefirst pin row 310. The three consecutive signal vias H1, H2, and H3 of thesignal vias 380 are sequentially disposed at the first side S11 of thefirst pin row 310, the first side S21 of thesecond pin row 320, and the second side S12 of thefirst pin row 310. Alternate arrangement of the signal vias H1, H2, and H3 as shown by the dashed arrows inFIG. 3C is thereby formed. In this way, the signal vias H1, H2, and H3 are prevented from being located too close to each other, and that crosstalk interference is prevented from being generated. Signal quality of the signal vias H1, H2, and H3 of thecircuit board 300C is thereby increased. -
FIG. 3D is a schematic diagram illustrating implementation of a circuit board according to still another embodiment of the invention. As shown inFIG. 3D , acircuit board 300D may include afirst pin row 310, asecond pin row 320, and a plurality ofsignal vias 380. Thefirst pin row 310 has a plurality ofpins 312 sequentially arranged, and thesecond pin row 320 has a plurality ofpins 322 sequentially arranged. Moreover, each of thesignal vias 380 is adjacent to a corresponding one pin of thepins traces 370 of thecircuit board 300D may be electrically connected to thepins 312 of thefirst pin row 310 and thepins 322 of thesecond pin row 320 respectively through thesignal vias 380. For instance, a signal via H1 is adjacent to a pin E1 of thefirst pin row 310, and a first trace of thecircuit board 300D may be electrically connected to the pin E1 of thefirst pin row 310 through the signal via H1; a signal via H2 is adjacent to a pin E2 of thesecond pin row 320, and a second trace of thecircuit board 300D may be electrically connected to the pin E2 of thesecond pin row 320 through the signal via H2; a signal via H3 is adjacent to a pin E3 of thefirst pin row 310, and a third trace of thecircuit board 300D may be electrically connected to the pin E3 of thefirst pin row 310 through the signal via H3. Nevertheless, the invention should not be construed as limited thereto. In fact, whether the signal via corresponding to each of the pins in thefirst pin row 310 and thesecond pin row 320 is required to be disposed depends on actual applications or design requirements. - The
first pin row 310 includes a first side S11 and a second side S12, wherein the first side S11 and the second side S12 are opposite to each other. Thesecond pin row 320 includes a first side S21 and a second side S22, wherein the first side S21 and the second side S22 are opposite to each other, and the first side S21 of thesecond pin row 320 is adjacent to the second side S12 of thefirst pin row 310. The three consecutive signal vias H1, H2, and H3 of thesignal vias 380 are sequentially disposed at the first side S11 of thefirst pin row 310, the first side S21 of thesecond pin row 320, and the second side S12 of thefirst pin row 310. Alternate arrangement of the signal vias H1, H2, and H3 as shown by the dashed arrows inFIG. 3D is thereby formed. In this way, the signal vias H1, H2, and H3 are prevented from being located too close to each other, and that crosstalk interference is prevented from being generated. Signal quality of the signal vias H1, H2, and H3 of thecircuit board 300D is thereby increased. - In an embodiment of the invention, the signal vias 380 of each of the
circuit boards 300A to 300D ofFIG. 3A toFIG. 3D may include a differential signal pair via (e.g. signal vias H5 and H6). A differential signal pair trace (e.g. traces 370A and 370B) of each of thecircuit boards 300A to 300D may be electrically connected to a differential signal pair pin (e.g. pins 312A and 312B inFIG. 3A ) of thefirst pin row 310 or a differential signal pair pin (e.g. pins 322A and 322B inFIG. 3C ) of thesecond pin row 320 through the differential signal pair via. Moreover, the differential signal pair vias are disposed at the same side of thefirst pin row 310 or the same side of thesecond pin row 320. - In an embodiment of the invention, the signal vias 380 of each of the
circuit boards 300A to 300D ofFIG. 3A toFIG. 3D may include at least two consecutive grounding vias (not shown). The at least two consecutive grounding vias are both disposed at the same side of thefirst pin row 310 or the same side of thesecond pin row 320. - In an embodiment of the invention, each of the
circuit boards 300A to 300D ofFIG. 3A toFIG. 3D may further include a plurality of grounding vias (not shown). The grounding vias may be distributed around the signal vias 380 so as to increase signal quality of thesignal vias 380. -
FIG. 4 is a schematic diagram illustrating implementation of a circuit board according to still another embodiment of the invention. With reference toFIG. 3A andFIG. 4 together, acircuit board 400 ofFIG. 4 may similarly include thefirst pin row 310, thesecond pin row 320, and thesignal vias 380. InFIG. 4 , the electrical connection relationship between thefirst pin row 310 and thesecond pin row 320 and the signal vias 380 can be referred to and inferred from related description ofFIG. 3A , and thus is not repeated hereinafter. - Comparing to the three consecutive signal vias H1, H2, and H3 in
FIG. 3A which are sequentially disposed at the first side S11 of thefirst pin row 310, the first side S21 of thesecond pin row 320, and the second side S12 of thefirst pin row 310, the four consecutive signal vias H1 to H4 of the signal vias 380 inFIG. 4 are sequentially disposed at the first side S11 of thefirst pin row 310, the first side S21 of thesecond pin row 320, the second side S12 of thefirst pin row 310, and the second side S22 of thesecond pin row 320. Alternate arrangement of the signal vias H1 to H4 as shown by the dashed arrows inFIG. 4 is thereby formed. In this way, the signal vias H1 to H4 ofFIG. 4 are prevented from being located too close to each other, and that crosstalk interference is prevented from being generated. Signal quality of the signal vias H1 to H4 of thecircuit board 400 is thereby increased. In addition, other implementation details of thecircuit board 400 ofFIG. 4 may be referred to related description of thecircuit board 300A ofFIG. 3A , and a relevant description thereof is thus omitted. - It should be understood that similarly, the five or more consecutive signal vias of the
signal vias 380 may sequentially be disposed at the first side S11 of thefirst pin row 310, the first side S21 of thesecond pin row 320, the second side S12 of thefirst pin row 310, and the second side S22 of thesecond pin row 320 in cycles by the designer for improving signal quality of the circuit board. Thus, details are not repeated hereinafter. Description of a circuit board with a number of pin rows greater than or equal to three is provided as follows. - In an embodiment of the invention, a circuit board may include N pin rows and a plurality of signal vias, wherein N is an integer greater than or equal to 3. Each of the N pin rows includes a first side and a second side. The first side and the second side of each of the N pin rows are opposite to each other. One of the first side and the second side of a Jth pin row of the N pin rows is adjacent to one of the first side and the second side of a J−1th pin row of the N pin rows. A plurality of traces of the circuit board may be electrically connected to a plurality of pins of the N pin rows respectively through the signal vias. Particularly, M consecutive signal vias of the signal vias are sequentially disposed at the first side of each of the N pin rows and the second side of a first pin row of the N pin rows, wherein M=N+1. N=3 is used as an example for description in the following. Description of other embodiments in which N equals to other numerical values may be deduced by analogy according to the description as follows.
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FIG. 5 is a schematic diagram illustrating implementation of a circuit board according to still another embodiment of the invention. As shown inFIG. 5 , acircuit board 500 may include afirst pin row 510, asecond pin row 520, athird pin row 530, and a plurality ofsignal vias 580. In an embodiment of the invention, thefirst pin row 510, thesecond pin row 520, and thethird pin row 530 may be, for example, three rows of pins of a surface-mount technology connector, which should however not be construed as limitations to the invention. Thefirst pin row 510 has a plurality ofpins 512 sequentially arranged, thesecond pin row 520 has a plurality ofpins 522 sequentially arranged, and thethird pin row 530 has a plurality ofpins 532 sequentially arranged. Each of thesignal vias 580 is adjacent to a corresponding one pin of thepins traces 570 of thecircuit board 500 may be electrically connected to thepins 512 of thefirst pin row 510, thepins 522 of thesecond pin row 520, and thepins 532 of thethird pin row 530 respectively through thesignal vias 580. For instance, the signal via H1 is adjacent to a pin F1 of thefirst pin row 510, and a first trace of thecircuit board 500 may be electrically connected to the pin F1 of thefirst pin row 510 through the signal via H1; the signal via H2 is adjacent to a pin F2 of thesecond pin row 520, and a second trace of thecircuit board 500 may be electrically connected to the pin F2 of thesecond pin row 520 through the signal via H2; the signal via H3 is adjacent to a pin F3 of thethird pin row 530, and a third trace of thecircuit board 500 may be electrically connected to the pin F3 of thethird pin row 530 through the signal via H3; the signal via H4 is adjacent to a pin F4 of thefirst pin row 510, and a fourth trace of thecircuit board 500 may be electrically connected to the pin F4 of thefirst pin row 510 through the signal via H4. Nevertheless, the invention should not be construed as limited thereto. In fact, whether the signal via corresponding to each of the pins in thefirst pin row 510, thesecond pin row 520, and thethird pin row 530 is required to be disposed depends on actual applications or design requirements. - The
first pin row 510 includes a first side S11 and a second side S12, wherein the first side S11 and the second side S12 are opposite to each other. Thesecond pin row 520 includes a first side S21 and a second side S22, wherein the first side S21 and the second side S22 are opposite to each other, and the second side S22 of thesecond pin row 520 is adjacent to the first side S11 of thefirst pin row 510. Thethird pin row 530 has a first side S31 and a second side S32, wherein the first side S31 and the second side S32 are opposite to each other, and the second side S32 of thethird pin row 530 is adjacent to the first side S21 of thesecond pin row 520. The four consecutive signal vias H1, H2, H3, and H4 of thesignal vias 580 are sequentially disposed at the first side S11 of thefirst pin row 510, the first side S21 of thesecond pin row 520, the first side S31 of thethird pin row 530, and the second side S12 of thefirst pin row 510. Alternate arrangement of the signal vias H1, H2, H3, and H4 as shown by the dashed arrows inFIG. 5 is thereby formed. In this way, the signal vias H1, H2, H3 and H4 are prevented from being located too close to each other, and crosstalk interference is thus prevented from being generated. Signal quality of the signal vias H1, H2, H3, and H4 of thecircuit board 500 is thereby increased. - It should be understood that similarly, five or more consecutive signal vias of the
signal vias 580 may be sequentially disposed at the first side S11 of thefirst pin row 510, the first side S21 of thesecond pin row 520, the first side S31 of thethird pin row 530, the second side S12 of thefirst pin row 510, the second side S22 of thesecond pin row 520, and the second side S32 of thethird pin row 530 in cycles by the designer for improving signal quality of thecircuit board 500. Thus, details are not repeated hereinafter. In addition, for variations in implementation details of thecircuit board 500 ofFIG. 5 and positions in which the signal vias 580 of thecircuit board 500 are disposed, enough teaching, suggestion, and implementation illustration may be obtained from the above embodiments ofFIG. 1 toFIG. 4 , and that detailed descriptions are not further provided hereinafter. -
FIG. 6 is a schematic chart of a crosstalk interference value of at least one pin row of a circuit board. InFIG. 6 , the horizontal axis represents numbering of pins in the at least one pin row, and the vertical axis represents a crosstalk interference value of each of the pins measured. The measured crosstalk interference value that the signal vias are disposed at a same side of the at least one pin row is labeled as 610. The measured crosstalk interference value that the signal vias are disposed at different sides of the at least one pin row is labeled as 620. In addition,FIG. 7 is a schematic chart of a signal-to-noise ratio of at least one pin row of a circuit board. InFIG. 7 , the horizontal axis represents numbering of pins in the at least one pin row, and the vertical axis represents the signal-to-noise ratio of each of the pins. The measured signal-to-noise ratio that the signal vias are disposed at a same side of the at least one pin row is labeled as 710. The measure signal-to-noise ratio that the signal vias are disposed at two opposite sides of the at least one pin row is labeled as 720. It thus can be seen that inFIG. 6 andFIG. 7 , in the circuit board provided by the embodiments of the invention, a lower crosstalk interference value and a higher signal-to-noise ratio can be provided when the signal vias of the pins are alternately disposed at different sides of the at least one pin row. - In view of the foregoing, in the circuit board provided by the embodiments of the invention, the signal vias of the at least one pin row of the circuit board are alternately disposed at two opposite sides of the at least one pin row. In this way, the signal vias are prevented from being located too close to each other, and therefore, signal quality of the circuit board is increased.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.
Claims (3)
Priority Applications (1)
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US17/125,475 US20210105893A1 (en) | 2017-08-23 | 2020-12-17 | Circuit board |
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TW106128590A TWI656812B (en) | 2017-08-23 | 2017-08-23 | Circuit board |
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US16/022,532 US20190069393A1 (en) | 2017-08-23 | 2018-06-28 | Circuit board |
US16/601,342 US10912189B2 (en) | 2017-08-23 | 2019-10-14 | Circuit board |
US17/125,475 US20210105893A1 (en) | 2017-08-23 | 2020-12-17 | Circuit board |
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US16/601,342 Division US10912189B2 (en) | 2017-08-23 | 2019-10-14 | Circuit board |
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Family
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Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/022,532 Abandoned US20190069393A1 (en) | 2017-08-23 | 2018-06-28 | Circuit board |
US16/601,342 Active US10912189B2 (en) | 2017-08-23 | 2019-10-14 | Circuit board |
US17/125,475 Abandoned US20210105893A1 (en) | 2017-08-23 | 2020-12-17 | Circuit board |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/022,532 Abandoned US20190069393A1 (en) | 2017-08-23 | 2018-06-28 | Circuit board |
US16/601,342 Active US10912189B2 (en) | 2017-08-23 | 2019-10-14 | Circuit board |
Country Status (2)
Country | Link |
---|---|
US (3) | US20190069393A1 (en) |
TW (1) | TWI656812B (en) |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6627999B2 (en) * | 2000-08-31 | 2003-09-30 | Micron Technology, Inc. | Flip-chip with matched signal lines, ground plane and ground bumps adjacent signal bumps |
US6462423B1 (en) * | 2000-08-31 | 2002-10-08 | Micron Technology, Inc. | Flip-chip with matched lines and ground plane |
DE10139985B4 (en) * | 2001-08-22 | 2005-10-27 | Infineon Technologies Ag | Electronic component with a semiconductor chip and method for its production |
SG111069A1 (en) * | 2002-06-18 | 2005-05-30 | Micron Technology Inc | Semiconductor devices including peripherally located bond pads, assemblies, packages, and methods |
TWI358243B (en) * | 2008-08-27 | 2012-02-11 | Advanced Semiconductor Eng | Circuit substrate having power/ground plane with g |
-
2017
- 2017-08-23 TW TW106128590A patent/TWI656812B/en active
-
2018
- 2018-06-28 US US16/022,532 patent/US20190069393A1/en not_active Abandoned
-
2019
- 2019-10-14 US US16/601,342 patent/US10912189B2/en active Active
-
2020
- 2020-12-17 US US17/125,475 patent/US20210105893A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20190069393A1 (en) | 2019-02-28 |
TWI656812B (en) | 2019-04-11 |
US20200045809A1 (en) | 2020-02-06 |
US10912189B2 (en) | 2021-02-02 |
TW201914376A (en) | 2019-04-01 |
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