US20210098462A1 - Semiconductor device with nanowire contact and method for fabricating the same - Google Patents
Semiconductor device with nanowire contact and method for fabricating the same Download PDFInfo
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- US20210098462A1 US20210098462A1 US16/585,460 US201916585460A US2021098462A1 US 20210098462 A1 US20210098462 A1 US 20210098462A1 US 201916585460 A US201916585460 A US 201916585460A US 2021098462 A1 US2021098462 A1 US 2021098462A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
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- H01L27/10855—
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- H01L27/10814—
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- H01L27/10823—
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- H01L27/10885—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Definitions
- the present disclosure relates to a semiconductor device and a method for fabricating the semiconductor device, and more particularly, to a semiconductor device with coverage layer and a method for fabricating the semiconductor device with coverage layer.
- Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment.
- the dimensions of semiconductor devices are continuously being scaled down to meet the increasing demand of computing ability.
- a variety of issues arise during the scaling-down process and impact the final electrical characteristics, quality, and yield. Therefore, challenges remain in achieving improved performance, quality, yield, and reliability.
- One aspect of the present disclosure provides a semiconductor device having a substrate including a plurality of doped regions; a plurality of silicide pads disposed respectively over the plurality of doped regions; and a plurality of conductive contacts disposed respectively over the plurality of silicide pads; wherein the plurality of conductive contacts comprise a plurality of nanowires, a conductive liner disposed over the plurality of nanowires, and a conductor disposed over the conductive liner.
- the semiconductor device further comprises a bit line disposed over one of the plurality of conductive contacts, and bit line is an undulating strip.
- the semiconductor device further comprises a plurality of capacitor contacts disposed over the substrate, at least one of the plurality of capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion.
- the upper width of the head portion is larger than a bottom width of the head portion, and the head portion has a curved sidewall.
- the upper width of the neck portion is substantially the same as a bottom width of the head portion, and the head portion has tapered profile.
- the semiconductor device further comprises a capacitor structure disposed over one of the plurality of conductive contacts.
- the semiconductor device further comprises a plurality of landing pads disposed respectively over the plurality of head portions, at least one of the plurality of landing pads comprising a protruding portion of the capacitor plug and a first spacer over the protruding portion, wherein a width of the first spacer is larger than a width of the capacitor plug.
- the first spacer comprises metal silicide and is disposed on a sidewall of the protruding portion.
- the first spacer comprises polysilicon and is disposed on a sidewall of the protruding portion.
- the semiconductor device further comprises a second spacer disposed over the first spacer, and the second spacer comprises metal silicide.
- Another aspect of the present disclosure provides a method for fabricating a semiconductor device comprising: providing a substrate including a plurality of doped regions; forming a plurality of silicide pads respectively over the plurality of doped regions; and forming a plurality of conductive contacts respectively over the plurality of silicide pads; wherein the plurality of conductive contacts comprise a plurality of nanowires, a conductive liner over the plurality of nanowires, and a conductor over the conductive liner.
- the method for fabricating a semiconductor device further comprises: forming a plurality of capacitor contacts over the substrate, at least one of the plurality of capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion.
- forming a plurality of capacitor contacts comprises: forming a contact hole in a dielectric stack having a first layer and a second layer over the first layer; removing a portion of the second layer around the contact hole to form a transformed hole having a narrow portion in the first layer and a wide portion in the second layer; and filling a conductive material into the transformed hole.
- the contact hole is formed integrally with a bit line trench in the second layer.
- the method for fabricating a semiconductor device further comprises: filling the bit line trench and a lower portion of the contact hole with a filling material.
- removing a portion of the second layer around the contact hole is performed after filling the lower portion of the contact hole with a sacrificial material.
- the method for fabricating a semiconductor device further comprises: forming a plurality of landing pads respectively over the plurality of head portions, at least one of the plurality of landing pads comprising a protruding portion of the capacitor plug and a first spacer over the protruding portion, wherein a width of the first spacer is larger than a width of the capacitor plug.
- the first spacer comprises metal silicide and is formed on a sidewall of the protruding portion.
- the first spacer comprises polysilicon and is on a sidewall of the protruding portion.
- the method for fabricating a semiconductor device further comprises: forming a plurality of second spacers respectively over the plurality of first spacers, wherein the second spacer comprises metal silicide.
- the high aspect ratio conductive contact is implemented by the nanowires to electrically connect the source/drain regions in the substrate and the capacitor structures over the source/drain regions.
- the high aspect ratio conductive contact is implemented by the nanowires to electrically connect the source/drain regions in the substrate and the bit line.
- the landing pad has the first spacer, wherein a width of the first spacer is larger than a width of the capacitor plug, the misalignment between the subsequently formed capacitor structure and the landing pad can be dramatically solved, wherein a width of the first spacer is larger than a width of the capacitor plug.
- the coverage layer may reduce formation of defects in the semiconductor device; therefore, the yield of the semiconductor device increases correspondingly.
- FIG. 1 illustrates, in a flowchart diagram form, a method for fabricating a semiconductor device in accordance with one embodiment of the present disclosure.
- FIGS. 2 and 3 illustrate, in schematic cross-sectional diagrams, part of a flow of fabricating a semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 4 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 3 .
- FIGS. 5 to 7 illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 8 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 7 .
- FIG. 9 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 10 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 11 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 10 .
- FIG. 12 to 17 illustrate, in a close-up schematic cross-sectional diagram, part of the flow of fabricating the conductive contacts in accordance with one embodiment of the present disclosure.
- FIG. 18 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 19 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 18 .
- FIG. 20 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 21 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 20 .
- FIG. 22 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 23 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 22 .
- FIG. 24 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 25 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 24 .
- FIG. 26 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 27 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 26 .
- FIGS. 28 to 33 illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIGS. 34 to 36 illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 37 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 36 .
- FIGS. 38 to 41 illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIGS. 42 to 43 illustrate, in schematic cross-sectional view diagrams, some semiconductor devices in accordance with some embodiments of the present disclosure.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes.
- the term “substantially” may be used herein to reflect this meaning.
- items described as “substantially the same,” “substantially equal,” or “substantially planar,” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.
- a semiconductor device generally means a device which can function by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of the semiconductor device.
- above corresponds to the direction of the arrow of the direction Z
- below corresponds to the opposite direction of the arrow of the direction Z.
- FIG. 1 illustrates, in a flowchart diagram form, a method 10 for fabricating a semiconductor device in accordance with one embodiment of the present disclosure.
- FIGS. 2 and 3 illustrate, in schematic cross-sectional diagrams, part of a flow of fabricating a semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 4 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 3 .
- a substrate 101 may be provided.
- the substrate 101 may be formed of, for example, silicon, doped silicon, silicon germanium, silicon on insulator, silicon on sapphire, silicon germanium on isulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, gallium arsenide phosphide, indium phosphide, or indium gallium phosphide.
- a plurality of isolation structures 103 may be formed in the substrate 101 .
- the plurality of isolation structures 103 are separated from each other in a cross-sectional view and define a plurality of active regions 105 .
- the plurality of isolation structures 103 may be formed of, for example, an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluoride-doped silicate, or the like.
- the plurality of active regions 105 may extend in a direction slanted with respect to a direction X in a top-view diagram.
- silicon oxynitride refers to a substance which contains silicon, nitrogen, and oxygen and in which a proportion of oxygen is greater than that of nitrogen.
- Silicon nitride oxide refers to a substance which contains silicon, oxygen, and nitrogen and in which a proportion of nitrogen is greater than that of oxygen.
- FIGS. 5 to 7 illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 8 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 7 .
- a plurality of word lines 103 may be formed in the substrate 101 .
- the plurality of word lines 103 may extend along the direction X.
- Each one of the plurality of word lines 201 includes a bottom layer 203 , a middle layer 205 , a top layer 207 , and a trench opening 209 .
- a photolithography process may be used to pattern the substrate 101 to define positions of a plurality of trench openings 209 .
- An etch process such as an anisotropic dry etch process, may be performed to form the plurality of trench openings 209 in the substrate 101 .
- the plurality of bottom layers 203 may be correspondingly formed and attached to sidewalls of the plurality of trench openings 209 and bottoms of the plurality of trench openings 209 .
- the plurality of bottom layers 203 may be formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like.
- the plurality of middle layers 205 may be correspondingly formed on the plurality of bottom layers 203 . Top surfaces of the plurality of middle layers 205 may be lower than a top surface of the substrate 101 .
- the plurality of middle layers 205 may be formed of, for example, doped polysilicon, metal material, or metal silicide. Metal silicide may be, for example, nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like.
- the plurality of top layers 207 may be correspondingly formed on the plurality of middle layers 205 .
- Top surfaces of the plurality of top layers 207 may be at the same vertical level as the top surface of the substrate 101 .
- the plurality of top layers 207 may be formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like.
- FIG. 9 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- a plurality of doped regions may be formed in the plurality of active regions 105 of the substrate 101 .
- the plurality of doped regions may include a first doped region 301 and second doped regions 303 .
- the first doped region 301 is disposed between an adjacent pair of the plurality of word lines 201 .
- the second doped regions 303 are respectively disposed between the plurality of isolation structures 103 and the plurality of word lines 201 .
- the first doped region 301 and the second doped regions 303 are respectively doped with a dopant such as phosphorus, arsenic, or antimony.
- the first doped region 301 and the second doped regions respectively have dopant concentrations ranging from about 1E17 atoms/cm 3 to about 1E19 atoms/cm 3 .
- a plurality of silicide pads 302 are formed respectively over the plurality of first doped region 301 and second doped regions 303 by conventional silicidation process of the top portion of the plurality of first doped region 301 and second doped regions 303 .
- FIG. 10 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the conductive contacts 401 of the semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 11 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 10 .
- a plurality of contacts may be formed above the substrate 101 .
- a first insulating film 801 may be formed on the substrate 101 .
- the first insulating film 801 may be formed of, for example, silicon nitride, silicon oxide, silicon oxynitride, undoped silica glass, borosilica glass, phosphosilica glass, borophosphosilica glass, or a combination thereof, but is not limited thereto.
- the plurality of conductive contacts 401 may be formed in the first insulating film 801 .
- the conductive contact 401 at middle is disposed over the first doped region 301 and is electrically connected to the first doped region 301 .
- the conductive contacts 401 at two sides are respectively disposed on the second doped regions 303 and are respectively electrically connected to the second doped regions 303 .
- the conductive contacts 401 is formed including tungsten.
- FIGS. 12 to 17 illustrate, in a close-up schematic cross-sectional diagram, part of the flow of fabricating the conductive contacts 401 in accordance with one embodiment of the present disclosure.
- FIGS. 12 to 17 illustrate, in a close-up schematic cross-sectional diagram, part of the flow of fabricating the conductive contacts 401 in accordance with one embodiment of the present disclosure.
- openings 401 - 1 are formed in the first insulating film 801 by conventional lithography and etching, exposing a portion of the silicide pad 302 .
- the location of the openings 401 - 1 defines the region that will be occupied by the conductive contacts 401 .
- catalyst dots 401 - 2 such as Au, Ga, Al, Ti, and Ni for the nanowire growth are formed over the exposed silicide pad 302 .
- the catalyst dots 401 - 2 can be formed by patterning a catalyst film into dots or by dispensing a colloid containing said catalyst. It is noted that the size, e.g., width, of the catalyst dots 401 - 2 defines the nanowire diameter. Thus, accurate control of the dot size is important for obtaining a tight distribution of the nanowire's diameter.
- Other methods for introducing the catalyst are also possible. For example, a thin catalyst film will agglomerate into separated catalyst droplets if annealed at elevated temperatures (e.g., above 350° C.).
- the catalyst agglomeration method does not yield a narrow distribution of the dot size as typically obtained by the catalyst suspension method.
- the catalyst dots can be formed utilizing a self-assembly process.
- self-assembly is used herein to denote the spontaneous organization of a material into a regular pattern.
- nanowires 401 - 3 are grown perpendicular to the exposed surface of the silicide pad 302 in the opening 401 - 1 .
- the growth of the nanowires 401 - 3 is assisted by the catalyst dots 401 - 2 and is typically carried out by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD).
- the growth temperature depends on the precursor used. For example, for silane (SiH4) a typical growth temperature is from about 370° C. to about 500° C. For silicon tetrachloride (SiCl4), the growth temperature is from about 800° C. to about 950° C. By adding chlorine to SiH4, the growth temperature can be raised to above 600° C.
- the growth rate of the nanowires 401 - 3 depends on the growth temperature and the gas pressure in the growth chamber. For example, a typical CVD growth rate for SiH4 diluted with H2 (1:1) at a pressure of 1 torr and a growth temperature of 450° C. is about 7.6 ⁇ m/hour.
- the anisotropic growth of the nanowires 401 - 3 is believed to be best described by the vapor-liquid-solid (VLS) mechanism.
- the nanowires 401 - 3 can be comprised of the same or different material as that of the semiconductor substrate. In one embodiment, the nanowires 401 - 3 by comprised of a material that is different from the semiconductor substrate.
- the nanowires are single-crystal Si nanowires having substantially the same crystal orientation.
- the silicon nanowires orientation is (111) as it is seeded from the substrate which also has the (111) orientation.
- the nanowires 401 - 3 are grown to a length that typically exceeds the thickness of the fifth insulating film 814 .
- a conformal silicide layer 401 - 4 is blanket deposited over the substrate.
- silicide layer include, but are not limited to, cobalt silicide.
- the deposition of the cobalt silicide layer 401 - 4 is performed by techniques such as, for example, CVD or atomic layer deposition (ALD).
- a conformal conductor 401 - 5 is deposited over the silicide layer 401 - 4 .
- the conductor 401 - 5 fills the space between the nanowires 401 - 3 .
- the conductor 401 - 5 can be doped polysilicon, or a conductive metal such as tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta). Alloys of the conductive metals as well as silicides or nitrides of said conductive metals are also contemplated herein.
- the structure is then planarized by CMP.
- the first insulating film 801 is used as a CMP stop layer.
- the CMP step trims the nanowires 401 - 3 to be all of the same length.
- the tip of each nanowire 401 - 3 is silicided, using the SALICIDE process.
- a conductor 401 - 7 is formed over the nanowires 401 - 3 , the silicide layer 401 - 4 , and the conductor 401 - 5 .
- FIG. 18 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 19 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 18 .
- a plurality of bit line contacts 405 may be formed above the substrate 101 .
- a second insulating film 803 may be formed on the first insulating film 801 .
- the second insulating film 803 may be formed of a same material as the material of the first insulating film 801 , but is not limited thereto.
- a photolithography process may be used to pattern the second insulating film 803 to define positions of the plurality of bit line contacts 405 .
- An etch process such as an anisotropic dry etch process, may be performed after the photolithography process to form a plurality of bit line contact openings in the second insulating film 803 .
- a top surface of the first contact 401 may be exposed through the plurality of bit line contact openings.
- a cleaning process using a reducing agent may be optionally performed to remove the defects on the top surface of the first contact 401 formed including tungsten.
- the reducing agent may be titanium tetrachloride, tantalum tetrachloride, or a combination thereof.
- a first coverage layer 407 including tungsten nitride may be formed to cover bottoms and sidewalls of the plurality of bit line contact openings.
- the first coverage layer 407 may prevent the top surface of the conductive contact 401 formed a material including tungsten from being exposed to oxygen or air; therefore, the first coverage layer 407 may reduce formation of the defects on the top surface of the conductive contact 401 formed including tungsten.
- a conductive material for example, aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy is deposited, by a metallization process such as chemical vapor deposition, physical vapor deposition, sputtering, or the like, in the plurality of bit line contact openings to form the plurality of bit line contacts 405 .
- a planarization process such as chemical mechanical polishing, may be performed after the metallization process to remove excess deposited material and provide a substantially flat surface for subsequent processing steps.
- the plurality of bit line contacts 405 are correspondingly electrically connected to the middle conductive contacts 401 ; that is to say, the plurality of bit line contacts 405 are electrically coupled to the first doped region 301 .
- FIG. 20 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 21 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 20 .
- a plurality of bit lines may be formed respectively over the plurality of bit line contact on the substrate.
- a third insulating film 805 may be formed on the second insulating film 803 .
- the third insulating film 805 may be formed of a same material as the material of the first insulating film 801 , but is not limited thereto.
- a photolithography process may be used to pattern the third insulating film 805 to define positions of the plurality of bit lines.
- An etch process such as an anisotropic dry etch process, may be performed after the photolithography process to form a plurality of bit line trench openings 408 in the third insulating film 805 .
- the photolithography process may also pattern the third insulating film 805 to define positions of a plurality of contact holes 402 , and an etch process may be performed to form a plurality of contact holes 402 penetrating through the third insulating film 805 and the second insulating film 803 .
- the contact holes 402 are considered deep holes, while the bit line trench openings 408 are considered relatively shallow holes.
- FIG. 22 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 23 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 22 .
- the bit line trench openings 408 and the contact holes 402 may be filled with material by processes such as chemical vapor deposition, physical vapor deposition, sputtering, or the like.
- the contact holes 402 is deeper than the bit line trench openings 408 , and the bit line trench openings 408 may be completely filled by a filling material 408 - 1 , and the contact holes 402 may be partially filled by a filling material 402 - 1 , which can be the same as the filling material 408 - 1 .
- the upper portion of the contact holes 402 in the third insulating film 805 is not filled by the filling material 402 - 1 .
- FIG. 24 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 25 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 24 .
- an etch process such as an isotropic etch process, may be performed to remove a portion of the third insulating film 805 around the contact holes 402 to form a plurality of transformed holes 404 having a narrow portion 404 - 1 occupied by the filling material 402 - 1 in the second insulating film 803 and a wide portion 404 - 2 in the third insulating film 805 .
- FIG. 26 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 27 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 26 .
- the filling material 402 - 1 and the filling material 408 - 1 are stripped from the transformed holes 404 and the bit line trench openings 408 , respectively.
- a conductive material for example, aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy is deposited, by a metallization process such as chemical vapor deposition, physical vapor deposition, sputtering, or the like, in the plurality of bit line trench openings 408 to form a plurality of bit lines 409 and in the transformed holes 404 to form a plurality of capacitor contacts 403 .
- a planarization process such as chemical mechanical polishing, may be performed after the metallization process to remove excess deposited material and provide a substantially flat surface for subsequent processing steps.
- the capacitor contact 403 includes a neck portion 403 - 1 and a head portion 403 - 2 over the neck portion 403 - 1 , wherein an upper width W 1 of the head portion 403 - 2 is larger than an upper width W 2 of the neck portion 403 - 1 .
- the upper width W 2 of the neck portion 403 - 1 is substantially the same as a bottom width of the head portion 403 - 2 .
- the head portion 403 - 2 has a curved sidewall 403 - 3 .
- the head portion has tapered profile.
- the plurality of bit lines 409 may extend along a direction Y and implemented as wavy lines in a top-view diagram.
- the plurality of bit line contacts 405 are located at intersections of the plurality of bit lines 409 and the plurality of active regions 105 .
- the plurality of bit lines 409 implemented as wavy lines may increase a contact area between the plurality of bit line contacts 405 and the plurality of active regions 105 ; therefore, a contact resistance between the plurality of bit line contacts 405 and the plurality of active regions 105 may be reduced.
- FIG. 28 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- a plurality of capacitor plugs 411 may be formed above the substrate 101 .
- a fourth insulating film 807 may be formed on the third insulating film 805 .
- the fourth insulating film 807 may be formed of a same material as the material of the first insulating film 801 , but is not limited thereto.
- a photolithography process may be used to pattern the fourth insulating film 807 to define positions of the plurality of capacitor plugs 411 .
- An etch process such as an anisotropic dry etch process, may be performed after the photolithography process to form a plurality of plug openings passing through the fourth insulating film 807 , the third insulating film 805 , and the second insulating film 803 .
- a conductive material for example, aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy is deposited, by a metallization process such as chemical vapor deposition, physical vapor deposition, sputtering, or the like, in the plurality of plug openings to form the plurality of capacitor plugs 411 over the head portion 403 - 2 .
- a planarization process such as chemical mechanical polishing, may be performed after the metallization process to remove excess deposited material and provide a substantially flat surface for subsequent processing steps.
- FIG. 29 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- an etching back process is performed to remove a top portion of the fourth insulating film 807 to expose a protruding portion 411 A of the capacitor plug 411 .
- the top surface of the capacitor plug 411 is higher than that of the fourth insulating film 807 , and the sidewall of the capacitor plug 411 (protruding portion 411 A) is exposed.
- FIG. 30 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- a deposition process is performed to form a liner layer 808 , covering the top surface of the fourth insulating film 807 , the top surface of the protruding portion 411 A, and the sidewall of the protruding portion 411 A.
- FIG. 31 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- an anisotropic dry etching process is performed to remove a portion of the liner layer 808 so as to form a plurality of first spacers 808 A respectively on the protruding portion 411 A.
- the first spacer 808 A comprises metal silicide and is disposed on a sidewall of the protruding portion 411 A.
- the width W 4 of the first spacer 808 A is larger than the width W 3 of the capacitor plug 411 .
- FIG. 32 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- a salicidation process is performed to form a plurality of second spacers 808 B respectively over the first spacers 808 A.
- the first spacer 808 A comprises polysilicon and is disposed on a sidewall of the protruding portion 411 A
- the second spacer 808 B comprises metal silicide from the polysilicon of the first spacer 808 A.
- the protruding portion 411 A, the first spacer 808 A, and the second spacer 808 B form a landing pad 810 over the capacitor contact 403 .
- FIG. 33 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- a fifth insulating film 814 having a plug 816 may be formed over the landing pad 810 .
- the fifth insulating film 814 may be formed of a same material as the material of the first insulating film 801 , but is not limited thereto.
- a photolithography process may be used to pattern the fifth insulating film 814 to define positions of the plurality of plugs 816 .
- An etch process such as an anisotropic dry etch process, may be performed after the photolithography process to form a plurality of plug openings passing through the fifth insulating film 814 .
- a conductive material for example, aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy is deposited, by a metallization process such as chemical vapor deposition, physical vapor deposition, sputtering, or the like, in the plurality of plug openings to form the plurality of plugs 816 over the landing pad 810 .
- a planarization process such as chemical mechanical polishing, may be performed after the metallization process to remove excess deposited material and provide a substantially flat surface for subsequent processing steps.
- FIGS. 34 to 36 illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 37 illustrates, in a schematic top-view diagram, the semiconductor device in accordance with FIG. 36 .
- the plurality of capacitor structures 501 may include a bottom electrode 505 , a capacitor insulating layer 507 , and a top electrode 509 .
- a fifth insulating film 809 may be formed on the fourth insulating film 807 .
- the fifth insulating film 809 may be formed of a same material as the material of the first insulating film 801 , but is not limited thereto.
- a photolithography process may be used to pattern the fifth insulating film 809 to define positions of a plurality of capacitor trenches 503 .
- An etch process such as an anisotropic dry etch process, may be performed after the photolithography process to form the plurality of capacitor trenches 503 passing through the fifth insulating film 809 .
- the plurality of plugs 816 may be exposed through the plurality of capacitor trenches 503 .
- a plurality of bottom electrodes 505 may be correspondingly respectively formed in the plurality of capacitor trenches 503 , in other words, the plurality of bottom electrodes 505 may be inwardly formed in the fifth insulating film 809 .
- the plurality of bottom electrodes 505 may be formed of, for example, doped polysilicon, metal silicide, aluminum, copper, or tungsten.
- the plurality of bottom electrodes 505 may be respectively correspondingly connected to the plurality of plugs 816 .
- the capacitor insulating layer 507 may be formed to attach to sidewalls and bottoms of the plurality of bottom electrodes 505 and the top surfaces of the fifth insulating film 809 .
- the capacitor insulating layer 507 may be a single layer or multiple layers.
- the capacitor insulating layer 507 may be a single layer or multiple layers.
- the capacitor insulating layer 507 may be a single layer formed of a high dielectric constant material such as barium strontium titanate, lead zirconium titanate, titanium oxide, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, or the like.
- the capacitor insulating layer 507 may be multiple layers consisting of silicon oxide, silicon nitride, and silicon oxide.
- the top electrode 509 may be formed to fill the plurality of capacitor trenches 503 and cover the capacitor insulating layer 507 .
- the top electrode 509 may be formed of, for example, doped polysilicon, copper, or aluminum.
- FIGS. 38 to 41 illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.
- a bottom via 413 and a first conductive layer 415 may be formed above the substrate 101 .
- a sixth insulating film 811 may be formed on the fifth insulating film 809 .
- the sixth insulating film 811 may be formed of a same material as the material of the first insulating film 801 , but is not limited thereto.
- a photolithography process may be used to pattern the sixth insulating film 811 to define positions of the bottom via 413 .
- An etch process such as an anisotropic dry etch process, may be performed after the photolithography process to form a bottom via opening passing through the sixth insulating film 811 .
- a conductive material for example, aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy is deposited, by a metallization process such as chemical vapor deposition, physical vapor deposition, sputtering, or the like, in the bottom via opening to form the bottom via 413 in the sixth insulating film 811 .
- a planarization process such as chemical mechanical polishing, may be performed after the metallization process to remove excess deposited material and provide a substantially flat surface for subsequent processing steps.
- the bottom via 413 is formed including tungsten. Defects may be easily formed on a top surface of the bottom via 413 formed including tungsten when the top surface of the bottom via 413 is exposed to oxygen or air. The defects may affect the yield of the semiconductor device.
- a seventh insulating film 813 may be formed on the sixth insulating film 811 .
- the seventh insulating film 813 may be formed of a same material as the material of the first insulating film 801 , but is not limited thereto.
- a photolithography process may be used to pattern the seventh insulating film 813 to define a position of the first conductive layer 415 .
- An etch process such as an anisotropic dry etch process, may be performed after the photolithography process to form a first conductive layer trench in the seventh insulating film 813 .
- the top surface of the bottom via 413 may be exposed through the first conductive layer trench.
- a cleaning process using a reducing agent may be optionally performed to remove the defects on the top surface of the bottom via 413 formed including tungsten.
- the reducing agent may be titanium tetrachloride, tantalum tetrachloride, or combination thereof.
- a second coverage layer 417 formed including tungsten nitride may be formed to cover a bottom and sidewalls of the first conductive layer trench.
- the second coverage layer 417 may prevent the top surface of the bottom via 413 formed including tungsten from being exposed to oxygen or air; therefore, the second coverage layer 417 may reduce formation of the defects on the top surface of the bottom via 413 formed including tungsten.
- a conductive material for example, aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy is deposited, by a metallization process such as chemical vapor deposition, physical vapor deposition, sputtering, or the like, in the first conductive layer trench to form the first conductive layer 415 .
- a planarization process such as chemical mechanical polishing, may be performed after the metallization process to remove excess deposited material and provide a substantially flat surface for subsequent processing steps.
- FIG. 41 illustrates, in a schematic cross-sectional view diagram, a semiconductor device in accordance with one embodiment of the present disclosure.
- a semiconductor device may include a substrate 101 , a plurality of isolation structures 103 , a plurality of word lines 201 , a plurality of doped regions, a plurality of insulating films, a plurality of contacts, a plurality of bit line contacts 405 , a first coverage layer 407 , a plurality of bit lines 409 , a plurality of plugs 411 , a plurality of landing pads 810 , a plurality of plugs 816 , a bottom via 413 , a first conductive layer 415 , a second coverage layer 417 , and a plurality of capacitor structures 501 .
- the plurality of isolation structures 103 may be disposed in the substrate 101 and separated from each other.
- the plurality of isolation structures 103 may define a plurality of active regions 105 .
- the plurality of word lines 201 may be disposed in the substrate 101 and separated from each other.
- Each one of the plurality of word lines 201 includes a bottom layer 203 , a middle layer 205 , and a top layer 207 .
- the plurality of bottom layers 203 may be respectively inwardly disposed in the substrate 101 .
- the plurality of middle layers 205 may be respectively correspondingly disposed on the plurality of bottom layers 203 .
- Top surfaces of the plurality of middle layers 205 may be lower than a top surface of the substrate 101 .
- the plurality of top layers 207 may be respectively correspondingly disposed on the plurality of middle layers 205 .
- Top surfaces of the plurality of top layers 207 may be at the same vertical level as the top surface of the substrate 101 .
- a plurality of doped regions may be disposed in the plurality of active regions 105 of the substrate 101 .
- Each of the plurality of doped regions includes a first doped region 301 and second doped regions 303 .
- the first doped region 301 is disposed between an adjacent pair of the plurality of word lines 201 .
- the second doped regions 303 are respectively disposed between the plurality of isolation structures 103 and the plurality of word lines 201 .
- the plurality of insulating films may be disposed above the substrate 101 .
- the plurality of insulating films may include a first insulating film 801 , a second insulating film 803 , a third insulating film 805 , a fourth insulating film 807 , a fifth insulating film 809 , a sixth insulating film 811 , and a seventh insulating film 813 .
- the first insulating film 801 may be disposed on the substrate 101 .
- the plurality of contacts may be disposed in the first insulating film 801 .
- the plurality of contacts may include a contact 401 and capacitor contacts 403 .
- the contact 401 is disposed on the first doped region 301 and is electrically connected to the first doped region 301 .
- the capacitor contacts 403 are respectively disposed on the second doped regions 303 and are respectively electrically connected to the second doped regions 303 .
- the contact 401 is formed including tungsten.
- the second insulating film 803 may be disposed on the first insulating film 801 .
- the plurality of bit line contacts 405 may be disposed in the second insulating film 803 .
- the first coverage layer 407 may be disposed in the second insulating film 803 and on a top surface of the contact 401 ; in other words, the first coverage layer 407 may be disposed between the plurality of bit line contacts 405 and the contact 401 .
- the first coverage layer 407 may be disposed on and attached to sidewalls of the plurality of bit line contacts 405 .
- the first coverage layer 407 may include tungsten nitride.
- the third insulating film 805 may be disposed on the second insulating film 803 .
- the plurality of bit lines 409 may be disposed in the third insulating film 805 and on the plurality of bit line contacts 405 and the first coverage layer 407 . (Only one bit line 409 is shown in FIG. 41 .)
- the fourth insulating film 807 may be disposed on the third insulating film 805 .
- the plurality of plugs 411 may be disposed to pass through the fourth insulating film 807 , the third insulating film 805 , and the second insulating film 803 .
- the plurality of plugs 411 may be respectively correspondingly electrically connected to the capacitor contacts 403 .
- the capacitor contact 403 includes a neck portion 403 - 1 and a head portion 403 - 2 over the neck portion 403 - 1 , wherein an upper width W 1 of the head portion 403 - 2 is larger than an upper width W 2 of the neck portion 403 - 1 .
- the upper width W 2 of the neck portion 403 - 1 is substantially the same as a bottom width of the head portion 403 - 2 .
- the head portion 403 - 2 has a curved sidewall 403 - 3 .
- the head portion has tapered profile.
- a plurality of first spacers 808 A are respectively disposed on the protruding portion 411 A of the plugs 411 .
- the first spacer 808 A comprises metal silicide and is disposed on a sidewall of the protruding portion 411 A.
- the width W 4 of the first spacer 808 A is larger than the width W 3 of the capacitor plug 411 .
- a plurality of second spacers 808 B are respectively disposed over the first spacers 808 A.
- the first spacer 808 A comprises polysilicon and is disposed on a sidewall of the protruding portion 411 A
- the second spacer 808 B comprises metal silicide from the polysilicon of the first spacer 808 A.
- the protruding portion 411 A, the first spacer 808 A, and the second spacer 808 B form a landing pad 810 over the capacitor contact 403 .
- the fifth insulating film 809 may be disposed on the fourth insulating film 807 .
- the plurality of capacitor structures 501 may be disposed in the fifth insulating film 809 .
- the plurality of capacitor structures 501 may include a plurality of bottom electrodes 505 , a capacitor insulating layer 507 , and a top electrode 509 .
- the plurality of bottom electrodes 505 may be inwardly disposed in the fifth insulating film 809 and respectively correspondingly electrically connected to the plurality of plugs 816 .
- the capacitor insulating layer 507 may be disposed on the plurality of bottom electrodes 505 .
- the top electrode 509 may be disposed on the capacitor insulating layer 507 .
- the sixth insulating film 811 may be disposed on the fifth insulating film 809 .
- the bottom via 413 may be disposed in the sixth insulating film 811 and electrically connected to the top electrode 509 .
- the bottom via 413 may include tungsten.
- a seventh insulating film 813 may be disposed on the sixth insulating film 811 .
- the first conductive layer 415 may be disposed in the seventh insulating film 813 and above the bottom via 413 .
- the second coverage layer 417 may be disposed on a top surface of the bottom via 413 , and the second coverage layer 417 may be disposed between the bottom via 413 and the first conductive layer 415 .
- the second coverage layer 417 may be disposed on and attached to sidewalls of the first conductive layer 415 .
- the second coverage layer 417 may include tungsten nitride.
- FIGS. 42 and 43 illustrate, in schematic cross-sectional view diagrams, some semiconductor devices in accordance with some embodiments of the present disclosure.
- the semiconductor device may include a plurality of third coverage layers 419 .
- the plurality of third coverage layers 419 may be respectively correspondingly disposed between the capacitor contacts 403 and the plurality of plugs 411 .
- the plurality of third coverage layers 419 may be respectively correspondingly disposed on top surfaces of the capacitor contacts 403 formed including tungsten.
- the plurality of third coverage layers 419 may be respectively correspondingly disposed on and attached to sidewalls of the plurality of plugs 411 .
- the plurality of third coverage layers 419 may include tungsten nitride.
- first coverage layer 407 the second coverage layer 417 , and the plurality of third coverage layers 419 are disposed on the contact 401 , the bottom via 413 , and the capacitor contacts 403 , respectively; however, other conductive layers or vias may also applicable.
- a coverage layer may be regarded as the first coverage layer 407 , the second coverage layer 417 , or the third coverage layer 419 , but is not limited thereto.
- a conductive feature may be regarded as the contact 401 , the second contact 403 , or the bottom via 413 , but is not limited thereto.
- the semiconductor device may include a first barrier layer 421 .
- the first barrier layer 421 may be disposed between the first coverage layer 407 and the plurality of bit line contacts 405 .
- the first barrier layer 421 may be formed of, for example, titanium, titanium nitride, titanium-tungsten alloy, tantalum, tantalum nitride, or the combination thereof.
- the first barrier layer 421 may improve adhesion between the first coverage layer 407 and the plurality of bit line contacts 405 .
- the first barrier layer 421 may also be implemented between the conductive contacts 401 and the first insulating film 801 .
- One aspect of the present disclosure provides a semiconductor device having a substrate including a plurality of doped regions; a plurality of silicide pads disposed respectively over the plurality of doped regions; and a plurality of conductive contacts disposed respectively over the plurality of silicide pads; wherein the plurality of conductive contacts comprise a plurality of nanowires, a conductive liner disposed over the plurality of nanowires, and a conductor disposed over the conductive liner.
- Another aspect of the present disclosure provides a method for fabricating a semiconductor device comprising: providing a substrate including a plurality of doped regions; forming a plurality of silicide pads respectively over the plurality of doped regions; and forming a plurality of conductive contacts respectively over the plurality of silicide pads; wherein the plurality of conductive contacts comprise a plurality of nanowires, a conductive liner over the plurality of nanowires, and a conductor over the conductive liner.
- the high aspect ratio conductive contact is implemented by the nanowires to electrically connect the source/drain regions in the substrate and the capacitor structures over the source/drain regions.
- the high aspect ratio conductive contact is implemented by the nanowires to electrically connect the source/drain regions in the substrate and the bit line.
- the landing pad has the first spacer, wherein a width of the first spacer is larger than a width of the capacitor plug, the misalignment between the subsequently formed capacitor structure and the landing pad can be dramatically solved, wherein a width of the first spacer is larger than a width of the capacitor plug.
- the coverage layer may reduce formation of defects in the semiconductor device; therefore, the yield of the semiconductor device increases correspondingly.
Abstract
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having a plurality of doped regions; a plurality of silicide pads disposed respectively over the plurality of doped regions; and a plurality of conductive contacts disposed respectively over the plurality of silicide pads. The plurality of conductive contacts comprise a plurality of nanowires, a conductive liner disposed over the plurality of nanowires, and a conductor disposed over the conductive liner.
Description
- The present disclosure relates to a semiconductor device and a method for fabricating the semiconductor device, and more particularly, to a semiconductor device with coverage layer and a method for fabricating the semiconductor device with coverage layer.
- Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. The dimensions of semiconductor devices are continuously being scaled down to meet the increasing demand of computing ability. However, a variety of issues arise during the scaling-down process and impact the final electrical characteristics, quality, and yield. Therefore, challenges remain in achieving improved performance, quality, yield, and reliability.
- This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.
- One aspect of the present disclosure provides a semiconductor device having a substrate including a plurality of doped regions; a plurality of silicide pads disposed respectively over the plurality of doped regions; and a plurality of conductive contacts disposed respectively over the plurality of silicide pads; wherein the plurality of conductive contacts comprise a plurality of nanowires, a conductive liner disposed over the plurality of nanowires, and a conductor disposed over the conductive liner.
- In some embodiments, the semiconductor device further comprises a bit line disposed over one of the plurality of conductive contacts, and bit line is an undulating strip.
- In some embodiments, the semiconductor device further comprises a plurality of capacitor contacts disposed over the substrate, at least one of the plurality of capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion.
- In some embodiments, the upper width of the head portion is larger than a bottom width of the head portion, and the head portion has a curved sidewall.
- In some embodiments, the upper width of the neck portion is substantially the same as a bottom width of the head portion, and the head portion has tapered profile.
- In some embodiments, the semiconductor device further comprises a capacitor structure disposed over one of the plurality of conductive contacts.
- In some embodiments, the semiconductor device further comprises a plurality of landing pads disposed respectively over the plurality of head portions, at least one of the plurality of landing pads comprising a protruding portion of the capacitor plug and a first spacer over the protruding portion, wherein a width of the first spacer is larger than a width of the capacitor plug.
- In some embodiments, the first spacer comprises metal silicide and is disposed on a sidewall of the protruding portion.
- In some embodiments, the first spacer comprises polysilicon and is disposed on a sidewall of the protruding portion.
- In some embodiments, the semiconductor device further comprises a second spacer disposed over the first spacer, and the second spacer comprises metal silicide.
- Another aspect of the present disclosure provides a method for fabricating a semiconductor device comprising: providing a substrate including a plurality of doped regions; forming a plurality of silicide pads respectively over the plurality of doped regions; and forming a plurality of conductive contacts respectively over the plurality of silicide pads; wherein the plurality of conductive contacts comprise a plurality of nanowires, a conductive liner over the plurality of nanowires, and a conductor over the conductive liner.
- In some embodiments, the method for fabricating a semiconductor device further comprises: forming a plurality of capacitor contacts over the substrate, at least one of the plurality of capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion.
- In some embodiments, forming a plurality of capacitor contacts comprises: forming a contact hole in a dielectric stack having a first layer and a second layer over the first layer; removing a portion of the second layer around the contact hole to form a transformed hole having a narrow portion in the first layer and a wide portion in the second layer; and filling a conductive material into the transformed hole.
- In some embodiments, the contact hole is formed integrally with a bit line trench in the second layer.
- In some embodiments, the method for fabricating a semiconductor device further comprises: filling the bit line trench and a lower portion of the contact hole with a filling material.
- In some embodiments, removing a portion of the second layer around the contact hole is performed after filling the lower portion of the contact hole with a sacrificial material.
- In some embodiments, the method for fabricating a semiconductor device further comprises: forming a plurality of landing pads respectively over the plurality of head portions, at least one of the plurality of landing pads comprising a protruding portion of the capacitor plug and a first spacer over the protruding portion, wherein a width of the first spacer is larger than a width of the capacitor plug.
- In some embodiments, the first spacer comprises metal silicide and is formed on a sidewall of the protruding portion.
- In some embodiments, the first spacer comprises polysilicon and is on a sidewall of the protruding portion.
- In some embodiments, the method for fabricating a semiconductor device further comprises: forming a plurality of second spacers respectively over the plurality of first spacers, wherein the second spacer comprises metal silicide.
- The high aspect ratio conductive contact is implemented by the nanowires to electrically connect the source/drain regions in the substrate and the capacitor structures over the source/drain regions. In addition, the high aspect ratio conductive contact is implemented by the nanowires to electrically connect the source/drain regions in the substrate and the bit line.
- Furthermore, the landing pad has the first spacer, wherein a width of the first spacer is larger than a width of the capacitor plug, the misalignment between the subsequently formed capacitor structure and the landing pad can be dramatically solved, wherein a width of the first spacer is larger than a width of the capacitor plug.
- In addition, due to the capacitor contact having the neck portion and the head portion with a tapered profile, the misalignment between the subsequently formed capacitor structure and the capacitor contact can be dramatically solved. In addition, the coverage layer may reduce formation of defects in the semiconductor device; therefore, the yield of the semiconductor device increases correspondingly.
- The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
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FIG. 1 illustrates, in a flowchart diagram form, a method for fabricating a semiconductor device in accordance with one embodiment of the present disclosure. -
FIGS. 2 and 3 illustrate, in schematic cross-sectional diagrams, part of a flow of fabricating a semiconductor device in accordance with one embodiment of the present disclosure. -
FIG. 4 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 3 . -
FIGS. 5 to 7 illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. -
FIG. 8 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 7 . -
FIG. 9 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. -
FIG. 10 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. -
FIG. 11 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 10 . -
FIG. 12 to 17 illustrate, in a close-up schematic cross-sectional diagram, part of the flow of fabricating the conductive contacts in accordance with one embodiment of the present disclosure. -
FIG. 18 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. -
FIG. 19 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 18 . -
FIG. 20 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. -
FIG. 21 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 20 . -
FIG. 22 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. -
FIG. 23 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 22 . -
FIG. 24 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. -
FIG. 25 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 24 . -
FIG. 26 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. -
FIG. 27 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 26 . -
FIGS. 28 to 33 illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. -
FIGS. 34 to 36 illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. -
FIG. 37 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 36 . -
FIGS. 38 to 41 illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. -
FIGS. 42 to 43 illustrate, in schematic cross-sectional view diagrams, some semiconductor devices in accordance with some embodiments of the present disclosure. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- It will be understood that when an element or layer is referred to as being “connected to,” or “coupled to” another element or layer, it can be directly connected to or coupled to another element or layer or intervening elements or layers may be present.
- It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. Unless indicated otherwise, these terms are only used to distinguish one element from another element. Thus, for example, a first element, a first component or a first section discussed below could be termed a second element, a second component or a second section without departing from the teachings of the present disclosure.
- Unless the context indicates otherwise, terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to reflect this meaning. For example, items described as “substantially the same,” “substantially equal,” or “substantially planar,” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.
- In the present disclosure, a semiconductor device generally means a device which can function by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of the semiconductor device.
- Note that, in the description of the present disclosure, above (or up) corresponds to the direction of the arrow of the direction Z, and below (or down) corresponds to the opposite direction of the arrow of the direction Z.
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FIG. 1 illustrates, in a flowchart diagram form, amethod 10 for fabricating a semiconductor device in accordance with one embodiment of the present disclosure.FIGS. 2 and 3 illustrate, in schematic cross-sectional diagrams, part of a flow of fabricating a semiconductor device in accordance with one embodiment of the present disclosure.FIG. 4 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 3 . - With reference to
FIGS. 1 and 2 , at step S11, asubstrate 101 may be provided. Thesubstrate 101 may be formed of, for example, silicon, doped silicon, silicon germanium, silicon on insulator, silicon on sapphire, silicon germanium on isulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, gallium arsenide phosphide, indium phosphide, or indium gallium phosphide. - With reference to
FIGS. 3 and 4 , at step S13, a plurality ofisolation structures 103 may be formed in thesubstrate 101. The plurality ofisolation structures 103 are separated from each other in a cross-sectional view and define a plurality ofactive regions 105. The plurality ofisolation structures 103 may be formed of, for example, an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluoride-doped silicate, or the like. The plurality ofactive regions 105 may extend in a direction slanted with respect to a direction X in a top-view diagram. Note that, in the present disclosure, silicon oxynitride refers to a substance which contains silicon, nitrogen, and oxygen and in which a proportion of oxygen is greater than that of nitrogen. Silicon nitride oxide refers to a substance which contains silicon, oxygen, and nitrogen and in which a proportion of nitrogen is greater than that of oxygen. -
FIGS. 5 to 7 illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.FIG. 8 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 7 . - With reference to
FIG. 1 andFIGS. 5 to 8 , at step S15, a plurality ofword lines 103 may be formed in thesubstrate 101. In the embodiment depicted, the plurality ofword lines 103 may extend along the direction X. Each one of the plurality ofword lines 201 includes abottom layer 203, amiddle layer 205, atop layer 207, and atrench opening 209. With reference toFIG. 5 , in the embodiment depicted, a photolithography process may be used to pattern thesubstrate 101 to define positions of a plurality oftrench openings 209. An etch process, such as an anisotropic dry etch process, may be performed to form the plurality oftrench openings 209 in thesubstrate 101. With reference toFIG. 6 , after the etch process, the plurality ofbottom layers 203 may be correspondingly formed and attached to sidewalls of the plurality oftrench openings 209 and bottoms of the plurality oftrench openings 209. The plurality ofbottom layers 203 may be formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like. - With reference to
FIGS. 7 and 8 , the plurality ofmiddle layers 205 may be correspondingly formed on the plurality of bottom layers 203. Top surfaces of the plurality ofmiddle layers 205 may be lower than a top surface of thesubstrate 101. The plurality ofmiddle layers 205 may be formed of, for example, doped polysilicon, metal material, or metal silicide. Metal silicide may be, for example, nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like. The plurality oftop layers 207 may be correspondingly formed on the plurality ofmiddle layers 205. Top surfaces of the plurality oftop layers 207 may be at the same vertical level as the top surface of thesubstrate 101. The plurality oftop layers 207 may be formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like. -
FIG. 9 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. - With reference to
FIG. 1 andFIG. 9 , at step S17, a plurality of doped regions may be formed in the plurality ofactive regions 105 of thesubstrate 101. The plurality of doped regions may include a firstdoped region 301 and seconddoped regions 303. The firstdoped region 301 is disposed between an adjacent pair of the plurality of word lines 201. The seconddoped regions 303 are respectively disposed between the plurality ofisolation structures 103 and the plurality of word lines 201. The firstdoped region 301 and the seconddoped regions 303 are respectively doped with a dopant such as phosphorus, arsenic, or antimony. The firstdoped region 301 and the second doped regions respectively have dopant concentrations ranging from about 1E17 atoms/cm3 to about 1E19 atoms/cm3. In some embodiments, a plurality ofsilicide pads 302 are formed respectively over the plurality of firstdoped region 301 and seconddoped regions 303 by conventional silicidation process of the top portion of the plurality of firstdoped region 301 and seconddoped regions 303. -
FIG. 10 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating theconductive contacts 401 of the semiconductor device in accordance with one embodiment of the present disclosure.FIG. 11 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 10 . - With reference to
FIG. 1 andFIGS. 10 and 11 , at step S19, a plurality of contacts may be formed above thesubstrate 101. A first insulatingfilm 801 may be formed on thesubstrate 101. The firstinsulating film 801 may be formed of, for example, silicon nitride, silicon oxide, silicon oxynitride, undoped silica glass, borosilica glass, phosphosilica glass, borophosphosilica glass, or a combination thereof, but is not limited thereto. The plurality ofconductive contacts 401 may be formed in the first insulatingfilm 801. - In some embodiments, with reference to
FIGS. 10 and 11 , theconductive contact 401 at middle is disposed over the firstdoped region 301 and is electrically connected to the firstdoped region 301. Theconductive contacts 401 at two sides are respectively disposed on the seconddoped regions 303 and are respectively electrically connected to the seconddoped regions 303. In the embodiment depicted, theconductive contacts 401 is formed including tungsten. -
FIGS. 12 to 17 illustrate, in a close-up schematic cross-sectional diagram, part of the flow of fabricating theconductive contacts 401 in accordance with one embodiment of the present disclosure. -
FIGS. 12 to 17 illustrate, in a close-up schematic cross-sectional diagram, part of the flow of fabricating theconductive contacts 401 in accordance with one embodiment of the present disclosure. - With reference to
FIG. 12 , in some embodiments, openings 401-1, one of which is shown inFIGS. 12 to 17 , are formed in the first insulatingfilm 801 by conventional lithography and etching, exposing a portion of thesilicide pad 302. The location of the openings 401-1 defines the region that will be occupied by theconductive contacts 401. - With reference to
FIG. 13 , in some embodiments, catalyst dots 401-2 such as Au, Ga, Al, Ti, and Ni for the nanowire growth are formed over the exposedsilicide pad 302. The catalyst dots 401-2 can be formed by patterning a catalyst film into dots or by dispensing a colloid containing said catalyst. It is noted that the size, e.g., width, of the catalyst dots 401-2 defines the nanowire diameter. Thus, accurate control of the dot size is important for obtaining a tight distribution of the nanowire's diameter. Other methods for introducing the catalyst are also possible. For example, a thin catalyst film will agglomerate into separated catalyst droplets if annealed at elevated temperatures (e.g., above 350° C.). The catalyst agglomeration method, however, does not yield a narrow distribution of the dot size as typically obtained by the catalyst suspension method. Moreover, the catalyst dots can be formed utilizing a self-assembly process. The term “self-assembly” is used herein to denote the spontaneous organization of a material into a regular pattern. - With reference to
FIG. 14 , in some embodiments, nanowires 401-3 are grown perpendicular to the exposed surface of thesilicide pad 302 in the opening 401-1. The growth of the nanowires 401-3 is assisted by the catalyst dots 401-2 and is typically carried out by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). The growth temperature depends on the precursor used. For example, for silane (SiH4) a typical growth temperature is from about 370° C. to about 500° C. For silicon tetrachloride (SiCl4), the growth temperature is from about 800° C. to about 950° C. By adding chlorine to SiH4, the growth temperature can be raised to above 600° C. The growth rate of the nanowires 401-3 depends on the growth temperature and the gas pressure in the growth chamber. For example, a typical CVD growth rate for SiH4 diluted with H2 (1:1) at a pressure of 1 torr and a growth temperature of 450° C. is about 7.6 μm/hour. The anisotropic growth of the nanowires 401-3 is believed to be best described by the vapor-liquid-solid (VLS) mechanism. Note that the nanowires 401-3 can be comprised of the same or different material as that of the semiconductor substrate. In one embodiment, the nanowires 401-3 by comprised of a material that is different from the semiconductor substrate. In yet another embodiment, the nanowires are single-crystal Si nanowires having substantially the same crystal orientation. In the specific example described herein in which Si nanowires are formed on a (111) oriented Si substrate, the silicon nanowires orientation is (111) as it is seeded from the substrate which also has the (111) orientation. The nanowires 401-3 are grown to a length that typically exceeds the thickness of the fifth insulatingfilm 814. - With reference to
FIG. 15 , in some embodiments, a conformal silicide layer 401-4 is blanket deposited over the substrate. Some examples of silicide layer include, but are not limited to, cobalt silicide. The deposition of the cobalt silicide layer 401-4 is performed by techniques such as, for example, CVD or atomic layer deposition (ALD). - With reference to
FIG. 16 , in some embodiments, a conformal conductor 401-5 is deposited over the silicide layer 401-4. The conductor 401-5 fills the space between the nanowires 401-3. The conductor 401-5 can be doped polysilicon, or a conductive metal such as tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta). Alloys of the conductive metals as well as silicides or nitrides of said conductive metals are also contemplated herein. - With reference to
FIG. 17 , in some embodiments, the structure is then planarized by CMP. The firstinsulating film 801 is used as a CMP stop layer. The CMP step trims the nanowires 401-3 to be all of the same length. In some embodiments, the tip of each nanowire 401-3 is silicided, using the SALICIDE process. Subsequently, a conductor 401-7 is formed over the nanowires 401-3, the silicide layer 401-4, and the conductor 401-5. -
FIG. 18 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.FIG. 19 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 18 . - With reference to
FIG. 1 andFIGS. 18 and 19 , at step S21, a plurality ofbit line contacts 405 may be formed above thesubstrate 101. (Only onebit line contact 405 is shown inFIG. 18 .) A secondinsulating film 803 may be formed on the first insulatingfilm 801. The secondinsulating film 803 may be formed of a same material as the material of the first insulatingfilm 801, but is not limited thereto. A photolithography process may be used to pattern the secondinsulating film 803 to define positions of the plurality ofbit line contacts 405. An etch process, such as an anisotropic dry etch process, may be performed after the photolithography process to form a plurality of bit line contact openings in the secondinsulating film 803. A top surface of thefirst contact 401 may be exposed through the plurality of bit line contact openings. A cleaning process using a reducing agent may be optionally performed to remove the defects on the top surface of thefirst contact 401 formed including tungsten. The reducing agent may be titanium tetrachloride, tantalum tetrachloride, or a combination thereof. - With reference to
FIGS. 18 and 19 , after the cleaning process, afirst coverage layer 407 including tungsten nitride may be formed to cover bottoms and sidewalls of the plurality of bit line contact openings. Thefirst coverage layer 407 may prevent the top surface of theconductive contact 401 formed a material including tungsten from being exposed to oxygen or air; therefore, thefirst coverage layer 407 may reduce formation of the defects on the top surface of theconductive contact 401 formed including tungsten. A conductive material, for example, aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy is deposited, by a metallization process such as chemical vapor deposition, physical vapor deposition, sputtering, or the like, in the plurality of bit line contact openings to form the plurality ofbit line contacts 405. A planarization process, such as chemical mechanical polishing, may be performed after the metallization process to remove excess deposited material and provide a substantially flat surface for subsequent processing steps. - With reference to
FIGS. 18 and 19 , the plurality ofbit line contacts 405 are correspondingly electrically connected to the middleconductive contacts 401; that is to say, the plurality ofbit line contacts 405 are electrically coupled to the firstdoped region 301. -
FIG. 20 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.FIG. 21 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 20 . - With reference to
FIG. 1 andFIGS. 20 and 21 , at step S15, a plurality of bit lines may be formed respectively over the plurality of bit line contact on the substrate. A thirdinsulating film 805 may be formed on the secondinsulating film 803. The thirdinsulating film 805 may be formed of a same material as the material of the first insulatingfilm 801, but is not limited thereto. A photolithography process may be used to pattern the thirdinsulating film 805 to define positions of the plurality of bit lines. An etch process, such as an anisotropic dry etch process, may be performed after the photolithography process to form a plurality of bitline trench openings 408 in the thirdinsulating film 805. In some embodiments, the photolithography process may also pattern the thirdinsulating film 805 to define positions of a plurality of contact holes 402, and an etch process may be performed to form a plurality ofcontact holes 402 penetrating through the thirdinsulating film 805 and the secondinsulating film 803. In other words, the contact holes 402 are considered deep holes, while the bitline trench openings 408 are considered relatively shallow holes. -
FIG. 22 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.FIG. 23 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 22 . In some embodiments, the bitline trench openings 408 and the contact holes 402 may be filled with material by processes such as chemical vapor deposition, physical vapor deposition, sputtering, or the like. In some embodiments, the contact holes 402 is deeper than the bitline trench openings 408, and the bitline trench openings 408 may be completely filled by a filling material 408-1, and the contact holes 402 may be partially filled by a filling material 402-1, which can be the same as the filling material 408-1. In some embodiments, the upper portion of the contact holes 402 in the thirdinsulating film 805 is not filled by the filling material 402-1. - With reference to
FIG. 1 andFIGS. 24 and 27 , at step S17, a plurality of capacitor contacts respectively over the second regions of the substrate.FIG. 24 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.FIG. 25 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 24 . In some embodiments, an etch process, such as an isotropic etch process, may be performed to remove a portion of the thirdinsulating film 805 around the contact holes 402 to form a plurality of transformedholes 404 having a narrow portion 404-1 occupied by the filling material 402-1 in the secondinsulating film 803 and a wide portion 404-2 in the thirdinsulating film 805. -
FIG. 26 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.FIG. 27 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 26 . In some embodiments, the filling material 402-1 and the filling material 408-1 are stripped from the transformedholes 404 and the bitline trench openings 408, respectively. After stripping the filling material, a conductive material, for example, aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy is deposited, by a metallization process such as chemical vapor deposition, physical vapor deposition, sputtering, or the like, in the plurality of bitline trench openings 408 to form a plurality ofbit lines 409 and in the transformedholes 404 to form a plurality ofcapacitor contacts 403. A planarization process, such as chemical mechanical polishing, may be performed after the metallization process to remove excess deposited material and provide a substantially flat surface for subsequent processing steps. - In some embodiments, the
capacitor contact 403 includes a neck portion 403-1 and a head portion 403-2 over the neck portion 403-1, wherein an upper width W1 of the head portion 403-2 is larger than an upper width W2 of the neck portion 403-1. In some embodiments, the upper width W2 of the neck portion 403-1 is substantially the same as a bottom width of the head portion 403-2. In some embodiments, the head portion 403-2 has a curved sidewall 403-3. In some embodiments, the head portion has tapered profile. - With reference to
FIGS. 26 and 27 , the plurality ofbit lines 409 may extend along a direction Y and implemented as wavy lines in a top-view diagram. The plurality ofbit line contacts 405 are located at intersections of the plurality ofbit lines 409 and the plurality ofactive regions 105. The plurality ofbit lines 409 implemented as wavy lines may increase a contact area between the plurality ofbit line contacts 405 and the plurality ofactive regions 105; therefore, a contact resistance between the plurality ofbit line contacts 405 and the plurality ofactive regions 105 may be reduced. - With reference to
FIG. 1 andFIG. 28 , at step S19, a plurality of capacitor plugs are respectively formed over the plurality of capacitor contacts.FIG. 28 illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. With reference toFIG. 1 andFIG. 28 , a plurality of capacitor plugs 411 may be formed above thesubstrate 101. A fourth insulatingfilm 807 may be formed on the thirdinsulating film 805. The fourthinsulating film 807 may be formed of a same material as the material of the first insulatingfilm 801, but is not limited thereto. A photolithography process may be used to pattern the fourth insulatingfilm 807 to define positions of the plurality of capacitor plugs 411. An etch process, such as an anisotropic dry etch process, may be performed after the photolithography process to form a plurality of plug openings passing through the fourth insulatingfilm 807, the thirdinsulating film 805, and the secondinsulating film 803. After the etch process, a conductive material, for example, aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy is deposited, by a metallization process such as chemical vapor deposition, physical vapor deposition, sputtering, or the like, in the plurality of plug openings to form the plurality of capacitor plugs 411 over the head portion 403-2. A planarization process, such as chemical mechanical polishing, may be performed after the metallization process to remove excess deposited material and provide a substantially flat surface for subsequent processing steps. - With reference to
FIG. 1 andFIGS. 29 to 32 , at step S21, a plurality of first spacers are respectively formed over a plurality of protruding portions of the plurality of capacitor plugs.FIG. 29 , illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. With reference toFIG. 1 andFIG. 29 , an etching back process is performed to remove a top portion of the fourth insulatingfilm 807 to expose a protrudingportion 411A of thecapacitor plug 411. In some embodiments, after the etching back process, the top surface of thecapacitor plug 411 is higher than that of the fourth insulatingfilm 807, and the sidewall of the capacitor plug 411 (protrudingportion 411A) is exposed. -
FIG. 30 , illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. In some embodiments, a deposition process is performed to form aliner layer 808, covering the top surface of the fourth insulatingfilm 807, the top surface of the protrudingportion 411A, and the sidewall of the protrudingportion 411A. -
FIG. 31 , illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. In some embodiments, an anisotropic dry etching process is performed to remove a portion of theliner layer 808 so as to form a plurality offirst spacers 808A respectively on the protrudingportion 411A. In some embodiments, thefirst spacer 808A comprises metal silicide and is disposed on a sidewall of the protrudingportion 411A. In some embodiments, the width W4 of thefirst spacer 808A is larger than the width W3 of thecapacitor plug 411. -
FIG. 32 , illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. In some embodiments, a salicidation process is performed to form a plurality ofsecond spacers 808B respectively over thefirst spacers 808A. In some embodiments, thefirst spacer 808A comprises polysilicon and is disposed on a sidewall of the protrudingportion 411A, and thesecond spacer 808B comprises metal silicide from the polysilicon of thefirst spacer 808A. In some embodiments, the protrudingportion 411A, thefirst spacer 808A, and thesecond spacer 808B form alanding pad 810 over thecapacitor contact 403. -
FIG. 33 , illustrates, in a schematic cross-sectional diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. In some embodiments, a fifthinsulating film 814 having aplug 816 may be formed over thelanding pad 810. The fifthinsulating film 814 may be formed of a same material as the material of the first insulatingfilm 801, but is not limited thereto. A photolithography process may be used to pattern the fifth insulatingfilm 814 to define positions of the plurality ofplugs 816. An etch process, such as an anisotropic dry etch process, may be performed after the photolithography process to form a plurality of plug openings passing through the fifth insulatingfilm 814. After the etch process, a conductive material, for example, aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy is deposited, by a metallization process such as chemical vapor deposition, physical vapor deposition, sputtering, or the like, in the plurality of plug openings to form the plurality ofplugs 816 over thelanding pad 810. A planarization process, such as chemical mechanical polishing, may be performed after the metallization process to remove excess deposited material and provide a substantially flat surface for subsequent processing steps. - With reference to
FIG. 1 andFIGS. 34 to 36 , at step S23, a plurality of capacitor structures are formed respectively over the plurality of first spacers of the landing pads.FIGS. 34 to 36 illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.FIG. 37 illustrates, in a schematic top-view diagram, the semiconductor device in accordance withFIG. 36 . - In some embodiments, the plurality of
capacitor structures 501 may include abottom electrode 505, acapacitor insulating layer 507, and atop electrode 509. With reference toFIG. 34 , a fifthinsulating film 809 may be formed on the fourth insulatingfilm 807. The fifthinsulating film 809 may be formed of a same material as the material of the first insulatingfilm 801, but is not limited thereto. A photolithography process may be used to pattern the fifth insulatingfilm 809 to define positions of a plurality ofcapacitor trenches 503. An etch process, such as an anisotropic dry etch process, may be performed after the photolithography process to form the plurality ofcapacitor trenches 503 passing through the fifth insulatingfilm 809. The plurality ofplugs 816 may be exposed through the plurality ofcapacitor trenches 503. - With reference to
FIG. 35 , a plurality ofbottom electrodes 505 may be correspondingly respectively formed in the plurality ofcapacitor trenches 503, in other words, the plurality ofbottom electrodes 505 may be inwardly formed in the fifth insulatingfilm 809. The plurality ofbottom electrodes 505 may be formed of, for example, doped polysilicon, metal silicide, aluminum, copper, or tungsten. The plurality ofbottom electrodes 505 may be respectively correspondingly connected to the plurality ofplugs 816. - With reference to
FIG. 35 , thecapacitor insulating layer 507 may be formed to attach to sidewalls and bottoms of the plurality ofbottom electrodes 505 and the top surfaces of the fifth insulatingfilm 809. Thecapacitor insulating layer 507 may be a single layer or multiple layers. In the embodiment depicted, thecapacitor insulating layer 507 may be a single layer or multiple layers. Specifically, thecapacitor insulating layer 507 may be a single layer formed of a high dielectric constant material such as barium strontium titanate, lead zirconium titanate, titanium oxide, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, or the like. Alternatively, in another embodiment, thecapacitor insulating layer 507 may be multiple layers consisting of silicon oxide, silicon nitride, and silicon oxide. - With reference to
FIGS. 36 and 37 , thetop electrode 509 may be formed to fill the plurality ofcapacitor trenches 503 and cover thecapacitor insulating layer 507. Thetop electrode 509 may be formed of, for example, doped polysilicon, copper, or aluminum. -
FIGS. 38 to 41 illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure. In some embodiments, a bottom via 413 and a firstconductive layer 415 may be formed above thesubstrate 101. With reference toFIG. 38 , a sixthinsulating film 811 may be formed on the fifth insulatingfilm 809. The sixthinsulating film 811 may be formed of a same material as the material of the first insulatingfilm 801, but is not limited thereto. A photolithography process may be used to pattern the sixthinsulating film 811 to define positions of the bottom via 413. An etch process, such as an anisotropic dry etch process, may be performed after the photolithography process to form a bottom via opening passing through the sixthinsulating film 811. After the etch process, a conductive material, for example, aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy is deposited, by a metallization process such as chemical vapor deposition, physical vapor deposition, sputtering, or the like, in the bottom via opening to form the bottom via 413 in the sixthinsulating film 811. A planarization process, such as chemical mechanical polishing, may be performed after the metallization process to remove excess deposited material and provide a substantially flat surface for subsequent processing steps. - With reference to
FIG. 38 , in the embodiment depicted, the bottom via 413 is formed including tungsten. Defects may be easily formed on a top surface of the bottom via 413 formed including tungsten when the top surface of the bottom via 413 is exposed to oxygen or air. The defects may affect the yield of the semiconductor device. - With reference to
FIG. 39 , a seventhinsulating film 813 may be formed on the sixthinsulating film 811. The seventhinsulating film 813 may be formed of a same material as the material of the first insulatingfilm 801, but is not limited thereto. A photolithography process may be used to pattern the seventh insulatingfilm 813 to define a position of the firstconductive layer 415. An etch process, such as an anisotropic dry etch process, may be performed after the photolithography process to form a first conductive layer trench in the seventh insulatingfilm 813. The top surface of the bottom via 413 may be exposed through the first conductive layer trench. A cleaning process using a reducing agent may be optionally performed to remove the defects on the top surface of the bottom via 413 formed including tungsten. The reducing agent may be titanium tetrachloride, tantalum tetrachloride, or combination thereof. - With reference to
FIGS. 39 and 40 , after the cleaning process, asecond coverage layer 417 formed including tungsten nitride may be formed to cover a bottom and sidewalls of the first conductive layer trench. Thesecond coverage layer 417 may prevent the top surface of the bottom via 413 formed including tungsten from being exposed to oxygen or air; therefore, thesecond coverage layer 417 may reduce formation of the defects on the top surface of the bottom via 413 formed including tungsten. A conductive material, for example, aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy is deposited, by a metallization process such as chemical vapor deposition, physical vapor deposition, sputtering, or the like, in the first conductive layer trench to form the firstconductive layer 415. A planarization process, such as chemical mechanical polishing, may be performed after the metallization process to remove excess deposited material and provide a substantially flat surface for subsequent processing steps. -
FIG. 41 illustrates, in a schematic cross-sectional view diagram, a semiconductor device in accordance with one embodiment of the present disclosure. - With reference to
FIG. 41 , a semiconductor device may include asubstrate 101, a plurality ofisolation structures 103, a plurality ofword lines 201, a plurality of doped regions, a plurality of insulating films, a plurality of contacts, a plurality ofbit line contacts 405, afirst coverage layer 407, a plurality ofbit lines 409, a plurality ofplugs 411, a plurality oflanding pads 810, a plurality ofplugs 816, a bottom via 413, a firstconductive layer 415, asecond coverage layer 417, and a plurality ofcapacitor structures 501. - With reference to
FIG. 41 , the plurality ofisolation structures 103 may be disposed in thesubstrate 101 and separated from each other. The plurality ofisolation structures 103 may define a plurality ofactive regions 105. The plurality ofword lines 201 may be disposed in thesubstrate 101 and separated from each other. - Each one of the plurality of
word lines 201 includes abottom layer 203, amiddle layer 205, and atop layer 207. The plurality ofbottom layers 203 may be respectively inwardly disposed in thesubstrate 101. The plurality ofmiddle layers 205 may be respectively correspondingly disposed on the plurality of bottom layers 203. Top surfaces of the plurality ofmiddle layers 205 may be lower than a top surface of thesubstrate 101. The plurality oftop layers 207 may be respectively correspondingly disposed on the plurality ofmiddle layers 205. Top surfaces of the plurality oftop layers 207 may be at the same vertical level as the top surface of thesubstrate 101. - With reference to
FIG. 41 , a plurality of doped regions may be disposed in the plurality ofactive regions 105 of thesubstrate 101. Each of the plurality of doped regions includes a firstdoped region 301 and seconddoped regions 303. For each of the plurality of doped regions, the firstdoped region 301 is disposed between an adjacent pair of the plurality of word lines 201. The seconddoped regions 303 are respectively disposed between the plurality ofisolation structures 103 and the plurality of word lines 201. - With reference to
FIG. 41 , the plurality of insulating films may be disposed above thesubstrate 101. The plurality of insulating films may include a firstinsulating film 801, a secondinsulating film 803, a thirdinsulating film 805, a fourthinsulating film 807, a fifthinsulating film 809, a sixthinsulating film 811, and a seventhinsulating film 813. The firstinsulating film 801 may be disposed on thesubstrate 101. The plurality of contacts may be disposed in the first insulatingfilm 801. The plurality of contacts may include acontact 401 andcapacitor contacts 403. Thecontact 401 is disposed on the firstdoped region 301 and is electrically connected to the firstdoped region 301. Thecapacitor contacts 403 are respectively disposed on the seconddoped regions 303 and are respectively electrically connected to the seconddoped regions 303. In the embodiment depicted, thecontact 401 is formed including tungsten. - With reference to
FIG. 41 , the secondinsulating film 803 may be disposed on the first insulatingfilm 801. The plurality ofbit line contacts 405 may be disposed in the secondinsulating film 803. (Only bit line contact is shown inFIG. 41 .) Thefirst coverage layer 407 may be disposed in the secondinsulating film 803 and on a top surface of thecontact 401; in other words, thefirst coverage layer 407 may be disposed between the plurality ofbit line contacts 405 and thecontact 401. In addition, thefirst coverage layer 407 may be disposed on and attached to sidewalls of the plurality ofbit line contacts 405. Thefirst coverage layer 407 may include tungsten nitride. - With reference to
FIG. 41 , the thirdinsulating film 805 may be disposed on the secondinsulating film 803. The plurality ofbit lines 409 may be disposed in the thirdinsulating film 805 and on the plurality ofbit line contacts 405 and thefirst coverage layer 407. (Only onebit line 409 is shown inFIG. 41 .) The fourthinsulating film 807 may be disposed on the thirdinsulating film 805. The plurality ofplugs 411 may be disposed to pass through the fourth insulatingfilm 807, the thirdinsulating film 805, and the secondinsulating film 803. The plurality ofplugs 411 may be respectively correspondingly electrically connected to thecapacitor contacts 403. - With reference to
FIG. 41 , thecapacitor contact 403 includes a neck portion 403-1 and a head portion 403-2 over the neck portion 403-1, wherein an upper width W1 of the head portion 403-2 is larger than an upper width W2 of the neck portion 403-1. In some embodiments, the upper width W2 of the neck portion 403-1 is substantially the same as a bottom width of the head portion 403-2. In some embodiments, the head portion 403-2 has a curved sidewall 403-3. In some embodiments, the head portion has tapered profile. - With reference to
FIG. 41 , in some embodiments, a plurality offirst spacers 808A are respectively disposed on the protrudingportion 411A of theplugs 411. In some embodiments, thefirst spacer 808A comprises metal silicide and is disposed on a sidewall of the protrudingportion 411A. In some embodiments, the width W4 of thefirst spacer 808A is larger than the width W3 of thecapacitor plug 411. In some embodiments, a plurality ofsecond spacers 808B are respectively disposed over thefirst spacers 808A. In some embodiments, thefirst spacer 808A comprises polysilicon and is disposed on a sidewall of the protrudingportion 411A, and thesecond spacer 808B comprises metal silicide from the polysilicon of thefirst spacer 808A. In some embodiments, the protrudingportion 411A, thefirst spacer 808A, and thesecond spacer 808B form alanding pad 810 over thecapacitor contact 403. - With reference to
FIG. 41 , the fifth insulatingfilm 809 may be disposed on the fourth insulatingfilm 807. The plurality ofcapacitor structures 501 may be disposed in the fifth insulatingfilm 809. The plurality ofcapacitor structures 501 may include a plurality ofbottom electrodes 505, acapacitor insulating layer 507, and atop electrode 509. The plurality ofbottom electrodes 505 may be inwardly disposed in the fifth insulatingfilm 809 and respectively correspondingly electrically connected to the plurality ofplugs 816. Thecapacitor insulating layer 507 may be disposed on the plurality ofbottom electrodes 505. Thetop electrode 509 may be disposed on thecapacitor insulating layer 507. - With reference to
FIG. 41 , the sixthinsulating film 811 may be disposed on the fifth insulatingfilm 809. The bottom via 413 may be disposed in the sixthinsulating film 811 and electrically connected to thetop electrode 509. The bottom via 413 may include tungsten. A seventh insulatingfilm 813 may be disposed on the sixthinsulating film 811. The firstconductive layer 415 may be disposed in the seventh insulatingfilm 813 and above the bottom via 413. Thesecond coverage layer 417 may be disposed on a top surface of the bottom via 413, and thesecond coverage layer 417 may be disposed between the bottom via 413 and the firstconductive layer 415. In addition, thesecond coverage layer 417 may be disposed on and attached to sidewalls of the firstconductive layer 415. Thesecond coverage layer 417 may include tungsten nitride. -
FIGS. 42 and 43 illustrate, in schematic cross-sectional view diagrams, some semiconductor devices in accordance with some embodiments of the present disclosure. - With reference to
FIG. 42 , the semiconductor device may include a plurality of third coverage layers 419. The plurality of third coverage layers 419 may be respectively correspondingly disposed between thecapacitor contacts 403 and the plurality ofplugs 411. In other words, the plurality of third coverage layers 419 may be respectively correspondingly disposed on top surfaces of thecapacitor contacts 403 formed including tungsten. The plurality of third coverage layers 419 may be respectively correspondingly disposed on and attached to sidewalls of the plurality ofplugs 411. The plurality of third coverage layers 419 may include tungsten nitride. In the present embodiment, only thefirst coverage layer 407, thesecond coverage layer 417, and the plurality of third coverage layers 419 are disposed on thecontact 401, the bottom via 413, and thecapacitor contacts 403, respectively; however, other conductive layers or vias may also applicable. - Note that, in the present embodiment, a coverage layer may be regarded as the
first coverage layer 407, thesecond coverage layer 417, or thethird coverage layer 419, but is not limited thereto. A conductive feature may be regarded as thecontact 401, thesecond contact 403, or the bottom via 413, but is not limited thereto. - With reference to
FIG. 43 , the semiconductor device may include afirst barrier layer 421. Thefirst barrier layer 421 may be disposed between thefirst coverage layer 407 and the plurality ofbit line contacts 405. Thefirst barrier layer 421 may be formed of, for example, titanium, titanium nitride, titanium-tungsten alloy, tantalum, tantalum nitride, or the combination thereof. Thefirst barrier layer 421 may improve adhesion between thefirst coverage layer 407 and the plurality ofbit line contacts 405. In some embodiments, thefirst barrier layer 421 may also be implemented between theconductive contacts 401 and the first insulatingfilm 801. - One aspect of the present disclosure provides a semiconductor device having a substrate including a plurality of doped regions; a plurality of silicide pads disposed respectively over the plurality of doped regions; and a plurality of conductive contacts disposed respectively over the plurality of silicide pads; wherein the plurality of conductive contacts comprise a plurality of nanowires, a conductive liner disposed over the plurality of nanowires, and a conductor disposed over the conductive liner.
- Another aspect of the present disclosure provides a method for fabricating a semiconductor device comprising: providing a substrate including a plurality of doped regions; forming a plurality of silicide pads respectively over the plurality of doped regions; and forming a plurality of conductive contacts respectively over the plurality of silicide pads; wherein the plurality of conductive contacts comprise a plurality of nanowires, a conductive liner over the plurality of nanowires, and a conductor over the conductive liner.
- The high aspect ratio conductive contact is implemented by the nanowires to electrically connect the source/drain regions in the substrate and the capacitor structures over the source/drain regions. In addition, the high aspect ratio conductive contact is implemented by the nanowires to electrically connect the source/drain regions in the substrate and the bit line.
- Furthermore, the landing pad has the first spacer, wherein a width of the first spacer is larger than a width of the capacitor plug, the misalignment between the subsequently formed capacitor structure and the landing pad can be dramatically solved, wherein a width of the first spacer is larger than a width of the capacitor plug.
- In addition, due to the capacitor contact having the neck portion and the head portion with a tapered profile, the misalignment between the subsequently formed capacitor structure and the capacitor contact can be dramatically solved. In addition, the coverage layer may reduce formation of defects in the semiconductor device; therefore, the yield of the semiconductor device increases correspondingly.
- Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.
- Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, and steps.
Claims (20)
1. A semiconductor device, comprising:
a substrate including a plurality of doped regions;
a plurality of silicide pads disposed respectively over the plurality of doped regions; and
a plurality of conductive contacts disposed respectively over the plurality of silicide pads;
wherein the plurality of conductive contacts comprise a plurality of nanowires, a conductive liner disposed over the plurality of nanowires, and a conductor disposed over the conductive liner.
2. The semiconductor device of claim 1 , further comprising a bit line disposed over one of the plurality of conductive contacts, and bit line is an undulating strip.
3. The semiconductor device of claim 1 , further comprising a plurality of capacitor contacts disposed over the substrate, at least one of the plurality of capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion.
4. The semiconductor device of claim 3 , wherein the upper width of the head portion is larger than a bottom width of the head portion, and the head portion has a curved sidewall.
5. The semiconductor device of claim 3 , wherein the upper width of the neck portion is substantially the same as a bottom width of the head portion, and the head portion has tapered profile.
6. The semiconductor device of claim 1 , further comprising a capacitor structure disposed over one of the plurality of conductive contacts.
7. The semiconductor device of claim 3 , further comprising a plurality of landing pads disposed respectively over the plurality of head portions, at least one of the plurality of landing pads comprising a protruding portion of the capacitor plug and a first spacer over the protruding portion, wherein a width of the first spacer is larger than a width of the capacitor plug.
8. The semiconductor device of claim 7 , wherein the first spacer comprises metal silicide and is disposed on a sidewall of the protruding portion.
9. The semiconductor device of claim 7 , wherein the first spacer comprises polysilicon and is disposed on a sidewall of the protruding portion.
10. The semiconductor device of claim 9 , further comprising a second spacer disposed over the first spacer, and the second spacer comprises metal silicide.
11. A method for fabricating a semiconductor device, comprising:
providing a substrate including a plurality of doped regions;
forming a plurality of silicide pads respectively over the plurality of doped regions; and
forming a plurality of conductive contacts respectively over the plurality of silicide pads;
wherein the plurality of conductive contacts comprise a plurality of nanowires, a conductive liner over the plurality of nanowires, and a conductor over the conductive liner.
12. The method for fabricating a semiconductor device of claim 11 , further comprising: forming a plurality of capacitor contacts over the substrate, at least one of the plurality of capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion.
13. The method for fabricating the semiconductor device of claim 11 , wherein forming a plurality of capacitor contacts comprises:
forming a contact hole in a dielectric stack having a first layer and a second layer over the first layer;
removing a portion of the second layer around the contact hole to form a transformed hole having a narrow portion in the first layer and a wide portion in the second layer; and
filling a conductive material into the transformed hole.
14. The method for fabricating the semiconductor device of claim 13 , wherein the contact hole is formed integrally with a bit line trench in the second layer.
15. The method for fabricating the semiconductor device of claim 14 , further comprising:
filling the bit line trench and a lower portion of the contact hole with a filling material.
16. The method for fabricating the semiconductor device of claim 15 , wherein removing a portion of the second layer around the contact hole is performed after filling the lower portion of the contact hole with a sacrificial material.
17. The method for fabricating a semiconductor device of claim 11 , further comprising: forming a plurality of landing pads respectively over the plurality of head portions, at least one of the plurality of landing pads comprising a protruding portion of the capacitor plug and a first spacer over the protruding portion, wherein a width of the first spacer is larger than a width of the capacitor plug.
18. The method for fabricating a semiconductor device of claim 17 , wherein the first spacer comprises metal silicide and is formed on a sidewall of the protruding portion.
19. The method for fabricating a semiconductor device of claim 17 , wherein the first spacer comprises polysilicon and is on a sidewall of the protruding portion.
20. The method for fabricating a semiconductor device of claim 19 , further comprising: forming a plurality of second spacers respectively over the plurality of first spacers, wherein the second spacer comprises metal silicide.
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