JP2013143485A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including a capacitor element having a structure which is easy to ensure conductive connection with a capacitive contact plug even when a capacitive contact pad causes overlay shift.SOLUTION: A semiconductor device includes a structure in which a capacitive contact plug and an electrode of a capacitor are conductively connected via capacitive contact pads. In the structure, a conductively connected part of the capacitive contact plug with the capacitive contact pad has an increased diameter in comparison with other sites of the capacitive contact plug.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a capacitor element of a memory cell and a manufacturing method thereof.

  With the progress of miniaturization of semiconductor devices, the area of a memory cell part constituting a DRAM (Dynamic Random Access Memory) element is being reduced. As the capacitor element disposed in the memory cell portion, generally, a three-dimensional capacitor element is used so that sufficient capacitance can be secured even if the area of the memory cell portion is reduced. Specifically, the lower electrode of the capacitor element is a crown type (crown type) or pillar (pedestal) type (column type), and the wall surface of the lower electrode is used as a capacitor element, thereby increasing the surface area and reducing the surface area. The electric capacity can be secured.

  In a COB (Capacitor Over Bitline) structure of a DRAM using a capacitor stacked in a cylinder shape above a semiconductor substrate, that is, a so-called stack type capacitor, a structure having a high aspect ratio is also formed in order to secure a capacitor capacity. There is a limit. Therefore, for example, in Patent Document 1, a contact pad is formed thick, and a capacitor cylinder (lower electrode) is formed thereon, whereby the side surface of the contact pad is also used as a capacitor lower electrode to increase the capacitance.

  In Patent Document 2, a semiconductor having a capacitor contact plug penetrating a lower interlayer insulating film and a capacitor contact pad connected to a transistor through the capacitor contact plug, and a lower electrode provided on the capacitor contact pad An apparatus is disclosed.

JP 2004-311918 A JP 2011-228338 A

  As the memory cell size of the DRAM becomes smaller, the overlap margin between the contact hole and the wiring also becomes smaller, and the contact hole and the wiring may be disconnected, which may cause a problem of contact failure.

  For example, in a semiconductor device having a structure as disclosed in Patent Document 2, when a displacement of a capacitor contact metal (plug) occurs during exposure of a capacitor contact pad, the capacitor contact pad metal and the capacitor contact metal (plug) are There may be a problem in that the contact area between the capacitor contact pad metal and the capacitor contact metal (plug) becomes very small and high resistance due to disconnection without being connected and disconnection.

  In view of the above, a semiconductor device including a capacitor element having a structure that facilitates ensuring a conductive connection with a capacitor contact plug even when the capacitor contact pads are overlaid is desired.

  In the first aspect, the following semiconductor device is provided. That is, a semiconductor device including a capacitor having a structure in which a capacitive contact plug and a capacitor electrode are conductively connected via a capacitive contact pad, wherein the conductive contact portion of the capacitive contact plug and the capacitive contact pad is other There is provided a semiconductor device having a structure in which the diameter is increased as compared with this part.

  According to a second aspect, there is provided a method of forming a capacitor having a structure in which a capacitor contact plug and a capacitor electrode are electrically connected via a capacitor contact pad, the step of forming a capacitor contact hole in an insulating film, Forming a sidewall film on the inner surface of the capacitor contact hole and then filling the capacitor contact hole with polysilicon; etching back the upper surface of the insulating film and the sidewall film; and exposing the upper portion of the polysilicon; Forming a polysilicon sidewall or polysilicon selective epitaxial growth film on the exposed polysilicon; and a capacitor contact pad to cover at least a part of the sidewall or polysilicon selective epitaxial growth film Forming the method.

As Example 1, (A) It is sectional drawing which deposited doped polysilicon as a capacity | capacitance contact plug, and performed CMP. (B) Next, it is a cross-sectional view of the interlayer oxide film and the sidewall nitride film of the capacitor contact plug etched back. (C) Next, polysilicon is selectively epitaxially grown on the upper portion of the capacitor contact plug to form a diameter-increased portion. (D) Next, a barrier metal and tungsten are deposited, and a photoresist for forming a capacitor contact pad is patterned. FIG. 2D is a cross-sectional view after forming a capacitive contact pad by dry etching the barrier metal and tungsten after FIG. As Example 2, (A) It is sectional drawing which grew the doped polysilicon on the capacity | capacitance contact plug after FIG. 1 (B). FIG. 4B is a cross-sectional view in which doped polysilicon is etched back to form polysilicon sidewalls on the capacitor contact plugs. (C) It is sectional drawing which deposited the barrier metal and the tungsten deposit, and also patterned the photoresist for capacitive contact pad formation. FIG. 4 is a cross-sectional view after forming a capacitive contact pad by dry etching the barrier metal and tungsten after FIG.

Form 1: As described in the first aspect.
Form 2: As described in the second viewpoint.
In the first aspect, it is preferable that the conductive contact portion of the capacitive contact plug with the capacitive contact pad is increased in diameter by a sidewall structure.

  Further, it is preferable that the conductive connection portion of the capacitive contact plug with the capacitive contact pad is increased in diameter by selective epitaxial growth.

  Moreover, it is preferable that the increased diameter portion of the capacitive contact plug with the capacitive contact pad is made of polysilicon.

  Further, it is preferable that the increased diameter portion of the capacitive contact plug is doped with arsenic.

  Moreover, it is preferable that a barrier metal is formed at the increased diameter portion of the capacitive contact plug and is electrically connected to the capacitive contact pad via the barrier metal.

  Further, it is preferable that the side surface portion of the increased diameter portion of the capacitive contact plug is electrically connected to the capacitive contact pad.

  Moreover, it is preferable that the said diameter increase is a diameter increase of 20-100 nm.

  In the second aspect, it is preferable that the method further includes a step of doping arsenic into the polysilicon sidewall or the polysilicon selective epitaxial growth film. Hereinafter, each example will be described in detail as an example in the present disclosure.

Example 1
FIG. 2 shows a connection structure of the capacitor contact plug and the capacitor contact pad according to the first embodiment of the present invention, which is not disconnected even when the displacement of the capacitor contact pad occurs and is less likely to be non-conductive. Unlike the structure of the prior art, after the top (upper) diameter of the capacitor contact plug is enlarged, the capacitor contact metal pad and the capacitor contact plug have side wall contacts so that they are not affected by the displacement of the capacitor contact pads. Yes.

  The manufacturing method of this structure is shown below. In FIG. 1A, an opening (contact hole) is formed by dry etching in an interlayer oxide film (insulating layer), and doped polysilicon is deposited as a capacitor contact sidewall nitride film 5a and a capacitor contact plug 5b. Then, a cross-sectional view after performing CMP is shown. Reference numeral 1 denotes STI (Shallow Trench Isolation, trench isolation oxide film), reference numeral 2 denotes a recess gate, reference numeral 3 denotes a bit contact plug (for example, W / TiN), and reference numeral 4 denotes a bit line.

FIG. 1B shows a cross-sectional view after etching back the interlayer oxide film and the capacitor contact sidewall nitride film 5a. The interlayer oxide film is etched by about 50 nm by dry etching with CF ₄ gas, and the capacitor contact sidewall nitride film 5a is etched back with phosphoric acid solution, thereby protruding the capacitor contact plug 5b by about 50 nm.

FIG. 1C shows a cross-sectional view after selective epitaxial growth of silicon on the upper portion (top portion) of the capacitor contact plug 5b. By the selective epitaxial growth layer 5e using Si ₂ H ₆ gas, the top diameter of the capacitive contact plug can be increased by about 30 nm on one side. As a result, the contact area with the side wall of the capacitor contact can be increased. In addition, it is preferable that the degree of expansion (increasing diameter) is about 10 nm to 50 nm on one side. Therefore, it is preferable to increase the diameter by about 20 to 100 nm as a whole.

  Further, after the selective epitaxial growth layer 5e of the capacitor contact plug 5b is grown, arsenic implantation (for example, implantation at a depth of about 30 nm by oblique implantation at As: 50 KeV (arsenic implantation into the plug top epitaxial growth portion 30 nm) is performed. )). The surface of the capacitive contact plug protruding about 50 nm by this arsenic implantation becomes amorphous, so that the subsequent CoSi reaction of the barrier metal is promoted, and the contact resistance of the barrier metal (TiN / Ti / CoSi) / poly on the side surface is reduced. it can.

  FIG. 1D shows a cross-sectional view after forming the capacitor contact barrier metal 5c and the tungsten (W) layer 5d for the capacitor contact pad and patterning the photoresist 9 for forming the capacitor contact pad. A capacitor contact barrier metal (TiN / Ti / CoSi) 5c and a tungsten layer 5d are formed, and then a photoresist 9 is applied and patterned.

FIG. 2 shows a cross-sectional view of the capacitor contact barrier metal 5c and the tungsten (W) layer 5d after dry etching. The capacitor contact pad 6 is formed by W dry etching using a mixed gas of Cl ₂ gas and SF ₆ gas, and a sidewall contact structure having a larger contact area between the capacitor contact plug 5b and the capacitor contact (metal) pad 6 can be formed. .

  As described above, even if an overlay shift occurs during exposure of the capacitor contact pad, the contact contact between the capacitor contact pad and the capacitor contact plug does not occur due to the sidewall contact structure with the capacitor contact plug having an enlarged capacitor contact top diameter. Prevention can be improved.

  The structure shown in Example 1 provides the following effects. First, even if an overlay error occurs during exposure of the capacitor contact pad, the sidewall contact structure prevents disconnection between the capacitor contact pad and the capacitor contact plug, thereby preventing non-conduction. Second, the contact area between the capacitor contact metal pad and the side surface of the capacitor contact plug can be secured by protruding the capacitor contact polyplug by about 50 nm. Third, by implanting arsenic on the capacitor contact plug, the surface of the capacitor contact plug becomes amorphous, and the CoSi reaction of the barrier metal to be formed later is promoted, and the barrier metal (TiN / CoSi) / The contact resistance of polysilicon can be reduced. Fourth, by enlarging the top diameter of the capacitive contact plug protruding about 50 nm, it is possible to increase the contact area of the side surface of the polysilicon plug that makes the side wall contact, and to reduce the resistance.

(Example 2)
FIG. 4 shows a structure according to the second embodiment of the present invention in which disconnection does not occur even when the displacement of the capacitor contact pads occurs, and non-conduction is unlikely to occur. Unlike the first embodiment, a polysilicon side wall is formed to enlarge the capacitor contact plug top diameter.

  The manufacturing method of the structure of Example 2 is shown below. The processes up to the interlayer oxide film and the capacitor contact sidewall nitride film etch-back in FIG.

FIG. 3A shows a cross-sectional view in which doped polysilicon is grown on the entire surface including the upper portion of the capacitor contact plug. A doped polysilicon film 5f is formed on the capacitive contact plug by about 30 nm using PH ₃ gas and SiH ₄ gas.

  FIG. 3B shows a cross-sectional view in which the sidewall structure 5g is formed by etching back the polysilicon in the capacitor contact plug top portion. A polysilicon sidewall structure 5g on the capacitor contact plug top is formed by polysilicon etch-back using HBr gas. Thereby, the top diameter can be enlarged by about 30 nm on one side. As a result, the contact area with the side wall of the capacitor contact can be increased.

  After the formation of the polysilicon side wall structure 5g of the capacitor contact plug top, arsenic implantation (for example, implantation at a depth of about 30 nm is performed by implanting at an angle of As: 50 KeV (the polysilicon sidewall of the plug top). Arsenic implantation is also applied to the portion 30 nm)). The surface of the capacitor contact plug protruding about 50 nm by this arsenic implantation becomes amorphous, so that the subsequent CoSi reaction of the barrier metal is promoted, and the contact resistance of the barrier metal (TiN / Ti / CoSi) / polysilicon on the side surface is increased. Can be reduced.

  FIG. 3C shows a cross-sectional view after patterning of the photoresist 9 for forming the capacitor contact barrier metal 5c and tungsten (W) and forming the capacitor contact pad. A capacitor contact barrier metal (TiN / Ti / CoSi) 5c and a tungsten layer 5d are formed, and then a photoresist 9 is applied and patterned.

FIG. 4 shows a cross-sectional view after dry etching of the tungsten layer 5d and the capacitor contact barrier metal 5c. The capacitor contact pad 6 is formed by tungsten dry etching using a mixed gas of Cl ₂ gas and SF ₆ gas, and a sidewall contact structure with a larger contact area between the capacitor contact plug 5b and the capacitor contact pad 6 can be formed.

  As described above, even if an overlay shift occurs during the exposure of the capacitor contact pad, the capacitor contact pad 6 and the capacitor contact plug 5b are not disconnected because the side wall contact structure is formed by the capacitor contact top diameter enlarged plug, thereby preventing non-conduction. It becomes possible to improve. In the structure shown in the second embodiment, the same effect as in the first embodiment can be obtained.

  Within the scope of the entire disclosure (including claims and drawings) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Further, various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) are possible within the scope of the claims of the present invention. It is. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1 STI
2 Recess gate 3 Bit contact plug 4 Bit line 5a Capacitor contact sidewall nitride film 5b Capacitor contact plug 5c Capacitor contact barrier metal 5d Tungsten layer (capacitor contact pad)
5e selective epitaxial growth layer 5f doped polysilicon film 5g sidewall structure 6 capacitive contact (metal) pad 9 photoresist

Claims (10)

A semiconductor device including a capacitor having a structure in which a capacitor contact plug and a capacitor electrode are conductively connected via a capacitor contact pad,
A semiconductor device characterized in that a conductive connection portion of the capacitive contact plug with the capacitive contact pad has a structure in which the diameter is increased as compared with other portions of the capacitive contact plug.   2. The semiconductor device according to claim 1, wherein the conductive contact portion of the capacitive contact plug with the capacitive contact pad has a diameter increased by a sidewall structure.   2. The semiconductor device according to claim 1, wherein the conductive contact portion of the capacitive contact plug with the capacitive contact pad is increased in diameter by selective epitaxial growth.   The semiconductor device according to claim 1, wherein the increased diameter portion of the capacitor contact plug with the capacitor contact pad is made of polysilicon.   The semiconductor device according to claim 1, wherein the increased diameter portion of the capacitive contact plug is doped with arsenic.   The barrier metal is formed at the increased diameter portion of the capacitor contact plug, and is electrically connected to the capacitor contact pad through the barrier metal. Semiconductor device.   The semiconductor device according to claim 1, wherein the side surface portion of the increased diameter portion of the capacitive contact plug is electrically connected to the capacitive contact pad.   The semiconductor device according to claim 1, wherein the increased diameter is an increased diameter of 20 to 100 nm. A method of forming a capacitor having a structure in which a capacitor contact plug and a capacitor electrode are conductively connected via a capacitor contact pad,
Forming a capacitor contact hole in the insulating film;
Filling the capacitor contact hole with polysilicon after forming a sidewall film on the inner surface of the capacitor contact hole;
Etching the upper surface of the insulating film and the sidewall film to expose the upper part of the polysilicon; and
Forming a polysilicon sidewall or a polysilicon selective epitaxial growth film on the exposed polysilicon; and
Forming a capacitor contact pad so as to cover at least part of the sidewall or the selective epitaxial growth film of polysilicon;
A method of forming a capacitor, comprising:   10. The method of forming a capacitor according to claim 9, further comprising a step of arsenic doping the polysilicon sidewall or the polysilicon selective epitaxial growth film.

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