JP2013175584A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve yield by stably separating a pair of adjacent capacitive contact plugs and to suppress the occurrence of junction leakage.SOLUTION: A method of manufacturing a semiconductor device comprises the steps of: forming element isolation regions (STI) 12a and 12b in a semiconductor substrate 11; forming word lines WL10a to WL10d in active regions 13a and 13b surrounded by the element isolation regions 12a and 12b; forming capacitive contact regions 27a to 27d between the element isolation regions 12a and 12b and the word lines WL10a to WL10d; forming, by etching, capacitive contact holes in the capacitive contact regions 27a to 27d using a plurality kinds of capacitive contact masks 29a to 29c, 31a, and 31b; forming capacitive contact plugs 27e to 27h in the capacitive contact holes; and forming a capacitor on the capacitive contact plugs 27e to 27h.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, the trend toward higher density and higher density in the field of semiconductor devices, particularly semiconductor memory devices, has been accelerated. As a pattern formation method of a contact (for example, a capacitor contact) suitable for such a high-density semiconductor device, there is, for example, Japanese Patent Application Laid-Open No. 2011-243960 (Patent Document 1).

  Patent Document 1 discloses a technique for etching a buried layer using a sidewall as a mask. However, in this method, when the semiconductor element is further miniaturized, the capacitor contact is embedded in the side wall (for example, silicon nitride film), and a pair of adjacent capacitors are etched at the time of etch back of the embedded layer (for example, polysilicon). There is a problem that contact plugs cannot be separated well and the yield is lowered. Further, since the capacitor contact plug is separated by polysilicon etch-back, there is a problem that the semiconductor substrate is etched during over-etching, resulting in junction leakage.

JP 2011-243960 A

  The present invention solves the above-mentioned problems of the prior art, and its purpose is to improve the yield by stably separating a pair of adjacent capacitor contact plugs and to suppress the occurrence of junction leakage. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of performing the above.

A method for manufacturing a semiconductor device according to one embodiment of the present invention includes:
Forming an element isolation region in a semiconductor substrate;
Forming a gate electrode constituting a word line in an active region surrounded by the element isolation region;
Forming a capacitor contact region between the element isolation region and the gate electrode;
Using a plurality of types of capacitor contact masks, a capacitor contact hole is formed by etching in the capacitor contact region,
Forming a capacitor contact plug in the capacitor contact hole;
A capacitor is formed on the capacitor contact plug.

  According to the present invention, it is possible to improve the yield and suppress the occurrence of junction leakage by stably separating a pair of adjacent capacitor contact plugs.

It is a top view which shows the structure of the semiconductor device by embodiment of this invention. (A) is BB sectional drawing of FIG. 1, (b) is AA sectional drawing of FIG. 2A and 2B are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention, in which FIG. 1A is a cross-sectional view taken along the line BB in FIG. 2A and 2B are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention, in which FIG. 1A is a cross-sectional view taken along the line BB in FIG. 2A and 2B are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention, in which FIG. 1A is a cross-sectional view taken along the line BB in FIG. 2A and 2B are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention, in which FIG. 1A is a cross-sectional view taken along the line BB in FIG. 2A and 2B are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention, in which FIG. 1A is a cross-sectional view taken along the line BB in FIG. 2A and 2B are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention, in which FIG. 1A is a cross-sectional view taken along the line BB in FIG. 2A and 2B are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention, in which FIG. 1A is a cross-sectional view taken along line BB in FIG. 1, and FIG. 2A and 2B are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention, in which FIG. 1A is a cross-sectional view taken along line BB in FIG. 1, and FIG. 2A and 2B are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention, in which FIG. 1A is a cross-sectional view taken along the line BB in FIG. 2A and 2B are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention, in which FIG. 1A is a cross-sectional view taken along the line BB in FIG. It is a top view which shows the structure of the semiconductor device by related technology. (A) is BB sectional drawing of FIG. 13, (b) is AA sectional drawing of FIG.

  First, a semiconductor device according to related art will be described so that the features of the present invention become clearer.

(Related technology)
13 to 14 are diagrams showing the structure of the semiconductor device 100 according to the related art.

  The semiconductor device 100 is a DRAM, and FIG. 13 is a plan view of a memory cell. 14A and 14B show the structure at the time when the formation of the capacitor is finished. FIG. 14A is a cross-sectional view taken along the line BB in FIG. 13, and FIG.

  First, a related art semiconductor device 100 will be described with reference to FIG.

  The semiconductor device 100 constitutes a DRAM memory cell. Similar to the first element isolation region (STI) 12a extending continuously in the X ″ direction and the second element isolation region (STI) 12b extending continuously in the X ′ direction on the semiconductor substrate 11. A plurality of first active regions 13a extending continuously in the X ″ direction and a plurality of second active regions 13b extending continuously in the X ′ direction are alternately arranged at equal intervals and at equal pitches in the Y direction. .

  The element isolation region 12 is composed of an element isolation insulating film embedded in the trench. A first embedded word line (hereinafter referred to as a first buried word line) extending continuously in the Y direction across the plurality of first element isolation regions 12a and the plurality of first active regions 13a extending continuously in the X ″ direction. A word line WL10a and a second buried word line (hereinafter referred to as a second word line) WL10b are arranged. Similarly, a third buried word line (hereinafter referred to as a first embedded word line) extending continuously in the Y direction across the plurality of second element isolation regions 12b and the plurality of second active regions 13b extending continuously in the X ′ direction. WL10c and a fourth embedded word line (hereinafter referred to as a fourth word line) WL10d are arranged.

  The first active region 13a includes a first capacitor contact region 27a disposed at the left end of the first active region 13a, a first word line WL10a disposed adjacent to the first capacitor contact region 27a, and a first word line First bit line contact region 22a disposed adjacent to WL10a, second word line WL10b disposed adjacent to first bit line contact region 22a, and disposed adjacent to second word line WL10b The second capacitor contact region 27b is formed.

  The first capacitor contact region 27a, the first word line WL10a, and the first bit line contact region 22a constitute a first transistor Tr1, and the first bit line contact region 22a, the second word line WL10b, A second transistor Tr2 is configured with the capacitor contact region 27b.

  Similarly, the second active region 13b includes a third capacitor contact region 27c disposed at the left end of the second active region 13b, a third word line WL10c disposed adjacent to the third capacitor contact region 27c, and the second A second bit line contact region 22b disposed adjacent to the third word line 10c, a fourth word line WL10d disposed adjacent to the second bit line contact region 22b, and a fourth word line WL10d. The fourth capacitor contact region 27d is arranged.

  The third capacitor contact region 27c, the third word line WL10c, and the second bit line contact region 22b constitute a third transistor Tr3, the second bit line contact region 22b, the fourth word line WL10d, and the fourth A fourth transistor Tr4 is configured by the capacitor contact region 27d.

  The memory cell of the related art is configured by arranging a plurality of configurations of the first active region 13 a and the second active region 13 b in the X direction via the element isolation region 12.

  Next, referring to FIGS. 14A and 14B, the semiconductor substrate 11 is provided with a word line groove 14 which also serves as a gate electrode of a transistor. The first word line WL10a, the second word line WL10b, the third word line WL10c, and the fourth word line WL10d are located at the bottom of each groove via the gate insulating film 6 covering the inner surface of each word line groove 14. Is provided. A cap insulating film 17 is provided so as to cover each word line and bury each groove 14.

  The semiconductor pillar located on the left side of the first word line WL10a becomes the first capacitor contact region 27a, and the impurity diffusion layer 19a serving as one of the source / drain is provided on the upper surface thereof. The semiconductor pillar located between the first word line WL10a and the second word line WL10b becomes the first BL contact region 22a, and an impurity diffusion layer 18a serving as the other one of the source / drain is provided on the upper surface thereof. The semiconductor pillar located on the right side of the second word line WL10b becomes the second capacitor contact region 22b, and an impurity diffusion layer 19b serving as one of the source / drain is provided on the upper surface thereof. Further, the semiconductor pillar located on the left side of the third word line WL10c becomes the third capacitor contact region 27c, and an impurity diffusion layer 19c serving as one of source / drain is provided on the upper surface thereof.

  The semiconductor pillar located between the third word line WL10c and the fourth word line WL10d becomes the second bit line contact region 22b, and an impurity diffusion layer 18b serving as the other one of the source / drain is provided on the upper surface thereof. It has been. Further, the semiconductor pillar located on the right side of the fourth word line WL10b becomes the fourth capacitor contact region 27d, and the impurity diffusion layer 19d serving as one of the source / drain is provided on the upper surface thereof.

  The impurity diffusion layer 19a, the gate insulating film 6, the first word line WL10a, and the impurity diffusion layer 18a constitute a first transistor Tr1. The impurity diffusion layer 18a, the gate insulating film 6, the second word line WL10b, and the impurity diffusion layer 19b constitute the second transistor Tr2. Further, the impurity diffusion layer 19c, the gate insulating film 6, the third word line WL10c, and the impurity diffusion layer 18b constitute a third transistor Tr3. The impurity diffusion layer 19d, the gate insulating film 6, the fourth word line WL10d, and the impurity diffusion layer 18b constitute a fourth transistor Tr4.

  A cap insulating film 17 is provided so as to cover the upper surface of each word line. On the cap insulating film 17, a first bit line (BL) 23a connected to the first impurity diffusion layer 18a in the first BL contact region 22a is provided. A cover insulating film 23d is provided on the upper surface of the first bit line (BL) 23a. A liner insulating film 24 is provided on the entire surface so as to cover the side wall of the first bit line (BL) 23a. On the liner insulating film 24, a buried insulating film is provided to bury a recessed space formed between adjacent BLs. A cap silicon oxide film is provided on the buried insulating film.

  A capacitor contact hole is provided through the buried insulating film and the liner insulating film 24. By this capacity contact hole, the first, second, third and fourth capacity contact plugs 27e, 27f, 27g, 27h are respectively added to the first, second, third and fourth capacity contact regions 27a, 27b, 27c, 27d. Is connected.

  In the related art, when the capacitor contact hole is formed by the SAC method, the second capacitor contact plug 27f and the third capacitor contact plug 27g are separated by using an etch back method. Specifically, using a lithography technique or a dry etching technique as a capacitive contact etching mask, the mask is positioned between the center of the first word line WL10a and the center of the second word line WL10b and extends in the Y direction. The second capacitor contact hard mask 26a is formed, and is positioned between the center of the third word line WL10c and the center of the fourth word line WL10d and extends in the Y direction. 26b are formed, and the capacitor contact is dry-etched using them.

  After the capacitive contact dry etching, polysilicon is buried in the second capacitor contact plug 27f and the third capacitor contact plug 27g that are not yet separated, and the polysilicon is etched back using the sidewall silicon nitride film as a mask. The capacitor contact plug 27f and the third capacitor contact plug 27g are separated.

  A capacitor contact pad 33 is connected to the first, second, third, and fourth capacitor contact plugs 27e, 27f, 27g, and 27h. A lower electrode 34 is provided on the capacitor contact pad 33. A capacitor insulating film 35 covering the inner surface of the lower electrode 34 and an upper electrode 36 are provided on the capacitor insulating film 35 to constitute a capacitor.

  In the above related technology, after capacitive contact dry etching, polysilicon is buried in the second capacitor contact plug 27f and the third capacitor contact plug 27g that are not yet separated, and the polysilicon is etched back using the sidewall silicon nitride film as a mask. Thus, the second capacitor contact plug 27f and the third capacitor contact plug 27g are separated.

  However, in this method, when the semiconductor device is miniaturized, the capacitor contact is buried with the sidewall silicon nitride film, and the second capacitor contact plug 27f and the third capacitor contact plug 27g are separated during the polysilicon etchback. There is a problem that it cannot be performed well and the yield is lowered. Further, since the capacitor contact plug is separated by polysilicon etch-back, there is a problem in that the semiconductor substrate 11 is etched during over-etching and junction leakage occurs.

  The present invention solves the above-mentioned problems of the related art. The second capacitor contact plug 27f and the third capacitor contact plug 27g are stably separated, thereby improving the yield and generating junction leakage. It is what suppresses.

(Embodiment of the present invention)
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  1 and 2 are diagrams showing the structure of a semiconductor device 100 according to a preferred embodiment of the present invention. The semiconductor device 100 according to this embodiment is, for example, a DRAM, FIG. 1 is a plan view, FIG. 2A is a cross-sectional view taken along the line BB in FIG. 1, and FIG. 3 to 12 are cross-sectional views showing a series of manufacturing steps of the semiconductor device 100.

  First, a semiconductor device 100 according to an embodiment of the present invention will be described with reference to FIG.

  The semiconductor device 100 constitutes a DRAM memory cell. Similar to the first element isolation region (STI) 12a extending continuously in the X ″ direction and the second element isolation region (STI) 12b extending continuously in the X ′ direction on the semiconductor substrate 11. A plurality of first active regions 13a extending continuously in the X ″ direction and a plurality of second active regions 13b extending continuously in the X ′ direction are alternately arranged at equal intervals and at equal pitches in the Y direction. .

  The element isolation region 12 is composed of an element isolation insulating film embedded in the trench. A first embedded word line (hereinafter referred to as a first buried word line) extending continuously in the Y direction across the plurality of first element isolation regions 12a and the plurality of first active regions 13a extending continuously in the X ″ direction. A word line WL10a and a second buried word line (hereinafter referred to as second word line y) WL10b are arranged.

  Similarly, a third buried word line (hereinafter referred to as a first embedded word line) extending continuously in the Y direction across the plurality of second element isolation regions 12b and the plurality of second active regions 13b extending continuously in the X ′ direction. WL10c and a fourth embedded word line (hereinafter referred to as a fourth word line) WL10d are arranged. These word lines correspond to the gate electrodes of the transistors.

  The first active region 13a includes a first capacitor contact region 27a disposed at the left end of the first active region 13a, a first word line WL10a disposed adjacent to the first capacitor contact region 27a, and a first word line First bit line contact region 22a disposed adjacent to WL10a, second word line WL10b disposed adjacent to first bit line contact region 22a, and disposed adjacent to second word line WL10b The second capacitor contact region 27b is formed.

  The first capacitor contact region 27a, the first word line WL10a, and the first bit line contact region 22a constitute a first transistor Tr1, and the first bit line contact region 22a, the second word line WL10b, A second transistor Tr2 is configured with the capacitor contact region 27b.

  Similarly, the second active region 13b includes a third capacitor contact region 27c disposed at the left end of the second active region 13b, a third word line WL10c disposed adjacent to the third capacitor contact region 27c, and the second A second bit line contact region 22b disposed adjacent to the third word line 10c, a fourth word line WL10d disposed adjacent to the second bit line contact region 22b, and a fourth word line WL10d. The fourth capacitor contact region 27d is arranged.

  The third capacitor contact region 27c, the third word line WL10c, and the second bit line contact region 22b constitute a third transistor Tr3, the second bit line contact region 22b, the fourth word line WL10d, and the fourth A fourth transistor Tr4 is configured with the capacitor contact region 27d. The memory cell of the present embodiment is configured by arranging a plurality of configurations of the first active region 13a and the second active region 13b in the X direction via an element isolation region (STI) 12.

  Next, referring to FIGS. 2A and 2B, the semiconductor substrate 11 is provided with a word line groove 14 which also serves as a gate electrode of a transistor. The first word line WL10a, the second word line WL10b, the third word line WL10c, and the fourth word line WL10d are located at the bottom of each groove via the gate insulating film 6 covering the inner surface of each word line groove 14. Is provided. A cap insulating film 17 is provided so as to cover each word line and bury each groove 14.

  The semiconductor pillar located on the left side of the first word line WL10a becomes the first capacitor contact region 27a, and the impurity diffusion layer 19a serving as one of the source / drain is provided on the upper surface thereof. The semiconductor pillar located between the first word line WL10a and the second word line WL10b becomes a first bit line contact region (first BL contact region) 22a, and an impurity diffusion layer serving as one of the other of the source / drain on the upper surface thereof 18a is provided.

  The semiconductor pillar located on the right side of the second word line WL10b becomes the second capacitor contact region 27b, and an impurity diffusion layer 19b serving as one of the source / drain is provided on the upper surface thereof. Further, the semiconductor pillar located on the left side of the third word line WL3 becomes the third capacitor contact region 27c, and the impurity diffusion layer 19c serving as one of the source / drain is provided on the upper surface thereof.

  The semiconductor pillar located between the third word line WL10c and the fourth word line WL10d becomes the second bit line contact region (second BL contact region) 22b, and the upper surface of the impurity becomes the other one of the source / drain A diffusion layer 18b is provided. Further, the semiconductor pillar located on the right side of the fourth word line WL10b becomes the fourth capacitor contact region 27d, and the impurity diffusion layer 19d serving as one of the source / drain is provided on the upper surface thereof.

  The impurity diffusion layer 19a, the gate insulating film 6, the first word line WL10a, and the impurity diffusion layer 18a constitute a first transistor Tr1. The impurity diffusion layer 18a, the gate insulating film 6, the second word line WL10b, and the impurity diffusion layer 19b constitute the second transistor Tr2. Further, the impurity diffusion layer 19c, the gate insulating film 6, the third word line WL10c, and the impurity diffusion layer 18b constitute a third transistor Tr3. The impurity diffusion layer 19d, the gate insulating film 6, the fourth word line WL10d, and the impurity diffusion layer 18b constitute a fourth transistor Tr4.

  A cap insulating film 17 is provided so as to cover the upper surface of each word line. On the cap insulating film 17, a first bit line (BL) 23a connected to the first impurity diffusion layer 18a in the first BL contact region 22a is provided. A cover insulating film 23d is provided on the upper surface of the first bit line (BL) 23a. A liner insulating film 24 is provided on the entire surface so as to cover the side wall of the first bit line (BL) 23a. On the liner insulating film 24, there is provided a buried insulating film 25 that fills a recessed space formed between adjacent bit lines (BL). A cap silicon oxide film 26 is provided on the buried insulating film 25.

  A capacitor contact hole 27 (see FIG. 10) is provided through the buried insulating film 25 and the liner film 24. The capacitor contact hole 27 allows the first, second, third and fourth capacitor contact regions 27a, 27b, 27c and 27d to be respectively connected to the first, second, third and fourth capacitor contact plugs 27e, 27f, 27g, 27h is connected.

  In the embodiment of the present invention, when the capacitor contact hole is formed by the SAC method, the related technology uses the etch back method to separate the second capacitor contact plug 27f and the third capacitor contact plug 27g by double patterning. It is performed stably by using the method.

  Specifically, as the first capacitive contact etching mask, the first first capacitive contact mask silicon nitride film 29a, which is located on the left side of the first active region 13a and extends in the Y direction, Located between the region 13a and the second active region 13b and extending in the Y direction, the second first capacitor contact mask silicon nitride film 29b extending in the Y direction and the right side of the second active region 13a and extending in the Y direction The third capacitor contact mask silicon nitride film 29c is used. Here, the interval between the first and second first capacitor contact masks 29a and 29b is 6F, and similarly, the interval between the second and third first capacitor contact masks 29b and 29c is 6F.

  Further, the second capacitor contact etching mask is composed of a resist 30c, silicon BARC 30b, and BARC 30a (see FIG. 9B), and is between the center of the first word line WL10a and the center of the second word line WL10b. The first second capacitor contact hard mask 31a, which is located and extends in the Y direction, and a resist 30c, silicon BARC 30b, and BARC 30a (see FIG. 9B), the center of the third word line WL10c and the first A second second capacitor contact hard mask 31b located between the centers of the four word lines WL10d and extending in the Y direction is used. Here, the interval between the first and second second capacitor contact masks 31a and 31b is 6F. The capacitor contact 27 is dry-etched using these capacitor contact etching masks. By doing so, the capacitor contact is buried with the sidewall silicon nitride film which has been a problem in the related art, so that the second capacitor contact plug 27e and the third capacitor contact plug 27f, which could not be successfully performed, can be stably separated. Become.

  A capacitor contact pad 33 is connected to the first, second, third, and fourth capacitor contact plugs 27e, 27f, 27g, and 27h. A lower electrode 34 is provided on the capacitor contact pad 33. A capacitor insulating film 35 covering the inner surface of the lower electrode 34 and an upper electrode 36 are provided on the capacitor insulating film 35 to constitute a capacitor.

  In the semiconductor device 100, the first first capacitor contact located on the left side of the first active region 13a and extending in the Y direction is used as a first capacitor contact etching mask when the capacitor contact 27 is dry-etched. The mask silicon nitride film 29a, the second first capacitor contact mask silicon nitride film 29b located between the first active region 13a and the second active region 13b and extending in the Y direction, and the second active region 13a A third first capacitor contact mask silicon nitride film 29c located on the right side and extending in the Y direction is used.

  Further, the second capacitor contact etching mask is composed of a resist 30c, silicon BARC 30b, and BARC 30a (see FIG. 9B), and is between the center of the first word line WL10a and the center of the second word line WL10b. The first second capacitor contact hard mask 31a, which is located and extends in the Y direction, and a resist 30c, silicon BARC 30b, and BARC 30a (see FIG. 9B), the center of the third word line WL10c and the first A second second capacitor contact hard mask 31b located between the centers of the four word lines WL10d and extending in the Y direction is used.

  In this way, by using the first capacitive contact etching mask and the second capacitive contact etching mask, the capacitive contacts are buried with the sidewall silicon nitride film, which has been a problem in the related art, and can be successfully performed. The separation of the second capacitor contact plug 27f and the third capacitor contact plug 27g which have not been made can be performed stably, and the yield is improved.

  In addition, since it is not necessary to separate the capacitor contact plugs by etch back, the semiconductor substrate 11 that has occurred at the time of etch back is not etched, so that occurrence of junction leakage can be suppressed.

  Next, a method for manufacturing the semiconductor device 100 shown in FIGS. 1 and 2 will be described with reference to FIGS. 3-12, (a) shows the BB sectional drawing in FIG. 1, (b) has shown the AA sectional drawing in FIG.

  First, as shown in FIG. 3, an element isolation region 12 embedded with an insulating film made of a silicon oxide film is formed on a semiconductor substrate 11 by a well-known STI method. As a result, an active region 13 that is surrounded by the element isolation region 2 and made of the substrate 11 is formed.

  Next, a pad oxide film 2 made of a silicon oxide film is formed on the entire surface of the semiconductor substrate 11, and an N well region and a P well region are formed through the pad oxide film 2 by a known method.

  Next, as shown in FIG. 4, a silicon nitride film or the like is deposited on the semiconductor substrate 11, and the hard mask 7 for forming the word line trenches 14 is patterned with a resist (not shown).

  Next, the semiconductor substrate 11 is etched by dry etching to form a word line groove 14.

Then, a gate oxide film 6 is formed on the active region 13 of the semiconductor substrate 11 using a thermal oxidation and nitridation process. Further, tungsten 9 or the like is deposited by, for example, a CVD method and etched back to form word lines WL10a, WL10b, WL10c, and WL10d.

  Next, as shown in FIG. 5, a liner film is formed by, for example, a CVD method using a silicon nitride film or the like so as to cover the remaining tungsten and the inner wall of the word line groove 14. A cap insulating film 17 is deposited on the liner film. Thereafter, CMP is performed to flatten the surface until the liner film is exposed, and then the silicon nitride film for mask and the buried insulating film 17 and a part of the liner film are removed by etching, and the surface of the buried insulating film is obtained. Is approximately the same height as the surface of the hard mask 7 on the semiconductor substrate 11. Thereby, a buried word line and a buried wiring for element isolation are formed.

  Next, as shown in FIG. 6, a part of the hard mask 7 is removed by using a photolithography technique and a dry etching technique, and the bit contact connected to the upper surfaces of the first bit contact region 22a and the second bit line contact region. Form. The bit contact is formed as a line-shaped opening pattern extending in the same direction as the word lines WL10a, WL10b, WL10c and WL10d (Y direction in FIG. 1).

  At the intersection of the bit contact pattern and the active region, the surface of the semiconductor substrate 11 is exposed. After forming the bit contact, an N-type impurity (such as arsenic) is ion-implanted to form an N-type impurity diffusion layer in the vicinity of the silicon surface. The formed N-type impurity diffusion layer functions as a source / drain region 18 of the transistor. Thereafter, a laminated film such as a polysilicon film, a tungsten film, or a silicon nitride film is formed by, for example, a CVD method. Then, patterning is performed into a line shape using a photolithography technique and a dry etching technique to form the bit line 23a. Bit line 23a is formed as a pattern extending in a direction (X direction in FIG. 1) intersecting word lines WL10a, WL10b, WL10c and WL10d. The polysilicon film under the bit line and the source / drain region 18 are connected at the silicon surface portion exposed in the bit contact.

  Next, as shown in FIG. 7, after forming the silicon nitride film 28 covering the side surface of the bit line, the liner film 24 covering the upper surface is formed of a silicon nitride film or the like by using, for example, the CVD method.

  After depositing the SOD film 25 which is a coating film so as to fill the space between the bit lines, an annealing process is performed in a high-temperature water vapor (H 2 O) atmosphere to modify the film into a solid film. After performing planarization by CMP until the upper surface of the liner film 24 is exposed, a silicon oxide film formed by, for example, a CVD method is formed as the cap silicon oxide film 26 to cover the surface of the SOD film 25.

  Next, as shown in FIG. 8, a capacitive contact is formed using a photolithography technique and a dry etching technique. In the embodiment of the present invention, when the capacitor contact hole is formed by the SAC method, the related second conventional contact plug 27f and the third capacitor contact plug 27g are separated by using the etch back method. Is performed stably by using a double patterning method.

  First, a silicon nitride film is formed on the second interlayer insulating film by, for example, a CVD method. Then, the first capacitor contact mask nitride film 29 is formed by patterning in a line shape at a pitch of 6F using a lithography technique and a dry etching technique. The first capacitor contact mask nitride film 29 is formed as a line-shaped opening pattern extending in the same direction as the word lines WL10a, WL10b, WL10c and WL10d (Y direction in FIG. 1).

  Next, as shown in FIG. 9, BARC 30a, silicon BARC 30b, and resist 30c are stacked and patterned in a line shape at a pitch of 6F using a lithography technique. A second capacitor contact hard mask 31 is formed. The second capacitor contact hard mask 31 is formed as a line-shaped opening pattern extending in the same direction as the word lines WL10a, WL10b, WL10c and WL10d (Y direction in FIG. 1).

  Next, as shown in FIG. 10, a capacitive contact hole 27 is formed through the SOD film 25 and the liner film 24 by using a dry etching technique. The surface of the silicon substrate 11 is exposed at the intersection of the capacitor contact hole 27 and the active region 13. Next, a silicon nitride film is formed using, for example, a CVD method and etched back to form a sidewall silicon nitride film 32.

  Next, as shown in FIG. 11, polysilicon doped with an N-type impurity (phosphorus or the like) is embedded in the capacitor contact hole 27 by using, for example, a CVD method. Subsequently, excess polysilicon on the second interlayer insulating film 26 is removed by, for example, CMP, and the polysilicon is etched back, so that the capacitor contact plugs 27e, 27f, 27g and 27h are formed. An N-type impurity diffusion layer is formed in the vicinity of the surface of the active region 13 by the N-type impurity doped in the polysilicon. The formed N-type impurity diffusion layer functions as the source / drain regions 19a, 19b, and 19c of the transistor.

  Next, as shown in FIG. 12, a wiring material layer such as tungsten is buried in the remaining portion in the capacitor contact by using the CVD method. Subsequently, an excessive wiring material layer on the cover insulating film 23d and the SOD film 25 is removed by CMP, and a capacitor contact pad 33 connected to the plug is formed.

  Next, as shown in FIG. 2, a stopper film 30 is formed using a silicon nitride film so as to cover the capacitor contact pad 33. A lower electrode 34 of the capacitor element is formed on the capacitor contact pad 33 with titanium nitride or the like.

  Then, after forming the capacitive insulating film 35 so as to cover the surface of the lower electrode 34, the upper electrode 36 of the capacitor element is formed of titanium nitride or the like.

  Thereafter, although not shown, the wiring formation process is repeated to form a multilayer wiring, and the semiconductor device 100 is formed.

  In the semiconductor device 100, when the capacitor contact 27 is dry-etched, the first capacitor contact mask is located on the left side of the first active region 13a as the first capacitor contact etching mask and extends in the Y direction. The right side of the silicon nitride film 29a, the second first capacitor contact mask silicon nitride film 29b located between the first active region 13a and the second active region 13b and extending in the Y direction, and the second active region 13a And a third first capacitor contact mask silicon nitride film 29c extending in the Y direction is used.

  Further, the second capacitive contact etching mask is composed of a resist 30c, silicon BARC30b, and BARC30a, and is positioned between the center of the first word line WL10a and the center of the second word line WL10b and extends in the Y direction. The second capacitor contact hard mask 31a, the resist 30c, the silicon BARC 30b, and the BARC 30a are located between the center of the third word line WL10c and the center of the fourth word line WL10d, and in the Y direction. The second second capacitor contact hard mask 31b extending in the step is used.

  In this way, by using the first capacitive contact etching mask and the second capacitive contact etching mask, the capacitive contacts are buried with the sidewall silicon nitride film, which has been a problem in the related art, and can be successfully performed. The separation of the second capacitor contact plug 27f and the third capacitor contact plug 27g which have not been made can be performed stably, and the yield is improved.

  In addition, since it is not necessary to separate the capacitor contact plugs by etch back, the semiconductor substrate 11 that has occurred at the time of etch back is not etched, so that occurrence of junction leakage can be suppressed.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

10a First word line 10b Second word line 10c Third word line 10d Fourth word line 11 Semiconductor substrate 12a First element isolation region (STI)
12b Second element isolation region (STI)
13a First active region 13b Second active region 22a First bit line contact region 22b Second bit line contact region 27 Capacitive contact (capacitor contact hole)
27a First capacitor contact region
27b Second capacitor contact region 27c Third capacitor contact region 27d Fourth capacitor contact region 27e First capacitor contact plug 27f Second capacitor contact plug 27g Third capacitor contact plug 27h Fourth capacitor contact plug 29a First capacitor contact mask Silicon nitride Film 29b First capacitor contact mask Silicon nitride film 29c First capacitor contact mask Silicon nitride film 31a Second capacitor contact hard mask 31b Second capacitor contact hard mask

Claims (13)

Forming an element isolation region in a semiconductor substrate;
Forming a gate electrode constituting a word line in an active region surrounded by the element isolation region;
Forming a capacitor contact region between the element isolation region and the gate electrode;
Using a plurality of types of capacitor contact masks, a capacitor contact hole is formed by etching in the capacitor contact region,
Forming a capacitor contact plug in the capacitor contact hole;
A method of manufacturing a semiconductor device, comprising forming a capacitor on the capacitor contact plug. The element isolation region is divided into first, second and third element isolation regions,
The active region is divided into a first active region divided by the first and second element isolation regions and a second active region divided by the second and third element isolation regions,
First and second gate electrodes are disposed in the first active region, and third and fourth gate electrodes are disposed in the second active region,
A first capacitor contact region is formed between the first element isolation region and the first gate electrode, and a second capacitor is formed between the second gate electrode and the second element isolation region. A contact region is formed, a third capacitor contact region is formed between the second element isolation region and the third gate electrode, and between the fourth gate electrode and the third element isolation region. A fourth capacitor contact region is formed,
A first capacitor contact plug is formed in the first capacitor contact region, a second capacitor contact plug is formed in the second capacitor contact region, and a third capacitor contact plug is formed in the third capacitor contact region. And a fourth capacitor contact plug is formed in the fourth capacitor contact region,
The plurality of types of capacitor contact masks are a capacitor contact mask nitride film and a capacitor contact hard mask, and the second capacitor contact plug and the third capacitor using the capacitor contact mask nitride film and the capacitor contact hard mask. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the contact plug is separated.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the capacitor contact mask nitride film and the capacitor contact hard mask are provided on a cap insulating film formed on the semiconductor substrate.   4. The method of manufacturing a semiconductor device according to claim 2, wherein the capacitor contact mask nitride film and the capacitor contact hard mask are different from a sidewall insulating film.   5. The manufacturing method of a semiconductor device according to claim 2, wherein the second capacitor contact plug and the third capacitor contact plug are separated without using an etch back method. 6. Method.   6. The method of manufacturing a semiconductor device according to claim 1, wherein the capacitor contact plug is provided on an impurity diffusion layer formed in the semiconductor substrate.   The method of manufacturing a semiconductor device according to claim 1, wherein the capacitor contact hole is formed by a SAC method.   As the capacitor contact mask nitride film, a first capacitor contact mask nitride film provided on the first element isolation region, a second capacitor contact mask nitride film provided on the second element isolation region, 8. The method of manufacturing a semiconductor device according to claim 2, wherein a third capacitor contact mask nitride film provided on the third element isolation region is used. 9. The first capacitive contact mask nitride film is located on the left side of the first active region and extends in the Y direction,
The second capacitive contact mask nitride film is located between the first active region and the second active region and extends in the Y direction;
9. The method of manufacturing a semiconductor device according to claim 8, wherein the third capacitor contact mask nitride film is located on the right side of the second active region and extends in the Y direction.   10. The semiconductor according to claim 9, wherein a distance between the first and second capacitive contact mask nitride films is 6F, and a distance between the second and third capacitive contact mask nitride films is 6F. Device manufacturing method.   As the capacitor contact hard mask, a first capacitor contact hard mask provided in the first active region and a second capacitor contact hard mask provided in the second active region are used. The method for manufacturing a semiconductor device according to claim 2, wherein: The first capacitor contact hard mask is located between a center of a first word line corresponding to the first gate electrode and a center of a second word line corresponding to the second gate electrode; and Extending in the Y direction,
The second capacitor contact hard mask is located between the center of the third word line corresponding to the third gate electrode and the center of the fourth word line corresponding to the fourth gate electrode; The method of manufacturing a semiconductor device according to claim 11, wherein the method extends in the Y direction.   13. The method of manufacturing a semiconductor device according to claim 12, wherein an interval between the first and second capacitive contact hard masks is 6F.

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