US20200379677A1 - Memory controller and memory controlling method where number of commands (executed by the memory controller prior to releasing host memory) is adjusted based on transmission speed of interface to host - Google Patents
Memory controller and memory controlling method where number of commands (executed by the memory controller prior to releasing host memory) is adjusted based on transmission speed of interface to host Download PDFInfo
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- US20200379677A1 US20200379677A1 US16/548,934 US201916548934A US2020379677A1 US 20200379677 A1 US20200379677 A1 US 20200379677A1 US 201916548934 A US201916548934 A US 201916548934A US 2020379677 A1 US2020379677 A1 US 2020379677A1
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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Definitions
- the present disclosure relates to a storage device. More particularly, the present disclosure relates to a storage device capable of increasing data transmission efficiency.
- NCQ native command queuing
- the disclosure provides a memory controller including an interface circuit and a control circuit.
- the interface circuit is configured to communicate with a host device.
- the control circuit finishes executing N commands transmitted from the host device, the memory controller notifies the host device to release corresponding memory in the host device corresponding to the N commands, and N is a positive integer.
- the control circuit compares a data transmission speed of the interface circuit with a predetermined value to generate a comparison result, and the control circuit adjusts a value of N based on the comparison result.
- the disclosure provides a controlling method, applicable to a memory controller comprising an interface circuit and a control circuit, comprising following operations: utilizing the interface circuit to receive N commands transmitted from a host device; when the control circuit finishes executing the N commands, utilizing the control circuit to notify the host device to release corresponding memory in the host device corresponding to the N commands, wherein N is a positive integer; utilizing the control circuit to compare a data transmission speed of the interface circuit with a predetermined value to generate a comparison result; utilizing the control circuit to adjust a value of N based on the comparison result.
- FIG. 1 is a simplified functional block diagram of a computer system according to one embodiment of the present disclosure.
- FIG. 2 is a flow chart of a memory controlling method according to one embodiment of the present disclosure.
- FIG. 3 is a simplified schematic diagram of a SDB FIS according to one embodiment of the present disclosure.
- FIGS. 4A and 4B are simplified schematic diagrams showing the regulation of a transmission pattern of SDB FISs when the computer system executes the memory controlling method of FIG. 2 .
- FIG. 5 is a flow chart of a memory controlling method according to another embodiment of the present disclosure.
- FIGS. 6A and 6B are simplified schematic diagrams showing the regulation of execution orders of multiple read commands when the computer system executes the memory controlling method of FIG. 5 .
- FIG. 1 is a simplified functional block diagram of a computer system 100 according to one embodiment of the present disclosure.
- the computer system 100 comprises a host device 110 , a memory controller 120 , a storage device 130 , and a memory module 140 .
- the host device 110 and the storage device 130 may be partial circuits of an electronic device.
- the host device 110 and the storage device 130 may respectively be a motherboard and a hard disk.
- the memory controller 120 and the memory module 140 may be partial circuits of another electronic device (e.g., SSD).
- the memory controller 120 and the memory module 140 may respectively be a SSD controller and a NAND flash memory in the SSD.
- other functional blocks of the computer system 100 are not shown in FIG. 1 .
- the host device 110 comprises a first control circuit 112 , a first direct memory access (DMA) circuit 114 , a first memory 116 (e.g., Main Memory), a first interface circuit 118 a , and a first interface circuit 118 b .
- the first interface circuit 118 a is configured to conduct data communications with the memory controller 120 .
- the first control circuit 112 is configured to control bidirectional data transmissions between the storage device 130 and the first memory 116 .
- the first DMA circuit 114 is configured to conduct bidirectional data transmissions between the first memory 116 and the memory controller 120 .
- the memory controller 120 comprises a second control circuit 122 , a second DMA circuit 124 , a second memory 126 , a second interface circuit 128 , and a memory controller Fc.
- the second interface circuit 128 is configured to conduct data transmissions with the first interface circuit 118 a .
- the second control circuit 122 is configured to control the second DMA circuit 124 and the memory interface circuit Fc according to commands transmitted from the host device 110 .
- the second DMA circuit 124 is configured to conduct bidirectional data transmissions between the second memory 126 and the host device 110 .
- the memory interface circuit Fc is configured to conduct bidirectional data transmissions between the second memory 126 and the memory module 140 .
- the first interface circuit 118 a and the second interface circuit 128 may be SATA interfaces, but this disclosure is not limited thereto.
- the first interface circuit 118 b may be a SATA interface or a peripheral component interconnect Express (PCIe) interface.
- PCIe peripheral component interconnect Express
- data transmitted between the host device 110 and the memory controller 120 is encapsulated as frame information structure (FIS).
- FIS frame information structure
- the command which the host device 110 transmits to the memory controller 120 is a host to device (H2D) FIS
- the command which the memory controller 120 responds to the host device 110 is a device to host (D2H) FIS.
- the memory controller 120 finishes executing N (one or more) commands
- the memory controller 120 transmits a set device bits (SDB) FIS to the host device 110 , so as to notify the host device 110 to release memory allocated to the N commands, wherein N is an positive integer, and N 1 .
- SDB set device bits
- the memory controller 120 transmits the SDB FIS for too few times (e.g., sending one SDB FIS after executing too many commands), the host device 110 would transmits hold primitives to the memory controller 120 continuously (for many times) because of insufficient memory space (since the first memory 116 is not efficiently released).
- the host device 110 has sufficient memory space or the first control circuit 112 has a fast processing speed, the fewer times the memory controller 120 transmits the SDB FIS, the better the transmission efficiency between the host device 110 and the memory controller 120 .
- FIG. 2 is a flow chart of a memory controlling method according to one embodiment of the present disclosure.
- FIG. 3 is a simplified schematic diagram of a SDB FIS according to one embodiment of the present disclosure.
- the controlling method of FIG. 2 enables the memory controller 120 adaptively regulating transmission patterns of the SDB FIS according to the behaviors of the host device 110 .
- the memory controller 120 may execute a command CMD 1 transmitted from the host device 110 .
- the content of the command CMD 1 is to read data from the memory module 140 , and the execution processes of the command CMD 1 comprise transmission stages TSa-TSb.
- the host device 110 transmits the command CMD 1 to the memory controller 120 by using the H2D FIS (operation 2102 ). Then, the memory controller 120 responds to the host device 110 , by using the D2H FIS, the command CMD 1 has been received (operation 2104 ).
- the memory interface circuit Fc of the memory controller 120 may transfer corresponding data from the memory module 140 to the second memory 126 for the following transmission (operation 2106 ).
- the memory controller 120 transmits a DMA setup FIS to the host device 110 , so as to notify the host device 110 to prepare to receive the corresponding data (operation 2108 ). Then, the memory controller 120 inserts the data to be transmitted into a data FIS, and transmits the data FIS to the host device 110 (operation 2110 ).
- the memory controller 120 may also execute a command CMD 2 transmitted from the host device 110 .
- the content of the command CMD 2 is to write data into the memory module 140 , and the execution processes of the command CMD 2 comprise transmission stages TSc-TSd.
- the host device 110 transmits the command CMD 2 to the memory controller 120 by using the H2D FIS (operation 2202 ).
- the second control circuit 122 responds to the host device 110 , by using the D2H FIS, the command CMD 2 has been received (operation 2204 ).
- the memory controller 120 transmits DMA setup FIS to the host device 110 , so as to notify the host device 110 to prepare to start data transmission (operation 52206 ). Then, the host device 110 inserts the data to be transmitted into a data FIS, and transmits the data FIS to the memory controller 120 (operation 52208 ).
- the memory controller 120 writes the received data into the memory module 140 (operation 2210 ).
- the memory controller 120 transmits the SDB FIS to the host device 110 , so that the host device 110 releases the memory of the first memory 116 corresponding to the commands CMD 1 and CMD 2 .
- the SDB FIS comprises a header 310 and a field 320 , and the field 320 has a 32-bit size.
- the header 310 may comprise an error entry, a FIS type entry, an interrupt entry, etc.
- Each of the bits of the field 320 represents one command sent by the host device 110 . If a value of a bit is configured to be 1, the host device 110 is required to release corresponding memory. If a value of a bit is configured to be 0, the host device 110 needs not to release corresponding memory.
- the memory controller 120 may configure two bits, which are respectively corresponding to the commands CMD 1 and CMD 2 , of the SDB FIS to 1, and may configure other bits to 0.
- the memory controller 120 may configure the first and second bits of the SDB FIS as 1, and may configure the third through 32-th bits of the SDB FIS as 0.
- the type and content of an FIS are determined by the first control circuit 112 and the second control circuit 122 of FIG. 1 , and the transmission of an FIS is conducted by the first DMA circuit 114 and the second DMA circuit 124 .
- the first DMA circuit 114 and the second DMA circuit 124 mutually transmit the data FISs, the first control circuit 112 and the second control circuit 122 need not to participate the transmission. As a result, the computing efficiency of the first control circuit 112 and the second control circuit 122 is improved.
- the first control circuit 112 may load a physical region description table, which comprises the addresses of the first memory 116 , into the first DMA circuit 114 to assign a size of the data to be received and addresses to store the data. Then, the first DMA circuit 114 may receive data FISs from the second DMA circuit 124 in operation 2110 .
- the first control circuit 112 loads addresses of the first memory 116 , which are corresponding to the data to be written, into the first DMA circuit 114 . Then, the first DMA circuit 114 transmits the data to be written to the second DMA circuit 124 by using the data FISs.
- the second control circuit 122 further stores multiple commands from the host device 110 into a queue, and adjusts the execution sequence of the commands.
- the orders of the transmission stages of FIG. 2 is merely used for an exemplary illustration, and can be adjusted base on practical situations. For example, in a situation that the host device 110 transmits multiple commands at a time, the orders of the transmission stages TSb and TSc may be swapped.
- the memory controller 120 has finished two commands CMD 1 and CMD 2 from the host device 110 , and each of the two commands comprises at least two transmission stages.
- the number of finished commands depicted in FIG. 2 is, however, an exemplary embodiment. Every time the memory controlling method of FIG. 2 is executed, before conducting operation 230 , the memory controller 120 can actually finish executing totally N commands from the host device 110 (i.e., finishing at least 2N transmission stages), and N is a positive integer lower than or equal to 32.
- the memory controller 120 configures N corresponding bits of the field 320 to 1, and configures other bits to 0, so as to notify the host device 110 to release memory of the first memory 116 which corresponding to the N commands, respectively.
- the memory controller 120 will be assumed to have finished N commands from the host device 110 before conducting operation 230 .
- the memory controller 120 calculates a transmission speed of the second interface circuit 128 .
- the second DMA circuit 124 notifies the second control circuit 122 at the beginning and end of each data transmission, for example, notifying the second control circuit 122 at the beginnings and ends of operations 2110 and 2208 . Therefore, the memory controller 120 may calculate a time length, which the second DMA circuit 124 is busy, during the execution for the N commands. The memory controller 120 may further calculate the data transmission speed of the second interface circuit 128 according to the time length and a sum of sizes of the data FISs transmitted during the execution for the N commands.
- the memory controller 120 compares the transmission speed of the second interface circuit 128 with a predetermined value. If the comparison result is that the transmission speed of the second interface circuit 128 is lower than the predetermined value, the memory controller 120 adjusts a number of commands which are finished before the SDB FIS is transmitted (i.e., before operation 230 ). The specific regulating method will be further illustrated by reference to FIGS. 4A and 4B . Of course, if the comparison result is that the transmission speed of the second interface circuit 128 is higher than the predetermined value, the memory controller 120 may increase the number of commands finished before the SDB FIS is transmitted, until the transmission speed is completely optimized.
- the memory controller 120 transmits, by default, the SDB FIS once every N commands (e.g., commands CMD[1]-CMD[N] or commands CMD[N+1]-CMD[2N]) are finished. That is, the memory controller 120 transmits the SDB FIS once every 2N transmission stages (e.g., transmission stages TS[1]-TS[2N] or transmission stages TS[2N+1]-TS[4N]) are finished.
- N commands e.g., commands CMD[1]-CMD[N] or commands CMD[N+1]-CMD[2N]
- 2N transmission stages e.g., transmission stages TS[1]-TS[2N] or transmission stages TS[2N+1]-TS[4N]
- the memory controller 120 may, as shown in FIG. 4B , switches to transmit the SDB FIS once every M commands (e.g., commands CMD[N+1]-CMD[N+M]) are finished, where M is different from N, and M is a positive integer less than or equal to 32. That is, the memory controller 120 switches to transmit the SDB FIS once at least every 2M transmission stages (e.g., transmission stages TS[2N+1]-TS[2N+2M]) are finished. In this case, when operation 230 of FIG.
- M commands e.g., commands CMD[N+1]-CMD[N+M]
- the memory controller 120 adjusts the number of bits, which are configured to be 1, of the SDB FIS from N to M.
- the host device 110 is then notified to release the addresses corresponding to the M commands (e.g., the commands CMD[N+1]-CMD[N+M]).
- the computer system 100 may execute the memory controlling method of FIG. 2 for multiple times, so that the memory controller 120 may adaptively optimize the data transmission efficiency according to the configuration of the host device 110 .
- the aforesaid configuration may be a combination of one or more the following elements of the host device 110 : the control circuit architecture of the first control circuit 112 , the southbridge, the northbridge, the capacity of the first memory 116 , the advanced host controller interface (AHCI) architecture, the OS, the driver software, and whether the NCQ technology is activated.
- the computer system 100 may reduce the value of N (e.g., adjusting N from 16 to 7) to increase the times the host device 110 releasing the memory.
- the computer system 100 may increase the value of N (e.g., adjusting N from 16 to 30).
- N e.g., adjusting N from 16 to 30.
- the memory controller 120 may determine that the host device supports the NCQ technology.
- the various host devices supporting the NCQ technology however, some of the host devices have higher processing speed regard to the data returned in disorder, while other host devices have higher processing speed regard to the data returned sequentially.
- FIG. 5 is a flow chart of a memory controlling method according to another embodiment of the present disclosure.
- the memory controlling method of FIG. 5 enables the memory controller 120 adaptively regulating the return order of data according to the behavior of the host device 110 .
- the memory controller 120 executes commands CMD 1 and CMD 2 , and the content of the commands CMD 1 and CMD 2 are both reading data from the memory module 140 .
- the execution processes of the command CMD 1 comprise transmission stages TSa and TSc.
- the execution processes of the command CMD 2 comprise transmission stages TSb and TSd.
- the host device 110 may transmit the command CMD 1 to the memory controller 120 by using the H2D FIS (operation 5102 ).
- the memory controller 120 may respond to the host device 110 that the command CMD 1 is received by using the D2H FIS (operation 5104 )
- the host device 110 may transmit the command CMD 2 to the memory controller 120 by using the H2D FIS (operation 5202 ).
- the memory controller 120 may respond to the host device 110 that the command CMD 2 is received by using the D2H FIS (operation 5204 ).
- the memory controller 120 may, relatively quickly, access the data corresponding to the command CMD 2 from the memory module 140 , and access, relatively slowly, the data corresponding to the command CMD 1 . That is, the memory interface circuit Fc may transfer, relatively quickly, the data corresponding to the command CMD 2 from the memory module 140 to the second memory 126 for transmission (operation 530 ).
- the memory controller 120 can determines the execution order of multiple commands from the host device 110 , and needs not to execute the multiple commands in an order in which the multiple commands are received. Therefore, the memory controller 120 then conducts transmission stage TSc, so as to transmit the data corresponding to the command CMD 2 to the host device 110 .
- transmission stage TSc operations S 206 and S 208 are respectively similar to operations 2108 and 2110 of FIG. 2 , the difference is that the data FIS corresponding to the command CMD 2 is transmitted in operation 5208 .
- those corresponding descriptions of operations S 206 and S 208 will not be repeated here.
- the memory interface circuit Fc may transfer the data corresponding to the command CMD 1 from the memory module 140 to the second memory 126 for transmission (operation 540 ).
- the memory controller 120 then conducts the transmission stage TSd, so as to transmit the data corresponding to the command CMD 1 to the host device 110 .
- transmission stage TSd operations 5106 and 5108 are respectively similar to operations 2108 and 2110 of FIG. 2 , and the difference is that the data FIS CMD 1 is transmitted in operation 5108 .
- those corresponding descriptions of operations 5106 and 5108 will not be repeated here.
- operation 550 of FIG. 5 is similar to operation 230 of FIG. 2 .
- those corresponding descriptions of operation 550 will not be repeated here.
- the memory controller 120 may transmit corresponding data without following the receiving order in which the commands CMD 1 and CMD 2 are received.
- the memory controller 120 improves work efficiency by transmitting the data, which is accessed in an earlier order, in advanced.
- the two commands CMD 1 and CMD 2 of FIG. 5 are merely an exemplary embodiment for illustrating convenience.
- the computer system 100 may finish totally N commands before conducting operation 550 , and N is a positive integer smaller than or equal to 32.
- the memory controller 120 will be assumed to have finished N commands from the host device 110 before conducting operation 550 .
- the memory controller 120 calculates the transmission speed of the second interface circuit 128 by a method similar to operation 240 of FIG. 2 .
- the memory controller 120 compares the transmission speed of the second interface circuit 128 with a predetermined value. If the transmission speed of the second interface circuit 128 is lower than the predetermined value, and the aforementioned N commands comprises i read commands, the memory controller 120 may adjust a transmission sequence of the i data corresponding to the i read commands.
- the memory controller 120 may adjust the transmission sequence of the i data from corresponding to a sequence in which the i data are accessed (i.e., the sequence transferring to the second memory 126 ) to corresponding to a sequence in which the i read commands are received, and I is a positive integer smaller than or equal to N.
- the memory controller 120 may swap the execution orders of transmission stages TSc and TSd of FIG. 5 .
- the detailed regulation method will be further described by reference to FIGS. 6A and 6B .
- FIGS. 6A and 6B only show read commands CMD[1]-CMD[N] and corresponding transmission stages TS[1]-TS[2N], and the write commands are omitted.
- the memory controller 120 transmits, by default, the data accessed in an earlier order in advanced. That is, the transmission sequence in which the memory controller 120 transmits the data FISs is corresponding to a sequence in which the corresponding multiple data are transferred to the second memory 126 (e.g., 3, 1, 2, . . . , N).
- the memory controller 120 may switch the transmission sequence of the data FISs to corresponding to the sequence in which the corresponding read commands are received (i.e., 1, 2, 3, . . . , N).
- the memory controller 120 may also adjust the transmission sequence of the DMA setup FISs when regulating the transmission sequence of the data FISs. That is, the memory controller 120 may adjust the transmission sequence of the DMA setup FIS from corresponding to a sequence in which the corresponding multiple data are accessed to corresponding to a sequence in which the corresponding read commands are received.
- the memory controller 120 transmits, by default, the corresponding data FISs and/or DMA setup FISs according to the sequence in which the read commands are received. If the transmission speed of the second interface circuit 128 is lower than the predetermined value, the memory controller 120 may switch the transmission sequence of the data FISs and/or the DMA setup FISs to corresponding to the sequence in which the corresponding multiple data are accessed.
- the memory controller 120 may also not to switch the transmission sequence of the data FISs and/or the DMA setup FISs.
- Operation 250 of FIG. 2 may comprise procedures corresponding to operation 570 of FIG. 5
- operation 570 of FIG. 5 may also comprise procedures corresponding to operation 250 of FIG. 2 . That is, in some embodiments, the memory controlling method is capable of regulating both of the transmission pattern of the SDB FISs and the transmission sequence of the data FISs of the memory controller 120 .
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Abstract
Description
- This application claims priority to China Application Serial Number 201910464541.2, filed May 30, 2019, which is herein incorporated by reference in its entirety.
- The present disclosure relates to a storage device. More particularly, the present disclosure relates to a storage device capable of increasing data transmission efficiency.
- Commercially available electronic devices (e.g., Solid-state disk (SSD), Flash memory card) can access data through a variety of interface circuits (e.g., ATA, PCI-e, and USB). Some of the interface circuits (e.g., serial advanced technology attachment, SATA) is capable of supporting the native command queuing (NCQ) technology to increase the transmission efficiency of the interface. The NCQ technology allows multiple commands to be stored in a queue for being executed sequentially or in parallel, and thus the NCQ technology is different from the conventional sorting technology which needs to wait for the end of execution of a pervious command before receiving a next command.
- Electronic device manufacturers have introduced a variety model of products (e.g., personal computers (PC), servers, notebooks, tablet, smart phone, etc.) to the market. The role of these products in data reading and writing operations is a host device. On the market, however, there are various host devices having different configurations, such as having different operating system (OS) or/and having different specification or/and different hardware architecture. If a slave device responds to the host devices with different configurations by only using the same operation mode, not only the overall transmission speed may not be increased, but the efficiency of both sides is also possibly decreased.
- The disclosure provides a memory controller including an interface circuit and a control circuit. The interface circuit is configured to communicate with a host device. When the control circuit finishes executing N commands transmitted from the host device, the memory controller notifies the host device to release corresponding memory in the host device corresponding to the N commands, and N is a positive integer. The control circuit compares a data transmission speed of the interface circuit with a predetermined value to generate a comparison result, and the control circuit adjusts a value of N based on the comparison result.
- The disclosure provides a controlling method, applicable to a memory controller comprising an interface circuit and a control circuit, comprising following operations: utilizing the interface circuit to receive N commands transmitted from a host device; when the control circuit finishes executing the N commands, utilizing the control circuit to notify the host device to release corresponding memory in the host device corresponding to the N commands, wherein N is a positive integer; utilizing the control circuit to compare a data transmission speed of the interface circuit with a predetermined value to generate a comparison result; utilizing the control circuit to adjust a value of N based on the comparison result.
- It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the disclosure as claimed.
-
FIG. 1 is a simplified functional block diagram of a computer system according to one embodiment of the present disclosure. -
FIG. 2 is a flow chart of a memory controlling method according to one embodiment of the present disclosure. -
FIG. 3 is a simplified schematic diagram of a SDB FIS according to one embodiment of the present disclosure. -
FIGS. 4A and 4B are simplified schematic diagrams showing the regulation of a transmission pattern of SDB FISs when the computer system executes the memory controlling method ofFIG. 2 . -
FIG. 5 is a flow chart of a memory controlling method according to another embodiment of the present disclosure. -
FIGS. 6A and 6B are simplified schematic diagrams showing the regulation of execution orders of multiple read commands when the computer system executes the memory controlling method ofFIG. 5 . - Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
-
FIG. 1 is a simplified functional block diagram of acomputer system 100 according to one embodiment of the present disclosure. Thecomputer system 100 comprises ahost device 110, amemory controller 120, astorage device 130, and amemory module 140. Thehost device 110 and thestorage device 130 may be partial circuits of an electronic device. For example, thehost device 110 and thestorage device 130 may respectively be a motherboard and a hard disk. Thememory controller 120 and thememory module 140 may be partial circuits of another electronic device (e.g., SSD). For example, thememory controller 120 and thememory module 140 may respectively be a SSD controller and a NAND flash memory in the SSD. For the sake of brevity, other functional blocks of thecomputer system 100 are not shown inFIG. 1 . - The
host device 110 comprises afirst control circuit 112, a first direct memory access (DMA)circuit 114, a first memory 116 (e.g., Main Memory), afirst interface circuit 118 a, and afirst interface circuit 118 b. Thefirst interface circuit 118 a is configured to conduct data communications with thememory controller 120. Thefirst control circuit 112 is configured to control bidirectional data transmissions between thestorage device 130 and thefirst memory 116. Thefirst DMA circuit 114 is configured to conduct bidirectional data transmissions between thefirst memory 116 and thememory controller 120. - The
memory controller 120 comprises asecond control circuit 122, asecond DMA circuit 124, asecond memory 126, asecond interface circuit 128, and a memory controller Fc. Thesecond interface circuit 128 is configured to conduct data transmissions with thefirst interface circuit 118 a. Thesecond control circuit 122 is configured to control thesecond DMA circuit 124 and the memory interface circuit Fc according to commands transmitted from thehost device 110. Thesecond DMA circuit 124 is configured to conduct bidirectional data transmissions between thesecond memory 126 and thehost device 110. The memory interface circuit Fc is configured to conduct bidirectional data transmissions between thesecond memory 126 and thememory module 140. - In an embodiment, the
first interface circuit 118 a and thesecond interface circuit 128 may be SATA interfaces, but this disclosure is not limited thereto. In one embodiment, thefirst interface circuit 118 b may be a SATA interface or a peripheral component interconnect Express (PCIe) interface. - In an embodiment, data transmitted between the
host device 110 and thememory controller 120 is encapsulated as frame information structure (FIS). For example, the command which thehost device 110 transmits to thememory controller 120 is a host to device (H2D) FIS, and the command which thememory controller 120 responds to thehost device 110 is a device to host (D2H) FIS. When thememory controller 120 finishes executing N (one or more) commands, thememory controller 120 transmits a set device bits (SDB) FIS to thehost device 110, so as to notify thehost device 110 to release memory allocated to the N commands, wherein N is an positive integer, andN 1. - In a situation that the
first memory 116 of thehost device 110 has a small memory capacity or thefirst control circuit 112 has a slow processing speed, if thememory controller 120 transmits the SDB FIS for too few times (e.g., sending one SDB FIS after executing too many commands), thehost device 110 would transmits hold primitives to thememory controller 120 continuously (for many times) because of insufficient memory space (since thefirst memory 116 is not efficiently released). In other hand, in a situation that thehost device 110 has sufficient memory space or thefirst control circuit 112 has a fast processing speed, the fewer times thememory controller 120 transmits the SDB FIS, the better the transmission efficiency between thehost device 110 and thememory controller 120. -
FIG. 2 is a flow chart of a memory controlling method according to one embodiment of the present disclosure.FIG. 3 is a simplified schematic diagram of a SDB FIS according to one embodiment of the present disclosure. The controlling method ofFIG. 2 enables thememory controller 120 adaptively regulating transmission patterns of the SDB FIS according to the behaviors of thehost device 110. Reference is made toFIGS. 1 through 3 , thememory controller 120 may execute a command CMD1 transmitted from thehost device 110. The content of the command CMD1 is to read data from thememory module 140, and the execution processes of the command CMD1 comprise transmission stages TSa-TSb. - In transmission stage TSa, the
host device 110 transmits the command CMD1 to thememory controller 120 by using the H2D FIS (operation 2102). Then, thememory controller 120 responds to thehost device 110, by using the D2H FIS, the command CMD1 has been received (operation 2104). - The memory interface circuit Fc of the
memory controller 120 may transfer corresponding data from thememory module 140 to thesecond memory 126 for the following transmission (operation 2106). - In transmission stage TSb, the
memory controller 120 transmits a DMA setup FIS to thehost device 110, so as to notify thehost device 110 to prepare to receive the corresponding data (operation 2108). Then, thememory controller 120 inserts the data to be transmitted into a data FIS, and transmits the data FIS to the host device 110 (operation 2110). - The
memory controller 120 may also execute a command CMD2 transmitted from thehost device 110. The content of the command CMD2 is to write data into thememory module 140, and the execution processes of the command CMD2 comprise transmission stages TSc-TSd. - In transmission stage TSc, the
host device 110 transmits the command CMD2 to thememory controller 120 by using the H2D FIS (operation 2202). Thesecond control circuit 122 responds to thehost device 110, by using the D2H FIS, the command CMD2 has been received (operation 2204). - In transmission stage TSd, the
memory controller 120 transmits DMA setup FIS to thehost device 110, so as to notify thehost device 110 to prepare to start data transmission (operation 52206). Then, thehost device 110 inserts the data to be transmitted into a data FIS, and transmits the data FIS to the memory controller 120 (operation 52208). - Then, the
memory controller 120 writes the received data into the memory module 140 (operation 2210). - In operation 5230, the
memory controller 120 transmits the SDB FIS to thehost device 110, so that thehost device 110 releases the memory of thefirst memory 116 corresponding to the commands CMD1 and CMD2. - Reference is made to
FIG. 3 , the SDB FIS comprises aheader 310 and afield 320, and thefield 320 has a 32-bit size. Theheader 310 may comprise an error entry, a FIS type entry, an interrupt entry, etc. Each of the bits of thefield 320 represents one command sent by thehost device 110. If a value of a bit is configured to be 1, thehost device 110 is required to release corresponding memory. If a value of a bit is configured to be 0, thehost device 110 needs not to release corresponding memory. - In this embodiment, the
memory controller 120 may configure two bits, which are respectively corresponding to the commands CMD1 and CMD2, of the SDB FIS to 1, and may configure other bits to 0. For example, thememory controller 120 may configure the first and second bits of the SDB FIS as 1, and may configure the third through 32-th bits of the SDB FIS as 0. - In one embodiment, the type and content of an FIS are determined by the
first control circuit 112 and thesecond control circuit 122 ofFIG. 1 , and the transmission of an FIS is conducted by thefirst DMA circuit 114 and thesecond DMA circuit 124. When thefirst DMA circuit 114 and thesecond DMA circuit 124 mutually transmit the data FISs, thefirst control circuit 112 and thesecond control circuit 122 need not to participate the transmission. As a result, the computing efficiency of thefirst control circuit 112 and thesecond control circuit 122 is improved. - For example, when the
host device 110 receives the DMA setup FIS inoperation 2108, thefirst control circuit 112 may load a physical region description table, which comprises the addresses of thefirst memory 116, into thefirst DMA circuit 114 to assign a size of the data to be received and addresses to store the data. Then, thefirst DMA circuit 114 may receive data FISs from thesecond DMA circuit 124 inoperation 2110. - As another example, when the
host device 110 receives the DMA setup FIS inoperation 2206, thefirst control circuit 112 loads addresses of thefirst memory 116, which are corresponding to the data to be written, into thefirst DMA circuit 114. Then, thefirst DMA circuit 114 transmits the data to be written to thesecond DMA circuit 124 by using the data FISs. - In one embodiment, if the
computer system 100 supports the NCQ technology, thesecond control circuit 122 further stores multiple commands from thehost device 110 into a queue, and adjusts the execution sequence of the commands. In other words, the orders of the transmission stages ofFIG. 2 is merely used for an exemplary illustration, and can be adjusted base on practical situations. For example, in a situation that thehost device 110 transmits multiple commands at a time, the orders of the transmission stages TSb and TSc may be swapped. - As can be appreciated from the foregoing descriptions, before
operation 230 is conducted, thememory controller 120 has finished two commands CMD1 and CMD2 from thehost device 110, and each of the two commands comprises at least two transmission stages. The number of finished commands depicted inFIG. 2 is, however, an exemplary embodiment. Every time the memory controlling method ofFIG. 2 is executed, before conductingoperation 230, thememory controller 120 can actually finish executing totally N commands from the host device 110 (i.e., finishing at least 2N transmission stages), and N is a positive integer lower than or equal to 32. In this situation, inoperation 230, thememory controller 120 configures N corresponding bits of thefield 320 to 1, and configures other bits to 0, so as to notify thehost device 110 to release memory of thefirst memory 116 which corresponding to the N commands, respectively. In the following paragraphs for continuing to explain the memory controlling method ofFIG. 2 , thememory controller 120 will be assumed to have finished N commands from thehost device 110 before conductingoperation 230. - In
operation 240, thememory controller 120 calculates a transmission speed of thesecond interface circuit 128. Specifically, thesecond DMA circuit 124 notifies thesecond control circuit 122 at the beginning and end of each data transmission, for example, notifying thesecond control circuit 122 at the beginnings and ends ofoperations memory controller 120 may calculate a time length, which thesecond DMA circuit 124 is busy, during the execution for the N commands. Thememory controller 120 may further calculate the data transmission speed of thesecond interface circuit 128 according to the time length and a sum of sizes of the data FISs transmitted during the execution for the N commands. - Then, in
operation 250, thememory controller 120 compares the transmission speed of thesecond interface circuit 128 with a predetermined value. If the comparison result is that the transmission speed of thesecond interface circuit 128 is lower than the predetermined value, thememory controller 120 adjusts a number of commands which are finished before the SDB FIS is transmitted (i.e., before operation 230). The specific regulating method will be further illustrated by reference toFIGS. 4A and 4B . Of course, if the comparison result is that the transmission speed of thesecond interface circuit 128 is higher than the predetermined value, thememory controller 120 may increase the number of commands finished before the SDB FIS is transmitted, until the transmission speed is completely optimized. - As shown in
FIG. 4A , thememory controller 120 transmits, by default, the SDB FIS once every N commands (e.g., commands CMD[1]-CMD[N] or commands CMD[N+1]-CMD[2N]) are finished. That is, thememory controller 120 transmits the SDB FIS once every 2N transmission stages (e.g., transmission stages TS[1]-TS[2N] or transmission stages TS[2N+1]-TS[4N]) are finished. - If the transmission speed of the
second interface circuit 128 is determined to be lower than the predetermined value inoperation 250, thememory controller 120 may, as shown inFIG. 4B , switches to transmit the SDB FIS once every M commands (e.g., commands CMD[N+1]-CMD[N+M]) are finished, where M is different from N, and M is a positive integer less than or equal to 32. That is, thememory controller 120 switches to transmit the SDB FIS once at least every 2M transmission stages (e.g., transmission stages TS[2N+1]-TS[2N+2M]) are finished. In this case, whenoperation 230 ofFIG. 2 is conducted again, thememory controller 120 adjusts the number of bits, which are configured to be 1, of the SDB FIS from N to M. Thehost device 110 is then notified to release the addresses corresponding to the M commands (e.g., the commands CMD[N+1]-CMD[N+M]). - The
computer system 100 may execute the memory controlling method ofFIG. 2 for multiple times, so that thememory controller 120 may adaptively optimize the data transmission efficiency according to the configuration of thehost device 110. The aforesaid configuration may be a combination of one or more the following elements of the host device 110: the control circuit architecture of thefirst control circuit 112, the southbridge, the northbridge, the capacity of thefirst memory 116, the advanced host controller interface (AHCI) architecture, the OS, the driver software, and whether the NCQ technology is activated. In an embodiment that thehost device 110 has a slow processing speed or a RAM with small capacity, thecomputer system 100 may reduce the value of N (e.g., adjusting N from 16 to 7) to increase the times thehost device 110 releasing the memory. As a result, the times thehost device 110 required for pausing the data transmission, which is caused by insufficient memory space due to release for too less times, is decreased. In another embodiment that thehost device 110 has sufficient RAM capacity or high processing speed, thecomputer system 100 may increase the value of N (e.g., adjusting N from 16 to 30). As a result, the time period required by thememory controller 120 for transmitting the SDB FISs is reduced, the data transmission efficiency between thehost device 110 and thememory controller 120 is increased, and the processing efficiency of thememory controller 120 is improved. - In addition, after the
memory controller 120 adjusts the value of N, when the value of N is larger than or equal to 2, thememory controller 120 may determine that the host device supports the NCQ technology. Among the various host devices supporting the NCQ technology, however, some of the host devices have higher processing speed regard to the data returned in disorder, while other host devices have higher processing speed regard to the data returned sequentially. -
FIG. 5 is a flow chart of a memory controlling method according to another embodiment of the present disclosure. The memory controlling method ofFIG. 5 enables thememory controller 120 adaptively regulating the return order of data according to the behavior of thehost device 110. In the embodiment ofFIG. 5 , thememory controller 120 executes commands CMD1 and CMD2, and the content of the commands CMD1 and CMD2 are both reading data from thememory module 140. The execution processes of the command CMD1 comprise transmission stages TSa and TSc. The execution processes of the command CMD2 comprise transmission stages TSb and TSd. - In transmission stage TSa, the
host device 110 may transmit the command CMD1 to thememory controller 120 by using the H2D FIS (operation 5102). Thememory controller 120 may respond to thehost device 110 that thecommand CMD 1 is received by using the D2H FIS (operation 5104) Then, in transmission stage TSb, thehost device 110 may transmit the command CMD2 to thememory controller 120 by using the H2D FIS (operation 5202). Thememory controller 120 may respond to thehost device 110 that the command CMD2 is received by using the D2H FIS (operation 5204). - In this embodiment, due to the variation of storage addresses and/or size of data, the
memory controller 120 may, relatively quickly, access the data corresponding to the command CMD2 from thememory module 140, and access, relatively slowly, the data corresponding to the command CMD1. That is, the memory interface circuit Fc may transfer, relatively quickly, the data corresponding to the command CMD2 from thememory module 140 to thesecond memory 126 for transmission (operation 530). - As can be appreciated from the foregoing descriptions, the
memory controller 120 can determines the execution order of multiple commands from thehost device 110, and needs not to execute the multiple commands in an order in which the multiple commands are received. Therefore, thememory controller 120 then conducts transmission stage TSc, so as to transmit the data corresponding to the command CMD2 to thehost device 110. In transmission stage TSc, operations S206 and S208 are respectively similar tooperations FIG. 2 , the difference is that the data FIS corresponding to the command CMD2 is transmitted inoperation 5208. For the sake of brevity, those corresponding descriptions of operations S206 and S208 will not be repeated here. - Then, the memory interface circuit Fc may transfer the data corresponding to the command CMD1 from the
memory module 140 to thesecond memory 126 for transmission (operation 540). Thememory controller 120 then conducts the transmission stage TSd, so as to transmit the data corresponding to the command CMD1 to thehost device 110. In transmission stage TSd,operations operations FIG. 2 , and the difference is that the data FIS CMD1 is transmitted inoperation 5108. For the sake of brevity, those corresponding descriptions ofoperations - In addition,
operation 550 ofFIG. 5 is similar tooperation 230 ofFIG. 2 . For the sake of brevity, those corresponding descriptions ofoperation 550 will not be repeated here. - As aforementioned, the
memory controller 120 may transmit corresponding data without following the receiving order in which the commands CMD1 and CMD2 are received. Thememory controller 120 improves work efficiency by transmitting the data, which is accessed in an earlier order, in advanced. - The two commands CMD1 and CMD2 of
FIG. 5 are merely an exemplary embodiment for illustrating convenience. In practice, in each time the memory controlling method ofFIG. 5 is executed, thecomputer system 100 may finish totally N commands before conductingoperation 550, and N is a positive integer smaller than or equal to 32. In the following paragraphs for continuing to explain the memory controlling method ofFIG. 5 , thememory controller 120 will be assumed to have finished N commands from thehost device 110 before conductingoperation 550. - In
operation 560, thememory controller 120 calculates the transmission speed of thesecond interface circuit 128 by a method similar tooperation 240 ofFIG. 2 . Inoperation 570, thememory controller 120 compares the transmission speed of thesecond interface circuit 128 with a predetermined value. If the transmission speed of thesecond interface circuit 128 is lower than the predetermined value, and the aforementioned N commands comprises i read commands, thememory controller 120 may adjust a transmission sequence of the i data corresponding to the i read commands. - Specifically, the
memory controller 120 may adjust the transmission sequence of the i data from corresponding to a sequence in which the i data are accessed (i.e., the sequence transferring to the second memory 126) to corresponding to a sequence in which the i read commands are received, and I is a positive integer smaller than or equal to N. For example, thememory controller 120 may swap the execution orders of transmission stages TSc and TSd ofFIG. 5 . The detailed regulation method will be further described by reference toFIGS. 6A and 6B . - For the convenience of explanation,
FIGS. 6A and 6B only show read commands CMD[1]-CMD[N] and corresponding transmission stages TS[1]-TS[2N], and the write commands are omitted. AS shown inFIG. 6A , thememory controller 120 transmits, by default, the data accessed in an earlier order in advanced. That is, the transmission sequence in which thememory controller 120 transmits the data FISs is corresponding to a sequence in which the corresponding multiple data are transferred to the second memory 126 (e.g., 3, 1, 2, . . . , N). - If the transmission speed of the
second interface circuit 128 is determined to be lower than the predetermined value inoperation 560, thememory controller 120 may switch the transmission sequence of the data FISs to corresponding to the sequence in which the corresponding read commands are received (i.e., 1, 2, 3, . . . , N). - In one embodiment, since the DMA setup FIS and the data FIS are transmitted in the same transmission stage, the
memory controller 120 may also adjust the transmission sequence of the DMA setup FISs when regulating the transmission sequence of the data FISs. That is, thememory controller 120 may adjust the transmission sequence of the DMA setup FIS from corresponding to a sequence in which the corresponding multiple data are accessed to corresponding to a sequence in which the corresponding read commands are received. - In some embodiments, the
memory controller 120 transmits, by default, the corresponding data FISs and/or DMA setup FISs according to the sequence in which the read commands are received. If the transmission speed of thesecond interface circuit 128 is lower than the predetermined value, thememory controller 120 may switch the transmission sequence of the data FISs and/or the DMA setup FISs to corresponding to the sequence in which the corresponding multiple data are accessed. - In other embodiments, when the transmission speed of the
second interface circuit 128 is higher than the predetermined value, thememory controller 120 may also not to switch the transmission sequence of the data FISs and/or the DMA setup FISs. - Notably, the memory controlling methods of
FIGS. 2 and 5 may be combined with each other.Operation 250 ofFIG. 2 may comprise procedures corresponding tooperation 570 ofFIG. 5 , andoperation 570 ofFIG. 5 may also comprise procedures corresponding tooperation 250 ofFIG. 2 . That is, in some embodiments, the memory controlling method is capable of regulating both of the transmission pattern of the SDB FISs and the transmission sequence of the data FISs of thememory controller 120. - Certain terms are used throughout the description and the claims to refer to particular components. One skilled in the art appreciates that a component may be referred to as different names. This disclosure does not intend to distinguish between components that differ in name but not in function. In the description and in the claims, the term “comprise” is used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to.” The term “couple” is intended to compass any indirect or direct connection. Accordingly, if this disclosure mentioned that a first device is coupled with a second device, it means that the first device may be directly or indirectly connected to the second device through electrical connections, wireless communications, optical communications, or other signal connections with/without other intermediate devices or connection means.
- The term “and/or” may comprise any and all combinations of one or more of the associated listed items. In addition, the singular forms “a,” “an,” and “the” herein are intended to comprise the plural forms as well, unless the context clearly indicates otherwise.
- Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
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US8984182B2 (en) * | 2011-10-06 | 2015-03-17 | Marvell International Ltd. | SCSI I/O command aggregation |
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