US20200096859A1 - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- US20200096859A1 US20200096859A1 US16/196,439 US201816196439A US2020096859A1 US 20200096859 A1 US20200096859 A1 US 20200096859A1 US 201816196439 A US201816196439 A US 201816196439A US 2020096859 A1 US2020096859 A1 US 2020096859A1
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- 238000000034 method Methods 0.000 claims description 33
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- 229910052804 chromium Inorganic materials 0.000 claims description 4
- GALOTNBSUVEISR-UHFFFAOYSA-N molybdenum;silicon Chemical compound [Mo]#[Si] GALOTNBSUVEISR-UHFFFAOYSA-N 0.000 claims description 4
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- G03F7/2002—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image
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- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
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- G03F7/2004—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image characterised by the use of a particular light source, e.g. fluorescent lamps or deep UV light
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- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
- G03F7/2002—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image
- G03F7/2004—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image characterised by the use of a particular light source, e.g. fluorescent lamps or deep UV light
- G03F7/2006—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image characterised by the use of a particular light source, e.g. fluorescent lamps or deep UV light using coherent light; using polarised light
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- G—PHYSICS
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- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
Definitions
- a wafer is provided and several circuitry patterns are formed over the wafer by photolithography operations.
- an electromagnetic radiation is irradiated on the wafer through a mask to pattern a photoresist disposed over the wafer.
- some of electromagnetic energy is absorbed by the mask. Heat is generated and cause thermal distortion of the mask. Such distortion may lead to misalignment between the mask and the wafer.
- FIG. 1 is a schematic top plan view of a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIG. 2 is a schematic cross sectional view of the semiconductor structure along AA′ of FIG. 1 .
- FIG. 3 is a schematic top plan view of a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIG. 4 is a schematic cross sectional view of the semiconductor structure along BB′ of FIG. 3 .
- FIG. 5 is a schematic top plan view of a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIG. 6 is a schematic cross sectional view of the semiconductor structure along CC′ of FIG. 5 .
- FIG. 7 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIGS. 7A-7L are schematic views of manufacturing a semiconductor structure by a method of FIG. 7 in accordance with some embodiments of the present disclosure.
- FIG. 8 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.
- FIGS. 8A-8J are schematic views of manufacturing a semiconductor structure by a method of FIG. 8 in accordance with some embodiments of the present disclosure.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- fin-type field effect transistors FinFETs
- the fins may be patterned to produce a relatively close spacing between features, for which the above disclosure is well suited.
- spacers used in forming fins of FinFETs also referred to as mandrels, can be processed according to the above disclosure.
- the circuitry patterns and the electrical components are formed by photolithography and etching operations.
- An electromagnetic radiation such as ultraviolet or laser is irradiated onto a photoresist over the wafer through a photomask, such that images of circuitry patterns and electrical components on the photomask are transferred to and patterned over the photoresist.
- the patterned photoresist becomes an etch mask.
- the wafer exposed from the patterned photoresist is etched to form the circuitry patterns and electrical components.
- the photomask can be a multi-layer mask (MLM) defined with several regions for patterning more than one layer of the wafer. Each region of a MLM is used to form a different layer on the wafer. By forming multiple regions for different layers on the same mask, the mask production cost is reduced.
- the photomask may absorb some energy of the electromagnetic radiation irradiated onto the photomask and thus generate heat. Since different regions of the photomask involve different materials with different thermal properties (e.g. different coefficient of thermal expansion (CTE), etc.), the photomask may deform and images of circuitry patterns or electrical components over some regions of the photomask are distorted.
- CTE coefficient of thermal expansion
- a material absorbing the electromagnetic radiation is present at an edge region of the photomask, while such material is absent from a central region of the photomask.
- circuitry patterns or electrical components projected from different regions of the photomask to the wafer may be misaligned, and ultimately results in poor electrical connection between circuitries or electrical components formed over the wafer.
- a semiconductor structure is disclosed.
- the semiconductor structure is a photomask, which includes a substrate, a first mask layer disposed over the substrate and including a plurality of first recesses extended through the first mask layer, and a second mask layer disposed over the first mask layer and including a plurality of second recesses extended through the second mask layer.
- the first mask layer is at least partially transparent to a predetermined electromagnetic radiation
- the second mask layer is opaque to the predetermined electromagnetic radiation.
- At least a portion of the second mask layer is disposed between two of the plurality of second recesses.
- FIG. 1 is a schematic top view of a semiconductor structure 100 in accordance with various embodiments of the present disclosure
- FIG. 2 is a schematic cross sectional view of the semiconductor structure 100 along AA′ in FIG. 1
- the semiconductor structure 100 includes a substrate 101 , a first mask layer 102 and a second mask layer 103 .
- the semiconductor structure 100 is a mask or a photomask for photolithography operations.
- the semiconductor structure 100 is a phase shift mask (PSM).
- the semiconductor structure 100 is an attenuated phase shift mask.
- the semiconductor structure 100 includes an image of a circuit feature such as a circuitry pattern, an electrical component, etc., and is configured to project the image of the circuit feature to a semiconductive wafer or a semiconductive substrate upon photolithography operations.
- the semiconductor structure 100 is defined with several regions 110 .
- Each region 110 includes an image of circuit features for different layers of a wafer and is configured to form circuit features over different layers of a wafer.
- the substrate 101 is transparent to a predetermined electromagnetic radiation.
- the substrate 101 allows the predetermined electromagnetic radiation passing through.
- the substrate 101 includes a front side 101 a and a back side 101 b opposite to the front side 101 a .
- the predetermined electromagnetic radiation can transmit from the front side 101 a to the back side 101 b or from the back side 101 b to the front side 101 a .
- the substrate 101 is quartz, fused quartz, glass or other suitable materials.
- the predetermined electromagnetic radiation is ultraviolet (UV), laser, visible light, x-ray, extreme ultraviolet (EUV), deep ultraviolet (DUV), ions beam, electrons beam, etc.
- the predetermined electromagnetic radiation has a wavelength of 365 nm, 248 nm or 193 nm.
- the substrate 101 has a top cross section (a cross section from the top view of the semiconductor structure 100 as shown in FIG. 1 ) in a circular, quadrilateral, rectangular, square or other suitable shapes.
- the first mask layer 102 is disposed over the substrate 101 .
- the first mask layer 102 is disposed over the front side 101 a of the substrate 101 .
- the first mask layer 102 is at least partially transparent to the predetermined electromagnetic radiation.
- the predetermined electromagnetic radiation is ultraviolet (UV), laser, visible light, x-ray, extreme ultraviolet (EUV), deep ultraviolet (DUV), ions beam, electrons beam, etc.
- UV ultraviolet
- EUV extreme ultraviolet
- DUV deep ultraviolet
- ions beam electrons beam
- electrons beam etc.
- about 5% to about 20% of the predetermined electromagnetic radiation is penetrable to the first mask layer 102 .
- about 6% to about 15% of the predetermined electromagnetic radiation is penetrable to the first mask layer 102 .
- the first mask layer 102 includes molybdenum silicon (MoSi).
- a phase of the predetermined electromagnetic radiation passing through the first mask layer 102 is shifted 180° with respect to a phase of the predetermined electromagnetic radiation passing through the substrate 101 upon projection of the predetermined electromagnetic radiation through the first mask layer 102 and the substrate 101 .
- the first mask layer 102 has a thickness such that a certain amount of the predetermined electromagnetic radiation can pass through the first mask layer 102 or a certain amount of the predetermined electromagnetic radiation is blocked by the first mask layer 102 .
- the first mask layer 102 has the thickness such that the phase of the predetermined electromagnetic radiation passing through the first mask layer 102 is shifted 180° with respect to the phase of the predetermined electromagnetic radiation passing through the substrate 101 upon projection of the predetermined electromagnetic radiation through the first mask layer 102 and the substrate 101 .
- the first mask layer 102 includes several first recesses 102 a extended through the first mask layer 102 .
- a portion of the front side 101 a of the substrate 101 is exposed from the first recess 102 a .
- the predetermined electromagnetic radiation can pass through the first recesses 102 a .
- the first recesses 102 a can be projected over a semiconductive substrate or wafer by the predetermined electromagnetic radiation.
- Each of the first recesses 102 a is an image of a circuit feature.
- the first recess 102 a is an image of a trace, a via, a contact, a plug, a trench, etc.
- the first recess 102 a is extended to the substrate 101 .
- the first recess 102 a has a top cross section (a cross section from the top view of the semiconductor structure 100 as shown in FIG. 1 ) in a quadrilateral, rectangular, polygonal or other suitable shapes.
- the first recesses 102 a - 1 and 102 a - 2 are substantially different from each other.
- the first recesses 102 a - 1 and 102 a - 2 are different circuit features.
- the first recesses 102 a - 1 and 102 a - 2 are configured to form the circuit features over different layers of the semiconductive substrate or wafer.
- the semiconductor structure 100 includes several regions 110 .
- the semiconductor structure 100 includes two different regions 110 a and 110 b .
- Each region 110 includes the first recesses 102 a of various shapes and sizes. Only one first recess 102 a is shown for each region 110 in the Figures for simplicity of description.
- the second mask layer 103 is disposed over the first mask layer 102 .
- the second mask layer 103 is in contact with the first mask layer 102 .
- the second mask layer 103 is opaque to the predetermined electromagnetic radiation.
- the predetermined electromagnetic radiation is ultraviolet (UV), laser, visible light, x-ray, extreme ultraviolet (EUV), deep ultraviolet (DUV), ions beam, electrons beam, etc. In some embodiments, about 100% of the predetermined electromagnetic radiation is absorbed or blocked by the second mask layer 103 .
- the second mask layer 103 includes chromium (Cr).
- the second mask layer 103 is a boundary layer surrounding several regions 110 .
- the second mask layer 103 includes several second recesses 103 a extended through the second mask layer 103 .
- the second recesses 103 a are disposed over the first recesses 102 a correspondingly.
- Each region 110 includes the second recess 103 a .
- the predetermined electromagnetic radiation can pass through the second recesses 103 a .
- the first recess 102 a is coupled with the second recess 103 a .
- the second recess 103 a has a top cross section (a cross section from the top view of the semiconductor structure 100 as shown in FIG. 1 ) in a quadrilateral, rectangular, polygonal or other suitable shapes.
- a width W 1 of the second recess 103 a is substantially greater than a width W 3 of the first recess 102 a .
- the width W 1 of the second recesses 103 a are substantially same as each other.
- shapes of the second recesses 103 a are substantially same as each other.
- the width W 1 of the second recess 103 a is about 5 mm to about 15 mm. In some embodiments, the width W 1 of the second recess 103 a is about 8 mm to about 10 mm.
- At least a portion of the second mask layer 103 is disposed between two of second recesses 103 a .
- a portion of the second mask layer 103 is disposed between the second recesses 103 a - 1 and 103 a - 2 .
- Each of the second recesses 103 a is surrounded or enclosed by the second mask layer 103 .
- at least a portion of the first mask layer 102 is disposed between two of the first recesses 102 a
- the portion of the second mask layer 103 is disposed over the portion of the first mask layer 102 .
- the portion of the second mask layer 103 disposed between the second recesses 103 a - 1 and 103 a - 2 is disposed over the portion of the first mask layer 102 disposed between the first recesses 102 a - 1 and 102 a - 2 .
- a ratio of a width W 2 of the portion of the second mask layer to the width W 1 of the second recess 103 a is substantially greater than or equal to 0.001. In some embodiments, the width W 2 of the second mask layer 103 surrounding each second recess 103 a is substantially consistent. In some embodiments, the width W 2 of the second mask layer 103 is about 50 um to about 70 um. In some embodiments, the width W 2 of the second mask layer 103 is about 60 um.
- FIG. 3 is a schematic top view of a semiconductor structure 200 in accordance with various embodiments of the present disclosure
- FIG. 4 is a schematic cross sectional view of the semiconductor structure 200 along BB′ in FIG. 3
- the semiconductor structure 200 is a photomask, which includes a substrate 101 , a first mask layer 102 and a second mask layer 103 , which have similar configurations as described above or illustrated in FIG. 1 or 2 .
- the semiconductor structure 200 is defined with several regions 110 .
- the semiconductor structure 200 is defined with four regions 110 a , 110 b , 110 c and 110 d .
- Each region 110 includes the first recesses 102 a of various shapes and sizes. Only one first recess 102 a is shown for each region 110 in the Figures for simplicity of description.
- the first mask layer 102 includes four first recesses 102 a - 1 , 102 a - 2 , 102 a - 3 and 102 a - 4
- the second mask layer 103 includes four second recesses 103 a - 1 , 103 a - 2 , 103 a - 3 and 103 a - 4 .
- Each of the first recesses 102 a - 1 , 102 a - 2 , 102 a - 3 and 102 a - 4 is an image of a circuit feature.
- the first recesses 102 a - 1 , 102 a - 2 , 102 a - 3 and 102 a - 4 are substantially different from each other.
- the first recesses 102 a - 1 , 102 a - 2 , 102 a - 3 and 102 a - 4 are four different circuit features.
- the first recesses 102 a - 1 , 102 a - 2 , 102 a - 3 and 102 a - 4 can be projected over a semiconductive substrate or wafer by the predetermined electromagnetic radiation.
- the first recesses 102 a - 1 , 102 a - 2 , 102 a - 3 and 102 a - 4 are configured to form the circuit features over different layers of a semiconductive substrate or wafer.
- each of the second recesses 103 a - 1 , 103 a - 2 , 103 a - 3 and 103 a - 4 surrounds the corresponding first recesses 102 a - 1 , 102 a - 2 , 102 a - 3 and 102 a - 4 .
- each region 110 is surrounded or enclosed by the second mask layer 103 .
- FIG. 5 is a schematic top view of a semiconductor structure 300 in accordance with various embodiments of the present disclosure
- FIG. 6 is a schematic cross sectional view of the semiconductor structure 300 along CC′ in FIG. 5
- the semiconductor structure 300 is a photomask which includes a substrate 101 , a first mask layer 102 and a second mask layer 103 , which have similar configurations as described above or illustrated in FIG. 1 or 2 .
- the semiconductor structure 300 is defined with several regions 110 .
- the semiconductor structure 300 is defined with nine regions 110 a , 110 b , 110 c , 110 d , 110 e , 110 f , 110 g , 110 h and 110 i .
- Each region 110 includes the first recesses 102 a of various shapes and sizes. Only one first recess 102 a is shown for each region 110 in the Figures for simplicity of description.
- the first mask layer 102 includes nine first recesses 102 a - 1 , 102 a - 2 , 102 a - 3 , 102 a - 4 , 102 a - 5 , 102 a - 6 , 102 a - 7 , 102 a - 8 and 102 a - 9
- the second mask layer 103 includes nine second recesses 103 a - 1 , 103 a - 2 , 103 a - 3 , 103 a - 4 , 103 a - 5 , 103 a - 6 , 103 a - 7 , 103 a - 8 and 103 a - 9 .
- each of the first recesses 102 a - 1 , 102 a - 2 , 102 a - 3 , 102 a - 4 , 102 a - 5 , 102 a - 6 , 102 a - 7 , 102 a - 8 and 102 a - 9 is an image of a circuit feature.
- the first recesses 102 a - 1 , 102 a - 2 , 102 a - 3 , 102 a - 4 , 102 a - 5 , 102 a - 6 , 102 a - 7 , 102 a - 8 , 102 a - 9 are substantially different from each other.
- the first recesses 102 a - 1 , 102 a - 2 , 102 a - 3 , 102 a - 4 , 102 a - 5 , 102 a - 6 , 102 a - 7 , 102 a - 8 and 102 a - 9 are nine different circuit features.
- the first recesses 102 a - 1 , 102 a - 2 , 102 a - 3 , 102 a - 4 , 102 a - 5 , 102 a - 6 , 102 a - 7 , 102 a - 8 and 102 a - 9 are configured to form the circuitry pattern, the electrical component or the circuit feature over different layers of a semiconductive substrate or wafer.
- Each of the second recesses 103 a - 1 , 103 a - 2 , 103 a - 3 , 103 a - 4 , 103 a - 5 , 103 a - 6 , 103 a - 7 , 103 a - 8 and 103 a - 9 includes an image of a circuit feature.
- the second recesses 103 a - 1 , 103 a - 2 , 103 a - 3 , 103 a - 4 , 103 a - 5 , 103 a - 6 , 103 a - 7 , 103 a - 8 and 103 a - 9 are configured to form images of circuit features over different layers of a semiconductive substrate or wafer.
- the second recesses 103 a - 1 , 103 a - 2 , 103 a - 3 , 103 a - 4 , 103 a - 5 , 103 a - 6 , 103 a - 7 , 103 a - 8 and 103 a - 9 are configured to form images of circuit features over nine different layers of a semiconductive substrate or wafer.
- each of the second recesses 103 a - 1 , 103 a - 2 , 103 a - 3 , 103 a - 4 , 103 a - 5 , 103 a - 6 , 103 a - 7 , 103 a - 8 and 103 a - 9 surrounds the corresponding first recesses 102 a - 1 , 102 a - 2 , 102 a - 3 , 102 a - 4 , 102 a - 5 , 102 a - 6 , 102 a - 7 , 102 a - 8 , 102 a - 9 .
- each region 110 is surrounded or enclosed by the second mask layer 103 .
- a method of manufacturing a semiconductor structure 100 , 200 or 300 is also disclosed.
- a semiconductor structure 100 , 200 or 300 is formed by a method 400 .
- the method 400 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations.
- FIG. 7 is an embodiment of the method 400 of manufacturing the semiconductor structure 100 , 200 or 300 .
- the method 400 includes a number of operations ( 401 , 402 , 403 , 404 , 405 , 406 , 407 , 408 , 409 , 410 and 411 ).
- a substrate 101 is provided or received as shown in FIG. 7A .
- the substrate 101 is transparent to a predetermined electromagnetic radiation.
- the substrate 101 includes a front side 101 a and a back side 101 b opposite to the front side 101 a .
- the predetermined electromagnetic radiation can transmit from the front side 101 a to the back side 101 b or from the back side 101 b to the front side 101 a .
- the substrate 101 includes quartz, fused quartz, glass or other suitable materials.
- the predetermined electromagnetic radiation is ultraviolet (UV), laser, visible light, x-ray, extreme ultraviolet (EUV), deep ultraviolet (DUV), ions beam, electrons beam, etc.
- the substrate 101 has similar configuration as described above or illustrated in FIGS. 1-6 .
- a first mask layer 102 is disposed over the substrate 101 as shown in FIG. 7B .
- the first mask layer 102 is disposed over the front side 101 a of the substrate 101 .
- the first mask layer 102 is at least partially transparent to the predetermined electromagnetic radiation.
- the first mask layer 102 includes molybdenum silicon (MoSi).
- the first mask layer 102 is disposed by spin coating, sputtering, chemical vapor deposition (CVD) or any other suitable operations.
- the first mask layer 102 has similar configuration as described above or illustrated in FIGS. 1-6 .
- a first photoresist 104 is disposed over the first mask layer 102 as shown in FIG. 7C .
- the first photoresist 104 is coated on the first mask layer 102 .
- the first photoresist 104 is a light sensitive material with chemical properties depending on an exposure of an electromagnetic radiation.
- the first photoresist 104 is sensitive to an electromagnetic radiation such as an ultra violet (UV), that the chemical properties of the first photoresist 104 are changed upon exposure to the electromagnetic radiation.
- the first photoresist 104 is disposed over the first mask layer 102 by spin coating or any other suitable operations.
- the first photoresist 104 is patterned to form several first openings 104 a as shown in FIG. 7D .
- the first photoresist 104 is patterned by removing portions of the first photoresist 104 .
- some portions of the first photoresist 104 are exposed to the electromagnetic radiation, and those exposed portions are dissolvable by a developer solution while those unexposed portions are not dissolvable by the developer solution.
- the first photoresist 104 is patterned after removal of the exposed portions of the first photoresist 104 .
- the first openings 104 a are formed after removal of the exposed portions of the first photoresist 104 .
- some portions of the first mask layer 102 are exposed from the first photoresist 104 by the first openings 104 a.
- portions of the first mask layer 102 exposed from the first photoresist 104 are removed to form several first recesses 102 a as shown in FIG. 7E .
- the first openings 104 a correspond to the first recesses 102 a respectively.
- the first recesses 102 a are extended through the first mask layer 102 .
- the portions of the first mask layer 102 exposed from the first photoresist 104 are removed by suitable etching operation such as plasma etching, an anisotropic dry etching, a reactive ion etching (RIE), a dry etching or etc.
- the first photoresist 104 is removed as shown in FIG. 7F .
- the first photoresist 104 is removed by suitable photoresist stripping technique, such as chemical solvent cleaning, plasma ashing, dry stripping and/or the like.
- a second mask layer 103 is disposed over the first mask layer 102 as shown in FIG. 7G .
- the second mask layer 103 is opaque to the predetermined electromagnetic radiation.
- the second mask layer 103 includes chromium (Cr).
- the second mask layer 103 is disposed by spin coating, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD) or any other suitable operations.
- the second mask layer 103 has similar configuration as described above or illustrated in FIGS. 1-6 .
- a second photoresist 105 is disposed over the second mask layer 103 as shown in FIG. 7H .
- the second photoresist 105 is coated on the second mask layer 103 .
- the second photoresist 105 is a light sensitive material with chemical properties depending on an exposure of an electromagnetic radiation.
- the second photoresist 105 is sensitive to an electromagnetic radiation such as an ultra violet (UV), that the chemical properties of the second photoresist 105 are changed upon exposure to the electromagnetic radiation.
- the second photoresist 105 is disposed over the second mask layer 103 by spin coating or any other suitable operations.
- the second photoresist 105 is patterned to form several second openings 105 a as shown in FIG. 7I .
- the second photoresist 105 is patterned by removing portions of the second photoresist 105 .
- some portions of the second photoresist 105 are exposed to the electromagnetic radiation, and those exposed portions are dissolvable by a developer solution while those unexposed portions are not dissolvable by the developer solution.
- the second photoresist 105 is patterned after removal of the exposed portions of the second photoresist 105 .
- the second openings 105 a are formed after removal of the exposed portions of the second photoresist 105 .
- the second opening 105 a of the second photoresist 105 is substantially greater than the first opening 104 a of the first photoresist 104 .
- a width W 4 of one of the second openings 105 a is about 5 mm to about 15 mm. In some embodiments, the width W 4 is about 8 mm to about 10 mm. In some embodiments, a width W 5 of a portion of the second photoresist 105 disposed between two of the second openings 105 a is about 50 um to about 70 um. In some embodiments, the width W 5 is about 60 um. In some embodiments, a ratio of the width W 5 of the second photoresist 105 disposed between two of the second openings 105 a to the width W 4 of one of the second openings 105 a is substantially greater than or equal to 0.001.
- the portions of the second mask layer 103 exposed from the second photoresist 105 are removed to for several second recesses 103 a as shown in FIGS. 7J and 7 K.
- the second openings 105 a correspond to the second recesses 103 a respectively.
- the second mask layer 103 is defined with several regions 110 . Each region 110 includes at least one of the first recesses 102 a .
- the second mask layer 103 is a boundary layer.
- the second recesses 103 a are formed one by one. For example, the left portion of the second mask layer 103 is removed first to form one of the second recesses 103 a as shown in FIG.
- the second recesses 103 a are extended through the second mask layer 103 .
- the portions of the second mask layer 103 exposed from the second photoresist 105 are removed by suitable etching operation such as wet etching, plasma etching, an anisotropic dry etching, a reactive ion etching (RIE), a dry etching or etc.
- the second photoresist 105 is removed as shown in FIG. 7L .
- the second photoresist 105 is removed by suitable photoresist stripping technique, such as chemical solvent cleaning, plasma ashing, dry stripping and/or the like.
- suitable photoresist stripping technique such as chemical solvent cleaning, plasma ashing, dry stripping and/or the like.
- a semiconductor structure 100 , 200 or 300 as shown in FIGS. 1-6 is formed.
- the semiconductor structure 100 , 200 or 300 is a multi-layer mask (MLM) configured for photolithography operations.
- MLM multi-layer mask
- a method of manufacturing a semiconductor structure is also disclosed.
- a semiconductor structure is formed by a method 500 .
- the method 500 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations.
- FIG. 8 is an embodiment of the method 500 of manufacturing the semiconductor structure.
- the method 500 includes a number of operations ( 501 , 502 , 503 , 504 and 505 ).
- a photomask 100 is formed or provided as shown in FIG. 8A .
- the photomask 100 is formed by the method 400 described above.
- the photomask 100 includes a first substrate 101 , a first mask layer 102 and a second mask layer 103 .
- the photomask 100 is defined with several regions 110 .
- the first mask layer 102 includes several first recesses 102 a
- the second mask layer 103 includes several second recesses 103 a .
- the first recesses 102 a - 1 and 102 a - 2 are different circuit features.
- the first recesses 102 a - 1 and 102 a - 2 can be projected over a semiconductive substrate or wafer by a predetermined electromagnetic radiation.
- the first recesses 102 a - 1 and 102 a - 2 are configured to form circuit features over different layers of a semiconductive substrate or wafer.
- At least a portion of the second mask layer 103 is disposed between two of the second recesses 103 s .
- the photomask 100 has similar configurations as the semiconductor structure 100 , 200 or 300 described above and shown in FIGS. 1-6 .
- a second substrate 106 is provided or received as shown in FIG. 8B .
- the second substrate 106 includes semiconductive materials such as silicon or other suitable materials.
- the second substrate 106 is a wafer.
- the second substrate 106 is a silicon substrate or silicon wafer.
- the second substrate 106 includes glass or ceramic.
- the second substrate 106 is a glass substrate.
- a third photoresist 107 is disposed over the second substrate 106 as shown in FIG. 8C .
- the third photoresist 107 is a light sensitive material with chemical properties depending on an exposure of an electromagnetic radiation.
- the third photoresist 107 is sensitive to an electromagnetic radiation such as an ultra violet (UV), that the chemical properties of the third photoresist 107 are changed upon exposure to the electromagnetic radiation.
- the third photoresist 107 is disposed over the second substrate 106 by spin coating or any other suitable operations.
- a predetermined electromagnetic radiation is projected through the photomask 100 towards the third photoresist 107 to pattern the third photoresist 107 as shown in FIG. 8D .
- the second recess 103 a - 1 of the second mask layer 103 is aligned with a predetermined position of the third photoresist 107 .
- the predetermined electromagnetic radiation is irradiated from a source 108 .
- the predetermined electromagnetic radiation is ultraviolet (UV), laser, visible light, x-ray, extreme ultraviolet (EUV), deep ultraviolet (DUV), ions beam, electrons beam, etc.
- the first mask layer 102 is at least partially transparent to the predetermined electromagnetic radiation
- the second mask layer 103 is opaque to the predetermined electromagnetic radiation.
- the predetermined electromagnetic radiation can pass through the first substrate 101 and the first recesses 102 a to the third photoresist 107 , such that an image of the first recesses 102 a can be projected over the third photoresist 107 to pattern the third photoresist 107 .
- a phase of the predetermined electromagnetic radiation passing through the first mask layer 102 is shifted 180° with respect to a phase of the predetermined electromagnetic radiation passing through the first substrate 101 upon the projection of the predetermined electromagnetic radiation, such that a quality of the image of the first recesses 102 a projected over the third photoresist 107 is increased or improved.
- the photomask 100 or the first recess 102 a - 1 is aligned with the third photoresist 107 or the second substrate 106 , such that the image of the first recess 102 a - 1 can be projected over a predetermined position of the third photoresist 107 .
- the third photoresist 107 is patterned by removing portions of the third photoresist 107 . In some embodiments, some portions of the third photoresist 107 are exposed to the predetermined electromagnetic radiation, and those exposed portions are dissolvable by a developer solution while those unexposed portions are not dissolvable by the developer solution.
- the third photoresist 107 is patterned after removal of the exposed portions of the third photoresist 107 .
- portions of the second substrate 106 exposed from the third photoresist 107 are removed as shown in FIG. 8E .
- the portions of the second substrate 106 exposed from the third photoresist 107 correspond to the first recesses 102 a respectively.
- the portion of the second substrate 106 corresponding to the first recess 102 a - 1 is removed, such that a circuit feature corresponding to the first recess 102 a - 1 is formed over a first layer of the second substrate 106 .
- the third photoresist 107 is removed as shown in FIG. 8F after the formation of the first recess 102 a - 1 over the second substrate 106 .
- the first recess 102 a - 1 is formed over a second layer of the second substrate 106 as shown in FIGS. 8G-8J .
- a fourth photoresist 109 is disposed over the second substrate 106 as shown in FIG. 8G .
- the fourth photoresist 109 has similar configurations as the third photoresist 107 .
- the photomask 100 is moved to project an image of the first recess 102 a - 2 over the fourth photoresist 109 to form a circuit feature corresponding to the first recess 102 a - 2 over a second layer of the second substrate 106 as shown in FIG. 8H .
- the photomask 100 is moved such that the second recess 103 a - 2 of the second mask layer 103 is aligned with a predetermined position of the second substrate 106 .
- the second recesses 103 a - 1 and 103 a - 2 are heated by the predetermined electromagnetic radiation upon projection of the predetermined electromagnetic radiation through the photomask 100 .
- heat expansion of the second recesses 103 a - 1 is substantially the same as heat expansion of the second recess 103 a - 2 , since the second mask layer 103 surrounds both of the second recesses 103 a - 1 and 103 a - 2 .
- a position of the second recess 103 a - 1 as shown in FIG. 8D is vertically aligned with a position of the second recess 103 a - 2 as shown in FIG. 8H .
- the source 108 irradiates the predetermined electromagnetic radiation through the second recess 103 a - 2 towards the fourth photoresist 109 to project the first recess 102 a - 2 over the fourth photoresist 109 .
- the fourth photoresist 109 is patterned by removing a portion of the fourth photoresist 109 exposed to the predetermined electromagnetic radiation.
- a portion of the second substrate 106 exposed from the fourth photoresist 109 is removed as shown in FIG. 8I .
- the first recess 102 a - 2 is formed over the second layer of the second substrate 106 .
- the fourth photoresist 109 is removed after the formation of the first recess 102 a - 2 .
- a semiconductor structure in the present disclosure, includes a substrate, a first mask layer disposed over the substrate and including a plurality of first recesses extended through the first mask layer, and a second mask layer disposed over the first mask layer and including a plurality of second recesses extended through the second mask layer. At least a portion of the second mask layer is disposed between two of the plurality of second recesses. As such, each region defined over the semiconductor structure is surrounded by the second mask layer, and thermal stress around each region upon photolithography operations is substantially consistent. Therefore, alignment between regions of the semiconductor structure is improved, and quality of formation of circuit feature over a semiconductive substrate or wafer by the semiconductor structure is also improved.
- a method of manufacturing a semiconductor structure includes providing a mask including a first substrate; a first mask layer disposed over the first substrate, including a plurality of first recesses extended through the first mask layer; a second mask layer disposed over the first mask layer and including a plurality of second recesses extended through the second mask layer; providing a second substrate including a photoresist disposed over the second substrate; and projecting a predetermined electromagnetic radiation through the mask towards the photoresist, wherein the first mask layer is at least partially transparent to the predetermined electromagnetic radiation, the second mask layer is opaque to the predetermined electromagnetic radiation, and at least a portion of the second mask layer is disposed between two of the plurality of second recesses.
- At least a portion of the first mask layer is disposed between two of the plurality of first recesses, and the portion of the second mask layer is disposed over the portion of the first mask layer.
- a ratio of a width of the portion of the second mask layer to a width of one of the plurality of second recesses is substantially greater than or equal to 0.001.
- a width of one of the plurality of second recesses is substantially greater than a width of one of the plurality of first recesses.
- a width of one of the plurality of second recesses is about 5 mm to about 15 mm.
- a width of the portion of the second mask layer disposed between two of the plurality of second recesses is about 50 um to about 70 um.
- the first mask layer includes molybdenum silicon (MoSi).
- the second mask layer includes chromium (Cr).
- the substrate is transparent to the predetermined electromagnetic radiation.
- the substrate includes quartz.
- about 5% to about 20% of the predetermined electromagnetic radiation is penetrable to the first mask layer.
- the predetermined electromagnetic radiation is an ultraviolet (UV) or laser.
- a method of manufacturing a semiconductor structure includes providing a substrate; disposing a first mask layer over the substrate; disposing a first photoresist over the first mask layer; patterning the first photoresist to form a plurality of first openings; removing portions of the first mask layer exposed from the first photoresist to form a plurality of first recesses extended through the first mask layer; removing the first photoresist; disposing a second mask layer over the first mask layer; disposing a second photoresist over the second mask layer; patterning the second photoresist to form a plurality of second openings; removing portions of the second mask layer exposed from the second photoresist to form a plurality of regions over the substrate; and removing the second photoresist, wherein each of the plurality of regions includes at least one of the plurality of first recesses, the first mask layer is at least partially transparent to a predetermined electromagnetic radiation, the second mask layer is opaque to the predetermined electromagnetic radiation, and at least a portion of the second
- the patterning of the first photoresist includes removing portions of the first photoresist, or the patterning of the second photoresist includes removing portions of the second photoresist.
- a width of one of the plurality of second openings is about 5 mm to about 15 mm.
- a ratio of a width of a portion of the second photoresist disposed between two of the plurality of second openings to a width of one of the plurality of second openings is substantially greater than or equal to 0.001.
- one of the plurality of second openings is substantially greater than one of the plurality of first openings.
- a method of manufacturing a semiconductor structure includes forming a photomask including providing a first substrate; forming a first mask layer over the first substrate, wherein the first mask layer includes a plurality of first recesses extended through the first layer; forming a second mask layer over the first mask layer, wherein the second mask layer includes a plurality of regions over the first substrate; providing a second substrate; disposing a photoresist over the second substrate; projecting a predetermined electromagnetic radiation through the photomask towards the photoresist to pattern the photoresist; and removing portions of the second substrate exposed from the photoresist, wherein each of the plurality of regions includes at least one of the plurality of first recesses, the first mask layer is at least partially transparent to the predetermined electromagnetic radiation, the second mask layer is opaque to the predetermined electromagnetic radiation, and at least a portion of the second mask layer is disposed between two of the plurality of regions.
- a phase of the predetermined electromagnetic radiation passing through the first mask layer is shifted 180° with respect to a phase of the predetermined electromagnetic radiation passing through the first substrate upon the projection of the predetermined electromagnetic radiation.
- the portions of the second substrate exposed from the photoresist correspond to the plurality of first recesses respectively.
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Abstract
Description
- This application claims the benefit of a provisional application Ser. 62/734,037 filed on Sep. 20, 2018, entitled “SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF,” the disclosure of which is hereby incorporated by reference in its entirety.
- Electronic equipments using semiconductor devices are essential for many modern applications. With the advancement of electronic technology, the semiconductor device is becoming increasingly smaller in size and having greater functionality and greater amounts of integrated circuitry. The manufacturing operations of the semiconductor device involve many steps and operations on such a small and thin semiconductor device.
- During the manufacturing of the semiconductor device, a wafer is provided and several circuitry patterns are formed over the wafer by photolithography operations. Upon the photolithography operations, an electromagnetic radiation is irradiated on the wafer through a mask to pattern a photoresist disposed over the wafer. However, some of electromagnetic energy is absorbed by the mask. Heat is generated and cause thermal distortion of the mask. Such distortion may lead to misalignment between the mask and the wafer.
- As such, there is a continuous need to modify and improve the manufacturing operations of the semiconductor device.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
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FIG. 1 is a schematic top plan view of a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIG. 2 is a schematic cross sectional view of the semiconductor structure along AA′ ofFIG. 1 . -
FIG. 3 is a schematic top plan view of a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIG. 4 is a schematic cross sectional view of the semiconductor structure along BB′ ofFIG. 3 . -
FIG. 5 is a schematic top plan view of a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIG. 6 is a schematic cross sectional view of the semiconductor structure along CC′ ofFIG. 5 . -
FIG. 7 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIGS. 7A-7L are schematic views of manufacturing a semiconductor structure by a method ofFIG. 7 in accordance with some embodiments of the present disclosure. -
FIG. 8 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. -
FIGS. 8A-8J are schematic views of manufacturing a semiconductor structure by a method ofFIG. 8 in accordance with some embodiments of the present disclosure. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- The advanced lithography process, method, and materials described above can be used in many applications, including fin-type field effect transistors (FinFETs). For example, the fins may be patterned to produce a relatively close spacing between features, for which the above disclosure is well suited. In addition, spacers used in forming fins of FinFETs, also referred to as mandrels, can be processed according to the above disclosure.
- In a semiconductor wafer, the circuitry patterns and the electrical components are formed by photolithography and etching operations. An electromagnetic radiation such as ultraviolet or laser is irradiated onto a photoresist over the wafer through a photomask, such that images of circuitry patterns and electrical components on the photomask are transferred to and patterned over the photoresist. The patterned photoresist becomes an etch mask. The wafer exposed from the patterned photoresist is etched to form the circuitry patterns and electrical components.
- The photomask can be a multi-layer mask (MLM) defined with several regions for patterning more than one layer of the wafer. Each region of a MLM is used to form a different layer on the wafer. By forming multiple regions for different layers on the same mask, the mask production cost is reduced. Upon photolithography operations, the photomask may absorb some energy of the electromagnetic radiation irradiated onto the photomask and thus generate heat. Since different regions of the photomask involve different materials with different thermal properties (e.g. different coefficient of thermal expansion (CTE), etc.), the photomask may deform and images of circuitry patterns or electrical components over some regions of the photomask are distorted. For example, a material absorbing the electromagnetic radiation is present at an edge region of the photomask, while such material is absent from a central region of the photomask. As such, circuitry patterns or electrical components projected from different regions of the photomask to the wafer may be misaligned, and ultimately results in poor electrical connection between circuitries or electrical components formed over the wafer.
- In the present disclosure, a semiconductor structure is disclosed. The semiconductor structure is a photomask, which includes a substrate, a first mask layer disposed over the substrate and including a plurality of first recesses extended through the first mask layer, and a second mask layer disposed over the first mask layer and including a plurality of second recesses extended through the second mask layer. The first mask layer is at least partially transparent to a predetermined electromagnetic radiation, and the second mask layer is opaque to the predetermined electromagnetic radiation. At least a portion of the second mask layer is disposed between two of the plurality of second recesses. As such, each region defined over the semiconductor structure is surrounded by the second mask layer, and thermal stress around each region upon photolithography operations is substantially consistent. Therefore, alignment between regions of the semiconductor structure is improved, and quality of formation of circuit feature over a semiconductive substrate or wafer by the semiconductor structure is also improved.
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FIG. 1 is a schematic top view of asemiconductor structure 100 in accordance with various embodiments of the present disclosure, andFIG. 2 is a schematic cross sectional view of thesemiconductor structure 100 along AA′ inFIG. 1 . In some embodiments, thesemiconductor structure 100 includes asubstrate 101, afirst mask layer 102 and asecond mask layer 103. Thesemiconductor structure 100 is a mask or a photomask for photolithography operations. In some embodiments, thesemiconductor structure 100 is a phase shift mask (PSM). In some embodiments, thesemiconductor structure 100 is an attenuated phase shift mask. Thesemiconductor structure 100 includes an image of a circuit feature such as a circuitry pattern, an electrical component, etc., and is configured to project the image of the circuit feature to a semiconductive wafer or a semiconductive substrate upon photolithography operations. Thesemiconductor structure 100 is defined withseveral regions 110. Eachregion 110 includes an image of circuit features for different layers of a wafer and is configured to form circuit features over different layers of a wafer. - The
substrate 101 is transparent to a predetermined electromagnetic radiation. Thesubstrate 101 allows the predetermined electromagnetic radiation passing through. In some embodiments, thesubstrate 101 includes afront side 101 a and aback side 101 b opposite to thefront side 101 a. In some embodiments, the predetermined electromagnetic radiation can transmit from thefront side 101 a to theback side 101 b or from theback side 101 b to thefront side 101 a. In some embodiments, thesubstrate 101 is quartz, fused quartz, glass or other suitable materials. In some embodiments, the predetermined electromagnetic radiation is ultraviolet (UV), laser, visible light, x-ray, extreme ultraviolet (EUV), deep ultraviolet (DUV), ions beam, electrons beam, etc. In some embodiments, the predetermined electromagnetic radiation has a wavelength of 365 nm, 248 nm or 193 nm. Thesubstrate 101 has a top cross section (a cross section from the top view of thesemiconductor structure 100 as shown inFIG. 1 ) in a circular, quadrilateral, rectangular, square or other suitable shapes. - The
first mask layer 102 is disposed over thesubstrate 101. In some embodiments, thefirst mask layer 102 is disposed over thefront side 101 a of thesubstrate 101. Thefirst mask layer 102 is at least partially transparent to the predetermined electromagnetic radiation. In some embodiments, the predetermined electromagnetic radiation is ultraviolet (UV), laser, visible light, x-ray, extreme ultraviolet (EUV), deep ultraviolet (DUV), ions beam, electrons beam, etc. In some embodiments, about 5% to about 20% of the predetermined electromagnetic radiation is penetrable to thefirst mask layer 102. In some embodiments, about 6% to about 15% of the predetermined electromagnetic radiation is penetrable to thefirst mask layer 102. In some embodiments, thefirst mask layer 102 includes molybdenum silicon (MoSi). - A phase of the predetermined electromagnetic radiation passing through the
first mask layer 102 is shifted 180° with respect to a phase of the predetermined electromagnetic radiation passing through thesubstrate 101 upon projection of the predetermined electromagnetic radiation through thefirst mask layer 102 and thesubstrate 101. In some embodiments, thefirst mask layer 102 has a thickness such that a certain amount of the predetermined electromagnetic radiation can pass through thefirst mask layer 102 or a certain amount of the predetermined electromagnetic radiation is blocked by thefirst mask layer 102. In some embodiments, thefirst mask layer 102 has the thickness such that the phase of the predetermined electromagnetic radiation passing through thefirst mask layer 102 is shifted 180° with respect to the phase of the predetermined electromagnetic radiation passing through thesubstrate 101 upon projection of the predetermined electromagnetic radiation through thefirst mask layer 102 and thesubstrate 101. - The
first mask layer 102 includes severalfirst recesses 102 a extended through thefirst mask layer 102. A portion of thefront side 101 a of thesubstrate 101 is exposed from thefirst recess 102 a. In some embodiments, the predetermined electromagnetic radiation can pass through thefirst recesses 102 a. The first recesses 102 a can be projected over a semiconductive substrate or wafer by the predetermined electromagnetic radiation. Each of thefirst recesses 102 a is an image of a circuit feature. In some embodiments, thefirst recess 102 a is an image of a trace, a via, a contact, a plug, a trench, etc. In some embodiments, thefirst recess 102 a is extended to thesubstrate 101. Thefirst recess 102 a has a top cross section (a cross section from the top view of thesemiconductor structure 100 as shown inFIG. 1 ) in a quadrilateral, rectangular, polygonal or other suitable shapes. In some embodiments, thefirst recesses 102 a-1 and 102 a-2 are substantially different from each other. In some embodiments, thefirst recesses 102 a-1 and 102 a-2 are different circuit features. In some embodiments, thefirst recesses 102 a-1 and 102 a-2 are configured to form the circuit features over different layers of the semiconductive substrate or wafer. Thesemiconductor structure 100 includesseveral regions 110. In some embodiments, thesemiconductor structure 100 includes twodifferent regions region 110 includes thefirst recesses 102 a of various shapes and sizes. Only onefirst recess 102 a is shown for eachregion 110 in the Figures for simplicity of description. - The
second mask layer 103 is disposed over thefirst mask layer 102. In some embodiments, thesecond mask layer 103 is in contact with thefirst mask layer 102. Thesecond mask layer 103 is opaque to the predetermined electromagnetic radiation. In some embodiments, the predetermined electromagnetic radiation is ultraviolet (UV), laser, visible light, x-ray, extreme ultraviolet (EUV), deep ultraviolet (DUV), ions beam, electrons beam, etc. In some embodiments, about 100% of the predetermined electromagnetic radiation is absorbed or blocked by thesecond mask layer 103. In some embodiments, thesecond mask layer 103 includes chromium (Cr). - In some embodiments, the
second mask layer 103 is a boundary layer surroundingseveral regions 110. Thesecond mask layer 103 includes severalsecond recesses 103 a extended through thesecond mask layer 103. In some embodiments, thesecond recesses 103 a are disposed over thefirst recesses 102 a correspondingly. In A portion of thefront side 101 a of thesubstrate 101 is exposed from thesecond recesses 103 a. Eachregion 110 includes thesecond recess 103 a. In some embodiments, the predetermined electromagnetic radiation can pass through thesecond recesses 103 a. In some embodiments, thefirst recess 102 a is coupled with thesecond recess 103 a. In some embodiments, at least a portion of thefirst mask layer 102 is exposed from thesecond recess 103 a. Thesecond recess 103 a has a top cross section (a cross section from the top view of thesemiconductor structure 100 as shown inFIG. 1 ) in a quadrilateral, rectangular, polygonal or other suitable shapes. - A width W1 of the
second recess 103 a is substantially greater than a width W3 of thefirst recess 102 a. In some embodiments, the width W1 of thesecond recesses 103 a are substantially same as each other. In some embodiments, shapes of thesecond recesses 103 a are substantially same as each other. In some embodiments, the width W1 of thesecond recess 103 a is about 5 mm to about 15 mm. In some embodiments, the width W1 of thesecond recess 103 a is about 8 mm to about 10 mm. - At least a portion of the
second mask layer 103 is disposed between two ofsecond recesses 103 a. For example, a portion of thesecond mask layer 103 is disposed between thesecond recesses 103 a-1 and 103 a-2. Each of thesecond recesses 103 a is surrounded or enclosed by thesecond mask layer 103. In some embodiments, at least a portion of thefirst mask layer 102 is disposed between two of thefirst recesses 102 a, and the portion of thesecond mask layer 103 is disposed over the portion of thefirst mask layer 102. In some embodiments, the portion of thesecond mask layer 103 disposed between thesecond recesses 103 a-1 and 103 a-2 is disposed over the portion of thefirst mask layer 102 disposed between thefirst recesses 102 a-1 and 102 a-2. - In some embodiments, a ratio of a width W2 of the portion of the second mask layer to the width W1 of the
second recess 103 a is substantially greater than or equal to 0.001. In some embodiments, the width W2 of thesecond mask layer 103 surrounding eachsecond recess 103 a is substantially consistent. In some embodiments, the width W2 of thesecond mask layer 103 is about 50 um to about 70 um. In some embodiments, the width W2 of thesecond mask layer 103 is about 60 um. -
FIG. 3 is a schematic top view of asemiconductor structure 200 in accordance with various embodiments of the present disclosure, andFIG. 4 is a schematic cross sectional view of thesemiconductor structure 200 along BB′ inFIG. 3 . Thesemiconductor structure 200 is a photomask, which includes asubstrate 101, afirst mask layer 102 and asecond mask layer 103, which have similar configurations as described above or illustrated inFIG. 1 or 2 . - The
semiconductor structure 200 is defined withseveral regions 110. In some embodiments, thesemiconductor structure 200 is defined with fourregions region 110 includes thefirst recesses 102 a of various shapes and sizes. Only onefirst recess 102 a is shown for eachregion 110 in the Figures for simplicity of description. In some embodiments, thefirst mask layer 102 includes fourfirst recesses 102 a-1, 102 a-2, 102 a-3 and 102 a-4, and thesecond mask layer 103 includes foursecond recesses 103 a-1, 103 a-2, 103 a-3 and 103 a-4. Each of thefirst recesses 102 a-1, 102 a-2, 102 a-3 and 102 a-4 is an image of a circuit feature. In some embodiments, thefirst recesses 102 a-1, 102 a-2, 102 a-3 and 102 a-4 are substantially different from each other. For example, thefirst recesses 102 a-1, 102 a-2, 102 a-3 and 102 a-4 are four different circuit features. In some embodiments, thefirst recesses 102 a-1, 102 a-2, 102 a-3 and 102 a-4 can be projected over a semiconductive substrate or wafer by the predetermined electromagnetic radiation. In some embodiments, thefirst recesses 102 a-1, 102 a-2, 102 a-3 and 102 a-4 are configured to form the circuit features over different layers of a semiconductive substrate or wafer. - In some embodiments, each of the
second recesses 103 a-1, 103 a-2, 103 a-3 and 103 a-4 surrounds the correspondingfirst recesses 102 a-1, 102 a-2, 102 a-3 and 102 a-4. In some embodiments, eachregion 110 is surrounded or enclosed by thesecond mask layer 103. -
FIG. 5 is a schematic top view of asemiconductor structure 300 in accordance with various embodiments of the present disclosure, andFIG. 6 is a schematic cross sectional view of thesemiconductor structure 300 along CC′ inFIG. 5 . In some embodiments, thesemiconductor structure 300 is a photomask which includes asubstrate 101, afirst mask layer 102 and asecond mask layer 103, which have similar configurations as described above or illustrated inFIG. 1 or 2 . - The
semiconductor structure 300 is defined withseveral regions 110. In some embodiments, thesemiconductor structure 300 is defined with nineregions region 110 includes thefirst recesses 102 a of various shapes and sizes. Only onefirst recess 102 a is shown for eachregion 110 in the Figures for simplicity of description. In some embodiments, thefirst mask layer 102 includes ninefirst recesses 102 a-1, 102 a-2, 102 a-3, 102 a-4, 102 a-5, 102 a-6, 102 a-7, 102 a-8 and 102 a-9, and thesecond mask layer 103 includes ninesecond recesses 103 a-1, 103 a-2, 103 a-3, 103 a-4, 103 a-5, 103 a-6, 103 a-7, 103 a-8 and 103 a-9. In some embodiments, each of thefirst recesses 102 a-1, 102 a-2, 102 a-3, 102 a-4, 102 a-5, 102 a-6, 102 a-7, 102 a-8 and 102 a-9 is an image of a circuit feature. In some embodiments, thefirst recesses 102 a-1, 102 a-2, 102 a-3, 102 a-4, 102 a-5, 102 a-6, 102 a-7, 102 a-8, 102 a-9 are substantially different from each other. For example, thefirst recesses 102 a-1, 102 a-2, 102 a-3, 102 a-4, 102 a-5, 102 a-6, 102 a-7, 102 a-8 and 102 a-9 are nine different circuit features. Thefirst recesses 102 a-1, 102 a-2, 102 a-3, 102 a-4, 102 a-5, 102 a-6, 102 a-7, 102 a-8 and 102 a-9 are configured to form the circuitry pattern, the electrical component or the circuit feature over different layers of a semiconductive substrate or wafer. - Each of the
second recesses 103 a-1, 103 a-2, 103 a-3, 103 a-4, 103 a-5, 103 a-6, 103 a-7, 103 a-8 and 103 a-9 includes an image of a circuit feature. In Thesecond recesses 103 a-1, 103 a-2, 103 a-3, 103 a-4, 103 a-5, 103 a-6, 103 a-7, 103 a-8 and 103 a-9 are configured to form images of circuit features over different layers of a semiconductive substrate or wafer. For example, thesecond recesses 103 a-1, 103 a-2, 103 a-3, 103 a-4, 103 a-5, 103 a-6, 103 a-7, 103 a-8 and 103 a-9 are configured to form images of circuit features over nine different layers of a semiconductive substrate or wafer. - In some embodiments, each of the
second recesses 103 a-1, 103 a-2, 103 a-3, 103 a-4, 103 a-5, 103 a-6, 103 a-7, 103 a-8 and 103 a-9 surrounds the correspondingfirst recesses 102 a-1, 102 a-2, 102 a-3, 102 a-4, 102 a-5, 102 a-6, 102 a-7, 102 a-8, 102 a-9. In some embodiments, eachregion 110 is surrounded or enclosed by thesecond mask layer 103. - In the present disclosure, a method of manufacturing a
semiconductor structure semiconductor structure method 400. Themethod 400 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations.FIG. 7 is an embodiment of themethod 400 of manufacturing thesemiconductor structure method 400 includes a number of operations (401, 402, 403, 404, 405, 406, 407, 408, 409, 410 and 411). - In
operation 401, asubstrate 101 is provided or received as shown inFIG. 7A . In Thesubstrate 101 is transparent to a predetermined electromagnetic radiation. In some embodiments, thesubstrate 101 includes afront side 101 a and aback side 101 b opposite to thefront side 101 a. In some embodiments, the predetermined electromagnetic radiation can transmit from thefront side 101 a to theback side 101 b or from theback side 101 b to thefront side 101 a. In some embodiments, thesubstrate 101 includes quartz, fused quartz, glass or other suitable materials. In some embodiments, the predetermined electromagnetic radiation is ultraviolet (UV), laser, visible light, x-ray, extreme ultraviolet (EUV), deep ultraviolet (DUV), ions beam, electrons beam, etc. In some embodiments, thesubstrate 101 has similar configuration as described above or illustrated inFIGS. 1-6 . - In
operation 402, afirst mask layer 102 is disposed over thesubstrate 101 as shown inFIG. 7B . Thefirst mask layer 102 is disposed over thefront side 101 a of thesubstrate 101. Thefirst mask layer 102 is at least partially transparent to the predetermined electromagnetic radiation. In some embodiments, thefirst mask layer 102 includes molybdenum silicon (MoSi). In some embodiments, thefirst mask layer 102 is disposed by spin coating, sputtering, chemical vapor deposition (CVD) or any other suitable operations. In some embodiments, thefirst mask layer 102 has similar configuration as described above or illustrated inFIGS. 1-6 . - In
operation 403, afirst photoresist 104 is disposed over thefirst mask layer 102 as shown inFIG. 7C . In Thefirst photoresist 104 is coated on thefirst mask layer 102. Thefirst photoresist 104 is a light sensitive material with chemical properties depending on an exposure of an electromagnetic radiation. In some embodiments, thefirst photoresist 104 is sensitive to an electromagnetic radiation such as an ultra violet (UV), that the chemical properties of thefirst photoresist 104 are changed upon exposure to the electromagnetic radiation. In some embodiments, thefirst photoresist 104 is disposed over thefirst mask layer 102 by spin coating or any other suitable operations. - In
operation 404, thefirst photoresist 104 is patterned to form severalfirst openings 104 a as shown inFIG. 7D . Thefirst photoresist 104 is patterned by removing portions of thefirst photoresist 104. In some embodiments, some portions of thefirst photoresist 104 are exposed to the electromagnetic radiation, and those exposed portions are dissolvable by a developer solution while those unexposed portions are not dissolvable by the developer solution. Thefirst photoresist 104 is patterned after removal of the exposed portions of thefirst photoresist 104. In some embodiments, thefirst openings 104 a are formed after removal of the exposed portions of thefirst photoresist 104. In some embodiments, some portions of thefirst mask layer 102 are exposed from thefirst photoresist 104 by thefirst openings 104 a. - In
operation 405, portions of thefirst mask layer 102 exposed from thefirst photoresist 104 are removed to form severalfirst recesses 102 a as shown inFIG. 7E . Thefirst openings 104 a correspond to thefirst recesses 102 a respectively. In some embodiments, thefirst recesses 102 a are extended through thefirst mask layer 102. In some embodiments, the portions of thefirst mask layer 102 exposed from thefirst photoresist 104 are removed by suitable etching operation such as plasma etching, an anisotropic dry etching, a reactive ion etching (RIE), a dry etching or etc. - In
operation 406, thefirst photoresist 104 is removed as shown inFIG. 7F . In some embodiment, thefirst photoresist 104 is removed by suitable photoresist stripping technique, such as chemical solvent cleaning, plasma ashing, dry stripping and/or the like. - In
operation 407, asecond mask layer 103 is disposed over thefirst mask layer 102 as shown inFIG. 7G . Thesecond mask layer 103 is opaque to the predetermined electromagnetic radiation. In some embodiments, thesecond mask layer 103 includes chromium (Cr). In some embodiments, thesecond mask layer 103 is disposed by spin coating, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD) or any other suitable operations. In some embodiments, thesecond mask layer 103 has similar configuration as described above or illustrated inFIGS. 1-6 . - In
operation 408, asecond photoresist 105 is disposed over thesecond mask layer 103 as shown inFIG. 7H . Thesecond photoresist 105 is coated on thesecond mask layer 103. Thesecond photoresist 105 is a light sensitive material with chemical properties depending on an exposure of an electromagnetic radiation. In some embodiments, thesecond photoresist 105 is sensitive to an electromagnetic radiation such as an ultra violet (UV), that the chemical properties of thesecond photoresist 105 are changed upon exposure to the electromagnetic radiation. In some embodiments, thesecond photoresist 105 is disposed over thesecond mask layer 103 by spin coating or any other suitable operations. - In
operation 409, thesecond photoresist 105 is patterned to form severalsecond openings 105 a as shown inFIG. 7I . Thesecond photoresist 105 is patterned by removing portions of thesecond photoresist 105. In some embodiments, some portions of thesecond photoresist 105 are exposed to the electromagnetic radiation, and those exposed portions are dissolvable by a developer solution while those unexposed portions are not dissolvable by the developer solution. In some embodiments, thesecond photoresist 105 is patterned after removal of the exposed portions of thesecond photoresist 105. Thesecond openings 105 a are formed after removal of the exposed portions of thesecond photoresist 105. Some portions of thesecond mask layer 103 are exposed from thesecond photoresist 105 by thesecond openings 105 a. In some embodiments, thesecond opening 105 a of thesecond photoresist 105 is substantially greater than thefirst opening 104 a of thefirst photoresist 104. - At least a portion of the
second photoresist 105 is disposed between two of thesecond openings 105 a after the patterning of thesecond photoresist 105. In some embodiments, a width W4 of one of thesecond openings 105 a is about 5 mm to about 15 mm. In some embodiments, the width W4 is about 8 mm to about 10 mm. In some embodiments, a width W5 of a portion of thesecond photoresist 105 disposed between two of thesecond openings 105 a is about 50 um to about 70 um. In some embodiments, the width W5 is about 60 um. In some embodiments, a ratio of the width W5 of thesecond photoresist 105 disposed between two of thesecond openings 105 a to the width W4 of one of thesecond openings 105 a is substantially greater than or equal to 0.001. - In
operation 410, the portions of thesecond mask layer 103 exposed from thesecond photoresist 105 are removed to for severalsecond recesses 103 a as shown inFIGS. 7J and 7K. Thesecond openings 105 a correspond to thesecond recesses 103 a respectively. Thesecond mask layer 103 is defined withseveral regions 110. Eachregion 110 includes at least one of thefirst recesses 102 a. In some embodiments, thesecond mask layer 103 is a boundary layer. In some embodiments, thesecond recesses 103 a are formed one by one. For example, the left portion of thesecond mask layer 103 is removed first to form one of thesecond recesses 103 a as shown inFIG. 7J , and then the right portion of the second mask layer is removed to form another one of thesecond recesses 103 a as shown inFIG. 7K . In some embodiments, thesecond recesses 103 a are extended through thesecond mask layer 103. In some embodiments, the portions of thesecond mask layer 103 exposed from thesecond photoresist 105 are removed by suitable etching operation such as wet etching, plasma etching, an anisotropic dry etching, a reactive ion etching (RIE), a dry etching or etc. - In
operation 411, thesecond photoresist 105 is removed as shown inFIG. 7L . In some embodiment, thesecond photoresist 105 is removed by suitable photoresist stripping technique, such as chemical solvent cleaning, plasma ashing, dry stripping and/or the like.Several regions 110 In some embodiments, asemiconductor structure FIGS. 1-6 is formed. In some embodiment, thesemiconductor structure - In the present disclosure, a method of manufacturing a semiconductor structure is also disclosed. In some embodiments, a semiconductor structure is formed by a
method 500. Themethod 500 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations.FIG. 8 is an embodiment of themethod 500 of manufacturing the semiconductor structure. Themethod 500 includes a number of operations (501, 502, 503, 504 and 505). - In
operation 501, aphotomask 100 is formed or provided as shown inFIG. 8A . In some embodiments, thephotomask 100 is formed by themethod 400 described above. Thephotomask 100 includes afirst substrate 101, afirst mask layer 102 and asecond mask layer 103. Thephotomask 100 is defined withseveral regions 110. Thefirst mask layer 102 includes severalfirst recesses 102 a, and thesecond mask layer 103 includes severalsecond recesses 103 a. In some embodiments, thefirst recesses 102 a-1 and 102 a-2 are different circuit features. In some embodiments, thefirst recesses 102 a-1 and 102 a-2 can be projected over a semiconductive substrate or wafer by a predetermined electromagnetic radiation. Thefirst recesses 102 a-1 and 102 a-2 are configured to form circuit features over different layers of a semiconductive substrate or wafer. At least a portion of thesecond mask layer 103 is disposed between two of the second recesses 103 s. In some embodiments, thephotomask 100 has similar configurations as thesemiconductor structure FIGS. 1-6 . - In
operation 502, asecond substrate 106 is provided or received as shown inFIG. 8B . Thesecond substrate 106 includes semiconductive materials such as silicon or other suitable materials. Thesecond substrate 106 is a wafer. In some embodiments, thesecond substrate 106 is a silicon substrate or silicon wafer. In some embodiments, thesecond substrate 106 includes glass or ceramic. In some embodiments, thesecond substrate 106 is a glass substrate. - In
operation 503, athird photoresist 107 is disposed over thesecond substrate 106 as shown inFIG. 8C . Thethird photoresist 107 is a light sensitive material with chemical properties depending on an exposure of an electromagnetic radiation. In some embodiments, thethird photoresist 107 is sensitive to an electromagnetic radiation such as an ultra violet (UV), that the chemical properties of thethird photoresist 107 are changed upon exposure to the electromagnetic radiation. In some embodiments, thethird photoresist 107 is disposed over thesecond substrate 106 by spin coating or any other suitable operations. - In
operation 504, a predetermined electromagnetic radiation is projected through thephotomask 100 towards thethird photoresist 107 to pattern thethird photoresist 107 as shown inFIG. 8D . Thesecond recess 103 a-1 of thesecond mask layer 103 is aligned with a predetermined position of thethird photoresist 107. The predetermined electromagnetic radiation is irradiated from asource 108. In some embodiments, the predetermined electromagnetic radiation is ultraviolet (UV), laser, visible light, x-ray, extreme ultraviolet (EUV), deep ultraviolet (DUV), ions beam, electrons beam, etc. In some embodiments, thefirst mask layer 102 is at least partially transparent to the predetermined electromagnetic radiation, thesecond mask layer 103 is opaque to the predetermined electromagnetic radiation. - The predetermined electromagnetic radiation can pass through the
first substrate 101 and thefirst recesses 102 a to thethird photoresist 107, such that an image of thefirst recesses 102 a can be projected over thethird photoresist 107 to pattern thethird photoresist 107. A phase of the predetermined electromagnetic radiation passing through thefirst mask layer 102 is shifted 180° with respect to a phase of the predetermined electromagnetic radiation passing through thefirst substrate 101 upon the projection of the predetermined electromagnetic radiation, such that a quality of the image of thefirst recesses 102 a projected over thethird photoresist 107 is increased or improved. - In some embodiments, the
photomask 100 or thefirst recess 102 a-1 is aligned with thethird photoresist 107 or thesecond substrate 106, such that the image of thefirst recess 102 a-1 can be projected over a predetermined position of thethird photoresist 107. Thethird photoresist 107 is patterned by removing portions of thethird photoresist 107. In some embodiments, some portions of thethird photoresist 107 are exposed to the predetermined electromagnetic radiation, and those exposed portions are dissolvable by a developer solution while those unexposed portions are not dissolvable by the developer solution. Thethird photoresist 107 is patterned after removal of the exposed portions of thethird photoresist 107. - In
operation 505, portions of thesecond substrate 106 exposed from thethird photoresist 107 are removed as shown inFIG. 8E . The portions of thesecond substrate 106 exposed from thethird photoresist 107 correspond to thefirst recesses 102 a respectively. In some embodiments, the portion of thesecond substrate 106 corresponding to thefirst recess 102 a-1 is removed, such that a circuit feature corresponding to thefirst recess 102 a-1 is formed over a first layer of thesecond substrate 106. In some embodiments, thethird photoresist 107 is removed as shown inFIG. 8F after the formation of thefirst recess 102 a-1 over thesecond substrate 106. - In some embodiments, after the formation of the
first recess 102 a-1 over the first layer of thesecond substrate 106, thefirst recess 102 a-2 is formed over a second layer of thesecond substrate 106 as shown inFIGS. 8G-8J . In some embodiments, afourth photoresist 109 is disposed over thesecond substrate 106 as shown inFIG. 8G . In some embodiments, thefourth photoresist 109 has similar configurations as thethird photoresist 107. - In some embodiments, after the formation of the
first recess 102 a-1 over the first layer of thesecond substrate 106, thephotomask 100 is moved to project an image of thefirst recess 102 a-2 over thefourth photoresist 109 to form a circuit feature corresponding to thefirst recess 102 a-2 over a second layer of thesecond substrate 106 as shown inFIG. 8H . In some embodiments, thephotomask 100 is moved such that thesecond recess 103 a-2 of thesecond mask layer 103 is aligned with a predetermined position of thesecond substrate 106. In some embodiments, thesecond recesses 103 a-1 and 103 a-2 are heated by the predetermined electromagnetic radiation upon projection of the predetermined electromagnetic radiation through thephotomask 100. In some embodiments, heat expansion of thesecond recesses 103 a-1 is substantially the same as heat expansion of thesecond recess 103 a-2, since thesecond mask layer 103 surrounds both of thesecond recesses 103 a-1 and 103 a-2. In some embodiments, a position of thesecond recess 103 a-1 as shown inFIG. 8D is vertically aligned with a position of thesecond recess 103 a-2 as shown inFIG. 8H . In some embodiments, thesource 108 irradiates the predetermined electromagnetic radiation through thesecond recess 103 a-2 towards thefourth photoresist 109 to project thefirst recess 102 a-2 over thefourth photoresist 109. In some embodiments, thefourth photoresist 109 is patterned by removing a portion of thefourth photoresist 109 exposed to the predetermined electromagnetic radiation. - In some embodiments, a portion of the
second substrate 106 exposed from thefourth photoresist 109 is removed as shown inFIG. 8I . In some embodiments, thefirst recess 102 a-2 is formed over the second layer of thesecond substrate 106. In some embodiments, thefourth photoresist 109 is removed after the formation of thefirst recess 102 a-2. - In the present disclosure, a semiconductor structure is disclosed. The semiconductor structure includes a substrate, a first mask layer disposed over the substrate and including a plurality of first recesses extended through the first mask layer, and a second mask layer disposed over the first mask layer and including a plurality of second recesses extended through the second mask layer. At least a portion of the second mask layer is disposed between two of the plurality of second recesses. As such, each region defined over the semiconductor structure is surrounded by the second mask layer, and thermal stress around each region upon photolithography operations is substantially consistent. Therefore, alignment between regions of the semiconductor structure is improved, and quality of formation of circuit feature over a semiconductive substrate or wafer by the semiconductor structure is also improved.
- In some embodiments, a method of manufacturing a semiconductor structure includes providing a mask including a first substrate; a first mask layer disposed over the first substrate, including a plurality of first recesses extended through the first mask layer; a second mask layer disposed over the first mask layer and including a plurality of second recesses extended through the second mask layer; providing a second substrate including a photoresist disposed over the second substrate; and projecting a predetermined electromagnetic radiation through the mask towards the photoresist, wherein the first mask layer is at least partially transparent to the predetermined electromagnetic radiation, the second mask layer is opaque to the predetermined electromagnetic radiation, and at least a portion of the second mask layer is disposed between two of the plurality of second recesses.
- In some embodiments, at least a portion of the first mask layer is disposed between two of the plurality of first recesses, and the portion of the second mask layer is disposed over the portion of the first mask layer. In some embodiments, a ratio of a width of the portion of the second mask layer to a width of one of the plurality of second recesses is substantially greater than or equal to 0.001. In some embodiments, a width of one of the plurality of second recesses is substantially greater than a width of one of the plurality of first recesses. In some embodiments, a width of one of the plurality of second recesses is about 5 mm to about 15 mm. In some embodiments, a width of the portion of the second mask layer disposed between two of the plurality of second recesses is about 50 um to about 70 um.
- In some embodiments, the first mask layer includes molybdenum silicon (MoSi). In some embodiments, the second mask layer includes chromium (Cr). In some embodiments, the substrate is transparent to the predetermined electromagnetic radiation. In some embodiments, the substrate includes quartz. In some embodiments, about 5% to about 20% of the predetermined electromagnetic radiation is penetrable to the first mask layer. In some embodiments, the predetermined electromagnetic radiation is an ultraviolet (UV) or laser.
- In some embodiments, a method of manufacturing a semiconductor structure includes providing a substrate; disposing a first mask layer over the substrate; disposing a first photoresist over the first mask layer; patterning the first photoresist to form a plurality of first openings; removing portions of the first mask layer exposed from the first photoresist to form a plurality of first recesses extended through the first mask layer; removing the first photoresist; disposing a second mask layer over the first mask layer; disposing a second photoresist over the second mask layer; patterning the second photoresist to form a plurality of second openings; removing portions of the second mask layer exposed from the second photoresist to form a plurality of regions over the substrate; and removing the second photoresist, wherein each of the plurality of regions includes at least one of the plurality of first recesses, the first mask layer is at least partially transparent to a predetermined electromagnetic radiation, the second mask layer is opaque to the predetermined electromagnetic radiation, and at least a portion of the second photoresist is disposed between two of the plurality of second openings after the patterning of the second photoresist.
- In some embodiments, the patterning of the first photoresist includes removing portions of the first photoresist, or the patterning of the second photoresist includes removing portions of the second photoresist. In some embodiments, a width of one of the plurality of second openings is about 5 mm to about 15 mm. In some embodiments, a ratio of a width of a portion of the second photoresist disposed between two of the plurality of second openings to a width of one of the plurality of second openings is substantially greater than or equal to 0.001. In some embodiments, one of the plurality of second openings is substantially greater than one of the plurality of first openings.
- In some embodiments, a method of manufacturing a semiconductor structure includes forming a photomask including providing a first substrate; forming a first mask layer over the first substrate, wherein the first mask layer includes a plurality of first recesses extended through the first layer; forming a second mask layer over the first mask layer, wherein the second mask layer includes a plurality of regions over the first substrate; providing a second substrate; disposing a photoresist over the second substrate; projecting a predetermined electromagnetic radiation through the photomask towards the photoresist to pattern the photoresist; and removing portions of the second substrate exposed from the photoresist, wherein each of the plurality of regions includes at least one of the plurality of first recesses, the first mask layer is at least partially transparent to the predetermined electromagnetic radiation, the second mask layer is opaque to the predetermined electromagnetic radiation, and at least a portion of the second mask layer is disposed between two of the plurality of regions.
- In some embodiments, a phase of the predetermined electromagnetic radiation passing through the first mask layer is shifted 180° with respect to a phase of the predetermined electromagnetic radiation passing through the first substrate upon the projection of the predetermined electromagnetic radiation. In some embodiments, the portions of the second substrate exposed from the photoresist correspond to the plurality of first recesses respectively.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
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