US20200028719A1 - Apparatus for performing baseline wander correction - Google Patents
Apparatus for performing baseline wander correction Download PDFInfo
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- US20200028719A1 US20200028719A1 US16/286,511 US201916286511A US2020028719A1 US 20200028719 A1 US20200028719 A1 US 20200028719A1 US 201916286511 A US201916286511 A US 201916286511A US 2020028719 A1 US2020028719 A1 US 2020028719A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
- H04L25/0276—Arrangements for coupling common mode signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45183—Long tailed pairs
- H03F3/45192—Folded cascode stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45269—Complementary non-cross coupled types
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/129—Indexing scheme relating to amplifiers there being a feedback over the complete amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45116—Feedback coupled to the input of the differential amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45241—Two dif amps realised in MOS or JFET technology, the dif amps being either both of the p-channel type or both of the n-channel type, are coupled in parallel with their gates
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
- H04L25/0274—Arrangements for ensuring balanced coupling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M7/00—Arrangements for interconnection between switching centres
- H04M7/12—Arrangements for interconnection between switching centres for working between exchanges having different types of switching equipment, e.g. power-driven and step by step or decimal and non-decimal
- H04M7/1205—Arrangements for interconnection between switching centres for working between exchanges having different types of switching equipment, e.g. power-driven and step by step or decimal and non-decimal where the types of switching equipement comprises PSTN/ISDN equipment and switching equipment of networks other than PSTN/ISDN, e.g. Internet Protocol networks
- H04M7/125—Details of gateway equipment
Definitions
- the present invention is related to signal processing, and more particularly, to an apparatus for performing baseline wander correction.
- Serializer/Deserializer (SerDes) architecture can be applied to data transmission, such as high speed data transmission between multiple circuits or devices performed through limited number of input/output terminals.
- SerDes Serializer/Deserializer
- a SerDes receiver front-end circuit may have some filters for filtering undesired low frequency signals.
- an input signal of the SerDes receiver front-end circuit carries a series of data such as consecutive logic values 0 or consecutive logic values 1 for a long period, these filters may introduce baseline wander effect.
- Some suggestions are provided in the related arts for trying to reduce this effect, but additional problems such as some side effects (e.g. complexity of circuit architecture, low efficiency, low speed, additional data processing, and so on) may be introduced.
- a novel architecture is needed, to improve overall performance without introducing any side effect or in a way that is less likely to introduce a side effect.
- An objective of the present invention is to provide an apparatus for performing baseline wander correction, to solve the aforementioned problems.
- Another objective of the present invention is to provide an apparatus for performing baseline wander correction, to improve overall performance without introducing any side effect or in a way that is less likely to introduce a side effect.
- At least one embodiment of the present invention provides an apparatus for performing baseline wander correction, wherein the apparatus is applicable to a front-end circuit of a receiver.
- the apparatus may comprise a plurality of filters, a common mode voltage generator and a compensation circuit, which are positioned in the front-end circuit.
- the plurality of filters are coupled to a set of input terminals of the receiver, and may be arranged to filter a set of input signals on the set of input terminals to generate a set of differential signals on a set of secondary terminals for further use of the receiver.
- the common mode voltage generator is electrically connected to the set of secondary terminals, and may be arranged to generate a common mode voltage between the set of differential signals.
- the compensation circuit is electrically connected to the set of secondary terminals, and may be arranged to perform compensation related to baseline wander correction on the set of differential signals.
- multiple current paths of the compensation circuit are associated with each other. Through a first current path and a second current path within the current paths, the compensation circuit may perform charge or discharge control on a first capacitor and a second capacitor within the plurality of filters to dynamically adjust compensation amounts of the compensation, to reduce or eliminate a baseline wander effect of the set of differential signals.
- the apparatus of the present invention can perform processing that is focusing on a receiver input common mode voltage while reducing or eliminating a baseline wander effect, having no need to worry about additional problems such as some side effects in the related arts.
- the compensation circuit is not directly connected to the set of input terminals.
- implementing the receiver according to the present invention can make it easier to optimize the range of the input common mode voltage and reduce power consumption.
- the apparatus of the present invention can directly compensate the input common mode voltage, and more particularly, perform real-time compensation through analog signals, rather than perform non-real-time processing through digital circuits.
- the apparatus of the present invention can perform baseline wander correction more efficiently and more quickly.
- the present invention can improve overall performance without introducing any side effect or in a way that is less likely to introduce a side effect.
- FIG. 1 is a diagram illustrating an apparatus for performing baseline wander correction according to an embodiment of the present invention.
- FIG. 2 illustrates implementation details of the common mode voltage generator shown in FIG. 1 according to an embodiment of the present invention.
- FIG. 3 illustrates implementation details of the baseline wander correction compensation circuit shown in FIG. 1 according to an embodiment of the present invention.
- FIG. 4 is a diagram illustrating a fully differential difference amplifier (FDDA) according to an embodiment of the present invention, where the FDDA may be taken as an example of an FDDA shown in FIG. 3 .
- FDDA fully differential difference amplifier
- FIG. 5 illustrates implementation details of the FDDA shown in FIG. 4 according to an embodiment of the present invention.
- FIG. 1 is a diagram illustrating an apparatus for performing baseline wander correction according to an embodiment of the present invention, where the apparatus is applicable to a front-end circuit of a receiver 100 .
- Example of the receiver 100 may include, but are not limited to: a receiver in a Serializer/Deserializer (SerDes) architecture (which may be referred to as SerDes receiver).
- the apparatus may comprise a plurality of filters (e.g.
- multiple passive components such as multiple capacitors ⁇ C acp , C acn , C fp , C fn ⁇ and multiple resistors ⁇ R acp , R acn , R fp , R fn , R cmp , R cmn , ⁇ R RX_term ⁇ ), and may comprise a common mode voltage generator 110 and a compensation circuit such as a baseline wander correction (BLWC) compensation circuit 120 , where the common mode voltage generator 110 may comprise a set of operational amplifiers 111 and 112 and a set of adjustment circuits 113 and 114 , the BLWC compensation circuit 120 may comprise a fully differential difference amplifier (FDDA) 125 , and the plurality of filters, the common mode voltage generator 110 and the compensation circuit such as the BLWC compensation circuit 120 may be positioned in the front-end circuit, but the present invention is not limited thereto.
- associated parameter of a component may be expressed with the name of the component in italics
- the plurality of filters such as the capacitors ⁇ C acp , C acn , C fp , C fn ⁇ and the resistors ⁇ R acp , R acn , R fp , R fn , R cmp , R cmn , ⁇ R RX_term ⁇ ⁇ are coupled to a set of input terminals of the receiver, such as the upper and lower terminals of a set of resistors ⁇ R RX_term ⁇ (which may have the same resistance R RX_term ) that are coupled to the channels shown in FIG.
- the common mode voltage generator 110 is electrically connected to the set of secondary terminals ⁇ inp_ctle, inn_ctle ⁇ , and may be arranged to generate a common mode voltage between the set of differential signals.
- the apparatus may control the common mode voltage to be equal to a reference voltage level such as a voltage level Vcm, where the voltage level Vcm may be inputted into a reference voltage terminal such as a terminal vcm_ 780 m , but the present invention is not limited thereto.
- the compensation circuit such as the BLWC compensation circuit 120 is electrically connected to the set of secondary terminals ⁇ inp_ctle, inn_ctle ⁇ , and may be arranged to perform compensation related to baseline wander correction (BLWC) on the set of differential signals.
- BLWC baseline wander correction
- multiple current paths of the compensation circuit are associated with each other. More particularly, through a first current path and a second current path within the multiple current paths, such as current paths passing through connection wires between the common mode voltage generator 110 and the BLWC compensation circuit 120 , respectively, the compensation circuit may perform charge or discharge control on the capacitors C acp and C acn within the plurality of filters to dynamically adjust compensation amounts of the compensation, to reduce or eliminate a baseline wander effect of the set of differential signals.
- the capacitor C acp is coupled between a first input terminal (such as the upper terminal of the set of resistors ⁇ R RX_term ⁇ , i.e. the terminal above the set of resistors ⁇ R RX_term ⁇ ) within the set of input terminals and the secondary terminal inp_ctle within the set of secondary terminals ⁇ inp_ctle, inn_ctle ⁇ , and the capacitor C acp has a first terminal and a second terminal (such as the left-side and the right-side terminals thereof) that are coupled to the first input terminal and the secondary terminal inp_ctle, respectively.
- a first input terminal such as the upper terminal of the set of resistors ⁇ R RX_term ⁇ , i.e. the terminal above the set of resistors ⁇ R RX_term ⁇
- the capacitor C acp has a first terminal and a second terminal (such as the left-side and the right-side terminals thereof) that are coupled to the first input terminal and
- the capacitor C acn is coupled between a second input terminal (such as the lower terminal of the set of resistors ⁇ R RX_term ⁇ , i.e. the terminal below the set of resistors ⁇ R RX_term ⁇ ) within the set of input terminals and the secondary terminal inn_ctle within the set of secondary terminals ⁇ inp_ctle, inn_ctle ⁇ , and the capacitor C acn has a first terminal and a second terminal that are coupled to the second input terminal and the secondary terminal inn_ctle, respectively.
- a second input terminal such as the lower terminal of the set of resistors ⁇ R RX_term ⁇ , i.e. the terminal below the set of resistors ⁇ R RX_term ⁇
- the capacitor C acn has a first terminal and a second terminal that are coupled to the second input terminal and the secondary terminal inn_ctle, respectively.
- the first current path is coupled to the capacitor C acp through the second terminal of the capacitor C acp (such as the right-side terminal thereof), rather than through the first terminal of the capacitor C acp (such as the left-side terminal thereof), and the second current path is coupled to the capacitor C acn through the second terminal of the capacitor C acn (such as the right-side terminal thereof), rather than through the first terminal of the capacitor C acn (such as the left-side terminal thereof).
- the BLWC compensation circuit 120 is not directly connected to the set of input terminals (or the respective first terminals of the capacitors C acp and C acn ).
- implementing the receiver 100 according to this architecture can make it easier to optimize the range of an input common mode voltage (such as the aforementioned common mode voltage) and reduce power consumption.
- respective input terminals of the operational amplifiers 111 and 112 are electrically connected to each other, and are electrically connected to a common output terminal (such as a terminal cm bias).
- Respective first input terminals of the operational amplifiers 111 and 112 (such as inverting input terminals labeled “ ⁇ ” respectively) are electrically connected to each other and are electrically connected to a reference voltage (such as the reference voltage level on the terminal vcm_ 780 m )
- respective second input terminals of the operational amplifiers 111 and 112 are electrically connected to the secondary terminals inp_ctle and inn_ctle, respectively.
- the set of adjustment circuits 113 and 114 are electrically connected to the secondary terminals inp_ctle and inn_ctle, respectively, and are electrically connected to the set of operational amplifiers 111 and 112 through the common output terminal (such as the terminal cm bias). According to a voltage level on the common output terminal (such as a common mode bias voltage cm bias on the terminal cm bias), the adjustment circuits 113 and 114 may apply the common mode voltage to the set of differential signals.
- the apparatus may comprise transistors, and the transistors may be implemented as Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) such as P-type MOSFETs and N-type MOSFETs.
- MOSFETs Metal Oxide Semiconductor Field Effect Transistor
- the beginning characters of a symbol of a certain transistor within the transistors may be “PM” or “NM”, to indicate that this transistor is a P-type MOSFET or an N-type MOSFET, but the present invention is not limited thereto.
- FIG. 2 illustrates implementation details of the common mode voltage generator 110 shown in FIG. 1 according to an embodiment of the present invention.
- Each partial circuit of multiple partial circuits within the set of operational amplifier 111 and 112 may comprise multiple transistors, where the operational amplifier 111 may comprise a first set of partial circuits ⁇ 210 , 211 , 212 ⁇ within the multiple partial circuits, and the operational amplifier 112 may comprise a second set of partial circuits ⁇ 220 , 221 , 222 ⁇ within the multiple partial circuits.
- the partial circuit 210 may comprise transistors ⁇ PM 31 , PM 32 , NM 31 , NM 32 , NM 33 , NM 34 ⁇
- the partial circuit 211 may comprise transistors ⁇ PM 11 , PM 23 ⁇
- the partial circuit 212 may comprise transistors ⁇ PM 12 , PM 22 ⁇
- the partial circuit 220 may comprise transistors ⁇ PM 41 , PM 42 , NM 41 , NM 42 , NM 43 , NM 44 ⁇
- the partial circuit 221 may comprise transistors ⁇ PM 13 , PM 21 ⁇
- the partial circuit 222 may comprise the transistors ⁇ PM 12 , PM 22 ⁇ . As shown in FIG.
- the partial circuit 222 may be equal to the partial circuit 212 .
- the operational amplifier 111 and 112 may share a partial circuit (the partial circuit 212 or 222 ) within the multiple partial circuits, where each set of the first set of partial circuits ⁇ 210 , 211 , 212 ⁇ and the second set of partial circuits ⁇ 220 , 221 , 222 ⁇ may comprise the partial circuit.
- a voltage level vbx on a terminal vbx may be a predetermined voltage level
- a voltage level vbiasn on a terminal vbiasn may be another predetermined voltage level, but the present invention is not limited thereto.
- FIG. 3 illustrates implementation details of the BLWC compensation circuit 120 shown in FIG. 1 according to an embodiment of the present invention.
- the FDDA 125 may comprise four input terminals (such as two non-inverting input terminals labeled “+” and two inverting input terminals labeled “ ⁇ ”, which are positioned on the left-side of the FDDA 125 ) and two output terminals (such as a non-inverting output terminal labeled “+” and an inverting output terminal labeled “ ⁇ ”, which are positioned on the right-side of the FDDA 125 ).
- the BLWC compensation circuit 120 may comprise a feedback control circuit such as a common mode feedback (CMFB) circuit 310 , a set of current sources 321 and 322 , a set of resistors ⁇ R ac ⁇ (which may have the same resistance R ac ) and a plurality of transistors ⁇ PM 51 , PM 52 , PM 53 , PM 54 , PM 61 , PM 62 , PM 63 , PM 64 , NM 52 , NM 62 ⁇ , where these transistors ⁇ PM 51 , PM 52 , PM 53 , PM 54 , PM 61 , PM 62 , PM 63 , PM 64 , NM 52 , NM 62 ⁇ may be arranged to provide the multiple current paths associated with each other.
- CMFB common mode feedback
- the multiple current paths may further comprise a third current path and a fourth current path.
- the first current path may pass through the transistors ⁇ PM 51 , PM 53 ⁇ and may be positioned on a first branch that comprises the transistors ⁇ PM 51 , PM 53 ⁇ .
- the second current path may pass through the transistors ⁇ PM 61 , PM 63 ⁇ and may be positioned on a second branch that comprises the transistors ⁇ PM 61 , PM 63 ⁇ .
- the third current path may pass through the transistors ⁇ PM 52 , PM 54 , NM 52 ⁇ and the current source 321 and may be positioned on a third branch that comprises the transistors ⁇ PM 52 , PM 54 , NM 52 ⁇ and the current source 321 .
- the fourth current path may pass through the transistors ⁇ PM 62 , PM 64 , NM 62 ⁇ and the current source 322 and may be positioned on a fourth branch that comprises the transistors ⁇ PM 62 , PM 64 , NM 62 ⁇ and the current source 322 .
- the set of current sources 321 and 322 may be respectively positioned on the third current path and the fourth current path, and more particularly, may control the respective currents I d of the third current path and the fourth current path, where the set of current sources 321 and 322 may be designed as current sources having the same current I d , and any slight difference caused by mismatch (if exists) may be within a predetermined allowable range, and therefore may be omitted.
- the set of resistors ⁇ R ac ⁇ are connected to each other in series and coupled between the third current path and the fourth current path, and more particularly, the set of resistors ⁇ R ac ⁇ may provide a feedback signal (such as a voltage level Vcmfb, which may be an average voltage level of voltage levels va and vb) on a terminal between the set of resistors ⁇ R ac ⁇ .
- a feedback signal such as a voltage level Vcmfb, which may be an average voltage level of voltage levels va and vb
- the feedback control circuit such as the CMFB circuit 310 is coupled to the terminal between the set of resistors ⁇ R ac ⁇ and coupled to the set of current sources 321 and 322 , and more particularly, may control the set of current sources 321 and 322 according to the feedback signal (such as the voltage level Vcmfb), to control respective currents I d of the third current path and the fourth current path.
- the feedback signal such as the voltage level Vcmfb
- the FDDA 125 is coupled to the multiple current paths and two transistors ⁇ NM 52 , MM 62 ⁇ through the four input terminals and the two output terminals, respectively, and more particularly, the FDDA 125 may control these two transistors ⁇ NM 52 , MM 62 ⁇ according to voltage levels on the multiple current paths, for example, by utilizing voltage levels outa and outb, where these two transistors ⁇ NM 52 , MM 62 ⁇ are positioned on the third current path and the fourth current path, respectively, and other transistors such as four sets of transistors ⁇ PM 51 , PM 53 ⁇ , ⁇ PM 61 , PM 63 ⁇ , ⁇ PM 52 , PM 54 ⁇ and ⁇ PM 62 , PM 64 ⁇ are positioned on the first current path, the second current path, the third current path and the fourth current path, respectively.
- a first input terminal within the aforementioned four input terminals (such as the lower non-inverting input terminal within the two non-inverting input terminals) is coupled to the capacitor C acp through the first current path and the second terminal of the capacitor C acp
- a second input terminal within the aforementioned four input terminals (such as the upper non-inverting input terminal within the two non-inverting input terminals) is coupled to the capacitor C acn through the second current path and the second terminal of the capacitor C acn
- a voltage level vbiasp on a terminal vbiasp may be a predetermined voltage level, but the present invention is not limited thereto.
- the CMFB circuit 310 may receive a reference voltage such as the voltage level Vcm, and compare the voltage level Vcmfb with the voltage level Vcm, to selectively pull up or pull down the voltage level Vcmfb through controlling the set of current sources 321 and 322 , to make the voltage level Vcmfb approach or reach the voltage level Vcm, but the present invention is not limited thereto.
- the aforementioned input common mode voltage (such as the voltage level Vcm) may be regarded as a bias voltage of the BLWC compensation circuit 120 , and the BLWC compensation circuit 120 may perform compensation according to the input common mode voltage (such as the voltage level Vcm) to reduce or eliminate the baseline wander effect.
- the apparatus may generate a common mode voltage within a predetermined input common mode range.
- the BLWC compensation circuit 120 may utilize a current mirror that generates additional current, to charge or discharge AC coupling capacitors (such as the capacitors C acp and C acn ) to perform compensation.
- the BLWC compensation circuit 120 may discharge the capacitor C acn while charging the capacitor C acp .
- the BLWC compensation circuit 120 may charge the capacitor C acn while discharging the capacitor C acp .
- the BLWC compensation circuit 120 can reduce or eliminate the baseline wander effect.
- FIG. 4 is a diagram illustrating a FDDA 400 according to an embodiment of the present invention, where the FDDA 400 may be taken as an example of the FDDA 125 shown in FIG. 3 .
- terminals ⁇ ipa, ima, ipb, imb ⁇ may respectively represent the four input terminals of the FDDA 125 from bottom to top as shown in FIG. 3
- terminals ⁇ outpa, outpb ⁇ may respectively represent the two output terminals of FDDA 125 from bottom to top as shown in FIG. 3 .
- the terminals outpa and outpb may output the voltage levels outa and outb, respectively.
- the lower half of FIG. 4 illustrates an example of circuit architecture of the FDDA 400 .
- the FDDA 400 may comprise three sets of transistors ⁇ NM 1 , NM 2 , NM 3 , NM 4 ⁇ , ⁇ NM 11 , NM 12 , NM 13 , NM 14 ⁇ and ⁇ NM 21 , NM 22 , NM 23 , NM 24 ⁇ , but the present invention is not limited thereto.
- FIG. 5 illustrates implementation details of the FDDA 400 shown in FIG. 4 according to an embodiment of the present invention.
- the terminals ⁇ ipa, ima, ipb, imb ⁇ may receive voltage levels ⁇ Va+, Va ⁇ , Vb+, Vb ⁇ , respectively, and the terminals ⁇ outpa, outpb ⁇ may output voltage levels ⁇ Vout ⁇ , Vout+ ⁇ , respectively, but the present invention is not limited thereto.
- FIG. 5 illustrates implementation details of the FDDA 400 shown in FIG. 4 according to an embodiment of the present invention.
- the terminals ⁇ ipa, ima, ipb, imb ⁇ may receive voltage levels ⁇ Va+, Va ⁇ , Vb+, Vb ⁇ , respectively, and the terminals ⁇ outpa, outpb ⁇ may output voltage levels ⁇ Vout ⁇ , Vout+ ⁇ , respectively, but the present invention is not limited thereto.
- FIG. 1 illustrates implementation details of the FDDA 400 shown in FIG. 4 according to an embodiment of the
- the FDDA 400 may comprise a set of first amplifiers having the same gain A 1 , a second amplifier having a gain A 2 , and a set of adders (illustrated with circles labeled “+” therein), where the set of first amplifiers output voltage levels ⁇ V x ⁇ , V x+ ⁇ and ⁇ V y+ , V y ⁇ ⁇ , respectively, and the set of adders output voltage levels V 2+ and V 2 , respectively.
- operations of the FDDA 400 may be expressed with the following equations:
- V 2+ V x ⁇ +V y+ ;
- V 2 ⁇ V x+ +V y ⁇ ;
- Vout, V x and V y represent differences between respective differential signals of the second amplifier, the upper first amplifier (i.e. the upper one of the set of first amplifiers) and the lower first amplifier (i.e. the lower one of the set of first amplifiers), respectively.
- the above equations may be arranged as follows:
- V out A 1 ⁇ A 2 ⁇ [( Vb+ ⁇ Va +) ⁇ ( Vb ⁇ Va ⁇ )];
Abstract
Description
- The present invention is related to signal processing, and more particularly, to an apparatus for performing baseline wander correction.
- According to related arts, Serializer/Deserializer (SerDes) architecture can be applied to data transmission, such as high speed data transmission between multiple circuits or devices performed through limited number of input/output terminals. In a situation where the SerDes architecture is not properly designed, there may be some problems. For example, a SerDes receiver front-end circuit may have some filters for filtering undesired low frequency signals. When an input signal of the SerDes receiver front-end circuit carries a series of data such as consecutive logic values 0 or consecutive logic values 1 for a long period, these filters may introduce baseline wander effect. Some suggestions are provided in the related arts for trying to reduce this effect, but additional problems such as some side effects (e.g. complexity of circuit architecture, low efficiency, low speed, additional data processing, and so on) may be introduced. Thus, a novel architecture is needed, to improve overall performance without introducing any side effect or in a way that is less likely to introduce a side effect.
- An objective of the present invention is to provide an apparatus for performing baseline wander correction, to solve the aforementioned problems.
- Another objective of the present invention is to provide an apparatus for performing baseline wander correction, to improve overall performance without introducing any side effect or in a way that is less likely to introduce a side effect.
- At least one embodiment of the present invention provides an apparatus for performing baseline wander correction, wherein the apparatus is applicable to a front-end circuit of a receiver. The apparatus may comprise a plurality of filters, a common mode voltage generator and a compensation circuit, which are positioned in the front-end circuit. The plurality of filters are coupled to a set of input terminals of the receiver, and may be arranged to filter a set of input signals on the set of input terminals to generate a set of differential signals on a set of secondary terminals for further use of the receiver. In addition, the common mode voltage generator is electrically connected to the set of secondary terminals, and may be arranged to generate a common mode voltage between the set of differential signals. Additionally, the compensation circuit is electrically connected to the set of secondary terminals, and may be arranged to perform compensation related to baseline wander correction on the set of differential signals. For example, multiple current paths of the compensation circuit are associated with each other. Through a first current path and a second current path within the current paths, the compensation circuit may perform charge or discharge control on a first capacitor and a second capacitor within the plurality of filters to dynamically adjust compensation amounts of the compensation, to reduce or eliminate a baseline wander effect of the set of differential signals.
- One of advantages of the present invention is, the apparatus of the present invention can perform processing that is focusing on a receiver input common mode voltage while reducing or eliminating a baseline wander effect, having no need to worry about additional problems such as some side effects in the related arts. For example, the compensation circuit is not directly connected to the set of input terminals. In this situation, implementing the receiver according to the present invention can make it easier to optimize the range of the input common mode voltage and reduce power consumption. In addition, the apparatus of the present invention can directly compensate the input common mode voltage, and more particularly, perform real-time compensation through analog signals, rather than perform non-real-time processing through digital circuits. In comparison with the related arts, the apparatus of the present invention can perform baseline wander correction more efficiently and more quickly. The present invention can improve overall performance without introducing any side effect or in a way that is less likely to introduce a side effect.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIG. 1 is a diagram illustrating an apparatus for performing baseline wander correction according to an embodiment of the present invention. -
FIG. 2 illustrates implementation details of the common mode voltage generator shown inFIG. 1 according to an embodiment of the present invention. -
FIG. 3 illustrates implementation details of the baseline wander correction compensation circuit shown inFIG. 1 according to an embodiment of the present invention. -
FIG. 4 is a diagram illustrating a fully differential difference amplifier (FDDA) according to an embodiment of the present invention, where the FDDA may be taken as an example of an FDDA shown inFIG. 3 . -
FIG. 5 illustrates implementation details of the FDDA shown inFIG. 4 according to an embodiment of the present invention. -
FIG. 1 is a diagram illustrating an apparatus for performing baseline wander correction according to an embodiment of the present invention, where the apparatus is applicable to a front-end circuit of areceiver 100. Example of thereceiver 100 may include, but are not limited to: a receiver in a Serializer/Deserializer (SerDes) architecture (which may be referred to as SerDes receiver). The apparatus may comprise a plurality of filters (e.g. multiple passive components such as multiple capacitors {Cacp, Cacn, Cfp, Cfn} and multiple resistors {Racp, Racn, Rfp, Rfn, Rcmp, Rcmn, {RRX_term}}), and may comprise a commonmode voltage generator 110 and a compensation circuit such as a baseline wander correction (BLWC)compensation circuit 120, where the commonmode voltage generator 110 may comprise a set ofoperational amplifiers adjustment circuits compensation circuit 120 may comprise a fully differential difference amplifier (FDDA) 125, and the plurality of filters, the commonmode voltage generator 110 and the compensation circuit such as the BLWCcompensation circuit 120 may be positioned in the front-end circuit, but the present invention is not limited thereto. For better comprehension, in some embodiments, associated parameter of a component may be expressed with the name of the component in italics, and/or a signal on a terminal may be expressed with the name of the terminal in italics. - According to the embodiment, the plurality of filters such as the capacitors {Cacp, Cacn, Cfp, Cfn} and the resistors {Racp, Racn, Rfp, Rfn, Rcmp, Rcmn, {RRX_term} } are coupled to a set of input terminals of the receiver, such as the upper and lower terminals of a set of resistors {RRX_term} (which may have the same resistance RRX_term) that are coupled to the channels shown in
FIG. 1 , and may be arranged to filter a set of input signals on the set of input terminals to generate a set of differential signals on a set of secondary terminals {inp_ctle, inn_ctle} for further use of the receiver. In addition, the commonmode voltage generator 110 is electrically connected to the set of secondary terminals {inp_ctle, inn_ctle}, and may be arranged to generate a common mode voltage between the set of differential signals. For example, the apparatus may control the common mode voltage to be equal to a reference voltage level such as a voltage level Vcm, where the voltage level Vcm may be inputted into a reference voltage terminal such as a terminal vcm_780 m, but the present invention is not limited thereto. Additionally, the compensation circuit such as the BLWCcompensation circuit 120 is electrically connected to the set of secondary terminals {inp_ctle, inn_ctle}, and may be arranged to perform compensation related to baseline wander correction (BLWC) on the set of differential signals. For example, multiple current paths of the compensation circuit are associated with each other. More particularly, through a first current path and a second current path within the multiple current paths, such as current paths passing through connection wires between the commonmode voltage generator 110 and theBLWC compensation circuit 120, respectively, the compensation circuit may perform charge or discharge control on the capacitors Cacp and Cacn within the plurality of filters to dynamically adjust compensation amounts of the compensation, to reduce or eliminate a baseline wander effect of the set of differential signals. - As shown in
FIG. 1 , the capacitor Cacp is coupled between a first input terminal (such as the upper terminal of the set of resistors {RRX_term}, i.e. the terminal above the set of resistors {RRX_term}) within the set of input terminals and the secondary terminal inp_ctle within the set of secondary terminals {inp_ctle, inn_ctle}, and the capacitor Cacp has a first terminal and a second terminal (such as the left-side and the right-side terminals thereof) that are coupled to the first input terminal and the secondary terminal inp_ctle, respectively. In addition, the capacitor Cacn is coupled between a second input terminal (such as the lower terminal of the set of resistors {RRX_term}, i.e. the terminal below the set of resistors {RRX_term}) within the set of input terminals and the secondary terminal inn_ctle within the set of secondary terminals {inp_ctle, inn_ctle}, and the capacitor Cacn has a first terminal and a second terminal that are coupled to the second input terminal and the secondary terminal inn_ctle, respectively. Regarding the BLWCcompensation circuit 120, the first current path is coupled to the capacitor Cacp through the second terminal of the capacitor Cacp (such as the right-side terminal thereof), rather than through the first terminal of the capacitor Cacp (such as the left-side terminal thereof), and the second current path is coupled to the capacitor Cacn through the second terminal of the capacitor Cacn (such as the right-side terminal thereof), rather than through the first terminal of the capacitor Cacn (such as the left-side terminal thereof). The BLWCcompensation circuit 120 is not directly connected to the set of input terminals (or the respective first terminals of the capacitors Cacp and Cacn). In a situation where there is no need to consider a transmitter common mode voltage (such as a voltage level on a terminal VTX_CM), implementing thereceiver 100 according to this architecture can make it easier to optimize the range of an input common mode voltage (such as the aforementioned common mode voltage) and reduce power consumption. - In addition, respective input terminals of the
operational amplifiers operational amplifiers 111 and 112 (such as inverting input terminals labeled “−” respectively) are electrically connected to each other and are electrically connected to a reference voltage (such as the reference voltage level on the terminal vcm_780 m), and respective second input terminals of theoperational amplifiers 111 and 112 (such as non-inverting input terminals labeled “+” respectively) are electrically connected to the secondary terminals inp_ctle and inn_ctle, respectively. The set ofadjustment circuits operational amplifiers adjustment circuits - According to some embodiments, the apparatus may comprise transistors, and the transistors may be implemented as Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) such as P-type MOSFETs and N-type MOSFETs. For better comprehension, the beginning characters of a symbol of a certain transistor within the transistors may be “PM” or “NM”, to indicate that this transistor is a P-type MOSFET or an N-type MOSFET, but the present invention is not limited thereto.
-
FIG. 2 illustrates implementation details of the commonmode voltage generator 110 shown inFIG. 1 according to an embodiment of the present invention. Each partial circuit of multiple partial circuits within the set ofoperational amplifier operational amplifier 111 may comprise a first set of partial circuits {210, 211, 212} within the multiple partial circuits, and theoperational amplifier 112 may comprise a second set of partial circuits {220, 221, 222} within the multiple partial circuits. For example, thepartial circuit 210 may comprise transistors {PM31, PM32, NM31, NM32, NM33, NM34}, thepartial circuit 211 may comprise transistors {PM11, PM23}, and thepartial circuit 212 may comprise transistors {PM12, PM22}. For another example, thepartial circuit 220 may comprise transistors {PM41, PM42, NM41, NM42, NM43, NM44}, thepartial circuit 221 may comprise transistors {PM13, PM21}, and thepartial circuit 222 may comprise the transistors {PM12, PM22}. As shown inFIG. 2 , thepartial circuit 222 may be equal to thepartial circuit 212. Theoperational amplifier partial circuit 212 or 222) within the multiple partial circuits, where each set of the first set of partial circuits {210, 211, 212} and the second set of partial circuits {220, 221, 222} may comprise the partial circuit. As a result, a chip area corresponding to thecommon mode generator 110 can be reduced. In addition, a voltage level vbx on a terminal vbx may be a predetermined voltage level, and a voltage level vbiasn on a terminal vbiasn may be another predetermined voltage level, but the present invention is not limited thereto. -
FIG. 3 illustrates implementation details of the BLWCcompensation circuit 120 shown inFIG. 1 according to an embodiment of the present invention. TheFDDA 125 may comprise four input terminals (such as two non-inverting input terminals labeled “+” and two inverting input terminals labeled “−”, which are positioned on the left-side of the FDDA 125) and two output terminals (such as a non-inverting output terminal labeled “+” and an inverting output terminal labeled “−”, which are positioned on the right-side of the FDDA 125). In addition to theFDDA 125, theBLWC compensation circuit 120 may comprise a feedback control circuit such as a common mode feedback (CMFB)circuit 310, a set ofcurrent sources - For example, in addition to the first current path and the second current path, the multiple current paths may further comprise a third current path and a fourth current path. The first current path may pass through the transistors {PM51, PM53} and may be positioned on a first branch that comprises the transistors {PM51, PM53}. The second current path may pass through the transistors {PM61, PM63} and may be positioned on a second branch that comprises the transistors {PM61, PM63}. The third current path may pass through the transistors {PM52, PM54, NM52} and the
current source 321 and may be positioned on a third branch that comprises the transistors {PM52, PM54, NM52} and thecurrent source 321. The fourth current path may pass through the transistors {PM62, PM64, NM62} and thecurrent source 322 and may be positioned on a fourth branch that comprises the transistors {PM62, PM64, NM62} and thecurrent source 322. The set ofcurrent sources current sources CMFB circuit 310 is coupled to the terminal between the set of resistors {Rac} and coupled to the set ofcurrent sources current sources - As shown in
FIG. 3 , theFDDA 125 is coupled to the multiple current paths and two transistors {NM52, MM62} through the four input terminals and the two output terminals, respectively, and more particularly, theFDDA 125 may control these two transistors {NM52, MM62} according to voltage levels on the multiple current paths, for example, by utilizing voltage levels outa and outb, where these two transistors {NM52, MM62} are positioned on the third current path and the fourth current path, respectively, and other transistors such as four sets of transistors {PM51, PM53}, {PM61, PM63}, {PM52, PM54} and {PM62, PM64} are positioned on the first current path, the second current path, the third current path and the fourth current path, respectively. According to this embodiment, a first input terminal within the aforementioned four input terminals (such as the lower non-inverting input terminal within the two non-inverting input terminals) is coupled to the capacitor Cacp through the first current path and the second terminal of the capacitor Cacp, and a second input terminal within the aforementioned four input terminals (such as the upper non-inverting input terminal within the two non-inverting input terminals) is coupled to the capacitor Cacn through the second current path and the second terminal of the capacitor Cacn. In addition, a voltage level vbiasp on a terminal vbiasp may be a predetermined voltage level, but the present invention is not limited thereto. - Based on the architecture shown in
FIG. 3 (more particularly, the components and the inter-component connections), theCMFB circuit 310 may receive a reference voltage such as the voltage level Vcm, and compare the voltage level Vcmfb with the voltage level Vcm, to selectively pull up or pull down the voltage level Vcmfb through controlling the set ofcurrent sources - According to some embodiments, the aforementioned input common mode voltage (such as the voltage level Vcm) may be regarded as a bias voltage of the
BLWC compensation circuit 120, and theBLWC compensation circuit 120 may perform compensation according to the input common mode voltage (such as the voltage level Vcm) to reduce or eliminate the baseline wander effect. For example, the apparatus may generate a common mode voltage within a predetermined input common mode range. In addition, theBLWC compensation circuit 120 may utilize a current mirror that generates additional current, to charge or discharge AC coupling capacitors (such as the capacitors Cacp and Cacn) to perform compensation. For example, theBLWC compensation circuit 120 may discharge the capacitor Cacn while charging the capacitor Cacp. For another example, theBLWC compensation circuit 120 may charge the capacitor Cacn while discharging the capacitor Cacp. As a result, theBLWC compensation circuit 120 can reduce or eliminate the baseline wander effect. -
FIG. 4 is a diagram illustrating aFDDA 400 according to an embodiment of the present invention, where theFDDA 400 may be taken as an example of theFDDA 125 shown inFIG. 3 . For example, terminals {ipa, ima, ipb, imb} may respectively represent the four input terminals of theFDDA 125 from bottom to top as shown inFIG. 3 , and terminals {outpa, outpb} may respectively represent the two output terminals ofFDDA 125 from bottom to top as shown inFIG. 3 . In this situation, the terminals outpa and outpb may output the voltage levels outa and outb, respectively. The lower half ofFIG. 4 illustrates an example of circuit architecture of theFDDA 400. TheFDDA 400 may comprise three sets of transistors {NM1, NM2, NM3, NM4}, {NM11, NM12, NM13, NM14} and {NM21, NM22, NM23, NM24}, but the present invention is not limited thereto. -
FIG. 5 illustrates implementation details of theFDDA 400 shown inFIG. 4 according to an embodiment of the present invention. The terminals {ipa, ima, ipb, imb} may receive voltage levels {Va+, Va−, Vb+, Vb−}, respectively, and the terminals {outpa, outpb} may output voltage levels {Vout−, Vout+}, respectively, but the present invention is not limited thereto. As shown inFIG. 5 , theFDDA 400 may comprise a set of first amplifiers having the same gain A1, a second amplifier having a gain A2, and a set of adders (illustrated with circles labeled “+” therein), where the set of first amplifiers output voltage levels {Vx−, Vx+} and {Vy+, Vy−}, respectively, and the set of adders output voltage levels V2+ and V2, respectively. According to this embodiment, operations of theFDDA 400 may be expressed with the following equations: -
Vout=Vout+−Vout−=A 2×(V 2+ −V 2−); -
V x =V x+ −V x− =A 1×(Va+−Va−); -
V y =V y+ −V y− =A 1×(Vb+−Vb−); -
V 2+ =V x− +V y+; -
V 2− =V x+ +V y−; - where Vout, Vx and Vy represent differences between respective differential signals of the second amplifier, the upper first amplifier (i.e. the upper one of the set of first amplifiers) and the lower first amplifier (i.e. the lower one of the set of first amplifiers), respectively. The above equations may be arranged as follows:
-
Vout=A 1 ×A 2×[(Vb+−Va+)−(Vb−−Va−)]; - but the present invention is not limited thereto.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
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TWI798894B (en) * | 2021-10-27 | 2023-04-11 | 瑞昱半導體股份有限公司 | Differential signaling receiver |
WO2023239498A1 (en) * | 2022-06-09 | 2023-12-14 | Macom Technology Solutions Holdings, Inc. | Baseline wander compensator and method |
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CN113497603B (en) * | 2020-04-01 | 2023-09-19 | 智原微电子(苏州)有限公司 | Device for baseline wander correction by means of differential wander current sensing |
KR20220057221A (en) | 2020-10-29 | 2022-05-09 | 삼성전자주식회사 | A analog front-end receiver and a electronic device including the same receiver |
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TWI798894B (en) * | 2021-10-27 | 2023-04-11 | 瑞昱半導體股份有限公司 | Differential signaling receiver |
WO2023239498A1 (en) * | 2022-06-09 | 2023-12-14 | Macom Technology Solutions Holdings, Inc. | Baseline wander compensator and method |
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TWI725327B (en) | 2021-04-21 |
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