US20190363087A1 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- US20190363087A1 US20190363087A1 US16/000,911 US201816000911A US2019363087A1 US 20190363087 A1 US20190363087 A1 US 20190363087A1 US 201816000911 A US201816000911 A US 201816000911A US 2019363087 A1 US2019363087 A1 US 2019363087A1
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- Prior art keywords
- channel layer
- bottom plate
- disposed
- semiconductor channel
- memory
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- H01L27/1052—
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
Definitions
- the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device including a memory structure and a manufacturing method thereof.
- DRAM Dynamic random access memory
- MOS metal oxide semiconductor
- FEOL front end of line
- BEOL back end of line
- the integrity of the integrated circuit may be increased when memory cells are formed by the BEOL process.
- problems such as process complexity, low manufacturing yield, and limitation of memory cell density when forming the memory cells by the BEOL process, and appropriate design modifications are required for improving these problems
- a semiconductor device and a manufacturing method thereof are provided in the present invention.
- a memory structure is integrated with a transistor structure for process simplification and/or memory density enhancement.
- a semiconductor device includes a substrate, a semiconductor channel layer, a gate electrode, and a first memory structure.
- the semiconductor channel layer is disposed on the substrate.
- the gate electrode is disposed on the semiconductor channel layer.
- the first memory structure is disposed on the semiconductor channel layer.
- the first memory structure includes a first bottom plate, a first top plate, and a first memory element layer.
- the first top plate is disposed on the first bottom plate.
- the first memory element layer is disposed between the first bottom plate and the first top plate.
- the first bottom plate contacts the semiconductor channel layer.
- a manufacturing method of a semiconductor device includes the following steps.
- a semiconductor channel layer is formed on a substrate.
- a gate electrode is formed on the semiconductor channel layer.
- a first memory structure is formed on the semiconductor channel layer.
- the first memory structure includes a first bottom plate, a first top plate, and a first memory element layer.
- the first top plate is disposed on the first bottom plate.
- the first memory element layer is disposed between the first bottom plate and the first top plate.
- the first bottom plate contacts the semiconductor channel layer.
- FIG. 1 is a schematic drawing illustrating a semiconductor device according to a first embodiment of the present invention.
- FIG. 2 is a partial enlarged view of the semiconductor device according to the first embodiment of the present invention.
- FIG. 3 is a schematic circuit diagram of the semiconductor device according to the first embodiment of the present invention.
- FIGS. 4-7 are schematic drawings illustrating a manufacturing method of the semiconductor device according to the first embodiment of the present invention, wherein FIG. 5 is a schematic drawing in a step subsequent to FIG. 4 , FIG. 6 is a schematic drawing in a step subsequent to FIG. 5 , and FIG. 7 is a schematic drawing in a step subsequent to FIG. 6 .
- FIG. 8 is a schematic drawing illustrating a semiconductor device according to a second embodiment of the present invention.
- FIG. 9 is a partial enlarged view of the semiconductor device according to the second embodiment of the present invention.
- FIG. 10 is a schematic circuit diagram of the semiconductor device according to the second embodiment of the present invention.
- FIG. 1 is a schematic drawing illustrating a semiconductor device according to a first embodiment of the present invention.
- FIG. 2 is a partial enlarged view of the semiconductor device in this embodiment.
- a semiconductor device 101 is provided in this embodiment.
- the semiconductor device 101 includes a substrate 10 , a semiconductor channel layer 50 , a gate electrode 80 , and a first memory structure S 1 .
- the semiconductor channel layer 50 is disposed on the substrate 10 .
- the gate electrode 80 and the first memory structure S 1 are disposed on the semiconductor channel layer 50 .
- the first memory structure S 1 includes a first bottom plate BP 1 , a first top plate TP 1 , and a first memory element layer M 1 .
- the first top plate TP 1 is disposed on the first bottom plate BP 1 .
- the first memory element layer M 1 is disposed between the first bottom plate BP 1 and the first top plate TP 1 .
- the first bottom plate BP 1 contacts the semiconductor channel layer 50 .
- the substrate 10 may include a semiconductor substrate or a non-semiconductor substrate.
- the semiconductor substrate mentioned above may include a silicon substrate, a silicon germanium substrate, or a silicon-on-insulator (SOI) substrate, and the none-semiconductor substrate mentioned above may include a glass substrate, a plastic substrate, or a ceramic substrate, but not limited thereto.
- a plurality of metal oxide semiconductor (MOS) structures 20 such as silicon based field effect transistors, an interlayer dielectric layer 30 , and interconnection structures disposed in the interlayer dielectric layer 30 (such as a first interconnection structure 41 and a second interconnection structure 42 shown in FIG. 1 ) may be formed on the substrate 10 , and the semiconductor channel layer 50 , the gate electrode 80 , and the first memory structure S 1 may be regarded as being disposed in the interconnection structure (such as the second interconnection structure 42 ), but not limited thereto.
- the semiconductor device 101 may further include the first interconnection structure 41 , the second interconnection structure 42 , and the metal oxide semiconductor structures 20 .
- the first interconnection structure 41 may be disposed between the substrate 10 and the semiconductor channel layer 50
- the metal oxide semiconductor structures 20 may be disposed between the substrate 10 and the first interconnection structure 41 , but not limited thereto.
- the semiconductor device 101 may further include a gate dielectric layer 71 and a source/drain electrode SD.
- the source/drain electrode SD is disposed on the semiconductor channel layer 50 .
- the gate dielectric layer 71 is disposed on the semiconductor channel layer 50 , the first memory structure S 1 , and the source/drain electrode SD, and the gate electrode 80 is disposed on the gate dielectric layer 71 .
- the gate electrode 80 , the gate dielectric layer 71 , the semiconductor channel layer 50 , the source/drain electrode SD, and the first bottom plate BP 1 may form a transistor T.
- the first bottom plate BP 1 of the first memory structure S 1 may be another source/drain electrode in the transistor T, and one source/drain electrode of the transistor T may be used as the first bottom plate BP 1 of the first memory structure S 1 in order to integrate the transistor T and the first memory structure S 1 for structure simplification and process simplification.
- the gate electrode 80 may overlap a part of the first memory structure S 1 and a part of the source/drain electrode SD in a thickness direction Z of the substrate 10 .
- apart of the first memory structure S 1 may be disposed between the gate electrode 80 and the semiconductor channel layer 50 in the thickness direction Z of the substrate 10 , but not limited thereto. Additionally, in some embodiments, the gate electrode may not overlap the first memory structure S 1 and/or the source/drain electrode SD according to some considerations.
- the gate electrode 80 , the first bottom plate BP 1 , the first top plate TP 1 , the source/drain electrode SD, the first interconnection structure 41 , and the second interconnection structure 42 may respectively include metal conductive materials, such as tungsten (W), aluminum (Al), copper (Cu), titanium aluminide (TiAl), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum oxide (TiAlO), or other suitable metal or non-metal conductive materials.
- the gate dielectric layer 71 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) material, or other appropriate dielectric materials.
- the high-k material mentioned above may include hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), or other appropriate high-k materials.
- the semiconductor channel layer 50 may include a semiconductor material, such as an oxide semiconductor material, a polysilicon semiconductor material, an amorphous silicon semiconductor material, or other suitable semiconductor materials.
- the oxide semiconductor material mentioned above may include II-VI compounds (such as zinc oxide, ZnO), II-VI compounds doped with alkaline-earth metals (such as zinc magnesium oxide, ZnMgO), II-VI compounds doped with IIIA compounds (such as indium gallium zinc oxide, IGZO), II-VI compounds doped with VA compounds (such as stannum stibium oxide, SnSbO 2 ), II-VI compounds doped with VIA compounds (such as zinc selenium oxide, ZnSeO), II-VI compounds doped with transition metals (such as zinc zirconium oxide, ZnZrO), or other oxide semiconductor materials composed of mixtures of the above-mentioned materials, but not limited thereto.
- II-VI compounds such as zinc oxide, ZnO
- II-VI compounds doped with alkaline-earth metals such as zinc magnesium oxide, ZnMgO
- II-VI compounds doped with IIIA compounds such as indium gallium zinc oxide, IGZO
- the semiconductor channel layer 50 may be a single layer or a multiple layer structure formed by the above-mentioned oxide semiconductor materials, and the crystalline conditions of the semiconductor channel layer 50 is not limited also.
- the semiconductor channel layer 50 may be amorphous IGZO (a-IGZO), crystal IGZO (c-IGZO), or C-axis aligned crystal IGZO (CAAC-IGZO).
- the first memory structure S 1 may include a capacitor structure, a random access memory (RAM) structure, a resistive RAM (RRAM) structure, a phase change RAM (PCRAM) structure, a magnetoresistive RAM (MRAM) structure, a ferroelectric RAM (FeRAM) structure, or other suitable memory structures.
- the first bottom plate BP 1 and the first top plate TP 1 may be regarded as a bottom electrode and a top electrode respectively, and the first memory element layer M 1 disposed between the first bottom plate BP 1 and the first top plate TP 1 may include different material compositions in accordance with the type of the first memory structure S 1 .
- the first memory element layer M 1 in the first memory structure S 1 may include a dielectric material, a material with switchable resistance, a phase change material, a magnetic tunnel junction (MTJ) film stack, a ferroelectric material, or other suitable memory element materials.
- the dielectric material mentioned above may include a high-k material.
- the material with switchable resistance mentioned above may include oxide (such as silicon oxide, hafnium oxide, titanium oxide, tantalum oxide, and aluminum oxide), perovskite material, transition metal oxide, chalcogenide, colossal magnetoresistance (CMR) material (such as praseodymium calcium manganese oxide), or other suitable materials with switchable resistance.
- oxide such as silicon oxide, hafnium oxide, titanium oxide, tantalum oxide, and aluminum oxide
- perovskite material such as silicon oxide, hafnium oxide, titanium oxide, tantalum oxide, and aluminum oxide
- perovskite material such as silicon oxide, hafnium oxide, titanium oxide, tantalum oxide, and
- the phase change material mentioned above may include germanium antimony telluride (Ge 2 Sb 2 Te 5 , GST) or other suitable phase change materials.
- the MTJ film stack mentioned above may include a stack composed of a metal conductive material, a ferromagnetic material (such as iron or cobalt-iron), and an antiferromagnetic material (such as iron manganese or cobalt/platinum multilayer), or a MTJ film stack formed by other suitable materials.
- the ferroelectric material mentioned above may include perovskite oxide material, such as hafnium zirconium oxide (HfZrO x ), barium titanate (BaTiO 3 ), lead titanate (PbTiO 3 ), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT), and barium strontium titanate (Ba x Sr 1-x TiO 3 , BST), or other suitable ferroelectric materials.
- perovskite oxide material such as hafnium zirconium oxide (HfZrO x ), barium titanate (BaTiO 3 ), lead titanate (PbTiO 3 ), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT), and barium strontium titanate (Ba x Sr 1-x TiO 3 , BST), or other suitable ferroelectric materials.
- FIG. 3 is a schematic circuit diagram of the semiconductor device 101 in this embodiment.
- the gate electrode 80 of the transistor T may be electrically connected with a word line WL
- the source/drain electrode SD of the transistor T may be electrically connected with a bit line BL.
- the first memory structure S 1 is a resistive random access memory (RRAM) structure
- a terminal of the first memory structure S 1 (such as the first bottom plate BP 1 ) may be connected with the transistor T
- another terminal of the first memory structure S 1 (such as the first top plate TP 1 ) may be connected to ground, but not limited thereto.
- RRAM resistive random access memory
- the first memory element layer M 1 may have different resistance for data storage.
- a memory cell composed of the transistor T and the first memory structure S 1 there may be not any signal applied to the source/drain electrode SD from the bit line BL, and a low level signal may be applied to the gate electrode 80 by the word line WL.
- a high level signal may be applied to the gate electrode 80 by the word line WL, and a set voltage (V set ) may be applied to the source/drain electrode SD by the bit line BL.
- a high level signal may be applied to the gate electrode 80 by the word line WL, and the resistance may be detected via the bit line BL.
- a reset operation a high level signal may be applied to the gate electrode 80 by the word line WL, and a reset voltage (V reset ) may be applied to the source/drain electrode SD by the bit line BL.
- V reset reset voltage
- the operation method of the semiconductor device 101 in this embodiment is not limited to the conditions described above and may be modified according to design requirements and/or the types of the first memory structure S 1 .
- the semiconductor device 101 may further include a back gate electrode BG disposed under the semiconductor channel layer 50 . Interference in the operations mentioned above may be reduced by the collaboration between the back gate electrode BG and the gate electrode 80 , and the operation performance of the semiconductor device 101 may be improved accordingly, but not limited thereto.
- FIG. 2 and FIGS. 4-7 are schematic drawings illustrating a manufacturing method of the semiconductor device 101 in this embodiment.
- FIG. 5 is a schematic drawing in a step subsequent to FIG. 4
- FIG. 6 is a schematic drawing in a step subsequent to FIG. 5
- FIG. 7 is a schematic drawing in a step subsequent to FIG. 6
- FIG. 2 may be regarded as a schematic drawing in a step subsequent to FIG. 7 .
- the manufacturing method of the semiconductor device in this embodiment may include the following steps. Firstly, the semiconductor channel layer 50 is formed on the substrate 10 .
- the gate electrode 80 is formed on the semiconductor channel layer 50 .
- the first memory structure S 1 is formed on the semiconductor channel layer 50 .
- the first memory structure S 1 includes the first bottom plate BP 1 , the first top plate TP 1 , and the first memory element layer M 1 .
- the first top plate TP 1 is disposed on the first bottom plate BP 1 .
- the first memory element layer M 1 is disposed between the first bottom plate BP 1 and the first top plate TP 1 .
- the first bottom plate BP 1 contacts the semiconductor channel layer 50 .
- the manufacturing method of the semiconductor device 101 in this embodiment may include but is not limited to the following steps.
- the interlayer dielectric layer 30 may include a first interlayer dielectric layer 31 and a second interlayer dielectric layer 32 .
- the first interlayer dielectric layer 31 and the second interlayer dielectric layer 32 may respectively include silicon oxide, silicon oxynitride, low dielectric constant (low-k) materials, or other suitable insulation materials.
- the back gate electrode BG may be formed in the first interlayer dielectric layer 31
- the semiconductor channel layer 50 may be formed on the first interlayer dielectric layer 31
- the second interlayer dielectric layer 32 may cover the transistor T and the first memory structure S 1 , but not limited thereto.
- the back gate electrode BG may be a part of the second interconnection structure 42 and/or the back gate electrode BG may be formed by the process of forming the second interconnection structure 42 .
- the back gate electrode BG may be connected downwards to the first interconnection structure 41 , and the back gate electrode BG may include metal conductive materials, such as tungsten, aluminum, copper, titanium aluminide, titanium, titanium nitride, tantalum, tantalum nitride, titanium aluminum oxide, or other suitable metal or non-metal conductive materials, but not limited thereto.
- the first interconnection structure 41 and the second interconnection structure 42 may include a plurality of metal conductive layers and a plurality of conductive plugs alternately disposed in the thickness direction Z and connected with one another, and the back gate electrode BG and one metal conductive layer in the second interconnection structure 42 may be formed concurrently by the same process, but not limited thereto.
- the semiconductor channel layer 50 , a first conductive layer 61 , a memory element material 62 , and a second conductive layer 63 may be sequentially formed on the first interlayer dielectric layer 31 .
- the first conductive layer 61 is formed on the semiconductor channel layer 50
- the memory element material 62 is formed on the first conductive layer 61
- the second conductive layer 63 is formed on the memory element material 62 .
- the second conductive layer 63 , the memory element material 62 , and the first conductive layer 61 are patterned for forming the first memory structure S 1 and the source/drain electrode SD.
- At least a part of the first conductive layer 61 may be patterned to be the first bottom plate BP 1 and the source/drain electrode SD separated from each other.
- At least a part of the memory element material 62 may be patterned to be the first memory element layer M 1 and a second memory element layer M 2 separated from each other.
- At least a part of the second conductive layer 63 may be patterned to be the first top plate TP 1 and a second top plate TP 2 separated from each other.
- the material composition of the first bottom plate BP may be identical to the material composition of the source/drain electrode SD
- the material composition of the first memory element layer M 1 may be identical to the material composition of the second memory element layer M 2
- the material composition of the first top plate TP 1 may be identical to the material composition of the second top plate TP 2 , but not limited thereto.
- the first bottom plate BP 1 and the source/drain electrode SD may be formed on the same plane (such as the top surface of the semiconductor channel layer 50 ), and the first bottom plate BP 1 and the source/drain electrode SD may be formed concurrently by the same process, but not limited thereto.
- the first bottom plate BP 1 and the source/drain electrode SD may directly and physically contact the top surface of the semiconductor channel layer 50 respectively, and the first bottom plate BP 1 may be regarded as another source/drain electrode.
- the first bottom plate BP 1 , the first memory element layer M 1 , and the first top plate TP 1 may be stacked in the thickness direction Z to be the first memory structure S 1 , and the source/drain electrode SD, the second memory element layer M 2 , and the second top plate TP 2 may be stacked in the thickness direction Z, but not limited thereto.
- the second memory element layer M 2 and the second top plate TP 2 on the source/drain electrode SD may be removed, and a protection layer 70 may be formed covering the semiconductor channel layer 50 , the first memory structure S 1 , and the source/drain electrode SD after the step of removing the second memory element layer M 2 and the second top plate TP 2 .
- the protection layer 70 may include am oxide semiconductor material similar to the semiconductor channel layer 50 , a material similar to the gate dielectric layer, or other suitable materials.
- the semiconductor channel layer 50 is then patterned for defining a semiconductor island structure required in the transistor. As shown in FIG.
- the gate dielectric layer 71 may be formed on the semiconductor channel layer 50 and the first memory structure S 1 , and the gate electrode 80 may be formed on the gate dielectric layer 71 .
- the second interlayer dielectric layer 32 may be formed covering the transistor T after the step of forming the gate electrode 80 .
- the gate dielectric layer 71 and the protection layer 70 may be regarded as the gate dielectric layer in the transistor T when the material composition of the protection layer 70 is the same as the material composition of the gate dielectric layer 71 .
- the gate dielectric layer 71 may cover the semiconductor channel layer 50 , the first memory structure S 1 , and the source/drain electrode SD, and the gate dielectric layer 71 may cover the sidewall of the semiconductor channel layer 50 , the sidewall of the first bottom plate BP 1 , the sidewall of the first memory element layer M 1 , and the sidewall of the first top plate TP 1 , but not limited thereto.
- the transistor T and the first memory structure S 1 may be formed by the process of forming the interconnection structure, and the structure of the memory cell may be simplified by integrating the transistor T with the first memory structure S 1 . More memory cells composed of the transistor T and the first memory structure S 1 may be formed at different levels in the interconnection structure for increasing the memory cell density accordingly.
- FIG. 8 is a schematic drawing illustrating a semiconductor device 102 according to a second embodiment of the present invention.
- FIG. 9 is a partial enlarged view of the semiconductor device 102 in this embodiment.
- the semiconductor device 102 may further include a second memory structure S 1 disposed on the semiconductor channel layer 50 .
- the first memory structure S 1 and the second memory structure S 2 are disposed at two opposite sides of the gate electrode 80 respectively.
- the second memory structure S 2 may include a second bottom plate BP 2 , a second memory element layer M 2 , and a second top plate TP 2 .
- the second top plate TP 2 is disposed on the second bottom plate BP 2 ; and the second memory element layer M 2 is disposed between the second bottom plate BP 2 and the second top plate TP 2 .
- the second bottom plate BP 2 contacts the semiconductor channel layer 50 .
- the gate dielectric layer 71 may be disposed on the semiconductor channel layer 50 , the first memory structure S 1 , and the second memory structure S 2 .
- the gate electrode 80 , the gate dielectric layer 71 , the semiconductor channel layer 50 , the first bottom plate BP 1 , and the second bottom plate BP 2 form a transistor T.
- the first bottom plate BP 1 of the first memory structure S 1 may be a source/drain electrode in the transistor T
- the second bottom plate BP 2 of the second memory structure S 2 may be another source/drain electrode in the transistor T. Accordingly, the structure and the process may be simplified by integrating the transistor T, the first memory structure S 1 , and the second memory structure S 2 .
- the gate electrode 80 may overlap a part of the first memory structure S 1 and a part of the second memory structure S 2 in the thickness direction Z of the substrate 10 .
- the first memory structure S 1 (such as a part of the first top plate TP 1 , a part of the first memory element layer M 1 , and/or a part of the first bottom plate BP 1 ) may be disposed between the gate electrode 80 and the semiconductor channel layer 50 in the thickness direction Z of the substrate 10
- a part of the second memory structure S 2 (such as a part of the second top plate TP 2 , a part of the second memory element layer M 2 , and/or apart of the second bottom plate BP 2 ) may be disposed between the gate electrode 80 and the semiconductor channel layer 50 in the thickness direction Z of the substrate 10 , but not limited thereto.
- the gate electrode 80 may not overlap the first memory structure S 1 and/or the second memory structure S 2 according to some considerations. Additionally, the gate dielectric layer 71 in this embodiment may be formed on the semiconductor channel layer 50 , the first memory structure S 1 , and the second memory structure S 2 , and the gate electrode 80 may be formed on the gate dielectric layer 71 . Therefore, the gate dielectric layer 71 may cover the semiconductor channel layer 50 , the first memory structure S 1 , and the second memory structure S 2 .
- the gate dielectric layer 71 may cover the sidewall of the semiconductor channel layer 50 , the sidewall of the first bottom plate BP 1 , the sidewall of the first memory element layer M 1 , the sidewall of the first top plate TP 1 , the sidewall of the second bottom plate BP 2 , the sidewall of the second memory element layer M 2 , and the sidewall of the second top plate TP 2 , but not limited thereto.
- the second memory structure S 2 may include a random access memory (RAM) structure, a resistive RAM structure, a phase change RAM structure, a magnetoresistive RAM structure, a ferroelectric RAM structure, or other suitable memory structures.
- the material composition of the second memory element layer M 2 may be similar to the material composition of the first memory element layer M 1 , but not limited thereto.
- FIG. 10 is a schematic circuit diagram of the semiconductor device 102 in this embodiment.
- the gate electrode 80 of the transistor T may be electrically connected with the word line WL.
- a terminal of the first memory structure S 1 (such as the first bottom plate BP 1 ) may be connected with the transistor T
- another terminal of the first memory structure S 1 such as the first top plate TP 1
- a terminal of the second memory structure S 2 (such as the second bottom plate BP 2 ) may be connected with the transistor T
- another terminal of the second memory structure S 2 (such as the second top plate TP 2 ) may be electrically connected with the bit line BL, but not limited thereto.
- the first memory element layer M 1 and/or the second memory element layer M 2 may have different resistance for data storage.
- a memory cell composed of the transistor T, the first memory structure S 1 , and the second memory structure S 2 there may be not any signal applied to the second memory structure S 2 from the bit line BL, and a high level signal may be applied to the gate electrode 80 by the word line WL.
- a low level signal may be applied to the gate electrode 80 by the word line WL, and a set voltage may be applied to the second top plate TP 2 of the second memory structure S 2 by the bit line BL.
- a low level signal may be applied to the gate electrode 80 by the word line WL, and the resistance may be detected via the bit line BL.
- a reset operation a low level signal may be applied to the gate electrode 80 by the word line WL, and a reset voltage may be applied to the second top plate TP 2 of the second memory structure S 2 by the bit line BL.
- the set voltage used in the writing operation of this embodiment may be higher than the set voltage used in the first embodiment described above (for example, the set voltage in this embodiment may be twice as high as the set voltage in the first embodiment), and the reset voltage used in the reset operation of this embodiment may be higher than the reset voltage used in the first embodiment described above (for example, the reset voltage in this embodiment may be twice as high as the reset voltage in the first embodiment) because of the two resistive random access memory structures, but not limited thereto. Additionally, because of the two resistive random access memory structures, the memory cell in this embodiment may be used to perform a multiple signal level operation.
- the operation method of the semiconductor device 102 in this embodiment is not limited to the conditions described above and may be modified according to design requirements and/or the types of the first memory structure S 1 and the second memory structure S 2 .
- FIG. 9 may be regarded as a schematic drawing in a step subsequent to 5.
- the second conductive layer 63 , the memory element material 62 , and the first conductive layer 61 may be patterned for forming the first memory structure S 1 and the second memory structure S 2 .
- the first memory structure S 1 and the second memory structure S 2 are formed on the semiconductor channel layer 50 .
- the first memory structure S 1 and the second memory structure S 2 may be formed at two opposite sides of the gate electrode 80 respectively. In other words, the first memory structure S 1 and the second memory structure S 2 may be formed concurrently by the same process, but not limited thereto.
- At least a part of the first conductive layer 61 may be patterned to be the first bottom plate BP 1 and the second bottom plate BP 2 separated from each other, at least a part of the memory element material 62 may be patterned to be the first memory element layer M 1 and the second memory element layer M 2 separated from each other, and at least a part of the second conductive layer 62 may be patterned to be the first top plate TP 1 and the second top plate TP 2 separated from each other.
- the material composition of the first bottom plate BP 1 may be identical to the material composition of the second bottom plate BP 2 , but not limited thereto.
- first bottom plate BP 1 and the second bottom plate BP 2 may be formed on the same plane (such as the top surface of the semiconductor channel layer 50 ), and the first bottom plate BP 1 and the second bottom plate BP 2 may be formed concurrently by the same process, but not limited thereto. Additionally, in some embodiments, the first bottom plate BP 1 and the second bottom plate BP 2 may directly and physically contact the top surface of the semiconductor channel layer 50 respectively.
- the first bottom plate BP 1 , the first memory element layer M 1 , and the first top plate TP 1 may be stacked in the thickness direction Z to be the first memory structure S 1
- the second bottom plate BP 2 , the second memory element layer M 2 , and the second top plate TP 2 may be stacked in the thickness direction Z to be the second memory structure S 2 .
- At least one source/drain electrode of the transistor may be integrated with the bottom plate of the memory structure for simplifying the structure and the process of the memory cell including the memory structure and the transistor.
- the memory cell density may be enhanced accordingly.
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Abstract
Description
- The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device including a memory structure and a manufacturing method thereof.
- Dynamic random access memory (DRAM) is a kind of volatile storage device which is an indispensable key part of many electronic products. DRAM includes a great number of memory cells arranged for forming an array configured to store data. Each of the memory cells may be composed of a metal oxide semiconductor (MOS) transistor connected with a capacitor. Generally, semiconductor processes may be roughly divided into a front end of line (FEOL) process for forming transistors on a wafer and a back end of line (BEOL) process for forming parts such as connection structures, inter layer dielectric, interconnection structure, and contact pads on the transistors. The integrity of the integrated circuit may be increased when memory cells are formed by the BEOL process. However, there are many problems, such as process complexity, low manufacturing yield, and limitation of memory cell density when forming the memory cells by the BEOL process, and appropriate design modifications are required for improving these problems
- A semiconductor device and a manufacturing method thereof are provided in the present invention. A memory structure is integrated with a transistor structure for process simplification and/or memory density enhancement.
- According to an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor channel layer, a gate electrode, and a first memory structure. The semiconductor channel layer is disposed on the substrate. The gate electrode is disposed on the semiconductor channel layer. The first memory structure is disposed on the semiconductor channel layer. The first memory structure includes a first bottom plate, a first top plate, and a first memory element layer. The first top plate is disposed on the first bottom plate. The first memory element layer is disposed between the first bottom plate and the first top plate. The first bottom plate contacts the semiconductor channel layer.
- According to an embodiment of the present invention, a manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A semiconductor channel layer is formed on a substrate. A gate electrode is formed on the semiconductor channel layer. A first memory structure is formed on the semiconductor channel layer. The first memory structure includes a first bottom plate, a first top plate, and a first memory element layer. The first top plate is disposed on the first bottom plate. The first memory element layer is disposed between the first bottom plate and the first top plate. The first bottom plate contacts the semiconductor channel layer.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIG. 1 is a schematic drawing illustrating a semiconductor device according to a first embodiment of the present invention. -
FIG. 2 is a partial enlarged view of the semiconductor device according to the first embodiment of the present invention. -
FIG. 3 is a schematic circuit diagram of the semiconductor device according to the first embodiment of the present invention. -
FIGS. 4-7 are schematic drawings illustrating a manufacturing method of the semiconductor device according to the first embodiment of the present invention, whereinFIG. 5 is a schematic drawing in a step subsequent toFIG. 4 ,FIG. 6 is a schematic drawing in a step subsequent toFIG. 5 , andFIG. 7 is a schematic drawing in a step subsequent toFIG. 6 . -
FIG. 8 is a schematic drawing illustrating a semiconductor device according to a second embodiment of the present invention. -
FIG. 9 is a partial enlarged view of the semiconductor device according to the second embodiment of the present invention. -
FIG. 10 is a schematic circuit diagram of the semiconductor device according to the second embodiment of the present invention. - Please refer to
FIG. 1 andFIG. 2 .FIG. 1 is a schematic drawing illustrating a semiconductor device according to a first embodiment of the present invention.FIG. 2 is a partial enlarged view of the semiconductor device in this embodiment. As shown inFIG. 1 andFIG. 2 , asemiconductor device 101 is provided in this embodiment. Thesemiconductor device 101 includes asubstrate 10, asemiconductor channel layer 50, agate electrode 80, and a first memory structure S1. Thesemiconductor channel layer 50 is disposed on thesubstrate 10. Thegate electrode 80 and the first memory structure S1 are disposed on thesemiconductor channel layer 50. The first memory structure S1 includes a first bottom plate BP1, a first top plate TP1, and a first memory element layer M1. The first top plate TP1 is disposed on the first bottom plate BP1. The first memory element layer M1 is disposed between the first bottom plate BP1 and the first top plate TP1. The first bottom plate BP1 contacts thesemiconductor channel layer 50. In some embodiments, thesubstrate 10 may include a semiconductor substrate or a non-semiconductor substrate. The semiconductor substrate mentioned above may include a silicon substrate, a silicon germanium substrate, or a silicon-on-insulator (SOI) substrate, and the none-semiconductor substrate mentioned above may include a glass substrate, a plastic substrate, or a ceramic substrate, but not limited thereto. For example, when thesubstrate 10 is a semiconductor substrate, a plurality of metal oxide semiconductor (MOS)structures 20, such as silicon based field effect transistors, an interlayerdielectric layer 30, and interconnection structures disposed in the interlayer dielectric layer 30 (such as afirst interconnection structure 41 and asecond interconnection structure 42 shown inFIG. 1 ) may be formed on thesubstrate 10, and thesemiconductor channel layer 50, thegate electrode 80, and the first memory structure S1 may be regarded as being disposed in the interconnection structure (such as the second interconnection structure 42), but not limited thereto. In other words, in some embodiments, thesemiconductor device 101 may further include thefirst interconnection structure 41, thesecond interconnection structure 42, and the metaloxide semiconductor structures 20. Thefirst interconnection structure 41 may be disposed between thesubstrate 10 and thesemiconductor channel layer 50, and the metaloxide semiconductor structures 20 may be disposed between thesubstrate 10 and thefirst interconnection structure 41, but not limited thereto. - As shown in
FIG. 1 andFIG. 2 , in some embodiments, thesemiconductor device 101 may further include a gatedielectric layer 71 and a source/drain electrode SD. The source/drain electrode SD is disposed on thesemiconductor channel layer 50. The gatedielectric layer 71 is disposed on thesemiconductor channel layer 50, the first memory structure S1, and the source/drain electrode SD, and thegate electrode 80 is disposed on the gatedielectric layer 71. Thegate electrode 80, the gatedielectric layer 71, thesemiconductor channel layer 50, the source/drain electrode SD, and the first bottom plate BP1 may form a transistor T. In other words, the first bottom plate BP1 of the first memory structure S1 may be another source/drain electrode in the transistor T, and one source/drain electrode of the transistor T may be used as the first bottom plate BP1 of the first memory structure S1 in order to integrate the transistor T and the first memory structure S1 for structure simplification and process simplification. Additionally, in some embodiments, thegate electrode 80 may overlap a part of the first memory structure S1 and a part of the source/drain electrode SD in a thickness direction Z of thesubstrate 10. Therefore, apart of the first memory structure S1 (such as apart of the first top plate TP1, apart of the first memory element layer M1, and/or a part of the first bottom plate BP1) may be disposed between thegate electrode 80 and thesemiconductor channel layer 50 in the thickness direction Z of thesubstrate 10, but not limited thereto. Additionally, in some embodiments, the gate electrode may not overlap the first memory structure S1 and/or the source/drain electrode SD according to some considerations. - In some embodiments, the
gate electrode 80, the first bottom plate BP1, the first top plate TP1, the source/drain electrode SD, thefirst interconnection structure 41, and thesecond interconnection structure 42 may respectively include metal conductive materials, such as tungsten (W), aluminum (Al), copper (Cu), titanium aluminide (TiAl), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum oxide (TiAlO), or other suitable metal or non-metal conductive materials. Thegate dielectric layer 71 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) material, or other appropriate dielectric materials. The high-k material mentioned above may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), or other appropriate high-k materials. Thesemiconductor channel layer 50 may include a semiconductor material, such as an oxide semiconductor material, a polysilicon semiconductor material, an amorphous silicon semiconductor material, or other suitable semiconductor materials. The oxide semiconductor material mentioned above may include II-VI compounds (such as zinc oxide, ZnO), II-VI compounds doped with alkaline-earth metals (such as zinc magnesium oxide, ZnMgO), II-VI compounds doped with IIIA compounds (such as indium gallium zinc oxide, IGZO), II-VI compounds doped with VA compounds (such as stannum stibium oxide, SnSbO2), II-VI compounds doped with VIA compounds (such as zinc selenium oxide, ZnSeO), II-VI compounds doped with transition metals (such as zinc zirconium oxide, ZnZrO), or other oxide semiconductor materials composed of mixtures of the above-mentioned materials, but not limited thereto. Additionally, thesemiconductor channel layer 50 may be a single layer or a multiple layer structure formed by the above-mentioned oxide semiconductor materials, and the crystalline conditions of thesemiconductor channel layer 50 is not limited also. For example, thesemiconductor channel layer 50 may be amorphous IGZO (a-IGZO), crystal IGZO (c-IGZO), or C-axis aligned crystal IGZO (CAAC-IGZO). - In addition, the first memory structure S1 may include a capacitor structure, a random access memory (RAM) structure, a resistive RAM (RRAM) structure, a phase change RAM (PCRAM) structure, a magnetoresistive RAM (MRAM) structure, a ferroelectric RAM (FeRAM) structure, or other suitable memory structures. In the first memory structure S1, the first bottom plate BP1 and the first top plate TP1 may be regarded as a bottom electrode and a top electrode respectively, and the first memory element layer M1 disposed between the first bottom plate BP1 and the first top plate TP1 may include different material compositions in accordance with the type of the first memory structure S1. Therefore, the first memory element layer M1 in the first memory structure S1 may include a dielectric material, a material with switchable resistance, a phase change material, a magnetic tunnel junction (MTJ) film stack, a ferroelectric material, or other suitable memory element materials. The dielectric material mentioned above may include a high-k material. The material with switchable resistance mentioned above may include oxide (such as silicon oxide, hafnium oxide, titanium oxide, tantalum oxide, and aluminum oxide), perovskite material, transition metal oxide, chalcogenide, colossal magnetoresistance (CMR) material (such as praseodymium calcium manganese oxide), or other suitable materials with switchable resistance. The phase change material mentioned above may include germanium antimony telluride (Ge2Sb2Te5, GST) or other suitable phase change materials. The MTJ film stack mentioned above may include a stack composed of a metal conductive material, a ferromagnetic material (such as iron or cobalt-iron), and an antiferromagnetic material (such as iron manganese or cobalt/platinum multilayer), or a MTJ film stack formed by other suitable materials. The ferroelectric material mentioned above may include perovskite oxide material, such as hafnium zirconium oxide (HfZrOx), barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconate titanate (PbZrxTi1-xO3, PZT), and barium strontium titanate (BaxSr1-xTiO3, BST), or other suitable ferroelectric materials.
- Please refer to
FIG. 2 andFIG. 3 .FIG. 3 is a schematic circuit diagram of thesemiconductor device 101 in this embodiment. As shown inFIG. 2 andFIG. 3 , thegate electrode 80 of the transistor T may be electrically connected with a word line WL, and the source/drain electrode SD of the transistor T may be electrically connected with a bit line BL. When the first memory structure S1 is a resistive random access memory (RRAM) structure, a terminal of the first memory structure S1 (such as the first bottom plate BP1) may be connected with the transistor T, and another terminal of the first memory structure S1 (such as the first top plate TP1) may be connected to ground, but not limited thereto. Under this circumstance, by applying different electric fields to the first memory structure S1, the first memory element layer M1 may have different resistance for data storage. For example, when a memory cell composed of the transistor T and the first memory structure S1 is not chosen, there may be not any signal applied to the source/drain electrode SD from the bit line BL, and a low level signal may be applied to thegate electrode 80 by the word line WL. In a writing operation, a high level signal may be applied to thegate electrode 80 by the word line WL, and a set voltage (Vset) may be applied to the source/drain electrode SD by the bit line BL. In a reading operation, a high level signal may be applied to thegate electrode 80 by the word line WL, and the resistance may be detected via the bit line BL. In a reset operation, a high level signal may be applied to thegate electrode 80 by the word line WL, and a reset voltage (Vreset) may be applied to the source/drain electrode SD by the bit line BL. It is worth noting that the operation method of thesemiconductor device 101 in this embodiment is not limited to the conditions described above and may be modified according to design requirements and/or the types of the first memory structure S1. Additionally, in some embodiments, thesemiconductor device 101 may further include a back gate electrode BG disposed under thesemiconductor channel layer 50. Interference in the operations mentioned above may be reduced by the collaboration between the back gate electrode BG and thegate electrode 80, and the operation performance of thesemiconductor device 101 may be improved accordingly, but not limited thereto. - Please refer to
FIGS. 4-7 ,FIG. 1 , andFIG. 2 .FIG. 2 andFIGS. 4-7 are schematic drawings illustrating a manufacturing method of thesemiconductor device 101 in this embodiment.FIG. 5 is a schematic drawing in a step subsequent toFIG. 4 ,FIG. 6 is a schematic drawing in a step subsequent toFIG. 5 ,FIG. 7 is a schematic drawing in a step subsequent toFIG. 6 , andFIG. 2 may be regarded as a schematic drawing in a step subsequent toFIG. 7 . As shown inFIG. 1 andFIG. 2 , the manufacturing method of the semiconductor device in this embodiment may include the following steps. Firstly, thesemiconductor channel layer 50 is formed on thesubstrate 10. Thegate electrode 80 is formed on thesemiconductor channel layer 50. The first memory structure S1 is formed on thesemiconductor channel layer 50. The first memory structure S1 includes the first bottom plate BP1, the first top plate TP1, and the first memory element layer M1. The first top plate TP1 is disposed on the first bottom plate BP1. The first memory element layer M1 is disposed between the first bottom plate BP1 and the first top plate TP1. The first bottom plate BP1 contacts thesemiconductor channel layer 50. - Specifically, the manufacturing method of the
semiconductor device 101 in this embodiment may include but is not limited to the following steps. As shown inFIG. 2 andFIG. 4 , theinterlayer dielectric layer 30 may include a firstinterlayer dielectric layer 31 and a secondinterlayer dielectric layer 32. The firstinterlayer dielectric layer 31 and the secondinterlayer dielectric layer 32 may respectively include silicon oxide, silicon oxynitride, low dielectric constant (low-k) materials, or other suitable insulation materials. The back gate electrode BG may be formed in the firstinterlayer dielectric layer 31, thesemiconductor channel layer 50 may be formed on the firstinterlayer dielectric layer 31, and the secondinterlayer dielectric layer 32 may cover the transistor T and the first memory structure S1, but not limited thereto. In some embodiments, the back gate electrode BG may be a part of thesecond interconnection structure 42 and/or the back gate electrode BG may be formed by the process of forming thesecond interconnection structure 42. The back gate electrode BG may be connected downwards to thefirst interconnection structure 41, and the back gate electrode BG may include metal conductive materials, such as tungsten, aluminum, copper, titanium aluminide, titanium, titanium nitride, tantalum, tantalum nitride, titanium aluminum oxide, or other suitable metal or non-metal conductive materials, but not limited thereto. For example, thefirst interconnection structure 41 and thesecond interconnection structure 42 may include a plurality of metal conductive layers and a plurality of conductive plugs alternately disposed in the thickness direction Z and connected with one another, and the back gate electrode BG and one metal conductive layer in thesecond interconnection structure 42 may be formed concurrently by the same process, but not limited thereto. - As shown in
FIG. 4 , thesemiconductor channel layer 50, a firstconductive layer 61, amemory element material 62, and a secondconductive layer 63 may be sequentially formed on the firstinterlayer dielectric layer 31. In other words, the firstconductive layer 61 is formed on thesemiconductor channel layer 50, thememory element material 62 is formed on the firstconductive layer 61, and the secondconductive layer 63 is formed on thememory element material 62. Subsequently, as shown inFIG. 4 andFIG. 5 , the secondconductive layer 63, thememory element material 62, and the firstconductive layer 61 are patterned for forming the first memory structure S1 and the source/drain electrode SD. In some embodiments, at least a part of the firstconductive layer 61 may be patterned to be the first bottom plate BP1 and the source/drain electrode SD separated from each other. At least a part of thememory element material 62 may be patterned to be the first memory element layer M1 and a second memory element layer M2 separated from each other. At least a part of the secondconductive layer 63 may be patterned to be the first top plate TP1 and a second top plate TP2 separated from each other. Therefore, the material composition of the first bottom plate BP may be identical to the material composition of the source/drain electrode SD, the material composition of the first memory element layer M1 may be identical to the material composition of the second memory element layer M2, and the material composition of the first top plate TP1 may be identical to the material composition of the second top plate TP2, but not limited thereto. In other words, the first bottom plate BP1 and the source/drain electrode SD may be formed on the same plane (such as the top surface of the semiconductor channel layer 50), and the first bottom plate BP1 and the source/drain electrode SD may be formed concurrently by the same process, but not limited thereto. Additionally, in some embodiments, the first bottom plate BP1 and the source/drain electrode SD may directly and physically contact the top surface of thesemiconductor channel layer 50 respectively, and the first bottom plate BP1 may be regarded as another source/drain electrode. The first bottom plate BP1, the first memory element layer M1, and the first top plate TP1 may be stacked in the thickness direction Z to be the first memory structure S1, and the source/drain electrode SD, the second memory element layer M2, and the second top plate TP2 may be stacked in the thickness direction Z, but not limited thereto. - As shown in
FIG. 5 andFIG. 6 , in some embodiments, the second memory element layer M2 and the second top plate TP2 on the source/drain electrode SD may be removed, and aprotection layer 70 may be formed covering thesemiconductor channel layer 50, the first memory structure S1, and the source/drain electrode SD after the step of removing the second memory element layer M2 and the second top plate TP2. In some embodiments, theprotection layer 70 may include am oxide semiconductor material similar to thesemiconductor channel layer 50, a material similar to the gate dielectric layer, or other suitable materials. As shown inFIG. 7 , thesemiconductor channel layer 50 is then patterned for defining a semiconductor island structure required in the transistor. As shown inFIG. 2 , before the step of forming thegate electrode 80, thegate dielectric layer 71 may be formed on thesemiconductor channel layer 50 and the first memory structure S1, and thegate electrode 80 may be formed on thegate dielectric layer 71. In some embodiments, the secondinterlayer dielectric layer 32 may be formed covering the transistor T after the step of forming thegate electrode 80. Thegate dielectric layer 71 and theprotection layer 70 may be regarded as the gate dielectric layer in the transistor T when the material composition of theprotection layer 70 is the same as the material composition of thegate dielectric layer 71. Therefore, thegate dielectric layer 71 may cover thesemiconductor channel layer 50, the first memory structure S1, and the source/drain electrode SD, and thegate dielectric layer 71 may cover the sidewall of thesemiconductor channel layer 50, the sidewall of the first bottom plate BP1, the sidewall of the first memory element layer M1, and the sidewall of the first top plate TP1, but not limited thereto. - It is worth noting that, in the present invention, the transistor T and the first memory structure S1 may be formed by the process of forming the interconnection structure, and the structure of the memory cell may be simplified by integrating the transistor T with the first memory structure S1. More memory cells composed of the transistor T and the first memory structure S1 may be formed at different levels in the interconnection structure for increasing the memory cell density accordingly.
- The following description will detail the different embodiments of the present invention. To simplify the description, identical components in each of the following embodiments are marked with identical symbols. For making it easier to understand the differences between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.
- Please refer to
FIG. 8 andFIG. 9 .FIG. 8 is a schematic drawing illustrating asemiconductor device 102 according to a second embodiment of the present invention.FIG. 9 is a partial enlarged view of thesemiconductor device 102 in this embodiment. As shown inFIG. 8 andFIG. 9 , the difference between thesemiconductor device 102 in this embodiment and the semiconductor device in the first embodiment described above is that thesemiconductor device 102 may further include a second memory structure S1 disposed on thesemiconductor channel layer 50. The first memory structure S1 and the second memory structure S2 are disposed at two opposite sides of thegate electrode 80 respectively. The second memory structure S2 may include a second bottom plate BP2, a second memory element layer M2, and a second top plate TP2. The second top plate TP2 is disposed on the second bottom plate BP2; and the second memory element layer M2 is disposed between the second bottom plate BP2 and the second top plate TP2. The second bottom plate BP2 contacts thesemiconductor channel layer 50. In this embodiment, thegate dielectric layer 71 may be disposed on thesemiconductor channel layer 50, the first memory structure S1, and the second memory structure S2. Thegate electrode 80, thegate dielectric layer 71, thesemiconductor channel layer 50, the first bottom plate BP1, and the second bottom plate BP2 form a transistor T. In other words, the first bottom plate BP1 of the first memory structure S1 may be a source/drain electrode in the transistor T, and the second bottom plate BP2 of the second memory structure S2 may be another source/drain electrode in the transistor T. Accordingly, the structure and the process may be simplified by integrating the transistor T, the first memory structure S1, and the second memory structure S2. - In some embodiments, the
gate electrode 80 may overlap a part of the first memory structure S1 and a part of the second memory structure S2 in the thickness direction Z of thesubstrate 10. Apart of the first memory structure S1 (such as a part of the first top plate TP1, a part of the first memory element layer M1, and/or a part of the first bottom plate BP1) may be disposed between thegate electrode 80 and thesemiconductor channel layer 50 in the thickness direction Z of thesubstrate 10, and a part of the second memory structure S2 (such as a part of the second top plate TP2, a part of the second memory element layer M2, and/or apart of the second bottom plate BP2) may be disposed between thegate electrode 80 and thesemiconductor channel layer 50 in the thickness direction Z of thesubstrate 10, but not limited thereto. In some embodiments, thegate electrode 80 may not overlap the first memory structure S1 and/or the second memory structure S2 according to some considerations. Additionally, thegate dielectric layer 71 in this embodiment may be formed on thesemiconductor channel layer 50, the first memory structure S1, and the second memory structure S2, and thegate electrode 80 may be formed on thegate dielectric layer 71. Therefore, thegate dielectric layer 71 may cover thesemiconductor channel layer 50, the first memory structure S1, and the second memory structure S2. Thegate dielectric layer 71 may cover the sidewall of thesemiconductor channel layer 50, the sidewall of the first bottom plate BP1, the sidewall of the first memory element layer M1, the sidewall of the first top plate TP1, the sidewall of the second bottom plate BP2, the sidewall of the second memory element layer M2, and the sidewall of the second top plate TP2, but not limited thereto. In some embodiments, the second memory structure S2 may include a random access memory (RAM) structure, a resistive RAM structure, a phase change RAM structure, a magnetoresistive RAM structure, a ferroelectric RAM structure, or other suitable memory structures. The material composition of the second memory element layer M2 may be similar to the material composition of the first memory element layer M1, but not limited thereto. - Please refer to
FIG. 9 andFIG. 10 .FIG. 10 is a schematic circuit diagram of thesemiconductor device 102 in this embodiment. As shown inFIG. 9 andFIG. 10 , thegate electrode 80 of the transistor T may be electrically connected with the word line WL. When the first memory structure S1 and the second memory structure S2 are resistive random access memory structures, a terminal of the first memory structure S1 (such as the first bottom plate BP1) may be connected with the transistor T, another terminal of the first memory structure S1 (such as the first top plate TP1) may be connected to ground, a terminal of the second memory structure S2 (such as the second bottom plate BP2) may be connected with the transistor T, and another terminal of the second memory structure S2 (such as the second top plate TP2) may be electrically connected with the bit line BL, but not limited thereto. Under this circumstance, by applying different electric fields to the first memory structure S1 and/or the second memory structure S2, the first memory element layer M1 and/or the second memory element layer M2 may have different resistance for data storage. For example, when a memory cell composed of the transistor T, the first memory structure S1, and the second memory structure S2 is not chosen, there may be not any signal applied to the second memory structure S2 from the bit line BL, and a high level signal may be applied to thegate electrode 80 by the word line WL. In a writing operation, a low level signal may be applied to thegate electrode 80 by the word line WL, and a set voltage may be applied to the second top plate TP2 of the second memory structure S2 by the bit line BL. In a reading operation, a low level signal may be applied to thegate electrode 80 by the word line WL, and the resistance may be detected via the bit line BL. In a reset operation, a low level signal may be applied to thegate electrode 80 by the word line WL, and a reset voltage may be applied to the second top plate TP2 of the second memory structure S2 by the bit line BL. It is worth noting that the set voltage used in the writing operation of this embodiment may be higher than the set voltage used in the first embodiment described above (for example, the set voltage in this embodiment may be twice as high as the set voltage in the first embodiment), and the reset voltage used in the reset operation of this embodiment may be higher than the reset voltage used in the first embodiment described above (for example, the reset voltage in this embodiment may be twice as high as the reset voltage in the first embodiment) because of the two resistive random access memory structures, but not limited thereto. Additionally, because of the two resistive random access memory structures, the memory cell in this embodiment may be used to perform a multiple signal level operation. However, the operation method of thesemiconductor device 102 in this embodiment is not limited to the conditions described above and may be modified according to design requirements and/or the types of the first memory structure S1 and the second memory structure S2. - Please refer to
FIG. 5 andFIG. 9 .FIG. 9 may be regarded as a schematic drawing in a step subsequent to 5. As shown inFIG. 5 andFIG. 9 , in the manufacturing method of thesemiconductor device 102, the secondconductive layer 63, thememory element material 62, and the firstconductive layer 61 may be patterned for forming the first memory structure S1 and the second memory structure S2. The first memory structure S1 and the second memory structure S2 are formed on thesemiconductor channel layer 50. The first memory structure S1 and the second memory structure S2 may be formed at two opposite sides of thegate electrode 80 respectively. In other words, the first memory structure S1 and the second memory structure S2 may be formed concurrently by the same process, but not limited thereto. In some embodiments, at least a part of the firstconductive layer 61 may be patterned to be the first bottom plate BP1 and the second bottom plate BP2 separated from each other, at least a part of thememory element material 62 may be patterned to be the first memory element layer M1 and the second memory element layer M2 separated from each other, and at least a part of the secondconductive layer 62 may be patterned to be the first top plate TP1 and the second top plate TP2 separated from each other. The material composition of the first bottom plate BP1 may be identical to the material composition of the second bottom plate BP2, but not limited thereto. In other words, the first bottom plate BP1 and the second bottom plate BP2 may be formed on the same plane (such as the top surface of the semiconductor channel layer 50), and the first bottom plate BP1 and the second bottom plate BP2 may be formed concurrently by the same process, but not limited thereto. Additionally, in some embodiments, the first bottom plate BP1 and the second bottom plate BP2 may directly and physically contact the top surface of thesemiconductor channel layer 50 respectively. The first bottom plate BP1, the first memory element layer M1, and the first top plate TP1 may be stacked in the thickness direction Z to be the first memory structure S1, and the second bottom plate BP2, the second memory element layer M2, and the second top plate TP2 may be stacked in the thickness direction Z to be the second memory structure S2. - To summarize the above descriptions, in the semiconductor device and the manufacturing method thereof according to the present invention, at least one source/drain electrode of the transistor may be integrated with the bottom plate of the memory structure for simplifying the structure and the process of the memory cell including the memory structure and the transistor. The memory cell density may be enhanced accordingly.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
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US11121140B2 (en) * | 2020-01-08 | 2021-09-14 | Sandisk Technologies Llc | Ferroelectric tunnel junction memory device with integrated ovonic threshold switches |
US20210320148A1 (en) * | 2019-11-23 | 2021-10-14 | Tetramem Inc. | Crossbar array circuit with parallel grounding lines |
US11195999B2 (en) * | 2019-11-13 | 2021-12-07 | International Business Machines Corporation | Phase change material with reduced reset state resistance drift |
US20210391383A1 (en) * | 2020-06-11 | 2021-12-16 | United Microelectronics Corp. | Magnetoresistive random access memory |
US20220148653A1 (en) * | 2020-11-12 | 2022-05-12 | Commissariat à I'Energie Atomique et aux Energies Alternatives | Hybrid resistive memory |
US20220352148A1 (en) * | 2021-04-30 | 2022-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Monolithic three dimensional integrated circuit |
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US20210391470A1 (en) * | 2020-06-15 | 2021-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layered structure, semiconductor device including the same, and manufacturing method thereof |
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US9741721B2 (en) * | 2013-09-27 | 2017-08-22 | Intel Corporation | Low leakage non-planar access transistor for embedded dynamic random access memory (eDRAM) |
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US11195999B2 (en) * | 2019-11-13 | 2021-12-07 | International Business Machines Corporation | Phase change material with reduced reset state resistance drift |
US20210320148A1 (en) * | 2019-11-23 | 2021-10-14 | Tetramem Inc. | Crossbar array circuit with parallel grounding lines |
US11610942B2 (en) * | 2019-11-23 | 2023-03-21 | Tetramem Inc. | Crossbar array circuit with parallel grounding lines |
US11121140B2 (en) * | 2020-01-08 | 2021-09-14 | Sandisk Technologies Llc | Ferroelectric tunnel junction memory device with integrated ovonic threshold switches |
US20210391383A1 (en) * | 2020-06-11 | 2021-12-16 | United Microelectronics Corp. | Magnetoresistive random access memory |
US11569295B2 (en) * | 2020-06-11 | 2023-01-31 | United Microelectronics Corp. | Magnetoresistive random access memory |
US11864391B2 (en) * | 2020-06-11 | 2024-01-02 | United Microelectronics Corp. | Magnetoresistive random access memory |
US20220148653A1 (en) * | 2020-11-12 | 2022-05-12 | Commissariat à I'Energie Atomique et aux Energies Alternatives | Hybrid resistive memory |
US20220352148A1 (en) * | 2021-04-30 | 2022-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Monolithic three dimensional integrated circuit |
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