US20190318931A1 - Self-aligned multiple patterning processes with layered mandrels - Google Patents
Self-aligned multiple patterning processes with layered mandrels Download PDFInfo
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- US20190318931A1 US20190318931A1 US15/950,364 US201815950364A US2019318931A1 US 20190318931 A1 US20190318931 A1 US 20190318931A1 US 201815950364 A US201815950364 A US 201815950364A US 2019318931 A1 US2019318931 A1 US 2019318931A1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
Definitions
- the present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning.
- a back-end-of-line (BEOL) interconnect structure may be used to connect device structures fabricated on a substrate during front-end-of-line (FEOL) processing with each other and with the environment external to the chip.
- Self-aligned patterning processes used to form a BEOL interconnect structure involve mandrel lines as sacrificial features that establish a feature pitch. Sidewall spacers are formed adjacent to the sidewalls of the mandrel lines. After selective removal of the mandrel lines, the spacers are used as an etch mask to etch an underlying hardmask over areas exposed by mandrel removal and areas between the spacers. The pattern is transferred from the hardmask to an interlayer dielectric layer to define trenches in which the wires of the BEOL interconnect structure are formed.
- Cuts may be formed in mandrel lines in order to section the mandrel lines and define discontinuities between the sections that subsequently are used to form adjacent wires that are spaced apart at their tips with a tip-to-tip spacing.
- Non-mandrel cuts may also be formed in the hardmask itself along non-mandrel lines exposed between the sidewall spacers and filled by spacer material when the sidewall spacers are formed on the mandrel lines.
- a pattern reflecting the cut mandrel lines, the non-mandrel lines, and non-mandrel cuts is transferred to the hardmask and subsequently from the hardmask to form the trenches in the interlayer dielectric layer.
- a method in an embodiment of the invention, includes forming a first mandrel line with a first mandrel layer disposed on a hardmask and a second mandrel layer disposed over the first mandrel layer.
- a first section of the second mandrel layer is removed to form a mandrel cut that exposes a first section of the first mandrel layer.
- the first section of the first mandrel layer is arranged along the first mandrel line between respective second sections of the second mandrel layer.
- the second sections of the second mandrel layer are removed with a first etching process to expose the second sections of the first mandrel layer.
- the second sections of the first mandrel layer are removed to expose first portions of the hardmask.
- the first portions of the hardmask are then removed with a second etching process to form a trench.
- a second portion of the hardmask is masked by the first section of the first mandrel layer to form a cut in the first trench in the hardmask.
- FIGS. 1-12 are cross-sectional views of a structure at successive fabrication stages of a processing method in accordance with embodiments of the invention.
- FIG. 5A is a top view of the structure in which FIG. 5 is taken generally along line 5 - 5 .
- FIG. 7A is a top view of the structure in which FIG. 7 is taken generally along line 7 - 7 .
- FIG. 8A is a top view of the structure in which FIG. 8 is taken generally along line 8 - 8 .
- FIG. 9A is a top view of the structure in which FIG. 9 is taken generally along line 9 - 9 .
- FIG. 12A is a top view of the structure in which FIG. 12 is taken generally along line 12 - 12 .
- a structure 10 includes an interlayer dielectric layer 20 , a hardmask 25 , and a multiple-layer mandrel stack 30 .
- the interlayer dielectric layer 20 may be comprised of an electrically-insulating dielectric material, such as hydrogen-enriched silicon oxycarbide (SiCOH) or another type of low-k dielectric material.
- the interlayer dielectric layer 20 may be located on a substrate (not shown in FIG. 1 ) that includes device structures fabricated by front-end-of-line (FEOL) processing to form an integrated circuit.
- the hardmask 25 overlies the interlayer dielectric layer 20 and may be comprised of a metal-based material, such as titanium nitride, suitable for use as a hardmask.
- the multiple-layer mandrel stack 30 includes a lower mandrel layer 32 comprised of a material and an upper mandrel layer 34 comprised of another material different from the material of the lower mandrel layer 32 .
- the materials of the upper mandrel layer 34 and lower mandrel layer 32 are selected so that, as described below, the material of the upper mandrel layer 34 may be selectively removed in an etching process that etches little to no material of the lower mandrel layer 32 .
- the lower mandrel layer 32 may be comprised of, for example, silicon dioxide, silicon oxynitride, silicon nitride, amorphous carbon, or a combination of these materials in a layered arrangement.
- the upper mandrel layer 34 may be comprised of amorphous silicon (a-Si) or another material that can be removed selective to the material of the lower mandrel layer 32 .
- a-Si amorphous silicon
- the material of the lower mandrel layer 32 should also exhibit high etch selectivity to the material of the hardmask 25 .
- the hardmask 25 may be a single hardmask comprised of a metal nitride, such as titanium nitride.
- a metal nitride such as titanium nitride.
- a dielectric hardmask such as a silicon nitride hardmask, is disposed over the metal nitride hardmask; mandrel lines and non-mandrel lines are then separately patterned in the dielectric hardmask and subsequently replicated in the metal oxide hardmask.
- the multiple-layer mandrel stack 30 eliminates the need for an additional dielectric hardmask, and allows for both mandrel lines and non-mandrel lines to be etched as trenches into the hardmask 25 in a single step, as described further below.
- the multiple-layer mandrel stack 30 is etched to form mandrel lines 35 , 37 .
- a patterning layer (not depicted in FIG. 2 ) may be provided over the multiple-layer mandrel stack 30 that masks portions of the bi-layer mandrel stack and leaves other portions of the multiple-layer mandrel stack 30 exposed, and the exposed portions of the bi-layer mandrel stack etched.
- the patterning layer may be comprised of a dielectric material, such as a low-temperature oxide (LTO) of silicon.
- LTO low-temperature oxide
- Each of the mandrel lines 35 , 37 includes a section of the upper mandrel layer 34 that is stacked over a section of the lower mandrel layer 32 in the representative bi-layer arrangement.
- the section of the lower mandrel layer 32 of each of the mandrel lines 35 , 37 is in direct contact with the hardmask 25 .
- the mandrel lines 35 , 37 which are comprised of a stack containing multiple materials provided by the different layers, are used in a self-aligned multiple patterning process and, in particular, are used in a self-aligned double patterning process.
- a lithography stack 40 and patterned resist 42 are formed over structure 10 .
- Lithography stack 40 may include one or more photolithography layers, such as an anti-reflective layer, a sacrificial hardmask layer, and a planarization layer.
- the patterned resist 42 is patterned with an opening 44 to expose a portion of the lithography stack 40 , the exposed portion of the lithography stack corresponding to a cut to be formed in the upper mandrel layer 34 of mandrel line 35 .
- the exposed portion of lithography stack 40 is etched to expose the underlying section of the upper mandrel layer 34 of the mandrel line 35 while remaining portions of the lithography stack mask the adjacent sections of the upper mandrel layer 34 . Subsequently the exposed section of upper mandrel layer 34 is selectively removed by an etching process.
- the etching of upper mandrel layer 34 may include a selective anisotropic reactive ion etch (RIE) process, for example, to remove the material of the upper mandrel layer 34 selective to the material of the lower mandrel layer 32 , which results in a mandrel cut 46 formed in the section of the upper mandrel layer 34 of mandrel line 35 .
- RIE reactive ion etch
- the term “selective” in reference to a material removal process denotes that, with an appropriate etchant choice, the material removal rate (i.e., etch rate) for the targeted material is greater than the removal rate for at least another material exposed to the material removal process.
- a selective anisotropic RIE process may be controlled to remove amorphous silicon at a greater etch rate than silicon oxynitride.
- FIGS. 5 and 5A With reference to FIGS. 5 and 5A in which like reference numerals refer to like features in FIG. 4 and at a subsequent fabrication stage of the processing method, remaining portions of lithography stack 40 are removed from structure 10 , which exposes mandrel lines 35 , 37 .
- the mandrel cut 46 in the upper mandrel layer 34 of mandrel line 35 is disposed between adjacent sections of upper mandrel layer 34 of mandrel line 35 , while lower mandrel layer 32 of mandrel line 35 is uncut and remains in place over a strip of the hardmask 25 .
- the section of the lower mandrel layer 32 remaining in the mandrel cut 46 maintains the continuity of the sidewalls 35 a, 35 b of the mandrel line 35 .
- a conformal layer 50 is deposited over mandrel lines 35 , 37 and over hardmask 25 at gaps between mandrel lines 35 , 37 .
- the conformal layer 50 may be deposited by, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD), and may be comprised of an oxide of titanium, such as titanium dioxide (TiO 2 ), if the hardmask 25 is comprised of titanium nitride.
- the conformal layer 50 may conform to sidewalls 35 a, 35 b of mandrel line 35 and the sidewalls 37 a, 37 b of mandrel lines 37 .
- portions of the conformal layer 50 conforms to sidewalls 35 a, 35 b of the lower mandrel layer 32 at mandrel cut 46 in the upper mandrel layer 34 of mandrel line 35 , and other portions of conformal layer 50 merges inside the mandrel cut 46 to fill between the adjacent uncut sections of the upper mandrel layer 34 of mandrel line 35 and mask the underlying portion of lower mandrel layer 32 .
- mandrel line cuts are generally defined by initially forming cuts in a mandrel patterning layer prior to forming mandrel lines from a single mandrel layer, such as single layer of amorphous silicon.
- forming mandrel line cuts in this manner may be undesirable for several reasons.
- the spacers follow the contour of the mandrel line ends and merge within the cuts, which produces gaps or indentations between the converging spacers at the edges of the cuts. This leads to a “necking” distortion effect in the non-mandrel lines at these gaps because the contours of the spacers are not planar.
- the non-mandrel lines are etched into masking layers, the non-mandrel lines are distorted and wider than designed at these gaps.
- the resulting metallization lines are thus also wider at these gaps and may be insufficiently separated from adjacent metallization lines, potentially leading to shorts in the circuit structure.
- some metallization lines may be less than 10 nm in width, such as metallization lines having widths less than or equal to 7 nm, the “necking” effect may also significantly increase electrical resistance in metallization lines due to the increased width of metallization lines across the distortions.
- cuts in a mandrel line 35 are not made through the entire mandrel line 35 so as to expose an underlying portion of the hardmask. Rather, the mandrel line 35 includes the upper mandrel layer 34 and the lower mandrel layer 32 , and the mandrel cut is initially defined only in the upper mandrel layer 34 . As a result, a section of the lower mandrel layer 32 remains intact and masks an underlying portion of hardmask 25 of equal area.
- portions of the conformal layer 50 fill the mandrel cut 46 in the upper mandrel layer 34 of mandrel line 35 and other portions of the conformal layer 50 conform to the sidewalls of the first mandrel layer 32 at the mandrel cut 46 .
- This prevents formation of indentations in the conformal layer 50 at the mandrel cut 46 and thus also prevents the formation of distortions in the non-mandrel lines 60 and trenches in hardmask 25 formed from the non-mandrel lines.
- the conformal layer 50 is etched with a reactive ion etching process to reveal portions 25 a of hardmask 25 corresponding to non-mandrel lines 60 and to form sidewall spacers 52 on sidewalls 35 a, 35 b, 37 a, 37 b of mandrel lines 35 , 37 .
- the etching process may remove the material of the conformal layer 50 selective to the materials of the hardmask 25 and the upper mandrel layer 34 in the mandrel lines 35 , 37 .
- the mandrel lines 35 , 37 are revealed by the etching of the conformal layer 50 .
- the etching process also reduces a thickness of the conformal layer 50 disposed in the mandrel cut 46 .
- the partial removal of the conformal layer 50 in the mandrel cut 46 leaves a mandrel cut mask 55 , which is comprised of the material of the conformal layer 50 , masking an underlying portion 33 of the lower mandrel layer 32 of mandrel line 35 .
- exposed sections of mandrel lines 35 , 37 are removed or “pulled” through one or more etching processes, which exposes underlying strips or portions 25 b of hardmask 25 .
- the one or more etching processes may, in one embodiment, include a single uninterrupted etching process that removes both sections of the upper mandrel layer 34 and lower mandrel layer 32 in the mandrel lines 35 , 37 selective to the sidewall spacers 52 and hardmask 25 .
- the one or more etching processes may include one selective etching process to first selectively remove the material of exposed sections of upper mandrel layer 34 selective to the lower mandrel layer 32 and sidewall spacers 52 and hardmask 25 , and another selective etching process to selectively remove the material of exposed sections of lower mandrel layer 32 selective to the sidewall spacers 52 and hardmask 25 .
- Mandrel cut mask 55 masks the underlying portion 33 of mandrel line 35 during the etching process.
- exposed portions 25 a, 25 b of hardmask 25 are etched to respectively form non-mandrel trenches 62 a, 62 b and mandrel trenches 64 a, 64 b in the hardmask 25 , which exposes underlying portions of the interlayer dielectric layer 20 .
- Non-mandrel trenches 62 a and 62 b which replicate the pattern of non-mandrel lines 60
- mandrel trenches 64 a and 64 b which replicate the pattern of pulled mandrel lines 35 , 37 and unpulled portion 33 of lower mandrel layer 32 of mandrel line 35
- may be etched in the hardmask 25 for example, by an anisotropic RIE process that removes the hardmask 25 selective to the interlayer dielectric layer 20 .
- the unpulled portion 33 of lower mandrel layer 32 and the mandrel cut mask 55 function during the etching process to transfer the mandrel cut in the mandrel line 35 to an underlying masked portion 66 of the hardmask 25 , as shown in FIG. 9A .
- Spacer 52 a which conform to one sidewall of the unpulled portion 33 of the lower mandrel layer 32 , defines a planar sidewall of the adjacent non-mandrel trench 62 a, that is, a sidewall without “necking” indentations or distortions, as described above.
- spacer 52 b conforms to another sidewall of the unpulled portion 33 of the lower mandrel layer 32 to define a planar sidewall of the adjacent non-mandrel trench 62 b.
- the mandrel cut mask 55 may be removed by the etching process forming the non-mandrel trenches 62 a, 62 b, and the mandrel trenches 64 a, 64 b.
- sidewall spacers 52 , 52 a, 52 b are removed from over hardmask 25 .
- the spacers may be removed, for example, by an etching process that selectively removes the material of sidewall spacers 52 , 52 a, 52 b selective to the hardmask 25 and interlayer dielectric layer 20 .
- portions of interlayer dielectric layer 20 exposed by mandrel trenches 64 a, 64 b and non-mandrel trenches 62 a, 62 b are etched to form metallization trenches 70 in the interlayer dielectric layer 20 that replicate the pattern of pulled mandrel lines 35 , 37 , non-mandrel trenches 62 a and 62 b, and masked portion 66 of the hardmask 25 .
- the exposed portions of interlayer dielectric layer 20 may be etched, for example, by an anisotropic RIE.
- the metallization trenches 70 are filled with a metal, such as copper or cobalt, to form metallization lines 80 , 82 , 84 , 86 in interlayer dielectric layer 20 .
- Metallization lines 80 , 82 , 84 , 86 may have a width of less than or equal to 7 nm.
- Metallization line 82 includes a mandrel cut 85 , which is filled with the material of the interlayer dielectric layer 20 and arranged along the length of the metallization line 82 in a row between portions of the metallization line 82 . The mandrel cut 85 is transferred from the masked portion 66 of the hardmask 25 to the metallization line 82 when the interlayer dielectric layer 20 is patterned using the patterned hardmask 25 .
- Metallization line 84 may have an outer sidewall 84 a that is adjacent to one outer sidewall 82 a of metallization line 82
- metallization line 86 may have an outer sidewall 86 a adjacent to another outer sidewall 82 b of metallization line 82
- a distance D 1 between the outer sidewall 84 a of metallization line 84 and outer sidewall 86 a of metallization line 86 that traverses the mandrel cut 85 in metallization line 82 may be equal to a distance D 2 between outer sidewall 84 a and outer sidewall 86 a that traverses a section of metallization line 82 .
- a width W of a portion of the interlayer dielectric layer 20 disposed between metallization line 82 and metallization line 84 may be uniform along a length of metallization lines 82 , 84 , as metallization line 84 may be formed without large distortions protruding toward or into the mandrel cut 85 .
- a width W of a portion of the interlayer dielectric layer 20 disposed between metallization line 82 and metallization line 86 may be uniform along a length of metallization lines 82 , 86 .
- the methods as described above are used in the fabrication of integrated circuit chips.
- the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
- the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections).
- the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.
- references herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference.
- the term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation.
- the terms “vertical” and “normal” refer to a direction perpendicular to the “horizontal”, as just defined.
- the term “lateral” refers to a direction within the horizontal plane. Terms such as “above” and “below” are used to indicate positioning of elements or structures relative to each other as opposed to relative elevation.
- a feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present.
- a feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent.
- a feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
Abstract
Description
- The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning.
- A back-end-of-line (BEOL) interconnect structure may be used to connect device structures fabricated on a substrate during front-end-of-line (FEOL) processing with each other and with the environment external to the chip. Self-aligned patterning processes used to form a BEOL interconnect structure involve mandrel lines as sacrificial features that establish a feature pitch. Sidewall spacers are formed adjacent to the sidewalls of the mandrel lines. After selective removal of the mandrel lines, the spacers are used as an etch mask to etch an underlying hardmask over areas exposed by mandrel removal and areas between the spacers. The pattern is transferred from the hardmask to an interlayer dielectric layer to define trenches in which the wires of the BEOL interconnect structure are formed.
- Cuts may be formed in mandrel lines in order to section the mandrel lines and define discontinuities between the sections that subsequently are used to form adjacent wires that are spaced apart at their tips with a tip-to-tip spacing. Non-mandrel cuts may also be formed in the hardmask itself along non-mandrel lines exposed between the sidewall spacers and filled by spacer material when the sidewall spacers are formed on the mandrel lines. A pattern reflecting the cut mandrel lines, the non-mandrel lines, and non-mandrel cuts is transferred to the hardmask and subsequently from the hardmask to form the trenches in the interlayer dielectric layer.
- At larger pitch nodes, imperfections in the interconnect lines resulting from self-aligned patterning processes were relatively insignificant. However, as feature sizes have progressively shrunk to sub-10 nanometer pitches, various effects of these imperfections have become magnified, such as increased electrical resistance in interconnect lines and generating shorts between interconnect lines.
- Improved methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning are thus needed.
- In an embodiment of the invention, a method includes forming a first mandrel line with a first mandrel layer disposed on a hardmask and a second mandrel layer disposed over the first mandrel layer. A first section of the second mandrel layer is removed to form a mandrel cut that exposes a first section of the first mandrel layer. The first section of the first mandrel layer is arranged along the first mandrel line between respective second sections of the second mandrel layer. After masking the first section of the first mandrel layer, the second sections of the second mandrel layer are removed with a first etching process to expose the second sections of the first mandrel layer. After removing the second sections of the second mandrel layer, the second sections of the first mandrel layer are removed to expose first portions of the hardmask. The first portions of the hardmask are then removed with a second etching process to form a trench. During the second etching process, a second portion of the hardmask is masked by the first section of the first mandrel layer to form a cut in the first trench in the hardmask.
- In another embodiment of the invention, a structure includes a first metallization line that has a first section, a second section, a first outer sidewall and a second outer sidewall, and a cut disposed between the first section and the second section. The structure further includes a second metallization line adjacent to the first metallization line, and the second metallization line has a third outer sidewall adjacent to the first outer sidewall. The structure further includes a third metallization line adjacent to the first metallization line, and the third metallization line has a fourth outer sidewall adjacent to the second outer sidewall. A first distance between the third outer sidewall and the fourth outer sidewall that traverses the cut in the first metallization line is equal to a second distance between the third outer sidewall and the fourth outer sidewall that traverses the first section of the first metallization line.
- The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.
-
FIGS. 1-12 are cross-sectional views of a structure at successive fabrication stages of a processing method in accordance with embodiments of the invention. -
FIG. 5A is a top view of the structure in whichFIG. 5 is taken generally along line 5-5. -
FIG. 7A is a top view of the structure in whichFIG. 7 is taken generally along line 7-7. -
FIG. 8A is a top view of the structure in whichFIG. 8 is taken generally along line 8-8. -
FIG. 9A is a top view of the structure in whichFIG. 9 is taken generally along line 9-9. -
FIG. 12A is a top view of the structure in whichFIG. 12 is taken generally along line 12-12. - With reference to
FIG. 1 and in accordance with embodiments of the invention, astructure 10 includes an interlayerdielectric layer 20, ahardmask 25, and a multiple-layer mandrel stack 30. The interlayerdielectric layer 20 may be comprised of an electrically-insulating dielectric material, such as hydrogen-enriched silicon oxycarbide (SiCOH) or another type of low-k dielectric material. The interlayerdielectric layer 20 may be located on a substrate (not shown inFIG. 1 ) that includes device structures fabricated by front-end-of-line (FEOL) processing to form an integrated circuit. Thehardmask 25 overlies the interlayerdielectric layer 20 and may be comprised of a metal-based material, such as titanium nitride, suitable for use as a hardmask. - The multiple-
layer mandrel stack 30 includes alower mandrel layer 32 comprised of a material and anupper mandrel layer 34 comprised of another material different from the material of thelower mandrel layer 32. The materials of theupper mandrel layer 34 andlower mandrel layer 32 are selected so that, as described below, the material of theupper mandrel layer 34 may be selectively removed in an etching process that etches little to no material of thelower mandrel layer 32. Thelower mandrel layer 32 may be comprised of, for example, silicon dioxide, silicon oxynitride, silicon nitride, amorphous carbon, or a combination of these materials in a layered arrangement. Theupper mandrel layer 34, in one example, may be comprised of amorphous silicon (a-Si) or another material that can be removed selective to the material of thelower mandrel layer 32. The material of thelower mandrel layer 32 should also exhibit high etch selectivity to the material of thehardmask 25. - The
hardmask 25 may be a single hardmask comprised of a metal nitride, such as titanium nitride. In conventional fabrication processes, in addition to a metal nitride hardmask, a dielectric hardmask, such as a silicon nitride hardmask, is disposed over the metal nitride hardmask; mandrel lines and non-mandrel lines are then separately patterned in the dielectric hardmask and subsequently replicated in the metal oxide hardmask. The multiple-layer mandrel stack 30 eliminates the need for an additional dielectric hardmask, and allows for both mandrel lines and non-mandrel lines to be etched as trenches into thehardmask 25 in a single step, as described further below. - With reference to
FIG. 2 in which like reference numerals refer to like features inFIG. 1 and at a subsequent fabrication stage of the processing method, the multiple-layer mandrel stack 30 is etched to formmandrel lines FIG. 2 ) may be provided over the multiple-layer mandrel stack 30 that masks portions of the bi-layer mandrel stack and leaves other portions of the multiple-layer mandrel stack 30 exposed, and the exposed portions of the bi-layer mandrel stack etched. The patterning layer may be comprised of a dielectric material, such as a low-temperature oxide (LTO) of silicon. Each of themandrel lines upper mandrel layer 34 that is stacked over a section of thelower mandrel layer 32 in the representative bi-layer arrangement. The section of thelower mandrel layer 32 of each of themandrel lines hardmask 25. Themandrel lines - With reference to
FIG. 3 in which like reference numerals refer to like features inFIG. 2 and at a subsequent fabrication stage of the processing method, alithography stack 40 and patternedresist 42 are formed overstructure 10.Lithography stack 40 may include one or more photolithography layers, such as an anti-reflective layer, a sacrificial hardmask layer, and a planarization layer. The patternedresist 42 is patterned with anopening 44 to expose a portion of thelithography stack 40, the exposed portion of the lithography stack corresponding to a cut to be formed in theupper mandrel layer 34 ofmandrel line 35. - With reference to
FIG. 4 in which like reference numerals refer to like features inFIG. 3 and at a subsequent fabrication stage of the processing method, the exposed portion oflithography stack 40 is etched to expose the underlying section of theupper mandrel layer 34 of themandrel line 35 while remaining portions of the lithography stack mask the adjacent sections of theupper mandrel layer 34. Subsequently the exposed section ofupper mandrel layer 34 is selectively removed by an etching process. The etching ofupper mandrel layer 34 may include a selective anisotropic reactive ion etch (RIE) process, for example, to remove the material of theupper mandrel layer 34 selective to the material of thelower mandrel layer 32, which results in amandrel cut 46 formed in the section of theupper mandrel layer 34 ofmandrel line 35. As used herein, the term “selective” in reference to a material removal process (e.g., etching) denotes that, with an appropriate etchant choice, the material removal rate (i.e., etch rate) for the targeted material is greater than the removal rate for at least another material exposed to the material removal process. For example, in embodiments in which theupper mandrel layer 34 is comprised of amorphous silicon and thelower mandrel layer 32 is comprised of silicon oxynitride, a selective anisotropic RIE process may be controlled to remove amorphous silicon at a greater etch rate than silicon oxynitride. - With reference to
FIGS. 5 and 5A in which like reference numerals refer to like features inFIG. 4 and at a subsequent fabrication stage of the processing method, remaining portions oflithography stack 40 are removed fromstructure 10, which exposesmandrel lines FIG. 5A , the mandrel cut 46 in theupper mandrel layer 34 ofmandrel line 35 is disposed between adjacent sections ofupper mandrel layer 34 ofmandrel line 35, whilelower mandrel layer 32 ofmandrel line 35 is uncut and remains in place over a strip of thehardmask 25. The section of thelower mandrel layer 32 remaining in the mandrel cut 46 maintains the continuity of the sidewalls 35 a, 35 b of themandrel line 35. - With reference to
FIG. 6 in which like reference numerals refer to like features inFIGS. 5 and 5A and at a subsequent fabrication stage of the processing method, aconformal layer 50 is deposited overmandrel lines hardmask 25 at gaps betweenmandrel lines conformal layer 50 may be deposited by, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD), and may be comprised of an oxide of titanium, such as titanium dioxide (TiO2), if thehardmask 25 is comprised of titanium nitride. Theconformal layer 50 may conform to sidewalls 35 a, 35 b ofmandrel line 35 and thesidewalls conformal layer 50 conforms to sidewalls 35 a, 35 b of thelower mandrel layer 32 at mandrel cut 46 in theupper mandrel layer 34 ofmandrel line 35, and other portions ofconformal layer 50 merges inside the mandrel cut 46 to fill between the adjacent uncut sections of theupper mandrel layer 34 ofmandrel line 35 and mask the underlying portion oflower mandrel layer 32. Gaps between theconformal layer 50 on sidewalls of adjacent mandrel lines, such assidewall 35 b ofmandrel line 35 andsidewall 37 a ofmandrel line 37, definenon-mandrel lines 60 disposed between adjacent pairs ofmandrel lines - In conventional fabrication processes, mandrel line cuts are generally defined by initially forming cuts in a mandrel patterning layer prior to forming mandrel lines from a single mandrel layer, such as single layer of amorphous silicon. However, forming mandrel line cuts in this manner may be undesirable for several reasons. For example, the spacers follow the contour of the mandrel line ends and merge within the cuts, which produces gaps or indentations between the converging spacers at the edges of the cuts. This leads to a “necking” distortion effect in the non-mandrel lines at these gaps because the contours of the spacers are not planar. At later stages when the non-mandrel lines are etched into masking layers, the non-mandrel lines are distorted and wider than designed at these gaps. The resulting metallization lines are thus also wider at these gaps and may be insufficiently separated from adjacent metallization lines, potentially leading to shorts in the circuit structure. In circuit structures where some metallization lines may be less than 10 nm in width, such as metallization lines having widths less than or equal to 7 nm, the “necking” effect may also significantly increase electrical resistance in metallization lines due to the increased width of metallization lines across the distortions.
- In the processes described herein, cuts in a
mandrel line 35 are not made through theentire mandrel line 35 so as to expose an underlying portion of the hardmask. Rather, themandrel line 35 includes theupper mandrel layer 34 and thelower mandrel layer 32, and the mandrel cut is initially defined only in theupper mandrel layer 34. As a result, a section of thelower mandrel layer 32 remains intact and masks an underlying portion ofhardmask 25 of equal area. As described above, when theconformal layer 50 is formed overmandrel lines conformal layer 50 fill the mandrel cut 46 in theupper mandrel layer 34 ofmandrel line 35 and other portions of theconformal layer 50 conform to the sidewalls of thefirst mandrel layer 32 at the mandrel cut 46. This prevents formation of indentations in theconformal layer 50 at the mandrel cut 46 and thus also prevents the formation of distortions in thenon-mandrel lines 60 and trenches inhardmask 25 formed from the non-mandrel lines. - With reference to
FIGS. 7 and 7A in which like reference numerals refer to like features inFIG. 6 and at a subsequent fabrication stage of the processing method, theconformal layer 50 is etched with a reactive ion etching process to revealportions 25 a ofhardmask 25 corresponding tonon-mandrel lines 60 and to formsidewall spacers 52 onsidewalls mandrel lines conformal layer 50 selective to the materials of thehardmask 25 and theupper mandrel layer 34 in the mandrel lines 35, 37. The mandrel lines 35, 37 are revealed by the etching of theconformal layer 50. The etching process also reduces a thickness of theconformal layer 50 disposed in the mandrel cut 46. The partial removal of theconformal layer 50 in the mandrel cut 46 leaves amandrel cut mask 55, which is comprised of the material of theconformal layer 50, masking anunderlying portion 33 of thelower mandrel layer 32 ofmandrel line 35. - With reference to
FIGS. 8 and 8A in which like reference numerals refer to like features inFIGS. 7 and 7A and at a subsequent fabrication stage of the processing method, exposed sections ofmandrel lines portions 25 b ofhardmask 25. The one or more etching processes may, in one embodiment, include a single uninterrupted etching process that removes both sections of theupper mandrel layer 34 andlower mandrel layer 32 in the mandrel lines 35, 37 selective to thesidewall spacers 52 andhardmask 25. In another embodiment, the one or more etching processes may include one selective etching process to first selectively remove the material of exposed sections ofupper mandrel layer 34 selective to thelower mandrel layer 32 andsidewall spacers 52 andhardmask 25, and another selective etching process to selectively remove the material of exposed sections oflower mandrel layer 32 selective to thesidewall spacers 52 andhardmask 25. Mandrel cutmask 55 masks theunderlying portion 33 ofmandrel line 35 during the etching process. - With reference to
FIGS. 9 and 9A in which like reference numerals refer to like features inFIGS. 8 and 8A and at a subsequent fabrication stage of the processing method, exposedportions hardmask 25 are etched to respectively formnon-mandrel trenches mandrel trenches hardmask 25, which exposes underlying portions of theinterlayer dielectric layer 20.Non-mandrel trenches non-mandrel lines 60, andmandrel trenches mandrel lines unpulled portion 33 oflower mandrel layer 32 ofmandrel line 35, may be etched in thehardmask 25, for example, by an anisotropic RIE process that removes thehardmask 25 selective to theinterlayer dielectric layer 20. Theunpulled portion 33 oflower mandrel layer 32 and the mandrel cutmask 55 function during the etching process to transfer the mandrel cut in themandrel line 35 to an underlyingmasked portion 66 of thehardmask 25, as shown inFIG. 9A .Spacer 52 a, which conform to one sidewall of theunpulled portion 33 of thelower mandrel layer 32, defines a planar sidewall of the adjacentnon-mandrel trench 62 a, that is, a sidewall without “necking” indentations or distortions, as described above. Similarly,spacer 52 b conforms to another sidewall of theunpulled portion 33 of thelower mandrel layer 32 to define a planar sidewall of the adjacentnon-mandrel trench 62 b. The mandrel cutmask 55 may be removed by the etching process forming thenon-mandrel trenches mandrel trenches - With reference to
FIG. 10 in which like reference numerals refer to like features inFIGS. 9 and 9A and at a subsequent fabrication stage of the processing method,sidewall spacers hardmask 25. The spacers may be removed, for example, by an etching process that selectively removes the material ofsidewall spacers hardmask 25 andinterlayer dielectric layer 20. - With reference to
FIG. 11 in which like reference numerals refer to like features inFIG. 10 and at a subsequent fabrication stage of the processing method, portions ofinterlayer dielectric layer 20 exposed bymandrel trenches non-mandrel trenches metallization trenches 70 in theinterlayer dielectric layer 20 that replicate the pattern of pulledmandrel lines non-mandrel trenches masked portion 66 of thehardmask 25. The exposed portions ofinterlayer dielectric layer 20 may be etched, for example, by an anisotropic RIE. - With reference to
FIGS. 12 and 12A in which like reference numerals refer to like features inFIG. 11 and at a subsequent fabrication stage of the processing method, themetallization trenches 70 are filled with a metal, such as copper or cobalt, to formmetallization lines interlayer dielectric layer 20.Metallization lines Metallization line 82 includes a mandrel cut 85, which is filled with the material of theinterlayer dielectric layer 20 and arranged along the length of themetallization line 82 in a row between portions of themetallization line 82. The mandrel cut 85 is transferred from the maskedportion 66 of thehardmask 25 to themetallization line 82 when theinterlayer dielectric layer 20 is patterned using the patternedhardmask 25. -
Metallization line 84 may have anouter sidewall 84 a that is adjacent to oneouter sidewall 82 a ofmetallization line 82, andmetallization line 86 may have anouter sidewall 86 a adjacent to anotherouter sidewall 82 b ofmetallization line 82. A distance D1 between theouter sidewall 84 a ofmetallization line 84 andouter sidewall 86 a ofmetallization line 86 that traverses the mandrel cut 85 inmetallization line 82 may be equal to a distance D2 betweenouter sidewall 84 a andouter sidewall 86 a that traverses a section ofmetallization line 82. That is, a width W of a portion of theinterlayer dielectric layer 20 disposed betweenmetallization line 82 andmetallization line 84 may be uniform along a length ofmetallization lines metallization line 84 may be formed without large distortions protruding toward or into the mandrel cut 85. Similarly, a width W of a portion of theinterlayer dielectric layer 20 disposed betweenmetallization line 82 andmetallization line 86 may be uniform along a length ofmetallization lines - The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.
- References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction perpendicular to the “horizontal”, as just defined. The term “lateral” refers to a direction within the horizontal plane. Terms such as “above” and “below” are used to indicate positioning of elements or structures relative to each other as opposed to relative elevation.
- A feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
- The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
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US10991596B2 (en) * | 2019-02-02 | 2021-04-27 | Semiconductor Manufacturing (Shanghai) International Corporation | Semiconductor structure and method for forming same |
US10998193B1 (en) * | 2020-01-22 | 2021-05-04 | International Business Machines Corporation | Spacer-assisted lithographic double patterning |
US11177160B2 (en) * | 2020-03-24 | 2021-11-16 | International Business Machines Corporation | Double patterned lithography using spacer assisted cuts for patterning steps |
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CN102789968B (en) * | 2011-05-20 | 2015-06-17 | 中芯国际集成电路制造(北京)有限公司 | Method for forming hard mask in semi-conductor manufacture process |
US8669180B1 (en) * | 2012-11-26 | 2014-03-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with self aligned end-to-end conductive line structure and method of forming the same |
US9786597B2 (en) | 2013-03-11 | 2017-10-10 | International Business Machines Corporation | Self-aligned pitch split for unidirectional metal wiring |
US9153478B2 (en) * | 2013-03-15 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Spacer etching process for integrated circuit design |
US9099400B2 (en) | 2013-09-30 | 2015-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device manufacturing methods |
US9209076B2 (en) * | 2013-11-22 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of double patterning lithography process using plurality of mandrels for integrated circuit applications |
US9177797B2 (en) | 2013-12-04 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lithography using high selectivity spacers for pitch reduction |
US9368349B2 (en) * | 2014-01-14 | 2016-06-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cut last self-aligned litho-etch patterning |
US9425049B2 (en) * | 2014-01-14 | 2016-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cut first self-aligned litho-etch patterning |
WO2017189993A1 (en) | 2016-04-29 | 2017-11-02 | Tokyo Electron Limited | Method for patterning a substrate using a layer with multiple materials |
US9711447B1 (en) | 2016-10-11 | 2017-07-18 | Globalfoundries Inc. | Self-aligned lithographic patterning with variable spacings |
US9818613B1 (en) * | 2016-10-18 | 2017-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned double spacer patterning process |
US9881794B1 (en) * | 2016-11-29 | 2018-01-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor methods and devices |
US9859120B1 (en) | 2016-12-13 | 2018-01-02 | Globalfoundries Inc. | Method of making self-aligned continuity cuts in mandrel and non-mandrel metal lines |
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US10991596B2 (en) * | 2019-02-02 | 2021-04-27 | Semiconductor Manufacturing (Shanghai) International Corporation | Semiconductor structure and method for forming same |
US10998193B1 (en) * | 2020-01-22 | 2021-05-04 | International Business Machines Corporation | Spacer-assisted lithographic double patterning |
US11177160B2 (en) * | 2020-03-24 | 2021-11-16 | International Business Machines Corporation | Double patterned lithography using spacer assisted cuts for patterning steps |
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US10446395B1 (en) | 2019-10-15 |
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