US20190295638A1 - Semiconductor memory device and method of controlling the same - Google Patents
Semiconductor memory device and method of controlling the same Download PDFInfo
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- US20190295638A1 US20190295638A1 US16/039,786 US201816039786A US2019295638A1 US 20190295638 A1 US20190295638 A1 US 20190295638A1 US 201816039786 A US201816039786 A US 201816039786A US 2019295638 A1 US2019295638 A1 US 2019295638A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/36—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using diodes, e.g. as threshold elements, i.e. diodes assuming a stable ON-stage when driven above their threshold (S- or N-characteristic)
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0045—Read using current through the cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/06—Sense amplifier related aspects
- G11C2207/063—Current sense amplifiers
Definitions
- Embodiments described herein relate to a semiconductor memory device and a method of controlling the same.
- FIG. 1 is a block diagram illustrating a configuration of a semiconductor memory device of a first embodiment
- FIG. 2 is a block diagram illustrating a configuration of a semiconductor memory device of a modification to the first embodiment
- FIGS. 3A to 4B are graphs for describing operations of the semiconductor memory device of the first embodiment
- FIGS. 5A and 5B are graphs for detailed description of FIGS. 3A to 4B ;
- FIGS. 6A and 6B are block diagrams illustrating examples of the configuration of the semiconductor memory device of the first embodiment
- FIGS. 7A to 7D are diagrams illustrating examples of operations of the semiconductor memory device of the first embodiment.
- FIGS. 8A to 8D are schematic views illustrating examples of the configuration of the semiconductor memory device of the first embodiment.
- FIG. 1 to FIG. 8D identical or similar components are assigned the same reference numerals, and hence redundant description is omitted.
- a semiconductor memory device includes a memory cell configured to store a first value or a second value as stored data, and a control circuit configured to read out the first value or the second value as the stored data from the memory cell.
- the memory cell includes a first operation area where a cell current flowing across the memory cell increases as a voltage across the memory cell increases, a second operation area where the cell current in the second operation area is larger than the cell current in the first operation area and the voltage across the memory cell decreases while the cell current increases, and a third operation area where the cell current in the third operation area is larger than the cell current in the second operation area and the cell current increases as the voltage across the memory cell increases.
- the control circuit performs first reading processing of reading out the stored data from the memory cell such that the cell current of a case where the stored data has the first value and the cell current of a case where the stored data has the second value respectively take values in the first operation area.
- the control circuit performs second reading processing of reading out the stored data from the memory cell such that at least one of the cell current in the case where the stored data has the first value and the cell current in the case where the stored data has the second value takes a value in the second operation area or the third operation area.
- FIG. 1 is a block diagram illustrating a configuration of a semiconductor memory device 1 of a first embodiment.
- FIG. 1 illustrates the semiconductor memory device 1 and an external device 2 that can transmit and receive signals to and from the semiconductor memory device 1 .
- the semiconductor memory device may be another semiconductor memory device (e.g., an ReRAM or an MRAM).
- the external device 2 may be an IC (integrated circuit) that controls an operation of the semiconductor memory device 1 or a PC (personal computer) in or on which the semiconductor memory device 1 is contained or mounted.
- the semiconductor memory device 1 includes a memory cell array 1 a including a plurality of memory cells and a peripheral circuit portion 1 b that performs processing such as control of the memory cell array 1 a.
- the memory cell array 1 a has a cross-point structure including memory cells, respectively, at points where a plurality of word lines and a plurality of bit lines intersect each other.
- the peripheral circuit portion 1 b performs processing such as writing data into the memory cells, reading data from the memory cells, receiving a signal from the external device 2 , and transmitting a signal to the external device 2 .
- the memory cell array 1 a includes a firmware data/trim data (FD/TD) storage area 11 , a user data (UD) storage area 12 , a first sense amplifier (SA) 13 , and a second sense amplifier (SA) 14 .
- FD/TD firmware data/trim data
- UD user data
- SA first sense amplifier
- SA second sense amplifier
- the FD/TD storage area 11 is a storage area including a memory cell which stores data (firmware data) for a basic operation of the external device 2 and a memory cell which stores data (trim data) for a basic operation of the peripheral circuit portion 1 b.
- the UD storage area 12 is a storage area including a memory cell for a user of the semiconductor memory device 1 to store data (user data).
- the first SA 13 and the second SA 14 each transfers read data, which has been received from a memory cell, to the external device 2 via the peripheral circuit portion 1 b and transfers write data, which has been received from the external device 2 via the peripheral circuit portion 1 b, to a memory cell.
- the first SA 13 is provided to handle the firmware data and the trim data
- the second SA 14 is provided to handle the user data.
- the first SA 13 , the second SA 14 , and the peripheral circuit portion 1 b are each an example of a control circuit.
- FIG. 2 is a block diagram illustrating a configuration of a semiconductor memory device 1 of a modification to the first embodiment.
- the semiconductor memory device 1 of the modification includes a firmware data/trim data/user data (FD/TD/UD) storage area 15 instead of the FD/TD storage area 11 and the UD storage area 12 .
- a storage area for firmware data and trim data and a storage area for user data are not separated from each other, and all the firmware data, the trim data, and the user data are stored in the FD/TD/UD storage area 15 .
- FIGS. 3A to 4B are graphs for describing an operation of the semiconductor memory device 1 of the first embodiment.
- a horizontal axis represents an applied voltage applied to each of the memory cells in the semiconductor memory device 1
- a vertical axis represents a cell current flowing through each of the memory cells in the semiconductor memory device 1 .
- FIGS. 3A to 4B illustrate four schemes for reading out 0 or 1 as stored data from the memory cell.
- the stored data “0” is an example of a first value, and indicates that the memory cell is in a high-resistance state, for example.
- the stored data “1” is an example of a second value, and indicates that the memory cell is in a low-resistive state, for example.
- a voltage reading scheme has been adopted. More specifically, a read voltage Vread is applied as an applied voltage to the memory cell, and it is determined whether the stored data is 0 or 1 based on the magnitude of a cell current generated depending on the read voltage Vread. In FIG. 3A , the read voltage Vread is applied such that snapback of the memory cell does not occur when the stored data is 0 but occurs if the stored data is 1. On the other hand, in FIG. 3B , the read voltage Vread is applied such that snapback of the memory cell does not occur regardless of whether the stored data is 0 or 1.
- FIGS. 4A and 4B a current reading scheme has been adopted. More specifically, an applied voltage is applied such that a read current Iread flows as a cell current through the memory cell, and it is determined whether the stored data is 0 or 1 based on the magnitude of the applied voltage. In FIG. 4A , the read current Iread is caused to flow such that snapback of the memory cell occurs regardless of whether the stored data is 0 or 1. On the other hand, in FIG. 4B , the read current Iread is caused to flow such that snapback of the memory cell does not occur regardless of whether the stored data is 0 or 1.
- FIGS. 3B to 4B will also be referred to, as needed.
- the memory cell in the present embodiment in case the stored data is 0 includes an operation area C 1 , an operation area C 2 where a cell current is larger than a cell current in the operation area C 1 , and an operation area C 5 where a cell current is larger than the cell current in the operation area C 2 .
- the memory cell in the present embodiment in case the stored data is 1 includes an operation area C 3 , an operation area C 4 where a cell current is larger than a cell current in the operation area C 3 , and the operation area C 5 where the cell current is larger than the cell current in the operation area C 4 .
- the operation areas C 1 and C 3 are each an example of a first operation area
- the operation areas C 2 and C 4 are each a second operation area
- the operation area C 5 is an example of a third operation area.
- the cell current increases as the applied voltage increases.
- the cell current in the operation area C 3 more steeply increases than the cell current in the operation area C 1 in response to the increase in the applied voltage.
- the applied voltage decreases while the cell current increases.
- the applied voltage in the operation area C 4 more gently decreases than the applied voltage in the operation area C 2 in response to the increase in the cell current.
- the cell current increases as the applied voltage increases.
- the memory cell has the same characteristic regardless of whether the stored data is 0 or 1.
- Reference character P 0 represents an inflection point between a curve representing the operation area C 1 and a curve representing the operation area C 2
- reference character Vth 0 represents an applied voltage at the inflection point P 0 .
- the applied voltage Vth 0 is referred to as a threshold voltage (snapback voltage) in a case where the stored data is 0.
- Reference character P 1 represents an inflection point between a curve representing the operation area C 3 and a curve representing the operation area C 4
- reference character Vth 1 represents an applied voltage at the inflection point P 1 .
- the applied voltage Vth 1 is referred to as a threshold voltage (snapback voltage) in a case where the stored data is 1.
- a cell current corresponding to the applied voltage Vth 0 and a cell current corresponding to the applied voltage Vth 1 have the same magnitude.
- the cell current will be each referred to as a snapback current.
- the semiconductor memory device of the present embodiment is the PCM.
- the characteristic of the memory cell changes from a characteristic of the operation area C 1 to a characteristic of the operation area C 2 at the inflection point P 0 and changes from a characteristic of the operation area C 3 to a characteristic of the operation area C 4 at the inflection point P 1 .
- the phenomenon is referred to as snapback.
- the snapback of the PCM occurs when the characteristic of the memory cell changes with temperature, for example. In a semiconductor memory device other than the PCM, snapback can occur due to another cause.
- the cell current is desirably larger than the snapback current. That is, to read out the stored data at high speed, the operation areas C 2 , C 4 , and C 5 are desirably used.
- the cell current when the cell current larger than the snapback current repeatedly flows through the memory cell, the stored data in the memory cell may be lost. Further, when the cell current becomes larger than Imelt illustrated in FIG. 3A , at least a part of the memory cell is dissolved so that the stored data may be lost. In this case, there is a risk that the stored data cannot be read out again unless the stored data is written again into the memory cell. Accordingly, to safely read out the stored data, the cell current is desirably smaller than the snapback current. That is, to safely read out the stored data, the operation areas C 1 and C 3 are desirably used.
- the read voltage Vread is applied such that snapback of the memory cell does not occur if the stored data is 0 but occurs if the stored data is 1. If the stored data is 0, only the cell current in the operation area C 1 smaller than the snapback current flows. However, if the stored data is 1, the cell current in the operation area C 5 larger than the snapback current flows.
- the reading is an example of second reading processing.
- the read voltage Vread is applied such that snapback of the memory cell does not occur regardless of whether the stored data is 0 or 1. If the stored data is 0, the cell current in the operation area C 1 smaller than the snapback current flows. If the stored data is 1, the cell current in the operation area C 3 smaller than the snapback current flows.
- the reading is an example of first reading processing.
- a time period taken to read out the stored data in FIG. 3A becomes shorter than a time period taken to read out the stored data in FIG. 3B . That is, according to the method illustrated in FIG. 3A , high-speed reading can be performed. On the other hand, according to the method illustrated in FIG. 3B , safe reading can be performed.
- the read current Iread is caused to flow such that snapback of the memory cell occurs regardless of whether the stored data is 0 or 1. If the stored data is 0, the cell current in the operation area C 2 larger than the snapback current flows. If the stored data is 1, the cell current in the operation area C 4 larger than the snapback current flows.
- the reading is an example of second reading processing.
- the read current Iread is caused to flow such that snapback of the memory cell does not occur regardless of whether the stored data is 0 or 1. If the stored data is 0, the cell current in the operation area C 1 smaller than the snapback current flows. If the stored data is 1, the cell current in the operation area C 3 smaller than the snapback current flows.
- the reading is an example of first reading processing.
- a time period taken to read out the stored data in FIG. 4A becomes shorter than a time period taken to read out the stored data in FIG. 4B . That is, according to the method illustrated in FIG. 4A , high-speed reading can be performed. On the other hand, according to the method illustrated in FIG. 4B , safe reading can be performed.
- the first SA 13 , the second SA 14 , and the peripheral circuit portion 1 b in the present embodiment are configured to be able to perform both the first reading processing and the second reading processing.
- the second reading processing is performed if the stored data needs to be read out at high speed
- the first reading processing is performed when the stored data needs to be safely read out.
- the stored data can also be read out at high speed and read out safely so that the stored data can be appropriately read out of each of the memory cells.
- either the processing illustrated in FIG. 3B or the processing illustrated in FIG. 4B may be adopted as the first reading processing
- either the processing illustrated in FIG. 3A or the processing illustrated in FIG. 4A may be adopted as the second reading processing.
- the firmware data and the trim data are safely read out by the first reading processing (the current reading scheme) illustrated in FIG. 4B and the user data is read out at high speed by the second reading processing (the voltage reading scheme) illustrated in FIG. 3A .
- the second reading processing the voltage reading scheme
- the stored data is read out of the memory cell such that the cell current takes respective values in the operation areas C 1 and C 3 regardless of whether the stored data is 0 or 1.
- the stored data is read out of the memory cell such that the cell current of a case where the stored data is 0 and/or 1 takes respective values in the operation areas C 2 , C 4 , and C 5 .
- the stored data can be favorably read out of each of the memory cells in consideration of high speed and safety.
- FIGS. 5A and 5B are graphs for detailed description of FIGS. 3A to 4B .
- FIG. 5A a change of the cell current of a case where the applied voltage is gradually increased when the stored data “0” is read out using the voltage reading scheme is indicated by a thick line. Note that the characteristic of the memory cell changes from the operation area C 1 to the operation area C 5 when the applied voltage becomes higher than the snapback voltage Vth 0 . The same is true when the stored data “1” is read out using the voltage reading scheme.
- FIG. 5B a change of the applied voltage in a case where the cell current is gradually increased when the stored data “0” is read out using the current reading scheme is indicated by a thick line. Note that the characteristic of the memory cell changes from the operation area C 1 to the operation area C 5 via the operation area C 2 . The same is true when the stored data “1” is read out using the current reading scheme.
- FIGS. 6A and 6B are block diagrams illustrating examples of the configuration of the semiconductor memory device 1 of the first embodiment.
- FIG. 6A illustrates a memory cell 16 , a current SA 17 , and a voltage SA 18 in the memory cell array 1 a.
- each of the first SA 13 and the second SA 14 includes the current SA 17 and the voltage SA 18 .
- the current SA 17 is a sense amplifier for the current reading scheme illustrated in FIG. 4A or 4B , and an applied voltage is applied such that a read current Iread flows through the memory cell 16 .
- the peripheral circuit portion 1 b can read stored data in the memory cell 16 based on the applied voltage.
- the read current Iread is an example of a cell current having a predetermined value.
- the voltage SA 18 is a sense amplifier for the voltage reading scheme illustrated in FIG. 3A or 3B , and a read voltage Vread is applied to the memory cell 16 .
- the peripheral circuit portion 1 b can read stored data in the memory cell 16 based on a cell current generated in response to the read voltage Vread.
- the read voltage Vread is an example of an applied voltage having a predetermined value.
- the current SA 17 and the voltage SA 18 each receive an SA selection signal from the peripheral circuit portion 1 b. If the SA selection signal includes an instruction to select the current SA 17 , the current SA 17 operates, to perform reading using the current reading scheme. If the SA selection signal includes the instruction to select the voltage SA 18 , the voltage SA 18 operates, to perform reading using the voltage reading scheme.
- the first SA 13 may include only the current SA 17
- the second SA 14 may include only the voltage SA 18 .
- the former current SA 17 executes the current reading scheme illustrated in FIG. 4B
- the latter voltage SA 18 executes the voltage reading scheme illustrated in FIG. 3A .
- FIG. 6B illustrates a memory cell 16 and an SA 19 in the memory cell array 1 a.
- each of the first SA 13 and the second SA 14 includes the SA 19 .
- the SA 19 is a sense amplifier capable of executing both the current reading scheme illustrated in FIG. 4A or 4B and the voltage reading scheme illustrated in FIG. 3A or 3B . If the SA 19 applies a read voltage Vread to the memory cell 16 , the peripheral circuit portion 1 b can read stored data in the memory cell 16 based on a cell current generated in response to the read voltage Vread. If the SA 19 applies an applied voltage to the memory cell 16 such that a read current Iread flows through the memory cell 16 , the peripheral circuit portion 1 b can read stored data in the memory cell 16 based on this applied voltage.
- the SA 19 receives a read current setting signal, a read voltage setting signal, and/or a current/voltage switching signal from the peripheral circuit portion 1 b.
- the read current setting signal is a signal for setting a value of the read current Iread.
- the read voltage setting signal is a signal for setting a value of the read voltage Vread.
- the current/voltage switching signal is a signal for issuing an instruction as to which of the current reading scheme and the voltage reading scheme is to be executed.
- the SA 19 performs reading using the current reading scheme when it receives the current/voltage switching signal for issuing an instruction to execute the current reading scheme and performs reading using the voltage reading scheme when it receives the current/voltage switching signal for issuing an instruction to execute the voltage reading scheme.
- FIGS. 7A to 7D are diagrams illustrating examples of operations of the semiconductor memory device 1 of the first embodiment.
- firmware data is read out such that snapback does not occur at the time of reading out 0 and 1 by the first reading processing illustrated in FIG. 3B or 4B .
- user data is read out such that snapback occurs at the time of reading out 0 and/or 1 by the second reading processing illustrated in FIG. 3A or 4A .
- the firmware data is data required when the external device 2 is started, for example. In this case, reading involving a risk that the firmware data cannot be correctly read out of the memory cell or the firmware data within the memory cell is lost, for example, is not desirable. Therefore, in this example, the firmware data is read out by safe first reading processing.
- trim data is read out such that snapback does not occur at the time of reading out 0 and 1 by the first reading processing illustrated in FIG. 3B or 4B .
- user data is read out such that snapback occurs at the time of reading out 0 and/or 1 by the second reading processing illustrated in FIG. 3A or 4A .
- trim data is data relating to a redundant cell in the memory cell array 1 a.
- firmware data and trim data are read out such that snapback does not occur at the time of reading out 0 and 1 by the first reading processing illustrated in FIG. 3B or FIG. 4B .
- user data is read out such that snapback occurs at the time of reading out 0 and/or 1 by the second reading processing illustrated in FIG. 3A or 4A .
- FIG. 7D if user data is read out of the memory cell within a certain address area in the UD storage area 12 , the user data is read out such that snapback does not occur at the time of reading out 0 and 1 by the first reading processing illustrated in FIG. 3B or FIG. 4B .
- the user data is read out of the memory cell within another address area in the UD storage area 12 , the user data is read out such that snapback occurs at the time of reading out 0 and/or 1 by the second reading processing illustrated in FIG. 3A or 4A .
- the former address area is an example of a first address area
- the latter address area is an example of a second address area different from the first address area.
- This example can be adopted when a reading speed, an error rate, and reliability required differ for each of the memory cells in the UD storage area 12 .
- This example may be applied to both the FD/TD storage area 11 and the UD storage area 12 .
- all address areas within the FD/TD storage area 11 may be considered as the first address area.
- FIGS. 8A to 8D are schematic views illustrating examples of the configuration of the semiconductor memory device 1 of the first embodiment.
- FIGS. 8A to 8D respectively illustrate various examples of one memory cell in the present embodiment.
- the memory cell illustrated in FIG. 8A includes only a storage element 21 .
- the storage element 21 has a function of storing 0 or 1 as stored data.
- a threshold voltage of the storage element 21 changes to a value like Vth 0 and Vth 1 , described above, depending on the stored data.
- snapback which differs depending on whether the stored data is 0 or 1, is implemented by the storage element 21 .
- the storage element 21 includes operation areas C 1 , C 2 , and C 5 if the stored data is 0 and includes operation areas C 3 , C 4 , and C 5 if the stored data is 1.
- the memory cell illustrated in FIG. 8B includes a storage element 22 and a nonlinear element 23 which are connected in series.
- the storage element 22 has a function of storing 0 or 1 as stored data.
- An example of the storage element 22 is an element which changes in resistance depending on the stored data.
- the nonlinear element 23 has a nonlinear I-V characteristic (current-voltage characteristic).
- An example of the nonlinear element 23 is an element which greatly changes in a current flowing through the nonlinear element 23 depending on a voltage to be applied to the nonlinear element 23 .
- snapback which differs depending on whether the stored data is 0 or 1, is implemented by the storage element 22 and the nonlinear element 23 .
- the nonlinear element 23 may be replaced with a diode, and a threshold voltage of the storage element 22 may change depending on the stored data.
- the memory cell illustrated in FIG. 8C includes a storage element 22 and a snapback element 24 which are connected in series.
- the storage element 22 has a function of storing 0 or 1 as stored data.
- An example of the storage element 22 is an element which changes in resistance depending on the stored data.
- the snapback element 24 has an I-V characteristic including snapback.
- the I-V characteristic of the snapback element 24 is the same regardless of whether the stored data in the storage element 22 is 0 or 1.
- snapback which differs depending on whether the stored data is 0 or 1, is implemented by the storage element 22 and the snapback element 24 .
- the snapback element 24 may be replaced with a select element for selecting a memory cell, and a threshold voltage of the storage element 22 may change depending on the stored data.
- the memory cell illustrated in FIG. 8D includes a storage element 25 and a snapback element 24 which are connected in series.
- the storage element 25 has a function of storing 0 or 1 as stored data.
- the storage element 25 has an I-V characteristic including snapback.
- the I-V characteristic of the storage element 25 differs depending on whether the stored data in the storage element 22 is 0 or 1.
- the snapback element 24 has an I-V characteristic including snapback.
- the I-V characteristic of the snapback element 24 is the same regardless of whether the stored data in the storage element 22 is 0 or 1.
- snapback which differs depending on whether the stored data is 0 or 1
- the snapback element 24 has a function of changing the snapback.
- the snapback element 24 may be replaced with a select element for selecting a memory cell.
- Each of the memory cells in the present embodiment is arranged at a point where one word line and one bit line intersect each other, for example.
- the storage element 22 and the nonlinear element 23 illustrated in FIG. 8B are connected in series between the word line and the bit line, and an applied voltage is the sum of a voltage applied to the storage element 22 and a voltage applied to the nonlinear element 23 .
- FIGS. 8C and 8D The same is true in cases illustrated in FIGS. 8C and 8D .
- the semiconductor memory device 1 of the present embodiment reads out the stored data from the memory cell by the first and second reading processing.
- the stored data is read out of the memory cell such that the cell current takes the respective values in the operation areas C 1 and C 3 regardless of whether the stored data is 0 or 1.
- the second reading processing the stored data is read out of the memory cell such that the cell current of a case where the stored data is 0 and/or 1 takes the respective values in the operation areas C 2 , C 4 , and C 5 .
- the stored data can be appropriately read out of each of the memory cells.
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Abstract
Description
- This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2018-053060, filed on Mar. 20, 2018, the entire contents of which are incorporated herein by reference.
- Embodiments described herein relate to a semiconductor memory device and a method of controlling the same.
- In recent years, research and development of various semiconductor memory devices such as a PCM (phase-change memory), an ReRAM (resistive random access memory) and an MRAM (magnetoresistive random access memory) have been advanced. Regarding reading data from a memory cell in a semiconductor memory device, there are various demands such as a demand for reading out the data at high speed and a demand for safely reading out the data. Accordingly, there is a problem how to implement appropriate data reading to meet the demands.
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FIG. 1 is a block diagram illustrating a configuration of a semiconductor memory device of a first embodiment; -
FIG. 2 is a block diagram illustrating a configuration of a semiconductor memory device of a modification to the first embodiment; -
FIGS. 3A to 4B are graphs for describing operations of the semiconductor memory device of the first embodiment; -
FIGS. 5A and 5B are graphs for detailed description ofFIGS. 3A to 4B ; -
FIGS. 6A and 6B are block diagrams illustrating examples of the configuration of the semiconductor memory device of the first embodiment; -
FIGS. 7A to 7D are diagrams illustrating examples of operations of the semiconductor memory device of the first embodiment; and -
FIGS. 8A to 8D are schematic views illustrating examples of the configuration of the semiconductor memory device of the first embodiment. - Embodiments will now be explained with reference to the accompanying drawings. In
FIG. 1 toFIG. 8D , identical or similar components are assigned the same reference numerals, and hence redundant description is omitted. - In one embodiment, a semiconductor memory device includes a memory cell configured to store a first value or a second value as stored data, and a control circuit configured to read out the first value or the second value as the stored data from the memory cell. The memory cell includes a first operation area where a cell current flowing across the memory cell increases as a voltage across the memory cell increases, a second operation area where the cell current in the second operation area is larger than the cell current in the first operation area and the voltage across the memory cell decreases while the cell current increases, and a third operation area where the cell current in the third operation area is larger than the cell current in the second operation area and the cell current increases as the voltage across the memory cell increases. The control circuit performs first reading processing of reading out the stored data from the memory cell such that the cell current of a case where the stored data has the first value and the cell current of a case where the stored data has the second value respectively take values in the first operation area. The control circuit performs second reading processing of reading out the stored data from the memory cell such that at least one of the cell current in the case where the stored data has the first value and the cell current in the case where the stored data has the second value takes a value in the second operation area or the third operation area.
-
FIG. 1 is a block diagram illustrating a configuration of asemiconductor memory device 1 of a first embodiment. -
FIG. 1 illustrates thesemiconductor memory device 1 and anexternal device 2 that can transmit and receive signals to and from thesemiconductor memory device 1. Although a PCM in the present embodiment, the semiconductor memory device may be another semiconductor memory device (e.g., an ReRAM or an MRAM). Theexternal device 2 may be an IC (integrated circuit) that controls an operation of thesemiconductor memory device 1 or a PC (personal computer) in or on which thesemiconductor memory device 1 is contained or mounted. - The
semiconductor memory device 1 includes amemory cell array 1 a including a plurality of memory cells and aperipheral circuit portion 1 b that performs processing such as control of thememory cell array 1 a. Thememory cell array 1 a has a cross-point structure including memory cells, respectively, at points where a plurality of word lines and a plurality of bit lines intersect each other. Theperipheral circuit portion 1 b performs processing such as writing data into the memory cells, reading data from the memory cells, receiving a signal from theexternal device 2, and transmitting a signal to theexternal device 2. - The
memory cell array 1 a includes a firmware data/trim data (FD/TD)storage area 11, a user data (UD)storage area 12, a first sense amplifier (SA) 13, and a second sense amplifier (SA) 14. - The FD/
TD storage area 11 is a storage area including a memory cell which stores data (firmware data) for a basic operation of theexternal device 2 and a memory cell which stores data (trim data) for a basic operation of theperipheral circuit portion 1 b. TheUD storage area 12 is a storage area including a memory cell for a user of thesemiconductor memory device 1 to store data (user data). - The
first SA 13 and thesecond SA 14 each transfers read data, which has been received from a memory cell, to theexternal device 2 via theperipheral circuit portion 1 b and transfers write data, which has been received from theexternal device 2 via theperipheral circuit portion 1 b, to a memory cell. The first SA 13 is provided to handle the firmware data and the trim data, and thesecond SA 14 is provided to handle the user data. Thefirst SA 13, thesecond SA 14, and theperipheral circuit portion 1 b are each an example of a control circuit. -
FIG. 2 is a block diagram illustrating a configuration of asemiconductor memory device 1 of a modification to the first embodiment. - The
semiconductor memory device 1 of the modification includes a firmware data/trim data/user data (FD/TD/UD)storage area 15 instead of the FD/TD storage area 11 and theUD storage area 12. In the modification, a storage area for firmware data and trim data and a storage area for user data are not separated from each other, and all the firmware data, the trim data, and the user data are stored in the FD/TD/UD storage area 15. - Although details of the
semiconductor memory device 1 illustrated inFIG. 1 will be described below, the following description is also applicable to thesemiconductor memory device 1 illustrated inFIG. 2 . -
FIGS. 3A to 4B are graphs for describing an operation of thesemiconductor memory device 1 of the first embodiment. - In
FIGS. 3A to 4B , a horizontal axis represents an applied voltage applied to each of the memory cells in thesemiconductor memory device 1, and a vertical axis represents a cell current flowing through each of the memory cells in thesemiconductor memory device 1. When the voltage represented by the horizontal axis is applied between terminals of any one of the memory cells, the cell current represented by the vertical axis flows from one of the terminals to the other terminal of the memory cell. When the cell current flowing between the terminals of any one of the memory cells changes, as with the above-described graph, a voltage between the terminals of the memory cell changes, as with the above-described graph. -
FIGS. 3A to 4B illustrate four schemes for reading out 0 or 1 as stored data from the memory cell. The stored data “0” is an example of a first value, and indicates that the memory cell is in a high-resistance state, for example. The stored data “1” is an example of a second value, and indicates that the memory cell is in a low-resistive state, for example. - In
FIGS. 3A and 3B , a voltage reading scheme has been adopted. More specifically, a read voltage Vread is applied as an applied voltage to the memory cell, and it is determined whether the stored data is 0 or 1 based on the magnitude of a cell current generated depending on the read voltage Vread. InFIG. 3A , the read voltage Vread is applied such that snapback of the memory cell does not occur when the stored data is 0 but occurs if the stored data is 1. On the other hand, inFIG. 3B , the read voltage Vread is applied such that snapback of the memory cell does not occur regardless of whether the stored data is 0 or 1. - In
FIGS. 4A and 4B , a current reading scheme has been adopted. More specifically, an applied voltage is applied such that a read current Iread flows as a cell current through the memory cell, and it is determined whether the stored data is 0 or 1 based on the magnitude of the applied voltage. InFIG. 4A , the read current Iread is caused to flow such that snapback of the memory cell occurs regardless of whether the stored data is 0 or 1. On the other hand, inFIG. 4B , the read current Iread is caused to flow such that snapback of the memory cell does not occur regardless of whether the stored data is 0 or 1. - An operation characteristic and snapback of the memory cell will be described below while mainly referring to
FIG. 3A . In the description,FIGS. 3B to 4B will also be referred to, as needed. - As illustrated in
FIG. 3A , the memory cell in the present embodiment in case the stored data is 0 includes an operation area C1, an operation area C2 where a cell current is larger than a cell current in the operation area C1, and an operation area C5 where a cell current is larger than the cell current in the operation area C2. Further, the memory cell in the present embodiment in case the stored data is 1 includes an operation area C3, an operation area C4 where a cell current is larger than a cell current in the operation area C3, and the operation area C5 where the cell current is larger than the cell current in the operation area C4. The operation areas C1 and C3 are each an example of a first operation area, the operation areas C2 and C4 are each a second operation area, and the operation area C5 is an example of a third operation area. - In the operation areas C1 and C3, the cell current increases as the applied voltage increases. The cell current in the operation area C3 more steeply increases than the cell current in the operation area C1 in response to the increase in the applied voltage. In the operation areas C2 and C4, the applied voltage decreases while the cell current increases. The applied voltage in the operation area C4 more gently decreases than the applied voltage in the operation area C2 in response to the increase in the cell current. In the operation area C5, the cell current increases as the applied voltage increases. In the operation area C5, the memory cell has the same characteristic regardless of whether the stored data is 0 or 1.
- Reference character P0 represents an inflection point between a curve representing the operation area C1 and a curve representing the operation area C2, and reference character Vth0 represents an applied voltage at the inflection point P0.
- The applied voltage Vth0 is referred to as a threshold voltage (snapback voltage) in a case where the stored data is 0.
- Reference character P1 represents an inflection point between a curve representing the operation area C3 and a curve representing the operation area C4, and reference character Vth1 represents an applied voltage at the inflection point P1. The applied voltage Vth1 is referred to as a threshold voltage (snapback voltage) in a case where the stored data is 1.
- In the present embodiment, a cell current corresponding to the applied voltage Vth0 and a cell current corresponding to the applied voltage Vth1 have the same magnitude.
- Hereinafter, the cell current will be each referred to as a snapback current.
- The semiconductor memory device of the present embodiment is the PCM. In this case, there occurs a phenomenon that the characteristic of the memory cell changes from a characteristic of the operation area C1 to a characteristic of the operation area C2 at the inflection point P0 and changes from a characteristic of the operation area C3 to a characteristic of the operation area C4 at the inflection point P1. The phenomenon is referred to as snapback. The snapback of the PCM occurs when the characteristic of the memory cell changes with temperature, for example. In a semiconductor memory device other than the PCM, snapback can occur due to another cause.
- If the stored data is read out of the memory cell, the larger the cell current is, the higher a speed at which the stored data can be read out becomes. Accordingly, to read out the stored data at high speed, the cell current is desirably larger than the snapback current. That is, to read out the stored data at high speed, the operation areas C2, C4, and C5 are desirably used.
- On the other hand, when the cell current larger than the snapback current repeatedly flows through the memory cell, the stored data in the memory cell may be lost. Further, when the cell current becomes larger than Imelt illustrated in
FIG. 3A , at least a part of the memory cell is dissolved so that the stored data may be lost. In this case, there is a risk that the stored data cannot be read out again unless the stored data is written again into the memory cell. Accordingly, to safely read out the stored data, the cell current is desirably smaller than the snapback current. That is, to safely read out the stored data, the operation areas C1 and C3 are desirably used. - Accordingly, in
FIG. 3A , to read out the stored data at high speed, the read voltage Vread is applied such that snapback of the memory cell does not occur if the stored data is 0 but occurs if the stored data is 1. If the stored data is 0, only the cell current in the operation area C1 smaller than the snapback current flows. However, if the stored data is 1, the cell current in the operation area C5 larger than the snapback current flows. The reading is an example of second reading processing. - On the other hand, in
FIG. 3B , to safely read out the stored data, the read voltage Vread is applied such that snapback of the memory cell does not occur regardless of whether the stored data is 0 or 1. If the stored data is 0, the cell current in the operation area C1 smaller than the snapback current flows. If the stored data is 1, the cell current in the operation area C3 smaller than the snapback current flows. The reading is an example of first reading processing. - For reading stored data from one memory cell, a time period taken to read out the stored data in
FIG. 3A becomes shorter than a time period taken to read out the stored data inFIG. 3B . That is, according to the method illustrated inFIG. 3A , high-speed reading can be performed. On the other hand, according to the method illustrated inFIG. 3B , safe reading can be performed. - Similarly, in
FIG. 4A , to read out the stored data at high speed, the read current Iread is caused to flow such that snapback of the memory cell occurs regardless of whether the stored data is 0 or 1. If the stored data is 0, the cell current in the operation area C2 larger than the snapback current flows. If the stored data is 1, the cell current in the operation area C4 larger than the snapback current flows. The reading is an example of second reading processing. - On the other hand, in
FIG. 4B , to safely read out the stored data, the read current Iread is caused to flow such that snapback of the memory cell does not occur regardless of whether the stored data is 0 or 1. If the stored data is 0, the cell current in the operation area C1 smaller than the snapback current flows. If the stored data is 1, the cell current in the operation area C3 smaller than the snapback current flows. The reading is an example of first reading processing. - For reading stored data from one memory cell, a time period taken to read out the stored data in
FIG. 4A becomes shorter than a time period taken to read out the stored data inFIG. 4B . That is, according to the method illustrated inFIG. 4A , high-speed reading can be performed. On the other hand, according to the method illustrated inFIG. 4B , safe reading can be performed. - The
first SA 13, thesecond SA 14, and theperipheral circuit portion 1 b in the present embodiment are configured to be able to perform both the first reading processing and the second reading processing. For example, the second reading processing is performed if the stored data needs to be read out at high speed, and the first reading processing is performed when the stored data needs to be safely read out. Accordingly, according to the present embodiment, the stored data can also be read out at high speed and read out safely so that the stored data can be appropriately read out of each of the memory cells. - In the present embodiment, either the processing illustrated in
FIG. 3B or the processing illustrated inFIG. 4B may be adopted as the first reading processing, and either the processing illustrated inFIG. 3A or the processing illustrated inFIG. 4A may be adopted as the second reading processing. For example, it is considered that the firmware data and the trim data are safely read out by the first reading processing (the current reading scheme) illustrated inFIG. 4B and the user data is read out at high speed by the second reading processing (the voltage reading scheme) illustrated inFIG. 3A . The reason is that the firmware data and the trim data are undesirably lost while the user data is desirably read out at high speed. Application of the first and second reading processing to the firmware data, the trim data, and the user data will be described in more detail below. - As described above, in the first reading processing illustrated in
FIGS. 3B and 4B , the stored data is read out of the memory cell such that the cell current takes respective values in the operation areas C1 and C3 regardless of whether the stored data is 0 or 1. On the other hand, in the second reading processing illustrated inFIG. 3A andFIG. 4A , the stored data is read out of the memory cell such that the cell current of a case where the stored data is 0 and/or 1 takes respective values in the operation areas C2, C4, and C5. As a result, the stored data can be favorably read out of each of the memory cells in consideration of high speed and safety. -
FIGS. 5A and 5B are graphs for detailed description ofFIGS. 3A to 4B . - In
FIG. 5A , a change of the cell current of a case where the applied voltage is gradually increased when the stored data “0” is read out using the voltage reading scheme is indicated by a thick line. Note that the characteristic of the memory cell changes from the operation area C1 to the operation area C5 when the applied voltage becomes higher than the snapback voltage Vth0. The same is true when the stored data “1” is read out using the voltage reading scheme. - In
FIG. 5B , a change of the applied voltage in a case where the cell current is gradually increased when the stored data “0” is read out using the current reading scheme is indicated by a thick line. Note that the characteristic of the memory cell changes from the operation area C1 to the operation area C5 via the operation area C2. The same is true when the stored data “1” is read out using the current reading scheme. -
FIGS. 6A and 6B are block diagrams illustrating examples of the configuration of thesemiconductor memory device 1 of the first embodiment. -
FIG. 6A illustrates amemory cell 16, acurrent SA 17, and avoltage SA 18 in thememory cell array 1 a. In an example illustrated inFIG. 6A , each of thefirst SA 13 and thesecond SA 14 includes thecurrent SA 17 and thevoltage SA 18. - The
current SA 17 is a sense amplifier for the current reading scheme illustrated inFIG. 4A or 4B , and an applied voltage is applied such that a read current Iread flows through thememory cell 16. Theperipheral circuit portion 1 b can read stored data in thememory cell 16 based on the applied voltage. The read current Iread is an example of a cell current having a predetermined value. - The
voltage SA 18 is a sense amplifier for the voltage reading scheme illustrated inFIG. 3A or 3B , and a read voltage Vread is applied to thememory cell 16. Theperipheral circuit portion 1 b can read stored data in thememory cell 16 based on a cell current generated in response to the read voltage Vread. The read voltage Vread is an example of an applied voltage having a predetermined value. - The
current SA 17 and thevoltage SA 18 each receive an SA selection signal from theperipheral circuit portion 1 b. If the SA selection signal includes an instruction to select thecurrent SA 17, thecurrent SA 17 operates, to perform reading using the current reading scheme. If the SA selection signal includes the instruction to select thevoltage SA 18, thevoltage SA 18 operates, to perform reading using the voltage reading scheme. - Suppose a case where firmware data and trim data are read out using the current reading scheme illustrated in
FIG. 4B , and user data is read out using the voltage reading scheme illustrated inFIG. 3A . In this case, thefirst SA 13 may include only thecurrent SA 17, and thesecond SA 14 may include only thevoltage SA 18. The formercurrent SA 17 executes the current reading scheme illustrated inFIG. 4B , and thelatter voltage SA 18 executes the voltage reading scheme illustrated inFIG. 3A . -
FIG. 6B illustrates amemory cell 16 and anSA 19 in thememory cell array 1 a. In an example illustrated inFIG. 6B , each of thefirst SA 13 and thesecond SA 14 includes theSA 19. - The
SA 19 is a sense amplifier capable of executing both the current reading scheme illustrated inFIG. 4A or 4B and the voltage reading scheme illustrated inFIG. 3A or 3B . If theSA 19 applies a read voltage Vread to thememory cell 16, theperipheral circuit portion 1 b can read stored data in thememory cell 16 based on a cell current generated in response to the read voltage Vread. If theSA 19 applies an applied voltage to thememory cell 16 such that a read current Iread flows through thememory cell 16, theperipheral circuit portion 1 b can read stored data in thememory cell 16 based on this applied voltage. - The
SA 19 receives a read current setting signal, a read voltage setting signal, and/or a current/voltage switching signal from theperipheral circuit portion 1 b. The read current setting signal is a signal for setting a value of the read current Iread. The read voltage setting signal is a signal for setting a value of the read voltage Vread. The current/voltage switching signal is a signal for issuing an instruction as to which of the current reading scheme and the voltage reading scheme is to be executed. TheSA 19 performs reading using the current reading scheme when it receives the current/voltage switching signal for issuing an instruction to execute the current reading scheme and performs reading using the voltage reading scheme when it receives the current/voltage switching signal for issuing an instruction to execute the voltage reading scheme. -
FIGS. 7A to 7D are diagrams illustrating examples of operations of thesemiconductor memory device 1 of the first embodiment. - In an example illustrated in
FIG. 7A , firmware data is read out such that snapback does not occur at the time of reading out 0 and 1 by the first reading processing illustrated inFIG. 3B or 4B . On the other hand, user data is read out such that snapback occurs at the time of reading out 0 and/or 1 by the second reading processing illustrated inFIG. 3A or 4A . - The firmware data is data required when the
external device 2 is started, for example. In this case, reading involving a risk that the firmware data cannot be correctly read out of the memory cell or the firmware data within the memory cell is lost, for example, is not desirable. Therefore, in this example, the firmware data is read out by safe first reading processing. - In an example illustrated in
FIG. 7B , trim data is read out such that snapback does not occur at the time of reading out 0 and 1 by the first reading processing illustrated inFIG. 3B or 4B . On the other hand, user data is read out such that snapback occurs at the time of reading out 0 and/or 1 by the second reading processing illustrated inFIG. 3A or 4A . - An example of the trim data is data relating to a redundant cell in the
memory cell array 1 a. In this case, reading involving a risk that the trim data cannot be correctly read out of the memory cell or the trim data within the memory cell is lost, for example, is not desirable. Therefore, in this example, the trim data is read out by safe first reading processing. - In an example illustrated in
FIG. 7C , firmware data and trim data are read out such that snapback does not occur at the time of reading out 0 and 1 by the first reading processing illustrated inFIG. 3B orFIG. 4B . On the other hand, user data is read out such that snapback occurs at the time of reading out 0 and/or 1 by the second reading processing illustrated inFIG. 3A or 4A . - In an example illustrated in
FIG. 7D , if user data is read out of the memory cell within a certain address area in theUD storage area 12, the user data is read out such that snapback does not occur at the time of reading out 0 and 1 by the first reading processing illustrated inFIG. 3B orFIG. 4B . On the other hand, if user data is read out of the memory cell within another address area in theUD storage area 12, the user data is read out such that snapback occurs at the time of reading out 0 and/or 1 by the second reading processing illustrated inFIG. 3A or 4A . The former address area is an example of a first address area, and the latter address area is an example of a second address area different from the first address area. - This example can be adopted when a reading speed, an error rate, and reliability required differ for each of the memory cells in the
UD storage area 12. This example may be applied to both the FD/TD storage area 11 and theUD storage area 12. In this case, all address areas within the FD/TD storage area 11 may be considered as the first address area. -
FIGS. 8A to 8D are schematic views illustrating examples of the configuration of thesemiconductor memory device 1 of the first embodiment.FIGS. 8A to 8D respectively illustrate various examples of one memory cell in the present embodiment. - The memory cell illustrated in
FIG. 8A includes only astorage element 21. Thestorage element 21 has a function of storing 0 or 1 as stored data. A threshold voltage of thestorage element 21 changes to a value like Vth0 and Vth1, described above, depending on the stored data. In the example illustrated inFIG. 8A , snapback, which differs depending on whether the stored data is 0 or 1, is implemented by thestorage element 21. More specifically, thestorage element 21 includes operation areas C1, C2, and C5 if the stored data is 0 and includes operation areas C3, C4, and C5 if the stored data is 1. - The memory cell illustrated in
FIG. 8B includes astorage element 22 and anonlinear element 23 which are connected in series. Thestorage element 22 has a function of storing 0 or 1 as stored data. An example of thestorage element 22 is an element which changes in resistance depending on the stored data. Thenonlinear element 23 has a nonlinear I-V characteristic (current-voltage characteristic). An example of thenonlinear element 23 is an element which greatly changes in a current flowing through thenonlinear element 23 depending on a voltage to be applied to thenonlinear element 23. In the example illustrated inFIG. 8B , snapback, which differs depending on whether the stored data is 0 or 1, is implemented by thestorage element 22 and thenonlinear element 23. - In the example illustrated in
FIG. 8B , thenonlinear element 23 may be replaced with a diode, and a threshold voltage of thestorage element 22 may change depending on the stored data. - The memory cell illustrated in
FIG. 8C includes astorage element 22 and asnapback element 24 which are connected in series. Thestorage element 22 has a function of storing 0 or 1 as stored data. An example of thestorage element 22 is an element which changes in resistance depending on the stored data. Thesnapback element 24 has an I-V characteristic including snapback. The I-V characteristic of thesnapback element 24 is the same regardless of whether the stored data in thestorage element 22 is 0 or 1. In the example illustrated inFIG. 8C , snapback, which differs depending on whether the stored data is 0 or 1, is implemented by thestorage element 22 and thesnapback element 24. - In the example illustrated in
FIG. 8C , thesnapback element 24 may be replaced with a select element for selecting a memory cell, and a threshold voltage of thestorage element 22 may change depending on the stored data. - The memory cell illustrated in
FIG. 8D includes astorage element 25 and asnapback element 24 which are connected in series. Thestorage element 25 has a function of storing 0 or 1 as stored data. Thestorage element 25 has an I-V characteristic including snapback. The I-V characteristic of thestorage element 25 differs depending on whether the stored data in thestorage element 22 is 0 or 1. On the other hand, thesnapback element 24 has an I-V characteristic including snapback. However, the I-V characteristic of thesnapback element 24 is the same regardless of whether the stored data in thestorage element 22 is 0 or 1. In the example illustrated inFIG. 8D , snapback, which differs depending on whether the stored data is 0 or 1, is implemented by only thestorage element 25. However, thesnapback element 24 has a function of changing the snapback. - In the example illustrated in
FIG. 8D , thesnapback element 24 may be replaced with a select element for selecting a memory cell. - Each of the memory cells in the present embodiment is arranged at a point where one word line and one bit line intersect each other, for example. In this case, the
storage element 22 and thenonlinear element 23 illustrated inFIG. 8B are connected in series between the word line and the bit line, and an applied voltage is the sum of a voltage applied to thestorage element 22 and a voltage applied to thenonlinear element 23. The same is true in cases illustrated inFIGS. 8C and 8D . - As described above, the
semiconductor memory device 1 of the present embodiment reads out the stored data from the memory cell by the first and second reading processing. In the first reading processing, the stored data is read out of the memory cell such that the cell current takes the respective values in the operation areas C1 and C3 regardless of whether the stored data is 0 or 1. In the second reading processing, the stored data is read out of the memory cell such that the cell current of a case where the stored data is 0 and/or 1 takes the respective values in the operation areas C2, C4, and C5. - As described above, according to the present embodiment, when the first reading processing and the second reading processing are differently used in consideration of high speed and safety of reading, for example, the stored data can be appropriately read out of each of the memory cells.
- While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel apparatuses and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the apparatuses and methods described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
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US20190295638A1 true US20190295638A1 (en) | 2019-09-26 |
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US (1) | US10418101B1 (en) |
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2018
- 2018-03-20 JP JP2018053060A patent/JP2019164873A/en active Pending
- 2018-06-22 TW TW107121475A patent/TWI689941B/en active
- 2018-07-19 US US16/039,786 patent/US10418101B1/en active Active
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JP2019164873A (en) | 2019-09-26 |
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CN110310679B (en) | 2023-08-11 |
CN110310679A (en) | 2019-10-08 |
US10418101B1 (en) | 2019-09-17 |
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