US20190287984A1 - Memory devices having vertically extending channel structures therein - Google Patents
Memory devices having vertically extending channel structures therein Download PDFInfo
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- US20190287984A1 US20190287984A1 US16/043,258 US201816043258A US2019287984A1 US 20190287984 A1 US20190287984 A1 US 20190287984A1 US 201816043258 A US201816043258 A US 201816043258A US 2019287984 A1 US2019287984 A1 US 2019287984A1
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Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H01L27/11582—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H01L27/1157—
-
- H01L27/11573—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Definitions
- the present inventive concept relates to memory devices and, more particularly, to vertical memory devices, such as vertical nonvolatile memory devices.
- Non-volatile memory devices including memory cells arranged in three dimensions have been proposed for high integration and reduction in the weight, width, length, and size of electronic products.
- a channel structure passing through a stacked structure is required and a channel pattern of the channel structure needs to be in electrical contact with a substrate.
- a selective epitaxial growth (SEG) process can be used after a lower portion of the channel structure is etched.
- SEG process may become exceptionally complex. Therefore, there have been attempts to use a technique in which an opening is formed in a side surface of a channel structure.
- the present inventive concept is directed to providing a memory device having a channel protective film therein, which enables an etched surface of an information storage pattern to be controlled to be uniform when an opening is formed in a side surface of a channel structure.
- the present inventive concept is directed to providing a memory device for preventing a problem of over-etching of an information storage pattern when an opening is formed in a side surface of a channel structure.
- the present inventive concept is directed to providing a method of manufacturing a memory device which controls the etching of an information storage pattern to be uniform when an opening is formed in a side surface of a channel structure.
- a memory device includes a lower stacked structure formed on a substrate and including a first source film and a second source film disposed below the first source film, an upper stacked structure disposed on the lower stacked structure, and a channel structure passing through the upper stacked structure and the first source film and including a channel pattern configured to extend downward and an information storage pattern disposed outside the channel pattern.
- the second source film is formed below the information storage pattern and is in contact with the channel pattern.
- the second source film includes a protrusion configured to extend upward, and a channel protective film is disposed on at least a portion between the protrusion and the information storage pattern.
- a method of manufacturing a memory device includes: forming a lower stacked structure including a first source film on a substrate, forming an upper stacked structure, in which an insulating layer and a sacrificial layer are alternately disposed, on the lower stacked structure, forming a channel structure passing through the upper stacked structure and the first source film and including a channel pattern and an information storage pattern, forming a word line cut passing through the first source film and configured to expose side surfaces of the insulating layer and the sacrificial layer, etching a portion of the information storage pattern through the word line cut, forming a channel protective film on a portion in which the information storage pattern is removed, exposing the channel pattern by etching a portion of the channel protective film, and forming a second source film in contact with the first source film and the channel pattern.
- a memory device includes a lower stacked structure formed on a substrate and including a first source film and a second source film disposed below the first source film, an upper stacked structure disposed on the lower stacked structure, and a channel structure passing through the upper stacked structure and the first source film and including a channel pattern configured to extend downward and an information storage pattern disposed outside the channel pattern.
- the second source film is formed below the information storage pattern and is in contact with the channel pattern.
- the second source film includes a protrusion configured to extend upward.
- a channel protective film is disposed between the protrusion and the information storage pattern.
- the channel protective film may be formed below a blocking layer and a charge storage layer of the information storage pattern, and a lower end of the channel protective film may be located at the same level as a lower end of a tunnel insulation layer of the information storage pattern.
- An upper end of the protrusion may be located at a lower level than an upper end of the first source film.
- FIG. 1 is a schematic layout of some regions of a semiconductor device according to an embodiment of the present inventive concept.
- FIG. 2 is a vertical sectional view taken along line I-I′ of FIG. 1 .
- FIG. 3 is an enlarged view of a region E shown in FIG. 2 .
- FIGS. 4 to 8 are enlarged views of a region E according to other embodiments of the inventive concept, which correspond to the region E of FIG. 3 .
- FIGS. 9 to 15, 16A, 16B, and 17 to 23 are cross-sectional views shown in accordance with a process sequence for describing a method of manufacturing a cell region according to an embodiment of the present inventive concept.
- FIGS. 24 to 28 are enlarged views of a region E shown in accordance with a process sequence for describing a process of forming a channel protective film shown in FIG. 6 .
- FIGS. 29 to 32 are enlarged views of a region E shown in accordance with a process sequence for describing a process of forming a channel protective film shown in FIG. 7 .
- FIGS. 33 to 35 are enlarged views of a region E shown in accordance with a process sequence for describing a process of forming a channel oxide film shown in FIG. 8 .
- first, second, third, etc. may be used herein to describe various elements, components and/or regions, these elements, components and/or regions should not be limited by these terms. These terms are only used to distinguish one element, component and/or region from another element, component and/or region. Thus, a first element, component and/or region discussed below could be termed a second element, component and/or region without departing from the teachings of the present invention.
- FIG. 1 is a schematic layout view of a semiconductor memory device according to an embodiment of the present inventive concept
- FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1 taken along line I-I′ of FIG. 1
- a memory device according to embodiments of the present inventive concept may include flash memory such as a VNAND (vertical NAND) or a 3D-NAND.
- the memory device may include a cell region 100 and a peripheral region 160 .
- the memory device may have a cell-on-peripheral (COP) structure in which a cell region 100 is formed on a peripheral region 160 , as illustrated by FIG. 2 .
- the cell region 100 may include a lower stacked structure 110 including a substrate 102 , an upper stacked structure 120 , bit lines BL, and word line cuts WLC.
- a first direction D 1 may refer to a direction in which the cell region 100 and the peripheral region 160 are stacked.
- the first direction D 1 may refer to a direction perpendicular to a main surface of the substrate 102 .
- a second direction D 2 may refer to a direction which is perpendicular to the first direction D 1 and parallel to the bit lines BL.
- a third direction D 3 may refer to a direction which is perpendicular to the first direction D 1 and the second direction D 2 and parallel to the word line cuts WLC.
- the lower stacked structure 110 may include the substrate 102 , a first source film 112 , and a second source film 114 .
- the first source film 112 and the second source film 114 may be formed on the substrate 102 .
- the second source film 114 may be formed below the first source film 112 , and at least a portion of the second source film 114 may be in contact with a side surface of the first source film 112 .
- the substrate 102 may be polysilicon containing a P-type impurity
- the first source film 112 and the second source film 114 may be polysilicon containing an N-type impurity.
- Insulating layers 122 and gate electrodes 124 may be alternately stacked within the upper stacked structure 120 , as illustrated by FIG. 2 .
- the insulating layers 122 may electrically insulate the gate electrodes 124 .
- Some of the gate electrodes 124 formed at a lower portion of the upper stacked structure 120 may be configured as ground selection lines GSL.
- Some of the gate electrodes 124 formed at an upper portion of the upper stacked structure 120 may be string selection lines SSL or drain selection lines DSL.
- an insulating film which surrounds each gate electrode 124 may be formed between the insulating layers 122 .
- the memory device may include channel holes CHH, which pass through the upper stacked structure 120 and the first source film 112 and extend downward in the first direction D 1 .
- channel holes CHH which pass through the upper stacked structure 120 and the first source film 112 and extend downward in the first direction D 1 .
- Four or five channel holes CHH may be formed between the common source lines 140 in the second direction D 2 .
- a channel structure 130 may be formed inside each channel hole CHH.
- the channel structure 130 may include an information storage pattern 131 , a channel pattern 135 , and a core pattern 136 which are sequentially formed from the outside of the channel hole CHH toward the inside thereof.
- the word line cut WLC disposed adjacent to the channel structure 130 may be formed in the memory device.
- the word line cut WLC may pass through the upper stacked structure 120 and the first source film 112 in the first direction D 1 and extend in the third direction D 3 .
- the common source line 140 , a sidewall insulating film 142 , and an impurity region 144 may be formed along the word line cut WLC.
- the sidewall insulating film 142 may be formed on a side surface of the word line cut WLC, and the impurity region 144 may be formed on a lower portion of the word line cut WLC.
- a string selection line cut SLC may be formed between the common source lines 140 .
- the string selection line cut SLC may be formed above a dummy channel structure 138 in the third direction D 3 .
- the string selection line cut SLC may divide at least one of the plurality of gate electrodes 124 .
- the string selection line cut SLC may divide the string selection line SSL.
- the dummy channel structure 138 may not be electrically connected to the bit line BL.
- Conductive pads 150 may be formed on the upper stacked structure 120 , and may be located at the same level as an interlayer dielectric 151 .
- the conductive pad 150 may be formed on the channel structure 130 in each channel hole CHH.
- the conductive pad 150 may be in contact with the channel pattern 135 .
- the conductive pad 150 may be connected to a sub bit line SBL through a first bit plug 153
- the sub bit line SBL may be connected to the bit line BL through a second bit plug 155 .
- insulating layers located at the same level may be formed on the first bit plug 153 , the second bit plug 155 , and the sub bit line SBL.
- the “level” may refer to a height from the substrate 102 in the first direction D 1 .
- the peripheral region 160 may be formed below the cell region 100 .
- the peripheral region 160 may include a lower substrate 162 and a lower insulating layer 164 formed on the lower substrate 162 .
- Peripheral transistors 170 may be formed in the peripheral region 160 .
- the peripheral transistor 170 may include a peripheral gate insulating film 171 , a peripheral gate electrode 172 , and a source/drain region 173 .
- the peripheral transistor 170 may be connected to an interconnection pattern 175 through a contact plug 174 , and the peripheral transistor 170 and the interconnection pattern 175 may constitute a peripheral circuit.
- the lower insulating layer 164 may be formed to cover the peripheral transistor 170 and the interconnection pattern 175 .
- FIG. 3 is an enlarged view of region E shown in FIG. 2 .
- the second source film 114 may be formed between the first source film 112 and the substrate 102 .
- the second source film 114 may be in contact with the channel pattern 135 .
- the second source film 114 may include a protrusion 115 which extends upward in the first direction D 1 .
- the information storage pattern 131 may be formed outside the channel pattern 135 .
- the information storage pattern 131 may include a blocking layer 132 , a charge storage layer 133 , and a tunnel insulation layer 134 , which are sequentially formed from the outside of the channel hole CHH toward the inside thereof.
- the information storage pattern 131 may be partially disconnected in the first direction D 1 .
- Lower ends of the blocking layer 132 , the charge storage layer 133 , and the tunnel insulation layer 134 may be located at a lower level than a lower end of the gate electrode 124 .
- a channel protective film 137 may be formed between a portion of the protrusion 115 of the second source film 114 and the information storage pattern 131 .
- the channel protective film 137 may be formed below the blocking layer 132 and the charge storage layer 133 .
- the channel protective film 137 may include an insulating material identical to the tunnel insulation layer 134 .
- the channel protective film 137 may include silicon oxynitride.
- the channel protective film 137 may include an insulating material having an etch selectivity with respect to the tunnel insulation layer 134 .
- the channel protective film 137 may fill a space, which is generated between the charge storage layer 133 and the insulating layer 122 as a result of the blocking layer 132 being over-etched.
- the channel protective film 137 may be formed at a lower end of the information storage pattern 131 and may cause the etching of the information storage pattern 131 to be uniform.
- the channel protective film 137 may be formed as two or more layers in some embodiments of the invention.
- a lower end of the channel protective film 137 may be located at the same level as an upper end of the first source film 112 , or may be located at a lower level than the upper end of the first source film 112 .
- the tunnel insulation layer 134 may be located at the same level as the upper end of the first source film 112 , or may be located at a lower level than the upper end of the first source film 112 .
- the lower end of the channel protective film 137 may be located at a low position at which a distance from the upper end of the first source film 112 is 150 A or less.
- the lower end of the channel protective film 137 When the lower end of the channel protective film 137 is located at a higher level than the upper end of the first source film 112 , particularly at a higher level than an upper end of the insulating layer 122 , a problem may occur with the on/off control of the gate electrode 124 due to the influence with the second source film 114 .
- the lower end of the channel protective film 137 when the lower end of the channel protective film 137 is located at a lower level at which a distance from the upper end of the first source film 112 is 150 ⁇ or more, a contact area between the channel pattern 135 and the second source film 114 may be reduced and thus channel resistance therebetween may be increased. Furthermore, it may be difficult to form holes during a memory erase operation.
- FIGS. 4 to 8 are highlighted (i.e., enlarged) views of a region E according to other embodiments of the invention and correspond to the region E of FIG. 3 .
- a channel protective film 237 may be formed below the blocking layer 132 and the charge storage layer 133 .
- the channel protective film 237 may be formed to protrude upward from a lower portion of the charge storage layer 133 in the first direction D 1 .
- a lower end of the charge storage layer 133 may be located at a higher level than lower ends of the blocking layer 132 and the tunnel insulation layer 134 .
- the channel protective film 237 is formed at the lower end of the information storage pattern 131 so that it is possible to control the etching of the information storage pattern 131 to be uniform.
- a lower end of a channel protective film 337 may include a convex portion 337 a which is convex upward.
- An upper end of the convex portion 337 a may be located at the same level as the upper end of the first source film 112 , or may be located at a lower level than the upper end of the first source film 112 .
- the upper and lower ends of the convex portion 337 a may be located at a low position at which a distance from the upper end of the first source film 112 is 150 A or less.
- a channel protective film 437 may be formed below the blocking layer 132 , the charge storage layer 133 , and the tunnel insulation layer 134 .
- the channel protective film 437 may be formed to protrude upward from a lower portion of the blocking layer 132 in the first direction D 1 .
- the lower end of the blocking layer 132 may be located at a higher level than the lower ends of the charge storage layer 133 and the tunnel insulation layer 134 .
- a lower end of the channel protective film 437 may be located at the same level as the upper end of the first source film 112 , or may be located at a lower level than the upper end of the first source film 112 .
- the channel protective film 437 may include silicon oxide.
- a channel protective film 537 may be formed below the blocking layer 132 .
- the lower end of the blocking layer 132 may be located at a higher level than the lower ends of the charge storage layer 133 and the tunnel insulation layer 134 .
- the channel protective film 537 may include silicon nitride (e.g., Si3N4).
- a channel oxide film 114 a is shown as another embodiment of the channel protective film 137 .
- the channel oxide film 114 a may be formed below the blocking layer 132 .
- An upper end of the channel oxide film 114 a may be located at a higher level than the upper end of the first source film 112 .
- the upper end of the channel oxide film 114 a may be located at the same level as the upper end of the insulating layer 122 , or may be located at a higher level than the upper end of the insulating layer 122 .
- the channel oxide film 114 a may include silicon oxide.
- the channel oxide film 114 a may be formed without a process of depositing the channel protective film 137 .
- the channel oxide film 114 a may be formed using a wet oxidation process after the second source film 114 is formed.
- a lower end of the channel oxide film 114 a may be located at the same level as the upper end of the first source film 112 , or may be located at a lower level than the upper end of the first source film 112 .
- FIGS. 9 to 15, 16A, 16B, and 17 to 23 are cross-sectional views, which are taken along line I-I′ of FIG. 1 and shown in accordance with a process sequence for describing a method of manufacturing a cell region 100 according to an embodiment of the present inventive concept.
- FIG. 16B is an enlarged view of a region E shown in FIG. 16A .
- an upper stacked structure 120 may be formed on a lower stacked structure 110 .
- the lower stacked structure 110 may include a substrate 102 .
- a first source film 112 , a sacrificial film 116 , and source insulating films 118 may be formed on the substrate 102 .
- the substrate 102 may include a silicon wafer, a silicon-on-insulator (SOI) substrate, a silicon monocrystalline film formed on an insulating film, or polysilicon region formed on an insulating film, for example.
- the substrate 102 may include a P-type impurity such as boron (B).
- the substrate 102 may be disposed on a peripheral region 160 .
- the substrate 102 may be formed by depositing a polysilicon film doped with a P-type impurity on the peripheral region 160 , or may be formed by depositing a polysilicon film/layer on the peripheral region 160 and then doping it with a P-type impurity.
- the first source film 112 may be formed on the sacrificial film 116 , and the source insulating films 118 may be formed above and below the sacrificial film 116 .
- the first source film 112 may include polysilicon and may include an N-type impurity.
- the sacrificial film 116 and the source insulating films 118 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.
- the sacrificial film 116 may include silicon nitride and the source insulating films 118 may include silicon oxide.
- the upper stacked structure 120 may be formed on the first source film 112 .
- the upper stacked structure 120 may be formed by insulating layers 122 and sacrificial layers 126 being alternately stacked, as shown.
- the insulating layer 122 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, for example.
- the sacrificial layer 126 may include an insulating material having an etch selectivity with respect to the insulating layer 122 .
- the insulating layer 122 may include silicon oxide and the sacrificial layer 126 may include silicon nitride.
- An interlayer dielectric 151 may be formed on the upper stacked structure 120 .
- the interlayer dielectric 151 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.
- channel holes CHH may be formed to pass through the upper stacked structure 120 , the first source film 112 , the sacrificial film 116 , and the source insulating films 118 .
- the channel holes CHH may have a cylindrical shape which extends downward in the first direction D 1 .
- the channel holes CHH may have a conical shape or a truncated conical shape of which a diameter decreases toward the substrate 102 .
- the channel holes CHH may be formed using an anisotropic etching process, such as a deep reactive-ion etching (DRIE) process.
- DRIE deep reactive-ion etching
- a channel structure 130 and a conductive pad 150 may be formed in the channel hole CHH.
- the channel structure 130 may include an information storage pattern 131 , a channel pattern 135 , and a core pattern 136 which are sequentially formed from the outside of the channel hole CHH toward the inside thereof.
- the information storage pattern 131 may include a blocking layer 132 , a charge storage layer 133 , and a tunnel insulation layer 134 which are sequentially formed from the outside of the channel hole CHH toward the inside thereof.
- the channel structure 130 may be formed by filling a space, which remains after the information storage pattern 131 and the channel pattern 135 are sequentially formed in the channel hole CHH, with the core pattern 136 .
- the information storage pattern 131 and the channel pattern 135 may be formed using a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, an atomic layer deposition (ALD) method, or a similar method.
- CVD chemical vapor deposition
- PVD physical vapor deposition
- ALD atomic layer deposition
- the blocking layer 132 , the charge storage layer 133 , and the tunnel insulation layer 134 may include an electrically insulating material.
- the blocking layer 132 may include silicon oxide and the charge storage layer 133 may include silicon nitride.
- the tunnel insulation layer 134 may include silicon oxynitride.
- the channel pattern 135 may include polysilicon, and the core pattern 136 may include an electrically insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a high-K material, for example.
- the conductive pad 150 may be formed on the channel structure 130 . After a thin film is formed on the interlayer dielectric 151 and the channel structure 130 , the conductive pad 150 may be formed using a planarization process, such as a chemical mechanical polishing (CMP) process and/or an etch-back process.
- CMP chemical mechanical polishing
- the conductive pad 150 may include a conductive material such as polysilicon, a metal, a metal silicide, or a combination thereof.
- a dummy channel structure 138 may be formed with the same method as the channel structure 130 .
- the word line cuts WLC may be formed by etching the upper stacked structure 120 .
- the word line cuts WLC may extend in the third direction D 3 .
- the word line cuts WLC may be formed using an anisotropic etching, method.
- the upper stacked structure 120 may be etched using an RIE (e.g., deep reactive ion etching (DRIE)) process.
- DRIE deep reactive ion etching
- the first source film 112 may be used as an etch stop film.
- the first source film 112 may be removed along the word line cuts WLC.
- the source insulating film 118 may be used as an etch stop film.
- a poly spacer 146 may be formed on side surfaces of the insulating layers 122 and the sacrificial layers 126 of the upper stacked structure 120 , which are exposed by the word line cuts WLC, and on the source insulating films 118 , as shown by FIG. 14 .
- the poly spacer 146 may be formed on the interlayer dielectric 151 . The poly spacer 146 may protect the insulating layer 122 and the sacrificial layer 126 from being damaged in a process of forming a second source film 114 to be described below.
- the poly spacer 146 formed on the source insulating film 118 along the word line cuts WLC may be removed.
- the poly spacer 146 may be removed using an anisotropic etching process.
- the poly spacer 146 may be etched using an RIE process.
- the sacrificial film 116 and the source insulating film 118 which is disposed on the substrate 102 may be exposed by removing the source insulating film 118 which is disposed on the sacrificial film 116 .
- a photomask may be used for etching the source insulating film 118 and the sacrificial film 116 .
- FIG. 16A is a cross-sectional view for describing the process of removing the sacrificial film 116
- FIG. 16B is an enlarged view of the region E shown in FIG. 16A
- the exposed sacrificial film 116 may be removed and an opening 119 may be formed between the source insulating films 118 .
- the sacrificial film 116 may be removed and thus the blocking layer 132 may be exposed.
- the sacrificial film 116 may be removed using an isotropic etching process and selectively removed.
- the source insulating films 118 and blocking layer 132 having an etch selectivity with respect to the sacrificial film 116 may not be damaged during the process of removing the sacrificial film 116 .
- FIGS. 17 to 20 are partially enlarged views of the region E for describing a method of forming a channel opening OP and the second source film 114 .
- a portion of the blocking layer 132 and the source insulating films 118 may be removed.
- a lower end of the blocking layer 132 may be located at the same level as an upper end of the first source film 112 , or may be located at a lower level than the upper end of the first source film 112 .
- the blocking layer 132 may be partially removed so that the channel opening OP may be formed below the information storage pattern 131 in the first direction D 1 .
- a portion of the charge storage layer 133 may be removed.
- the blocking layer 132 and tunnel insulation layer 134 having an etch selectivity with respect to the charge storage layer 133 may not be damaged.
- a lower end of the charge storage layer 133 may be located at the same level as the lower end of the blocking layer 132 .
- a channel protective layer 137 a may be formed on surfaces of the substrate 102 , the first source film 112 , the blocking layer 132 , the charge storage layer 133 , and the tunnel insulation layer 134 , which are exposed by the opening 119 and the channel opening OP.
- the channel protective layer 137 a may completely fill the channel opening OP.
- the channel protective layer 137 a may include an insulating material identical to the tunnel insulation layer 134 .
- the channel protective layer 137 a may include silicon oxide.
- the channel protective layer 137 a formed in the opening 119 and a portion of the channel protective layer 137 a formed in the channel opening OP may be removed, and a channel protective film 137 may be formed.
- the channel opening OP may be formed outside the channel pattern 135 to extend in the first direction D 1 .
- the channel opening OP may be located at the same level as the information storage pattern 131 in a second direction D 2 .
- the channel opening OP may expose the channel pattern 135 , and may be filled with a portion of the second source film 114 .
- the channel protective film 137 may be located at both ends of the channel opening OP.
- the information storage pattern 131 may be composed of the blocking layer 132 , the charge storage layer 133 , and the tunnel insulation layer 134 which are different layers, it may be difficult to control a depth of an etched surface of the information storage pattern 131 to be constant when the information storage pattern 131 is etched.
- the channel protective layer 137 a is formed in the channel opening OP, which is formed by removing portions of the blocking layer 132 and the charge storage layer 133 , and then is etched again, and thus it is possible to control the information storage pattern 131 composed of a multi-layer film to be uniformly etched.
- the second source film 114 may be formed in the opening 119 and the channel opening OP.
- the second source film 114 may be in contact with the channel pattern 135 .
- the second source film 114 may include a protrusion 115 which protrudes upward from a lower portion of the first source film 112 in the first direction D 1 .
- the protrusion 115 may be in contact with a side surface of the first source film 112 and the channel protective film 137 .
- the poly spacer 146 may be removed.
- a photomask may be used for removing the poly spacer 146 .
- the sacrificial layer 126 of the upper stacked structure 120 may be selectively removed.
- the sacrificial layer 126 may be removed using an isotropic etching process and openings 148 may be formed.
- the insulating layer 122 , first source film 112 , and second source film 114 having an etch selectivity with respect to the sacrificial layer 126 may not be damaged in the process of removing the sacrificial layer 126 .
- a gate electrode 124 may be formed in the opening 148 .
- the gate electrode 124 may include an electrically conductive material such as a metal, a metal oxide, a metal nitride, polysilicon, conductive carbon, or any combination thereof.
- the conductive material may include Ti, TiN, Ta, TaN, CoSi, NiSi, WSi, or a combination thereof.
- the conductive material formed above the interlayer dielectric 151 , and below the word line cuts WLC and at side portions of the word line cuts WLC may be removed using an anisotropic etching process or an isotropic etching process.
- a common source line 140 , a sidewall insulating film 142 , and an impurity region 144 may be formed in the word line cut WLC.
- the sidewall insulating film 142 may be formed on side surfaces of the insulating layers 122 and the gate electrodes 124 , which are exposed by the word line cut WLC after the gate electrodes 124 are formed.
- the sidewall insulating film 142 may electrically insulate the common source line 140 from the gate electrodes 124 .
- the impurity region 144 may be formed in a lower portion of the word line cut WLC.
- the impurity region 144 may be formed by implanting impurity ions into the lower portion of the word line cut WLC.
- the impurity region 144 may include an N-type impurity such as phosphorous (P) or arsenic (As).
- the common source line 140 may be formed along the word line cut WLC after the impurity region 144 is formed.
- the common source line 140 may include a conductive material such as polysilicon, a metal, a metal oxide, a metal nitride, a metal silicide, or a combination thereof.
- the common source line 140 may include an insulating material such as silicon oxide or silicon nitride.
- the string selection line cut SLC may be formed between the common source lines 140 .
- the string selection line cut SLC may be formed above the dummy channel structure 138 in the third direction D 3 .
- the string selection line cut SLC may divide at least one of the plurality of gate electrodes 124 .
- first bit plugs 153 , second bit plugs 155 , bit lines BL, sub bit lines SBL, and the string selection line cut SLC may be formed.
- insulating layers may be formed at the same level as each of the first bit plugs 153 , the second bit plugs 155 , and the sub bit lines SBL.
- the first bit plug 153 , the second bit plug 155 , the bit line BL, and the sub bit line SBL may include an electrically conductive material such as a metal, a metal silicide, a metal oxide, a metal nitride, polysilicon, conductive carbon, or a combination thereof.
- FIGS. 24 to 28 are enlarged views of the region E shown in accordance with a process sequence for describing the process of forming the channel protective film 437 shown in FIG. 6 .
- the source insulating films 118 formed in the opening 119 may be removed.
- the blocking layer 132 may be partially removed to form the channel opening OP.
- the charge storage layer 133 may be selectively removed. In the process of removing the charge storage layer 133 , the blocking layer 132 and the tunnel insulation layer 134 having an etch selectivity with respect to the charge storage layer 133 may not be damaged.
- the blocking layer 132 and the tunnel insulation layer 134 may be partially removed.
- the charge storage layer 133 having an etch selectivity with respect to the blocking layer 132 and the tunnel insulation layer 134 may not be damaged.
- the blocking layer 132 may be partially removed so that the lower end of the blocking layer 132 may be located at the same level as the upper end of the first source film 112 or may be located at a higher level than the upper end of the first source film 112 .
- the side surface of the insulating layer 122 or the sacrificial layer 126 may be exposed by the removed portion of the blocking layer 132 .
- a channel protective layer 437 a may be formed on surfaces of the substrate 102 , the first source film 112 , the blocking layer 132 , the charge storage layer 133 , and the tunnel insulation layer 134 , which are exposed by the opening 119 and the channel opening OP.
- the channel protective layer 437 a may fill a space between the charge storage layer 133 and the insulating layer 122 or a space between the charge storage layer 133 and the sacrificial layer 126 .
- the channel protective layer 437 a may include silicon oxide.
- the channel protective layer 437 a formed in the opening 119 and a portion of the channel protective layer 437 a formed in the channel opening OP may be removed and the channel protective film 437 may be formed.
- a lower end of the channel protective film 437 may be located at the same level as the upper end of the first source film 112 , or may be located at a lower level than the upper end of the first source film 112 .
- the second source film 114 may be formed between the first source film 112 and the substrate 102 .
- the sacrificial layer 126 may be removed and the gate electrode 124 may be formed.
- the channel protective film 437 is formed, and thus even when the blocking layer 132 is excessively etched in comparison to the charge storage layer 133 and the tunnel insulation layer 134 , it is possible to control the etching of the information storage pattern 131 to be uniform.
- FIGS. 29 to 32 are enlarged views of the region E shown in accordance with a process sequence for describing the process of forming the channel protective film 537 shown in FIG. 7 .
- the source insulating films 118 formed in the opening 119 may be removed.
- the blocking layer 132 may be partially removed and the channel opening OP may be formed.
- a channel protective layer 537 a may be formed on surfaces of the substrate 102 , the first source film 112 , the blocking layer 132 , and the charge storage layer 133 , which are exposed by the opening 119 and the channel opening OP.
- the channel protective layer 537 a may include an insulating material having an etch selectivity with respect to the tunnel insulation layer 134 .
- the channel protective layer 537 a may include silicon nitride.
- portions of the charge storage layer 133 and the channel protective layer 537 a may be removed.
- the channel protective layer 537 a may be etched and the channel protective film 537 may be formed.
- the tunnel insulation layer 134 having an etch selectivity with respect to the charge storage layer 133 and the channel protective film 537 may not be damaged.
- the channel protective film 537 located at a lower end of the blocking layer 132 may remain without being completely removed.
- a portion of the tunnel insulation layer 134 may be removed.
- the charge storage layer 133 and the channel protective film 537 having an etch selectivity with respect to the tunnel insulation layer 134 may not be damaged.
- the second source film 114 may be formed between the first source film 112 and the substrate 102 .
- the sacrificial layer 126 may be removed and the gate electrode 124 may be formed.
- the channel protective film 537 having an etch selectivity with respect to the tunnel insulation layer 134 may be formed, and thus damage on the blocking layer 132 may be prevented during the process of etching the tunnel insulation layer 134 . Since the blocking layer 132 is not removed, the gate electrode 124 may not be exposed during the etching process. The malfunction of the gate electrode 124 may be prevented due to the above-described processes.
- FIGS. 33 to 35 are enlarged views of the region E shown in accordance with a process sequence for describing the process of forming the channel oxide film 114 a shown in FIG. 8 .
- the information storage pattern 131 shown in FIG. 33 may be formed by performing the same processes as those in FIGS. 24 and 25 .
- the tunnel insulation layer 134 may be exposed by sequentially removing portions of the blocking layer 132 and the charge storage layer 133 .
- the blocking layer 132 may be excessively etched during the process of etching the blocking layer 132 and the tunnel insulation layer 134 , and thus the side surface of the insulating layer 122 or the sacrificial layer 126 may be exposed.
- the second source film 114 may be formed between the first source film 112 and the substrate 102 . The second source film 114 may fill the opening OP so that the side surface of the insulating layer 122 or the sacrificial layer 126 is not exposed
- the poly spacer 146 and the sacrificial layer 126 may be removed and the opening 148 may be formed.
- a portion of the second source film 114 may be oxidized by the opening 148 and the channel oxide film 114 a may be formed.
- the channel oxide film 114 a may be formed by wet oxidation.
- a channel protective film can be formed during a process of etching a side surface of a channel structure, and thus it is possible to control the etching of an information storage pattern having different triple films to be uniform.
- a contact area between a channel pattern and a second source film is increased, and thus channel resistance therebetween can be reduced and a stable cell driving current can be ensured.
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Abstract
Description
- This U.S. non-provisional patent application claims priority, under 35 U.S.C. § 119, to Korean Patent Application No. 10-2018-0031251, filed Mar. 19, 2018, the disclosure of which is hereby incorporated herein by reference in its entirety.
- The present inventive concept relates to memory devices and, more particularly, to vertical memory devices, such as vertical nonvolatile memory devices.
- Non-volatile memory devices including memory cells arranged in three dimensions have been proposed for high integration and reduction in the weight, width, length, and size of electronic products. When memory cells are formed, a channel structure passing through a stacked structure is required and a channel pattern of the channel structure needs to be in electrical contact with a substrate. In order to electrically connect the channel pattern of the channel structure to the substrate, a selective epitaxial growth (SEG) process can be used after a lower portion of the channel structure is etched. However, as the number of stacked memory cells increases, the SEG process may become exceptionally complex. Therefore, there have been attempts to use a technique in which an opening is formed in a side surface of a channel structure.
- The present inventive concept is directed to providing a memory device having a channel protective film therein, which enables an etched surface of an information storage pattern to be controlled to be uniform when an opening is formed in a side surface of a channel structure.
- In addition, the present inventive concept is directed to providing a memory device for preventing a problem of over-etching of an information storage pattern when an opening is formed in a side surface of a channel structure.
- Further, the present inventive concept is directed to providing a method of manufacturing a memory device which controls the etching of an information storage pattern to be uniform when an opening is formed in a side surface of a channel structure.
- A memory device according to an embodiment of the present inventive concept includes a lower stacked structure formed on a substrate and including a first source film and a second source film disposed below the first source film, an upper stacked structure disposed on the lower stacked structure, and a channel structure passing through the upper stacked structure and the first source film and including a channel pattern configured to extend downward and an information storage pattern disposed outside the channel pattern. The second source film is formed below the information storage pattern and is in contact with the channel pattern. The second source film includes a protrusion configured to extend upward, and a channel protective film is disposed on at least a portion between the protrusion and the information storage pattern.
- A method of manufacturing a memory device according to an embodiment of the present inventive concept includes: forming a lower stacked structure including a first source film on a substrate, forming an upper stacked structure, in which an insulating layer and a sacrificial layer are alternately disposed, on the lower stacked structure, forming a channel structure passing through the upper stacked structure and the first source film and including a channel pattern and an information storage pattern, forming a word line cut passing through the first source film and configured to expose side surfaces of the insulating layer and the sacrificial layer, etching a portion of the information storage pattern through the word line cut, forming a channel protective film on a portion in which the information storage pattern is removed, exposing the channel pattern by etching a portion of the channel protective film, and forming a second source film in contact with the first source film and the channel pattern.
- A memory device according to an embodiment of the present inventive concept includes a lower stacked structure formed on a substrate and including a first source film and a second source film disposed below the first source film, an upper stacked structure disposed on the lower stacked structure, and a channel structure passing through the upper stacked structure and the first source film and including a channel pattern configured to extend downward and an information storage pattern disposed outside the channel pattern. The second source film is formed below the information storage pattern and is in contact with the channel pattern. The second source film includes a protrusion configured to extend upward. A channel protective film is disposed between the protrusion and the information storage pattern. The channel protective film may be formed below a blocking layer and a charge storage layer of the information storage pattern, and a lower end of the channel protective film may be located at the same level as a lower end of a tunnel insulation layer of the information storage pattern. An upper end of the protrusion may be located at a lower level than an upper end of the first source film.
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FIG. 1 is a schematic layout of some regions of a semiconductor device according to an embodiment of the present inventive concept. -
FIG. 2 is a vertical sectional view taken along line I-I′ ofFIG. 1 . -
FIG. 3 is an enlarged view of a region E shown inFIG. 2 . -
FIGS. 4 to 8 are enlarged views of a region E according to other embodiments of the inventive concept, which correspond to the region E ofFIG. 3 . -
FIGS. 9 to 15, 16A, 16B, and 17 to 23 are cross-sectional views shown in accordance with a process sequence for describing a method of manufacturing a cell region according to an embodiment of the present inventive concept. -
FIGS. 24 to 28 are enlarged views of a region E shown in accordance with a process sequence for describing a process of forming a channel protective film shown inFIG. 6 . -
FIGS. 29 to 32 are enlarged views of a region E shown in accordance with a process sequence for describing a process of forming a channel protective film shown inFIG. 7 . -
FIGS. 33 to 35 are enlarged views of a region E shown in accordance with a process sequence for describing a process of forming a channel oxide film shown inFIG. 8 . - The present invention now will be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.
- It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components and/or regions, these elements, components and/or regions should not be limited by these terms. These terms are only used to distinguish one element, component and/or region from another element, component and/or region. Thus, a first element, component and/or region discussed below could be termed a second element, component and/or region without departing from the teachings of the present invention.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising”, “including”, “having” and variants thereof, when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. In contrast, the term “consisting of” when used in this specification, specifies the stated features, steps, operations, elements, and/or components, and precludes additional features, steps, operations, elements and/or components.
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FIG. 1 is a schematic layout view of a semiconductor memory device according to an embodiment of the present inventive concept, andFIG. 2 is a cross-sectional view of the semiconductor device ofFIG. 1 taken along line I-I′ ofFIG. 1 . A memory device according to embodiments of the present inventive concept may include flash memory such as a VNAND (vertical NAND) or a 3D-NAND. - Referring to
FIGS. 1 and 2 , the memory device according to the embodiment of the present inventive concept may include acell region 100 and aperipheral region 160. The memory device may have a cell-on-peripheral (COP) structure in which acell region 100 is formed on aperipheral region 160, as illustrated byFIG. 2 . Thecell region 100 may include a lowerstacked structure 110 including asubstrate 102, an upperstacked structure 120, bit lines BL, and word line cuts WLC. - Hereinafter, a first direction D1 may refer to a direction in which the
cell region 100 and theperipheral region 160 are stacked. For example, the first direction D1 may refer to a direction perpendicular to a main surface of thesubstrate 102. A second direction D2 may refer to a direction which is perpendicular to the first direction D1 and parallel to the bit lines BL. A third direction D3 may refer to a direction which is perpendicular to the first direction D1 and the second direction D2 and parallel to the word line cuts WLC. - The lower stacked
structure 110 may include thesubstrate 102, afirst source film 112, and asecond source film 114. Thefirst source film 112 and thesecond source film 114 may be formed on thesubstrate 102. Thesecond source film 114 may be formed below thefirst source film 112, and at least a portion of thesecond source film 114 may be in contact with a side surface of thefirst source film 112. Thesubstrate 102 may be polysilicon containing a P-type impurity, and thefirst source film 112 and thesecond source film 114 may be polysilicon containing an N-type impurity. -
Insulating layers 122 andgate electrodes 124 may be alternately stacked within the upper stackedstructure 120, as illustrated byFIG. 2 . Theinsulating layers 122 may electrically insulate thegate electrodes 124. Some of thegate electrodes 124 formed at a lower portion of the upper stackedstructure 120 may be configured as ground selection lines GSL. Some of thegate electrodes 124 formed at an upper portion of the upper stackedstructure 120 may be string selection lines SSL or drain selection lines DSL. In some embodiments of the invention, an insulating film which surrounds eachgate electrode 124 may be formed between the insulating layers 122. - The memory device may include channel holes CHH, which pass through the upper
stacked structure 120 and thefirst source film 112 and extend downward in the first direction D1. Four or five channel holes CHH, for example, may be formed between thecommon source lines 140 in the second direction D2. Achannel structure 130 may be formed inside each channel hole CHH. Thechannel structure 130 may include aninformation storage pattern 131, achannel pattern 135, and acore pattern 136 which are sequentially formed from the outside of the channel hole CHH toward the inside thereof. - The word line cut WLC disposed adjacent to the
channel structure 130 may be formed in the memory device. The word line cut WLC may pass through the upperstacked structure 120 and thefirst source film 112 in the first direction D1 and extend in the third direction D3. Thecommon source line 140, asidewall insulating film 142, and animpurity region 144 may be formed along the word line cut WLC. Thesidewall insulating film 142 may be formed on a side surface of the word line cut WLC, and theimpurity region 144 may be formed on a lower portion of the word line cut WLC. - A string selection line cut SLC may be formed between the common source lines 140. The string selection line cut SLC may be formed above a
dummy channel structure 138 in the third direction D3. The string selection line cut SLC may divide at least one of the plurality ofgate electrodes 124. For example, the string selection line cut SLC may divide the string selection line SSL. Thedummy channel structure 138 may not be electrically connected to the bit line BL. -
Conductive pads 150 may be formed on the upperstacked structure 120, and may be located at the same level as aninterlayer dielectric 151. Theconductive pad 150 may be formed on thechannel structure 130 in each channel hole CHH. Theconductive pad 150 may be in contact with thechannel pattern 135. Theconductive pad 150 may be connected to a sub bit line SBL through afirst bit plug 153, and the sub bit line SBL may be connected to the bit line BL through asecond bit plug 155. Although not shown, insulating layers located at the same level may be formed on thefirst bit plug 153, thesecond bit plug 155, and the sub bit line SBL. Here, the “level” may refer to a height from thesubstrate 102 in the first direction D1. - The
peripheral region 160 may be formed below thecell region 100. Theperipheral region 160 may include alower substrate 162 and a lower insulatinglayer 164 formed on thelower substrate 162.Peripheral transistors 170 may be formed in theperipheral region 160. Theperipheral transistor 170 may include a peripheralgate insulating film 171, aperipheral gate electrode 172, and a source/drain region 173. Theperipheral transistor 170 may be connected to aninterconnection pattern 175 through acontact plug 174, and theperipheral transistor 170 and theinterconnection pattern 175 may constitute a peripheral circuit. The lowerinsulating layer 164 may be formed to cover theperipheral transistor 170 and theinterconnection pattern 175. -
FIG. 3 is an enlarged view of region E shown inFIG. 2 . Referring toFIG. 3 , thesecond source film 114 may be formed between thefirst source film 112 and thesubstrate 102. Thesecond source film 114 may be in contact with thechannel pattern 135. In an embodiment of the invention, thesecond source film 114 may include aprotrusion 115 which extends upward in the first direction D1. - The
information storage pattern 131 may be formed outside thechannel pattern 135. Theinformation storage pattern 131 may include ablocking layer 132, acharge storage layer 133, and atunnel insulation layer 134, which are sequentially formed from the outside of the channel hole CHH toward the inside thereof. Theinformation storage pattern 131 may be partially disconnected in the first direction D1. Lower ends of theblocking layer 132, thecharge storage layer 133, and thetunnel insulation layer 134 may be located at a lower level than a lower end of thegate electrode 124. - A channel
protective film 137 may be formed between a portion of theprotrusion 115 of thesecond source film 114 and theinformation storage pattern 131. For example, the channelprotective film 137 may be formed below theblocking layer 132 and thecharge storage layer 133. The channelprotective film 137 may include an insulating material identical to thetunnel insulation layer 134. For example, the channelprotective film 137 may include silicon oxynitride. In an embodiment of the invention, the channelprotective film 137 may include an insulating material having an etch selectivity with respect to thetunnel insulation layer 134. The channelprotective film 137 may fill a space, which is generated between thecharge storage layer 133 and the insulatinglayer 122 as a result of theblocking layer 132 being over-etched. The channelprotective film 137 may be formed at a lower end of theinformation storage pattern 131 and may cause the etching of theinformation storage pattern 131 to be uniform. The channelprotective film 137 may be formed as two or more layers in some embodiments of the invention. - A lower end of the channel
protective film 137 may be located at the same level as an upper end of thefirst source film 112, or may be located at a lower level than the upper end of thefirst source film 112. Also, thetunnel insulation layer 134 may be located at the same level as the upper end of thefirst source film 112, or may be located at a lower level than the upper end of thefirst source film 112. For example, the lower end of the channelprotective film 137 may be located at a low position at which a distance from the upper end of thefirst source film 112 is 150A or less. When the lower end of the channelprotective film 137 is located at a higher level than the upper end of thefirst source film 112, particularly at a higher level than an upper end of the insulatinglayer 122, a problem may occur with the on/off control of thegate electrode 124 due to the influence with thesecond source film 114. Alternatively, when the lower end of the channelprotective film 137 is located at a lower level at which a distance from the upper end of thefirst source film 112 is 150 Å or more, a contact area between thechannel pattern 135 and thesecond source film 114 may be reduced and thus channel resistance therebetween may be increased. Furthermore, it may be difficult to form holes during a memory erase operation. -
FIGS. 4 to 8 are highlighted (i.e., enlarged) views of a region E according to other embodiments of the invention and correspond to the region E ofFIG. 3 . Referring toFIG. 4 , a channelprotective film 237 may be formed below theblocking layer 132 and thecharge storage layer 133. The channelprotective film 237 may be formed to protrude upward from a lower portion of thecharge storage layer 133 in the first direction D1. A lower end of thecharge storage layer 133 may be located at a higher level than lower ends of theblocking layer 132 and thetunnel insulation layer 134. As shown inFIG. 4 , even when the partially etched lower end of theinformation storage pattern 131 is not uniform, the channelprotective film 237 is formed at the lower end of theinformation storage pattern 131 so that it is possible to control the etching of theinformation storage pattern 131 to be uniform. - Referring to
FIG. 5 , a lower end of a channelprotective film 337 may include aconvex portion 337 a which is convex upward. An upper end of theconvex portion 337 a may be located at the same level as the upper end of thefirst source film 112, or may be located at a lower level than the upper end of thefirst source film 112. The upper and lower ends of theconvex portion 337 a may be located at a low position at which a distance from the upper end of thefirst source film 112 is 150A or less. - Referring to
FIG. 6 , a channelprotective film 437 may be formed below theblocking layer 132, thecharge storage layer 133, and thetunnel insulation layer 134. The channelprotective film 437 may be formed to protrude upward from a lower portion of theblocking layer 132 in the first direction D1. The lower end of theblocking layer 132 may be located at a higher level than the lower ends of thecharge storage layer 133 and thetunnel insulation layer 134. A lower end of the channelprotective film 437 may be located at the same level as the upper end of thefirst source film 112, or may be located at a lower level than the upper end of thefirst source film 112. The channelprotective film 437 may include silicon oxide. - Referring to
FIG. 7 , a channelprotective film 537 may be formed below theblocking layer 132. The lower end of theblocking layer 132 may be located at a higher level than the lower ends of thecharge storage layer 133 and thetunnel insulation layer 134. The channelprotective film 537 may include silicon nitride (e.g., Si3N4). - Referring to
FIG. 8 , achannel oxide film 114 a is shown as another embodiment of the channelprotective film 137. Thechannel oxide film 114 a may be formed below theblocking layer 132. An upper end of thechannel oxide film 114 a may be located at a higher level than the upper end of thefirst source film 112. For example, the upper end of thechannel oxide film 114 a may be located at the same level as the upper end of the insulatinglayer 122, or may be located at a higher level than the upper end of the insulatinglayer 122. Thechannel oxide film 114 a may include silicon oxide. Thechannel oxide film 114 a may be formed without a process of depositing the channelprotective film 137. For example, thechannel oxide film 114 a may be formed using a wet oxidation process after thesecond source film 114 is formed. A lower end of thechannel oxide film 114 a may be located at the same level as the upper end of thefirst source film 112, or may be located at a lower level than the upper end of thefirst source film 112. -
FIGS. 9 to 15, 16A, 16B, and 17 to 23 are cross-sectional views, which are taken along line I-I′ ofFIG. 1 and shown in accordance with a process sequence for describing a method of manufacturing acell region 100 according to an embodiment of the present inventive concept.FIG. 16B is an enlarged view of a region E shown inFIG. 16A . - Referring to
FIG. 9 , an upperstacked structure 120 may be formed on a lowerstacked structure 110. The lowerstacked structure 110 may include asubstrate 102. Afirst source film 112, asacrificial film 116, and source insulatingfilms 118 may be formed on thesubstrate 102. Thesubstrate 102 may include a silicon wafer, a silicon-on-insulator (SOI) substrate, a silicon monocrystalline film formed on an insulating film, or polysilicon region formed on an insulating film, for example. Thesubstrate 102 may include a P-type impurity such as boron (B). In an embodiment, thesubstrate 102 may be disposed on aperipheral region 160. For example, thesubstrate 102 may be formed by depositing a polysilicon film doped with a P-type impurity on theperipheral region 160, or may be formed by depositing a polysilicon film/layer on theperipheral region 160 and then doping it with a P-type impurity. - The
first source film 112 may be formed on thesacrificial film 116, and thesource insulating films 118 may be formed above and below thesacrificial film 116. Thefirst source film 112 may include polysilicon and may include an N-type impurity. Thesacrificial film 116 and thesource insulating films 118 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an embodiment, thesacrificial film 116 may include silicon nitride and thesource insulating films 118 may include silicon oxide. - The upper
stacked structure 120 may be formed on thefirst source film 112. The upperstacked structure 120 may be formed by insulatinglayers 122 andsacrificial layers 126 being alternately stacked, as shown. The insulatinglayer 122 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, for example. Thesacrificial layer 126 may include an insulating material having an etch selectivity with respect to the insulatinglayer 122. For example, the insulatinglayer 122 may include silicon oxide and thesacrificial layer 126 may include silicon nitride. Aninterlayer dielectric 151 may be formed on the upperstacked structure 120. Theinterlayer dielectric 151 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. - Referring to
FIGS. 1 and 10 , channel holes CHH may be formed to pass through the upperstacked structure 120, thefirst source film 112, thesacrificial film 116, and thesource insulating films 118. The channel holes CHH may have a cylindrical shape which extends downward in the first direction D1. In an embodiment, the channel holes CHH may have a conical shape or a truncated conical shape of which a diameter decreases toward thesubstrate 102. The channel holes CHH may be formed using an anisotropic etching process, such as a deep reactive-ion etching (DRIE) process. - Referring to
FIG. 11 , achannel structure 130 and aconductive pad 150 may be formed in the channel hole CHH. Thechannel structure 130 may include aninformation storage pattern 131, achannel pattern 135, and acore pattern 136 which are sequentially formed from the outside of the channel hole CHH toward the inside thereof. Theinformation storage pattern 131 may include ablocking layer 132, acharge storage layer 133, and atunnel insulation layer 134 which are sequentially formed from the outside of the channel hole CHH toward the inside thereof. - The
channel structure 130 may be formed by filling a space, which remains after theinformation storage pattern 131 and thechannel pattern 135 are sequentially formed in the channel hole CHH, with thecore pattern 136. Theinformation storage pattern 131 and thechannel pattern 135 may be formed using a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, an atomic layer deposition (ALD) method, or a similar method. - The
blocking layer 132, thecharge storage layer 133, and thetunnel insulation layer 134 may include an electrically insulating material. For example, theblocking layer 132 may include silicon oxide and thecharge storage layer 133 may include silicon nitride. Thetunnel insulation layer 134 may include silicon oxynitride. - The
channel pattern 135 may include polysilicon, and thecore pattern 136 may include an electrically insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a high-K material, for example. Theconductive pad 150 may be formed on thechannel structure 130. After a thin film is formed on theinterlayer dielectric 151 and thechannel structure 130, theconductive pad 150 may be formed using a planarization process, such as a chemical mechanical polishing (CMP) process and/or an etch-back process. Theconductive pad 150 may include a conductive material such as polysilicon, a metal, a metal silicide, or a combination thereof. Adummy channel structure 138 may be formed with the same method as thechannel structure 130. - Referring to
FIGS. 1 and 12 , the word line cuts WLC may be formed by etching the upperstacked structure 120. The word line cuts WLC may extend in the third direction D3. The word line cuts WLC may be formed using an anisotropic etching, method. For example, the upperstacked structure 120 may be etched using an RIE (e.g., deep reactive ion etching (DRIE)) process. In the etching of the upperstacked structure 120, thefirst source film 112 may be used as an etch stop film. - Referring to
FIGS. 13-14 , thefirst source film 112 may be removed along the word line cuts WLC. In the removal of thefirst source film 112, thesource insulating film 118 may be used as an etch stop film. Then, apoly spacer 146 may be formed on side surfaces of the insulatinglayers 122 and thesacrificial layers 126 of the upperstacked structure 120, which are exposed by the word line cuts WLC, and on thesource insulating films 118, as shown byFIG. 14 . Further, thepoly spacer 146 may be formed on theinterlayer dielectric 151. Thepoly spacer 146 may protect the insulatinglayer 122 and thesacrificial layer 126 from being damaged in a process of forming asecond source film 114 to be described below. - Referring to
FIG. 15 , thepoly spacer 146 formed on thesource insulating film 118 along the word line cuts WLC may be removed. Thepoly spacer 146 may be removed using an anisotropic etching process. For example, thepoly spacer 146 may be etched using an RIE process. Next, thesacrificial film 116 and thesource insulating film 118 which is disposed on thesubstrate 102 may be exposed by removing thesource insulating film 118 which is disposed on thesacrificial film 116. Although not shown, a photomask may be used for etching thesource insulating film 118 and thesacrificial film 116. -
FIG. 16A is a cross-sectional view for describing the process of removing thesacrificial film 116, andFIG. 16B is an enlarged view of the region E shown inFIG. 16A . Referring toFIGS. 16A and 16B , the exposedsacrificial film 116 may be removed and anopening 119 may be formed between thesource insulating films 118. Further, thesacrificial film 116 may be removed and thus theblocking layer 132 may be exposed. Thesacrificial film 116 may be removed using an isotropic etching process and selectively removed. Thesource insulating films 118 and blockinglayer 132 having an etch selectivity with respect to thesacrificial film 116 may not be damaged during the process of removing thesacrificial film 116. -
FIGS. 17 to 20 are partially enlarged views of the region E for describing a method of forming a channel opening OP and thesecond source film 114. Referring toFIG. 17 , a portion of theblocking layer 132 and thesource insulating films 118 may be removed. A lower end of theblocking layer 132 may be located at the same level as an upper end of thefirst source film 112, or may be located at a lower level than the upper end of thefirst source film 112. Theblocking layer 132 may be partially removed so that the channel opening OP may be formed below theinformation storage pattern 131 in the first direction D1. - Referring to
FIG. 18 , a portion of thecharge storage layer 133 may be removed. In the process of removing thecharge storage layer 133, theblocking layer 132 andtunnel insulation layer 134 having an etch selectivity with respect to thecharge storage layer 133 may not be damaged. A lower end of thecharge storage layer 133 may be located at the same level as the lower end of theblocking layer 132. - Referring to
FIG. 19 , a channelprotective layer 137 a may be formed on surfaces of thesubstrate 102, thefirst source film 112, theblocking layer 132, thecharge storage layer 133, and thetunnel insulation layer 134, which are exposed by theopening 119 and the channel opening OP. In one embodiment of the inventive concept, the channelprotective layer 137 a may completely fill the channel opening OP. The channelprotective layer 137 a may include an insulating material identical to thetunnel insulation layer 134. For example, the channelprotective layer 137 a may include silicon oxide. - Referring to
FIG. 20 , the channelprotective layer 137 a formed in theopening 119 and a portion of the channelprotective layer 137 a formed in the channel opening OP may be removed, and a channelprotective film 137 may be formed. The channel opening OP may be formed outside thechannel pattern 135 to extend in the first direction D1. The channel opening OP may be located at the same level as theinformation storage pattern 131 in a second direction D2. The channel opening OP may expose thechannel pattern 135, and may be filled with a portion of thesecond source film 114. The channelprotective film 137 may be located at both ends of the channel opening OP. - Since the
information storage pattern 131 may be composed of theblocking layer 132, thecharge storage layer 133, and thetunnel insulation layer 134 which are different layers, it may be difficult to control a depth of an etched surface of theinformation storage pattern 131 to be constant when theinformation storage pattern 131 is etched. As shown inFIGS. 19 and 20 , the channelprotective layer 137 a is formed in the channel opening OP, which is formed by removing portions of theblocking layer 132 and thecharge storage layer 133, and then is etched again, and thus it is possible to control theinformation storage pattern 131 composed of a multi-layer film to be uniformly etched. - Referring now to
FIG. 21 , thesecond source film 114 may be formed in theopening 119 and the channel opening OP. Thesecond source film 114 may be in contact with thechannel pattern 135. Thesecond source film 114 may include aprotrusion 115 which protrudes upward from a lower portion of thefirst source film 112 in the first direction D1. Theprotrusion 115 may be in contact with a side surface of thefirst source film 112 and the channelprotective film 137. After thesecond source film 114 is formed, thepoly spacer 146 may be removed. Although not shown, a photomask may be used for removing thepoly spacer 146. - After the
poly spacer 146 is removed, thesacrificial layer 126 of the upperstacked structure 120 may be selectively removed. Thesacrificial layer 126 may be removed using an isotropic etching process andopenings 148 may be formed. The insulatinglayer 122,first source film 112, andsecond source film 114 having an etch selectivity with respect to thesacrificial layer 126 may not be damaged in the process of removing thesacrificial layer 126. - Referring to
FIG. 22 , agate electrode 124 may be formed in theopening 148. Thegate electrode 124 may include an electrically conductive material such as a metal, a metal oxide, a metal nitride, polysilicon, conductive carbon, or any combination thereof. For example, the conductive material may include Ti, TiN, Ta, TaN, CoSi, NiSi, WSi, or a combination thereof. Although not shown, the conductive material formed above theinterlayer dielectric 151, and below the word line cuts WLC and at side portions of the word line cuts WLC may be removed using an anisotropic etching process or an isotropic etching process. - A
common source line 140, asidewall insulating film 142, and animpurity region 144 may be formed in the word line cut WLC. Thesidewall insulating film 142 may be formed on side surfaces of the insulatinglayers 122 and thegate electrodes 124, which are exposed by the word line cut WLC after thegate electrodes 124 are formed. Thesidewall insulating film 142 may electrically insulate thecommon source line 140 from thegate electrodes 124. - The
impurity region 144 may be formed in a lower portion of the word line cut WLC. Theimpurity region 144 may be formed by implanting impurity ions into the lower portion of the word line cut WLC. In an embodiment, theimpurity region 144 may include an N-type impurity such as phosphorous (P) or arsenic (As). - The
common source line 140 may be formed along the word line cut WLC after theimpurity region 144 is formed. Thecommon source line 140 may include a conductive material such as polysilicon, a metal, a metal oxide, a metal nitride, a metal silicide, or a combination thereof. In another embodiment, thecommon source line 140 may include an insulating material such as silicon oxide or silicon nitride. - Referring to
FIGS. 1 and 23 , the string selection line cut SLC may be formed between the common source lines 140. The string selection line cut SLC may be formed above thedummy channel structure 138 in the third direction D3. The string selection line cut SLC may divide at least one of the plurality ofgate electrodes 124. As shown byFIG. 23 , first bit plugs 153, second bit plugs 155, bit lines BL, sub bit lines SBL, and the string selection line cut SLC may be formed. Although not shown, insulating layers may be formed at the same level as each of the first bit plugs 153, the second bit plugs 155, and the sub bit lines SBL. Thefirst bit plug 153, thesecond bit plug 155, the bit line BL, and the sub bit line SBL may include an electrically conductive material such as a metal, a metal silicide, a metal oxide, a metal nitride, polysilicon, conductive carbon, or a combination thereof. -
FIGS. 24 to 28 are enlarged views of the region E shown in accordance with a process sequence for describing the process of forming the channelprotective film 437 shown inFIG. 6 . Referring toFIGS. 16B and 24 , thesource insulating films 118 formed in theopening 119 may be removed. Theblocking layer 132 may be partially removed to form the channel opening OP. As shown byFIG. 25 , thecharge storage layer 133 may be selectively removed. In the process of removing thecharge storage layer 133, theblocking layer 132 and thetunnel insulation layer 134 having an etch selectivity with respect to thecharge storage layer 133 may not be damaged. - Referring to
FIG. 26 , theblocking layer 132 and thetunnel insulation layer 134 may be partially removed. Thecharge storage layer 133 having an etch selectivity with respect to theblocking layer 132 and thetunnel insulation layer 134 may not be damaged. Theblocking layer 132 may be partially removed so that the lower end of theblocking layer 132 may be located at the same level as the upper end of thefirst source film 112 or may be located at a higher level than the upper end of thefirst source film 112. In an embodiment, the side surface of the insulatinglayer 122 or thesacrificial layer 126 may be exposed by the removed portion of theblocking layer 132. - Referring to
FIG. 27 , a channelprotective layer 437 a may be formed on surfaces of thesubstrate 102, thefirst source film 112, theblocking layer 132, thecharge storage layer 133, and thetunnel insulation layer 134, which are exposed by theopening 119 and the channel opening OP. The channelprotective layer 437 a may fill a space between thecharge storage layer 133 and the insulatinglayer 122 or a space between thecharge storage layer 133 and thesacrificial layer 126. Using a process of depositing the channelprotective layer 437 a, the insulatinglayer 122 and thesacrificial layer 126 may be prevented from being exposed. In one embodiment of the inventive concept, the channelprotective layer 437 a may include silicon oxide. - Referring to
FIG. 28 , the channelprotective layer 437 a formed in theopening 119 and a portion of the channelprotective layer 437 a formed in the channel opening OP may be removed and the channelprotective film 437 may be formed. A lower end of the channelprotective film 437 may be located at the same level as the upper end of thefirst source film 112, or may be located at a lower level than the upper end of thefirst source film 112. - Referring to
FIGS. 6 and 28 , thesecond source film 114 may be formed between thefirst source film 112 and thesubstrate 102. In a subsequent process, thesacrificial layer 126 may be removed and thegate electrode 124 may be formed. - As shown in
FIGS. 24 to 28 , the channelprotective film 437 is formed, and thus even when theblocking layer 132 is excessively etched in comparison to thecharge storage layer 133 and thetunnel insulation layer 134, it is possible to control the etching of theinformation storage pattern 131 to be uniform. -
FIGS. 29 to 32 are enlarged views of the region E shown in accordance with a process sequence for describing the process of forming the channelprotective film 537 shown inFIG. 7 . Referring toFIGS. 16B and 29 , thesource insulating films 118 formed in theopening 119 may be removed. Theblocking layer 132 may be partially removed and the channel opening OP may be formed. Referring toFIG. 30 , a channelprotective layer 537 a may be formed on surfaces of thesubstrate 102, thefirst source film 112, theblocking layer 132, and thecharge storage layer 133, which are exposed by theopening 119 and the channel opening OP. The channelprotective layer 537 a may include an insulating material having an etch selectivity with respect to thetunnel insulation layer 134. For example, the channelprotective layer 537 a may include silicon nitride. - Referring to
FIG. 31 , portions of thecharge storage layer 133 and the channelprotective layer 537 a may be removed. The channelprotective layer 537 a may be etched and the channelprotective film 537 may be formed. Thetunnel insulation layer 134 having an etch selectivity with respect to thecharge storage layer 133 and the channelprotective film 537 may not be damaged. After the etching process, the channelprotective film 537 located at a lower end of theblocking layer 132 may remain without being completely removed. Referring toFIG. 32 , a portion of thetunnel insulation layer 134 may be removed. Thecharge storage layer 133 and the channelprotective film 537 having an etch selectivity with respect to thetunnel insulation layer 134 may not be damaged. Referring toFIGS. 7 and 32 , thesecond source film 114 may be formed between thefirst source film 112 and thesubstrate 102. In a subsequent process, thesacrificial layer 126 may be removed and thegate electrode 124 may be formed. - As shown in
FIGS. 29 to 32 , the channelprotective film 537 having an etch selectivity with respect to thetunnel insulation layer 134 may be formed, and thus damage on theblocking layer 132 may be prevented during the process of etching thetunnel insulation layer 134. Since theblocking layer 132 is not removed, thegate electrode 124 may not be exposed during the etching process. The malfunction of thegate electrode 124 may be prevented due to the above-described processes. -
FIGS. 33 to 35 are enlarged views of the region E shown in accordance with a process sequence for describing the process of forming thechannel oxide film 114 a shown inFIG. 8 . Theinformation storage pattern 131 shown inFIG. 33 may be formed by performing the same processes as those inFIGS. 24 and 25 . As shown inFIGS. 24 and 25 , thetunnel insulation layer 134 may be exposed by sequentially removing portions of theblocking layer 132 and thecharge storage layer 133. - Referring to
FIG. 33 , theblocking layer 132 may be excessively etched during the process of etching theblocking layer 132 and thetunnel insulation layer 134, and thus the side surface of the insulatinglayer 122 or thesacrificial layer 126 may be exposed. Referring toFIG. 34 , thesecond source film 114 may be formed between thefirst source film 112 and thesubstrate 102. Thesecond source film 114 may fill the opening OP so that the side surface of the insulatinglayer 122 or thesacrificial layer 126 is not exposed - As shown in
FIG. 21 , after thesecond source film 114 is formed, thepoly spacer 146 and thesacrificial layer 126 may be removed and theopening 148 may be formed. - Referring to
FIG. 8 , a portion of thesecond source film 114 may be oxidized by theopening 148 and thechannel oxide film 114 a may be formed. For example, thechannel oxide film 114 a may be formed by wet oxidation. By the processes shown inFIGS. 33 to 35 , it is possible to control the etching of theinformation storage pattern 131 to be uniform without depositing the channelprotective film 137. Further, by oxidizing thesecond source film 114 adjacent to thegate electrode 124 with thechannel oxide film 114 a, malfunction of thegate electrode 124 may be prevented. - According to at least some embodiments of the present inventive concept, a channel protective film can be formed during a process of etching a side surface of a channel structure, and thus it is possible to control the etching of an information storage pattern having different triple films to be uniform. According to at least some embodiments of the present inventive concept, a contact area between a channel pattern and a second source film is increased, and thus channel resistance therebetween can be reduced and a stable cell driving current can be ensured.
- While the embodiments of the present inventive concept have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the present inventive concept and without changing essential features thereof. Therefore, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation.
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CN110289267B (en) | 2023-10-17 |
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