US20190214458A1 - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
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- US20190214458A1 US20190214458A1 US15/893,715 US201815893715A US2019214458A1 US 20190214458 A1 US20190214458 A1 US 20190214458A1 US 201815893715 A US201815893715 A US 201815893715A US 2019214458 A1 US2019214458 A1 US 2019214458A1
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- ild layer
- trap rich
- layer
- rich structure
- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
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- 239000002184 metal Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 6
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910000951 Aluminide Inorganic materials 0.000 description 4
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- OQPDWFJSZHWILH-UHFFFAOYSA-N [Al].[Al].[Al].[Ti] Chemical compound [Al].[Al].[Al].[Ti] OQPDWFJSZHWILH-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
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- 229910021324 titanium aluminide Inorganic materials 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
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- 239000010936 titanium Substances 0.000 description 3
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- 229910015846 BaxSr1-xTiO3 Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910020696 PbZrxTi1−xO3 Inorganic materials 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- VNSWULZVUKFJHK-UHFFFAOYSA-N [Sr].[Bi] Chemical compound [Sr].[Bi] VNSWULZVUKFJHK-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- JPNWDVUTVSTKMV-UHFFFAOYSA-N cobalt tungsten Chemical compound [Co].[W] JPNWDVUTVSTKMV-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
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- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Definitions
- the invention relates to a method for fabricating semiconductor device, and more particularly, to a method of forming trap rich structure adjacent to metal-oxide semiconductor (MOS) transistor.
- MOS metal-oxide semiconductor
- RF radio frequency
- SOI semiconductor-on-insulator
- a method for fabricating semiconductor device includes: forming a metal-oxide semiconductor (MOS) transistor on a substrate; forming a first interlayer dielectric (ILD) layer on the MOS transistor; removing part of the first ILD layer to form a trench adjacent to the MOS transistor; forming a trap rich structure in the trench; forming a second ILD layer on the MOS transistor and the trap rich structure; forming a contact plug in the first ILD layer and the second ILD layer and electrically connected to the MOS transistor; and forming a metal interconnection on the second ILD layer and electrically connected to the contact plug.
- MOS metal-oxide semiconductor
- ILD interlayer dielectric
- a semiconductor device includes: a metal-oxide semiconductor (MOS) transistor on a substrate; a trap rich structure on the substrate and adjacent to the MOS transistor, wherein a bottom surface of the trap rich structure is even with a top surface of the substrate; and an interlayer dielectric (ILD) layer on the MOS transistor and the trap rich structure.
- MOS metal-oxide semiconductor
- ILD interlayer dielectric
- FIGS. 1-3 illustrate a method for fabricating semiconductor device according to an embodiment of the present invention.
- FIG. 4 illustrates a structural view of a semiconductor device according to an embodiment of the present invention.
- FIG. 5 illustrates a structural view of a semiconductor device according to an embodiment of the present invention.
- FIG. 6 illustrates a structural view of a semiconductor device according to an embodiment of the present invention.
- FIGS. 1-3 illustrate a method for fabricating semiconductor device according to an embodiment of the present invention.
- a substrate 12 such as a semiconductor substrate having high resistance or more specifically a silicon substrate having high resistance is first provided, a plurality of isolation structures such as deep trench isolation structures 14 preferably made of silicon oxide are formed in the substrate 12 , and MOS transistors such as MOS transistors 16 , 18 , 20 are formed on the substrate 12 between the deep trench isolation structures 14 .
- MOS transistors 16 , 18 , 20 having same conductive type are disposed on the substrate 12 in this embodiment, the number and conductive type of the MOS transistors 16 , 18 , 20 could all be adjusted depending on the demand of the process or product.
- the formation of the MOS transistors 16 , 18 , 20 could be accomplished by first forming a deep well and a well region in the substrate 12 , and then forming transistor elements such as but not limited to for example gate structures 22 and source/drain regions 24 on the substrate 12 .
- the conductive type of the deep well and the well region could be adjusted depending on the type of device being fabricated.
- the deep well in this embodiment preferably includes a deep n-well 26 while the well region preferably includes a p-well 28 , but not limited thereto.
- the formation of the gate structures 22 could be accomplished by a gate first process, a high-k first approach from gate last process, or a high-k last approach from gate last process. Since this embodiment pertains to a gate first approach, a gate dielectric layer 30 or interfacial layer, a gate material layer 32 made of polysilicon, and a selective hard mask could be formed sequentially on the substrate 12 , and a photo-etching process is then conducted by using a patterned resist (not shown) as mask to remove part of the gate material layer 32 and part of the gate dielectric layer 30 through single or multiple etching processes. After stripping the patterned resist, gate structures 22 each composed of a patterned gate dielectric layer 30 and a patterned material layer 32 are formed on the substrate 12 .
- the spacer 34 could be a single spacer or a composite spacer, such as a spacer including but not limited to for example an offset spacer and a main spacer.
- the offset spacer and the main spacer could include same material or different material while both the offset spacer and the main spacer could be made of material including but not limited to for example SiO 2 , SiN, SiON, SiCN, or combination thereof.
- the source/drain regions 24 could include n-type dopants or p-type dopants depending on the type of device being fabricated.
- the source/drain region 24 preferably includes n-type dopants in this embodiment, but not limited thereto.
- a selective contact etch stop layer (CESL) (not shown) could be formed on the gate structures 22 to cover the gate structures 22 , and a first interlayer dielectric (ILD) layer 36 is formed on the CESL.
- a pattern transfer process is conducted by using patterned mask (not shown) as mask to remove part of the first ILD layer 36 adjacent to the MOS transistor 20 for forming trench 38 exposing the surface of the substrate 12 , and then forming a trap rich structures 40 in the trench 38 .
- the formation of the trap rich structure 40 could be accomplished by first conducting a deposition such as chemical vapor deposition (CVD) process to form a dielectric layer 42 in the trench 38 and on the surface of the first ILD layer 36 .
- a deposition such as chemical vapor deposition (CVD) process to form a dielectric layer 42 in the trench 38 and on the surface of the first ILD layer 36 .
- the dielectric layer 42 is deposited to cover the top surface of the first ILD layer 36 , sidewalls of the first ILD layer 36 within the trench 38 , and the top surface of the substrate 12 in the bottom of the trench 38 without filling the trench 38 completely.
- CVD chemical vapor deposition
- a planarizing process such as chemical mechanical polishing (CMP) process is conducted to remove part of the part of the dielectric layer 42 on the top surface of the first ILD layer 36 so that the top surface of the remaining dielectric layer 42 is even with the top surface of the first ILD layer 36 , in which a cross-section of the remaining dielectric layer 42 includes a U-shaped profile.
- the dielectric layer 42 preferably includes doped polysilicon or silicon nitride, but not limited thereto.
- the bottom of the U-shaped trap rich structure 40 is even with the surface of the substrate 12 or the bottom of the gate structure 22 , it would also be desirable to adjust the depth of the trench 38 so that the bottom surface of the trench 38 could be slightly higher than the surface of the substrate 12 or lower than the surface of the substrate 12 , and the dielectric layer 42 is deposited in the trench 38 thereafter to form the trap rich structure 40 .
- the bottom surface of the U-shaped trap rich structure 40 could be slightly higher than the bottom surface of the adjacent gate structure 22 while the top surface of the trap rich structure 40 is even with the top surface of the first ILD layer 36 , or the bottom surface of the trap rich structure 40 could be slightly lower than the bottom surface of the gate structure 22 while the top surface of the trap rich structure 40 is even with the top surface of the first ILD layer 36 , which are all within the scope of the present invention.
- a second ILD layer 44 is formed on the first ILD layer 36 and covering the MOS transistors 16 , 18 , 20 , and the trap rich structure 40 , and contact plugs 46 are formed in the first ILD layer 36 and the second ILD layer 44 to electrically connect the MOS transistors, 16 , 18 , 20 .
- the first ILD layer 36 and the second ILD layer 44 preferably include same material, such as both being made of dielectric material including but not limited to for example silicon oxide.
- the formation of the contact plugs 46 could be accomplished by first conducting a patterned transfer or photo-etching process by using a patterned mask (not shown) as mask to remove part of the second ILD layer 44 and part of the first ILD layer 36 adjacent to the gate structures 22 for forming contact holes (not shown) exposing the source/drain regions 24 underneath.
- metals including a barrier layer selected from the group consisting of Ti, TiN, Ta, and TaN and a low resistance metal layer selected from the group consisting of W, Cu, Al, TiAl, and CoWP are deposited into the contact holes, and a planarizing process such as CMP is conducted to remove part of aforementioned barrier layer and low resistance metal layer for forming contact plugs 46 electrically connecting the source/drain regions 24 .
- inter-metal dielectric (IMD) layer (not shown) on the second ILD layer 44 and metal interconnections 48 connected to each of the contact plugs 46 .
- IMD inter-metal dielectric
- FIG. 3 further discloses a structural view of a semiconductor device according to an embodiment of the present invention.
- the semiconductor device includes at least a MOS transistor such as MOS transistors 16 , 18 , 20 on the substrate 12 , a trap rich structure 40 disposed on the substrate 12 and adjacent to the MOS transistors 16 , 18 , 20 , and an ILD layer 50 disposed on the MOS transistors 16 , 18 , 20 and the trap rich structure 40 .
- the ILD layer 50 further includes a first ILD layer 36 covering the MOS transistors 16 , 18 , 20 and a second ILD layer 44 disposed on the first ILD layer 36 while covering the MOS transistors 16 , 18 , 20 and the trap rich structure 40 at the same time.
- the bottom surface of the trap rich structure 40 is even with the top surface of the substrate 12
- the trap rich structure 40 includes a U-shaped cross-section
- the top surface of the trap rich structure 40 is even with the top surface of the first ILD layer 36
- the trap rich structure 40 is preferably made of dielectric material including but not limited to for example undoped polysilicon or silicon nitride.
- the semiconductor device further includes contact plug 46 disposed in the first ILD layer 36 and the second ILD 44 and electrically connected to the source/drain regions 24 of the MOS transistors 16 , 18 , 20 and metal interconnections 48 disposed on the second ILD layer 44 and electrically connected to the contact plugs 46 .
- at least one of the metal interconnection 48 is disposed directly on top of the trap rich structure 40 to cover or shield the trap rich structure 40 completely, in which the presence of the trap rich structure 40 could be used to shield noises generated between the metal interconnections 48 and the substrate 12 or other devices thereby improving the performance of the device.
- FIG. 4 illustrates a structural view of a semiconductor device according to an embodiment of the present invention.
- the trap rich structure 40 in contrast to the trap rich structure 40 having U-shaped cross-section as disclosed in the aforementioned embodiment, it would also be desirable to control the amount of dielectric layer 42 deposited into the trench 38 such as by filling the trench 38 with the dielectric layer 42 completely, and then conducting a planarizing process such as CMP to remove part of the dielectric layer 42 for forming a trap rich structure 40 , in which the top surface of the trap rich structure 40 or the remaining dielectric layer 42 is even with the top surface of the first ILD layer 36 .
- the trap rich structure 40 preferably includes a rectangular cross-section, which is also within the scope of the present invention.
- FIG. 5 illustrates a structural view of a semiconductor device according to an embodiment of the present invention.
- the formation of the trap rich structure 40 could also be accomplished by first forming a trench 60 in the first ILD layer 36 and then conducting an ion implantation process to implant non-conductive ions including but not limited to for example silicon, germanium, carbon, nitrogen, or combination thereof into the first ILD layer 36 around the trench 60 to form a doped region 62 or a trap rich structure 40 made of the doped region 62 .
- the present embodiment conducts an ion implantation process to form a doped region 62 outside the trench 60 to forma trap rich structure 40 made of the doped region 62 .
- the depth of the trench 60 it would also be desirable to adjust the depth of the trench 60 so that the bottom surface of the U-shaped trap rich structure 40 made of doped region 62 could be slightly higher than the bottom surface of the adjacent gate structure 22 while the top surface of the trap rich structure 40 is even with the top surface of the first ILD layer 36 , or the bottom surface of the trap rich structure 40 is slightly lower than the bottom surface of the gate structure 22 while the top surface of the trap rich structures is even with the top surface of the first ILD layer 36 , which are all within the scope of the present invention.
- FIG. 6 illustrates a method of transforming the gate structure 22 made of polysilicon from the aforementioned embodiment into a metal gate according to a high-k last process.
- a planarizing process such as CMP could be conducted to remove part of the first ILD layer 36 to expose the top surface of the gate material layer 32 made of polysilicon layer so that the top surface of the gate material layer 32 is even with the top surface of the first ILD layer 36 .
- a replacement metal gate (RMG) process is conducted to transform the gate structures 22 of the MOS transistors 16 , 18 , 20 into metal gates.
- the RMG process could be accomplished by first performing a selective dry etching or wet etching process using etchants including but not limited to for example ammonium hydroxide (NH 4 OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 32 and even gate dielectric layer 30 from each of the gate structures 22 for forming recesses (not shown) in the first ILD layer 36 .
- etchants including but not limited to for example ammonium hydroxide (NH 4 OH) or tetramethylammonium hydroxide (TMAH)
- each of the gate structures or metal gates fabricated through high-k last process of a gate last process preferably includes an interfacial layer 52 or gate dielectric layer (not shown), a U-shaped high-k dielectric layer 54 , a U-shaped work function metal layer 56 , and a low resistance metal layer 58 .
- the high-k dielectric layer 54 is preferably selected from dielectric materials having dielectric constant (k value) larger than 4.
- the high-k dielectric layer 54 may be selected from hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ) , lanthanum oxide (La 2 O 3 ) , tantalum oxide (Ta 2 O 5 ) , yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate (SrBi 2 Ta 2 O 9 , SBT) , lead zirconate titanate (PbZr x Ti 1 ⁇ x O 3 , PZT
- the work function metal layer 56 is formed for tuning the work function of the metal gate in accordance with the conductivity of the device.
- the work function metal layer 56 having a work function ranging between 3.9 eV and 4.3 eV may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WA 1 ), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC), but it is not limited thereto.
- the work function metal layer 56 having a work function ranging between 4.8 eV and 5.2 eV may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), but it is not limited thereto.
- An optional barrier layer (not shown) could be formed between the work function metal layer 56 and the low resistance metal layer 58 , in which the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN).
- the material of the low-resistance metal layer 58 may include copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) or any combination thereof.
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Abstract
Description
- The invention relates to a method for fabricating semiconductor device, and more particularly, to a method of forming trap rich structure adjacent to metal-oxide semiconductor (MOS) transistor.
- In radio frequency (RF) integrated circuit application, such as RF switch device or power amplifier device, performance is suffered from “parasitic surface charge” issue, which in turn generates harmonic effect. There are several wafer process technologies available for solving the issue such as using semiconductor-on-insulator (SOI) wafer to isolate the charges from the high resistivity wafer substrate. However, as the RF switch goes high frequency, it is more sensitive to RF harmonic effect induced by the parasitic surface charges hence how to resolve this problem and improve the performance of the device has become an important task in this field.
- According to an embodiment of the present invention, a method for fabricating semiconductor device includes: forming a metal-oxide semiconductor (MOS) transistor on a substrate; forming a first interlayer dielectric (ILD) layer on the MOS transistor; removing part of the first ILD layer to form a trench adjacent to the MOS transistor; forming a trap rich structure in the trench; forming a second ILD layer on the MOS transistor and the trap rich structure; forming a contact plug in the first ILD layer and the second ILD layer and electrically connected to the MOS transistor; and forming a metal interconnection on the second ILD layer and electrically connected to the contact plug.
- According to another aspect of the present invention, a semiconductor device includes: a metal-oxide semiconductor (MOS) transistor on a substrate; a trap rich structure on the substrate and adjacent to the MOS transistor, wherein a bottom surface of the trap rich structure is even with a top surface of the substrate; and an interlayer dielectric (ILD) layer on the MOS transistor and the trap rich structure.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIGS. 1-3 illustrate a method for fabricating semiconductor device according to an embodiment of the present invention. -
FIG. 4 illustrates a structural view of a semiconductor device according to an embodiment of the present invention. -
FIG. 5 illustrates a structural view of a semiconductor device according to an embodiment of the present invention. -
FIG. 6 illustrates a structural view of a semiconductor device according to an embodiment of the present invention. - Referring to
FIGS. 1-3 ,FIGS. 1-3 illustrate a method for fabricating semiconductor device according to an embodiment of the present invention. As shown inFIG. 1 , asubstrate 12 such as a semiconductor substrate having high resistance or more specifically a silicon substrate having high resistance is first provided, a plurality of isolation structures such as deeptrench isolation structures 14 preferably made of silicon oxide are formed in thesubstrate 12, and MOS transistors such asMOS transistors substrate 12 between the deeptrench isolation structures 14. It should be noted that even though threeMOS transistors substrate 12 in this embodiment, the number and conductive type of theMOS transistors - In this embodiment, the formation of the
MOS transistors substrate 12, and then forming transistor elements such as but not limited to forexample gate structures 22 and source/drain regions 24 on thesubstrate 12. Preferably, the conductive type of the deep well and the well region could be adjusted depending on the type of device being fabricated. For instance, the deep well in this embodiment preferably includes a deep n-well 26 while the well region preferably includes a p-well 28, but not limited thereto. - In this embodiment, the formation of the
gate structures 22 could be accomplished by a gate first process, a high-k first approach from gate last process, or a high-k last approach from gate last process. Since this embodiment pertains to a gate first approach, a gatedielectric layer 30 or interfacial layer, agate material layer 32 made of polysilicon, and a selective hard mask could be formed sequentially on thesubstrate 12, and a photo-etching process is then conducted by using a patterned resist (not shown) as mask to remove part of thegate material layer 32 and part of the gatedielectric layer 30 through single or multiple etching processes. After stripping the patterned resist,gate structures 22 each composed of a patterned gatedielectric layer 30 and a patternedmaterial layer 32 are formed on thesubstrate 12. - Next, at least a
spacer 34 is formed on the sidewalls of the each of thegate structures 22, a source/drain region 24 and/or epitaxial layer is formed in thesubstrate 12 adjacent to two sides of thespacer 34, and selective silicide layers (not shown) could be formed on the surface of the source/drain regions 24. In this embodiment, thespacer 34 could be a single spacer or a composite spacer, such as a spacer including but not limited to for example an offset spacer and a main spacer. Preferably, the offset spacer and the main spacer could include same material or different material while both the offset spacer and the main spacer could be made of material including but not limited to for example SiO2, SiN, SiON, SiCN, or combination thereof. The source/drain regions 24 could include n-type dopants or p-type dopants depending on the type of device being fabricated. For instance, the source/drain region 24 preferably includes n-type dopants in this embodiment, but not limited thereto. - Next, as shown in
FIG. 2 , a selective contact etch stop layer (CESL) (not shown) could be formed on thegate structures 22 to cover thegate structures 22, and a first interlayer dielectric (ILD)layer 36 is formed on the CESL. Next, a pattern transfer process is conducted by using patterned mask (not shown) as mask to remove part of thefirst ILD layer 36 adjacent to theMOS transistor 20 for formingtrench 38 exposing the surface of thesubstrate 12, and then forming a traprich structures 40 in thetrench 38. - In this embodiment, the formation of the trap
rich structure 40 could be accomplished by first conducting a deposition such as chemical vapor deposition (CVD) process to form adielectric layer 42 in thetrench 38 and on the surface of thefirst ILD layer 36. Specifically, thedielectric layer 42 is deposited to cover the top surface of thefirst ILD layer 36, sidewalls of thefirst ILD layer 36 within thetrench 38, and the top surface of thesubstrate 12 in the bottom of thetrench 38 without filling thetrench 38 completely. Next, a planarizing process such as chemical mechanical polishing (CMP) process is conducted to remove part of the part of thedielectric layer 42 on the top surface of thefirst ILD layer 36 so that the top surface of the remainingdielectric layer 42 is even with the top surface of thefirst ILD layer 36, in which a cross-section of the remainingdielectric layer 42 includes a U-shaped profile. In this embodiment, thedielectric layer 42 preferably includes doped polysilicon or silicon nitride, but not limited thereto. - It should be noted that even though the bottom of the U-shaped trap
rich structure 40 is even with the surface of thesubstrate 12 or the bottom of thegate structure 22, it would also be desirable to adjust the depth of thetrench 38 so that the bottom surface of thetrench 38 could be slightly higher than the surface of thesubstrate 12 or lower than the surface of thesubstrate 12, and thedielectric layer 42 is deposited in thetrench 38 thereafter to form the traprich structure 40. In other word, the bottom surface of the U-shaped traprich structure 40 could be slightly higher than the bottom surface of theadjacent gate structure 22 while the top surface of the traprich structure 40 is even with the top surface of thefirst ILD layer 36, or the bottom surface of the traprich structure 40 could be slightly lower than the bottom surface of thegate structure 22 while the top surface of the traprich structure 40 is even with the top surface of thefirst ILD layer 36, which are all within the scope of the present invention. - Next, as shown in
FIG. 3 , asecond ILD layer 44 is formed on thefirst ILD layer 36 and covering theMOS transistors rich structure 40, andcontact plugs 46 are formed in thefirst ILD layer 36 and thesecond ILD layer 44 to electrically connect the MOS transistors, 16, 18, 20. - In this embodiment, the
first ILD layer 36 and thesecond ILD layer 44 preferably include same material, such as both being made of dielectric material including but not limited to for example silicon oxide. Next, the formation of thecontact plugs 46 could be accomplished by first conducting a patterned transfer or photo-etching process by using a patterned mask (not shown) as mask to remove part of thesecond ILD layer 44 and part of thefirst ILD layer 36 adjacent to thegate structures 22 for forming contact holes (not shown) exposing the source/drain regions 24 underneath. Next, metals including a barrier layer selected from the group consisting of Ti, TiN, Ta, and TaN and a low resistance metal layer selected from the group consisting of W, Cu, Al, TiAl, and CoWP are deposited into the contact holes, and a planarizing process such as CMP is conducted to remove part of aforementioned barrier layer and low resistance metal layer for formingcontact plugs 46 electrically connecting the source/drain regions 24. - Next, a metal interconnective process is conducted to form inter-metal dielectric (IMD) layer (not shown) on the
second ILD layer 44 andmetal interconnections 48 connected to each of thecontact plugs 46. This completes the fabrication of a semiconductor device according to a preferred embodiment of the present invention. - Referring again to
FIG. 3 ,FIG. 3 further discloses a structural view of a semiconductor device according to an embodiment of the present invention. As shown inFIG. 3 , the semiconductor device includes at least a MOS transistor such asMOS transistors substrate 12, a traprich structure 40 disposed on thesubstrate 12 and adjacent to theMOS transistors ILD layer 50 disposed on theMOS transistors rich structure 40. - In this embodiment, the
ILD layer 50 further includes afirst ILD layer 36 covering theMOS transistors second ILD layer 44 disposed on thefirst ILD layer 36 while covering theMOS transistors rich structure 40 at the same time. Preferably, the bottom surface of the traprich structure 40 is even with the top surface of thesubstrate 12, the traprich structure 40 includes a U-shaped cross-section, the top surface of the traprich structure 40 is even with the top surface of thefirst ILD layer 36, and the traprich structure 40 is preferably made of dielectric material including but not limited to for example undoped polysilicon or silicon nitride. - The semiconductor device further includes
contact plug 46 disposed in thefirst ILD layer 36 and thesecond ILD 44 and electrically connected to the source/drain regions 24 of theMOS transistors metal interconnections 48 disposed on thesecond ILD layer 44 and electrically connected to thecontact plugs 46. In this embodiment, at least one of themetal interconnection 48 is disposed directly on top of the traprich structure 40 to cover or shield the traprich structure 40 completely, in which the presence of the traprich structure 40 could be used to shield noises generated between themetal interconnections 48 and thesubstrate 12 or other devices thereby improving the performance of the device. - Referring to
FIG. 4 ,FIG. 4 illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown inFIG. 4 , in contrast to the traprich structure 40 having U-shaped cross-section as disclosed in the aforementioned embodiment, it would also be desirable to control the amount ofdielectric layer 42 deposited into thetrench 38 such as by filling thetrench 38 with thedielectric layer 42 completely, and then conducting a planarizing process such as CMP to remove part of thedielectric layer 42 for forming a traprich structure 40, in which the top surface of the traprich structure 40 or the remainingdielectric layer 42 is even with the top surface of thefirst ILD layer 36. In this embodiment, the traprich structure 40 preferably includes a rectangular cross-section, which is also within the scope of the present invention. - Referring to
FIG. 5 ,FIG. 5 illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown inFIG. 5 , the formation of the traprich structure 40 could also be accomplished by first forming atrench 60 in thefirst ILD layer 36 and then conducting an ion implantation process to implant non-conductive ions including but not limited to for example silicon, germanium, carbon, nitrogen, or combination thereof into thefirst ILD layer 36 around thetrench 60 to form adoped region 62 or a traprich structure 40 made of thedoped region 62. In other words, instead of using the inner portion of thetrench 38 to form a traprich structure 40 made of dielectric material as disclosed in the aforementioned embodiment, the present embodiment conducts an ion implantation process to form adoped region 62 outside thetrench 60 to forma traprich structure 40 made of thedoped region 62. Similar to the aforementioned embodiment, it would also be desirable to adjust the depth of thetrench 60 so that the bottom surface of the U-shaped traprich structure 40 made ofdoped region 62 could be slightly higher than the bottom surface of theadjacent gate structure 22 while the top surface of the traprich structure 40 is even with the top surface of thefirst ILD layer 36, or the bottom surface of the traprich structure 40 is slightly lower than the bottom surface of thegate structure 22 while the top surface of the trap rich structures is even with the top surface of thefirst ILD layer 36, which are all within the scope of the present invention. - Referring to
FIG. 6 ,FIG. 6 illustrates a method of transforming thegate structure 22 made of polysilicon from the aforementioned embodiment into a metal gate according to a high-k last process. As shown inFIG. 6 , after thefirst ILD layer 36 is formed, a planarizing process such as CMP could be conducted to remove part of thefirst ILD layer 36 to expose the top surface of thegate material layer 32 made of polysilicon layer so that the top surface of thegate material layer 32 is even with the top surface of thefirst ILD layer 36. - Next, a replacement metal gate (RMG) process is conducted to transform the
gate structures 22 of theMOS transistors gate material layer 32 and even gatedielectric layer 30 from each of thegate structures 22 for forming recesses (not shown) in thefirst ILD layer 36. - Next, a selective
interfacial layer 52 or gate dielectric layer (not shown) , a high-kdielectric layer 54, a workfunction metal layer 56, and a lowresistance metal layer 58 are formed in the recesses, and a planarizing process such as CMP is conducted to remove part of lowresistance metal layer 58, part of workfunction metal layer 56, and part of high-kdielectric layer 54 to form metal gates. In this embodiment, each of the gate structures or metal gates fabricated through high-k last process of a gate last process preferably includes aninterfacial layer 52 or gate dielectric layer (not shown), a U-shaped high-kdielectric layer 54, a U-shaped workfunction metal layer 56, and a lowresistance metal layer 58. - In this embodiment, the high-
k dielectric layer 54 is preferably selected from dielectric materials having dielectric constant (k value) larger than 4. For instance, the high-k dielectric layer 54 may be selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3) , lanthanum oxide (La2O3) , tantalum oxide (Ta2O5) , yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT) , lead zirconate titanate (PbZrxTi1−xO3, PZT), barium strontium titanate (BaxSr1−xTiO3, BST) or a combination thereof. - In this embodiment, the work
function metal layer 56 is formed for tuning the work function of the metal gate in accordance with the conductivity of the device. For an NMOS transistor, the workfunction metal layer 56 having a work function ranging between 3.9 eV and 4.3 eV may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WA1), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC), but it is not limited thereto. For a PMOS transistor, the workfunction metal layer 56 having a work function ranging between 4.8 eV and 5.2 eV may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), but it is not limited thereto. An optional barrier layer (not shown) could be formed between the workfunction metal layer 56 and the lowresistance metal layer 58, in which the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). Furthermore, the material of the low-resistance metal layer 58 may include copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) or any combination thereof. - Next, it would be desirable to follow the aforementioned embodiments by removing part of the
first ILD layer 36 adjacent to theMOS transistor 20 to form atrench 38 exposing the surface of thesubstrate 12, forming a traprich structure 40 in thetrench 38, forming asecond ILD layer 44 on thefirst ILD layer 36, theMOS transistors rich structure 40, and then forming contact plugs 46 in thefirst ILD layer 36 and thesecond ILD layer 44 to electrically connect theMOS transistors - It should be noted that since the top surface of the metal gates are even with the top surface of the
first ILD layer 36 as polysilicon gates are transformed into metal gates, the top surface of the traprich structure 40 formed afterwards is not only even with the top surface of thefirst ILD layer 36 but also even with the top surface of thegate structures 22 made of metal gates. - Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
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US9865649B2 (en) * | 2015-09-25 | 2018-01-09 | Globalfoundries Singapore Pte. Ltd. | Integrated two-terminal device and logic device with compact interconnects having shallow via for embedded application |
CN107170750B (en) * | 2017-05-08 | 2019-08-02 | 合肥市华达半导体有限公司 | A kind of semiconductor components and devices structure and preparation method thereof |
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- 2018-01-09 CN CN201810018793.8A patent/CN110021559B/en active Active
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