CN1967785A - Method for forming contact window and via by etching dielectric layer and inlay technics - Google Patents
Method for forming contact window and via by etching dielectric layer and inlay technics Download PDFInfo
- Publication number
- CN1967785A CN1967785A CN 200510120487 CN200510120487A CN1967785A CN 1967785 A CN1967785 A CN 1967785A CN 200510120487 CN200510120487 CN 200510120487 CN 200510120487 A CN200510120487 A CN 200510120487A CN 1967785 A CN1967785 A CN 1967785A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- conductive mask
- patterning
- substrate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a method for using conductive mask to etch dielectric layer, wherein it comprises that: providing dielectric layer on the substrate, forming pattern conductive mask on dielectric layer contacted with substrate; using said mask to etch dielectric layer; using mask to disperse the charge generated by etching process, to avoid accumulating charge on etched dielectric layer, to restrain the crack of metal line and element covered by dielectric layer.
Description
Technical field
The present invention relates to a kind of engraving method that uses conductive mask, relate in particular to a kind of dry-etching method that utilizes conductive mask to disperse stored charge.
Background technology
Along with semiconductor fabrication is more and more accurate, great change also takes place in integrated circuit, makes the operational performance of computer and memory capacity advance by leaps and bounds, and drives peripheral industry and develop rapidly.And semiconductor industry is also predicted as Moore's Law, developing with per 18 months speed of transistor size on integrated circuit that doubles, so technology is more and more accurate.Semiconductor technology from 90 nanometers (0.09 micron) in 0.13 micron, 2003 of 0.18 micron in 1999, calendar year 2001, enters into 2005 65 nanometers (0.065 micron technology).
In semiconductor technology, contact plunger (contact plug), interlayer connector (via plug) are the important techniques contents always, in order to electrically connect elements such as all transistors, electric capacity and metal interconnecting and then to constitute whole integrated circuit, it also can directly use process for copper (copper process) to finish except can utilizing tungsten metal, the material of aluminium alloy as contact plunger, interlayer connector.And because the copper metal is difficult for etching, therefore utilize the copper metal as metal interconnecting conduct material the time, be to utilize singly to inlay (single damascene) or dual damascene (dual damascene) technology forms required copper interlayer connector (via plug) and copper conductor mostly.But; when carrying out dry etching process with formation contact hole (contact hole), interlayer hole (via hole) and lead irrigation canals and ditches (trench); usually can be accumulated on the dielectric layer in a large number because of electric charge; so the metal level below being etched to dielectric layer soon, element or when having touched metal level, element; just the metal explosion situation of metal level, element takes place in regular meeting, makes yield descend.
See also Fig. 1, Fig. 1 is the schematic diagram of existing etching technique generation metal level explosion.As shown in Figure 1, semiconductor chip 100 includes a nmos pass transistor and a PMOS transistor, be respectively formed on the p type wells (P-well) 102 and N type well (N-well) 104 of P type semiconductor substrate 101, and all has a shallow isolating trough (shallow trenchisolation around nmos pass transistor and the PMOS transistor, STI) 106, in order to separate each nmos pass transistor and each PMOS transistor; And PMOS transistor AND gate nmos pass transistor respectively includes a grid 108,109, and source/drain (source/drain) 110,111 is arranged in p type wells 102 and N type and 104.Then, on P type semiconductor substrate 101, deposit a contact etch stop layer (contact etch stop layer in regular turn, CESL) 113, one non-doped silicon glass (undoped silica glass, USG) 112 and one phosphorosilicate glass (phosphorus-doped silica glass, PSG) 114, and cover grid 108,109, source/drain 110,111, shallow isolating trough 106, p type wells 102 and N type well 104 tops.Subsequently, for with nmos pass transistor and PMOS transistor AND gate other element and the metal interconnecting of follow-up making electrically connect, must utilize photoetching, etching, deposition, chemico-mechanical polishing technologies such as (CMP), form contact plunger (contact plug) 116, and make an end of contact plunger 116 connect grid 108, perhaps connect source/drain 110, an other end then is connected with the metal level 118 of follow-up making.And metal level 118 tops, more deposit a dielectric layer 120, and this dielectric layer 120 can be considered according to different technology again and include the dielectric layer (HDPoxide) 119 that utilizes high density plasma deposition (HDPCVD) to form in addition, the oxide layer (PEoxide) 121 that one plasma assistant chemical vapor deposition (PECVD) forms, and an oxidation cap layer (cap oxide) 123.
Equally as shown in Figure 1, above dielectric layer 120, carry out a gold-tinted technology subsequently, in order to form the photoresist layer 122 of a patterning, then utilize the photoresist 122 of this patterning to carry out a dry ecthing again, in dielectric layer 120, to form required interlayer hole 124.Owing to be to utilize plasma dry etch to carry out the interlayer hole etch process mostly at present, therefore when etch process carries out, can produce a large amount of electric charges is accumulated in the dielectric layer 120, so when the interlayer hole etch process is etched to metal level 118 surfaces, or when soon being etched to metal level 118, these a large amount of electric charges of accumulating just can be led off fast from here, and then cause metal level 118 to pop forming explosion 125, even more the elements such as grid 108 of bottom also can be influenced by charges accumulated and impaired.
Therefore, the metal explosion of how avoiding the dry ecthing dielectric layer and being caused is real is this area subject under discussion anxious to be solved.
Summary of the invention
The invention provides a kind of engraving method that uses conductive mask, to address the above problem.
The present invention discloses a kind of method of using the conductive mask etching dielectric layer, provides dielectric layer to be positioned on the substrate, the conductive mask that forms patterning on dielectric layer and and substrate contact, utilize the conductive mask of patterning that dielectric layer is carried out dry etching process again.
In the preferred embodiment of the present invention, it is a kind of method that forms contact hole, including provides substrate, and substrate is provided with at least one element, forming dielectric layer is covered on element and the substrate, form conductive mask on dielectric layer and and substrate contact, and utilize conductive mask to carry out etch process, in dielectric layer, to etch contact hole until element surface.
In another preferred embodiment of the present invention, it is a kind of method that forms interlayer hole, including provides substrate, on substrate, be formed with first dielectric layer, and first dielectric layer is provided with at least one metal interconnecting layer, form that second dielectric layer is covered on the metal interconnecting layer and first dielectric layer on, the conductive mask that forms patterning on second dielectric layer and and substrate contact, and utilize the conductive mask of patterning to carry out etch process, in second dielectric layer, to etch at least one interlayer hole until the metal interconnecting laminar surface.
In another preferred embodiment of the present invention, it is a kind of mosaic technology method, including provides substrate, and substrate is provided with at least one conducting wire, form dielectric layer on the conducting wire, the conductive mask that forms patterning on dielectric layer and and substrate contact, utilize the conductive mask of patterning to carry out etch process, forming at least one opening in dielectric layer, and fill the copper metal in opening until the surface, conducting wire.
The present invention utilizes conductive mask, make the electric charge that dry ecthing produced, be distributed on the large-area conductive mask, and in the importing substrate, so can not accumulate electric charge in a large number in etched dielectric layer region, the metal explosion situation of metal interconnecting and element just can not take place yet, and allows the yield of semiconductor wafer improve.
Description of drawings
Fig. 1 is the schematic diagram of existing etching technique generation metal level explosion;
Fig. 2 is the process schematic representation that the present invention is applied in the etching contact hole;
Fig. 3 is the process schematic representation that the present invention is applied in the etching interlayer hole;
Fig. 4 is the process schematic representation that the present invention is applied in another embodiment of etching interlayer hole;
Fig. 5 is the schematic diagram that the present invention is applied in a preferred embodiment of dual damascene (dual damascene) technology.
The main element symbol description
100,200 CMOS (Complementary Metal Oxide Semiconductor) transistor
101,201 P type semiconductor substrates
102,202 p type wellses, 104,204 N type wells
106,206 shallow isolating trough
108,109,208,209 grids
110,111,210,211 source/drains
112,212 non-doped silicon glasses
113,213 contact etch stop layers
114,214 phosphorosilicate glasses
116,216 contact hole connectors
118,218 metal levels
119,121,219,221 oxide layers
123,223 oxidation cap layers
120,220,302,306,308 dielectric layers
122 photoresists
124,224 interlayer holes
125 explosions
215,222,314 conductive mask
217 contact holes
225 metal levels
227 photoresist layers
300 transistors
301 substrates
304 bronze medal connectors
310,316 openings
Embodiment
See also Fig. 2, Fig. 2 is the process schematic representation that the present invention is applied in the etching contact hole.Semiconductor chip 200 comprises a nmos pass transistor and a PMOS transistor, be respectively formed on the p type wells (P-well) 202 and N type well (N-well) 204 of P type semiconductor substrate 201, and all has a shallow isolating trough (STI) 206 around nmos pass transistor and the PMOS transistor, in order to separate each nmos pass transistor and each PMOS transistor; And PMOS transistor AND gate nmos pass transistor respectively comprises a grid 208,209, and source/drain (source/drain) 210,211 is arranged in p type wells 202 and the N type well 204.
Then, on P type semiconductor substrate 201, deposit a contact etch stop layer (CESL) 213, one a non-doped silicon glass (USG) 212 and a phosphorosilicate glass (PSG) 214 in regular turn, and cover grid 208,209, source/drain 210,211, shallow isolating trough 206, p type wells 202 and N type well 204 tops.Subsequently, the present invention carries out a gold-tinted (lithography) technology and photoetching (Photo-lithography) technology again, cover phosphorosilicate glass 214 tops in order to the conductive mask 215 that forms a patterning, and the edge that the conductive mask 215 of patterning extends to semiconductor chip 200 always contacts with P type semiconductor substrate 201, and then carries out the dry etching process of contact hole 217.
It should be noted that, in an embodiment of the present invention, conductive mask 215 is made of a conduction photoresist, it comprises electroconductive resin (resin), solvent and sensitizer (sensitizer), for example electroconductive resin can be 3-hexyl thiophene-3-thiophene-ethane-methacrylate copolymer (3-hexyl-thiophene-3thiophene-ethane-methcylate copolymer), solvent can be used acetonitrile (the aceto-nitrile solution ofgold chloride) solution of chlorauride, sensitizer then can be chlorauride (goldchloride) etc., certainly the material of conduction photoresist is not limited to mentioned component, and the present invention also can select for use the conduction photoresist product of other commercially available formula components to use.In addition, also the demand of visual technology and other are considered, and form an anti-reflecting layer (ARC) above phosphorosilicate glass 214 earlier, and then form conductive mask 215, with when photoetching (Photo-lithography) technology, obtain conductive mask 215 structures of preferable patterning.Moreover, the conductive mask 215 that is positioned at the patterning of phosphorosilicate glass 214 tops can be selected the complete edge that covers whole semiconductor chip 200, also can select the edge of part contact semiconductor chip 200, no matter the conductive mask 215 of patterning is that the edge of complete covering or part contact semiconductor chip 200 all can make the electrostatic charge that produces in the dry etching process of contact hole 217 be imported in the P type semiconductor substrate 201.
The present invention also can be applicable to the standard technology of etching interlayer hole, please refer to Fig. 3, and Fig. 3 is the process schematic representation that the present invention is applied in the etching interlayer hole.The semiconductor technology of hookup 2, after the etching step of contact hole 217 is finished, remove conductive mask 215 immediately, and carry out a cleaning, so just can in non-doped silicon glass 212 and phosphorosilicate glass 214, form the surface of required contact hole 217, next, get final product metals such as deposition of tantalum (Ta), tantalum nitride (TaN), tungsten until grid 208,209 surfaces or source/drain 210,211, and utilize a chemico-mechanical polishing (CMP), to form contact plunger 216.Then, utilize technologies such as deposition, gold-tinted, etching again, to form the metal level 218 of the patterning that an aluminium copper etc. forms, make an end of contact hole connector 216 connect grid 208, perhaps connect source/drain (source/drain) 210 doped regions such as grade, an other end then is connected with the metal level 218 of patterning, and then forms the metal interconnecting layer.Look product demand more subsequently and technology is considered, deposit a composite dielectric layer 220, for example this dielectric layer 220 can comprise the oxide layer (HDP oxide) 219 of utilizing high density plasma deposition to go out, one oxide layer (PE oxide) 221 of utilizing plasma auxiliary chemical vapor deposition (PECVD) to form, and an oxidation cap layer (cap oxide) 223.The conductive mask 222 that last the present invention forms a patterning again covers dielectric layer 220 tops, and the edge that the conductive mask 222 of patterning extends to semiconductor chip 200 always contacts with P type semiconductor substrate 201, carry out the dry etching process of interlayer hole 224 then, in dielectric layer 220, to form metal level 218 surfaces of required interlayer hole 224 until corresponding patterning.
Similarly, the conductive mask 222 of present embodiment also is a conduction photoresist, and the demand of visual technology and other are considered, and elder generation forms an anti-reflecting layer (ARC) above dielectric layer 220, and then formation conductive mask 222, with when photoetching (Photo-lithography) technology, obtain conductive mask 222 structures of preferable patterning.The conductive mask 222 of this patterning also can be selected the complete edge that covers whole semiconductor chip 200, but the also edge of part contact semiconductor chip 200 is imported in the P type semiconductor substrate 201 electrostatic charge that produces in the dry etching process of interlayer hole 224.
What deserves to be mentioned is conductive mask 215,222 of the present invention except can constituting, also can be the upper and lower structure of piling up of a metal level and a photoresist layer by the conduction photoresist of the foregoing description.For example, please refer to Fig. 4, Fig. 4 is the process schematic representation that the present invention is applied in another embodiment of etching interlayer hole.As shown in Figure 4, dielectric layer 220 can first sputter one metal level 225 after deposition finishes, and then forms the photoresist layer 227 of a patterning thereon, is used for the position of in dielectric layer 220 each interlayer hole 224 of definition.Because conductive mask 222 shown in Figure 4 is upper and lower structures of piling up of a metal level 225 and a photoresist layer 227, wherein the stacked structure of this metal level 225 and photoresist layer 227 extends to the edge of semiconductor chip 200 always, contacts with P type semiconductor substrate 201.Therefore when carrying out design transfer, can directly utilize the photoresist layer 227 of patterning to be used as etching mask, elder generation's etch metal layers 225, and then etching dielectric layer 220, in dielectric layer 220, to etch each required interlayer hole 224, or utilize the pattern transfering process of two-part, that is the photoresist layer 227 that utilizes patterning earlier is used as etching mask and is come etch metal layers 225, with with the design transfer of photoresist layer 227 to metal level 225, then remove after the photoresist layer 227, utilize the metal level 225 of patterning to be used as the dry etching process that etching mask carries out interlayer hole 224 again.
Because the present invention utilizes the conductive mask of patterning 215,222 are used as etching mask, therefore carrying out contact hole (contact hole) 217, interlayer hole (via hole) 224, or shallow ridges (trench) etc. singly inlay the plasma dry etch technology of (single damascene) opening the time, formed electric charge just can be respectively by conductive mask 215,222 characteristics of electrical conductivity on average disperses, and can not be accumulated in phosphorosilicate glass (PSG) 214, non-doped silicon glass (USG) 212, in contact etch stop layer (CESL) 213 and the dielectric layer 220, add conductive mask 215,222 all contact with P type semiconductor substrate 201, so the formed electric charge of dry etching process just can import in the P type semiconductor substrate 201, therefore just can be as prior art, cause electric charge to be accumulated in a large number in the regional area of dielectric layer, and at the metal level that is etched to soon below the dielectric layer, element or touched metal level, during element, metal level takes place, the metal explosion situation of element.In addition, if during the stacked structure of conductive mask metal level of the present invention and photoresist layer, it is different functional also can to select specific metal material to come to have in conjunction with follow-up technology, if for example conductive mask 222 is by titanium nitride (TiN), when tantalum nitride titaniums (TaN) etc. constitute, except the situation that can avoid metal explosion in the prior art, can increase again with KLA-TencorAIT model chip detection system dielectric layer 220 is measured defective and particulate on the line, for example residual (residues), scratch the recall rate of defectives such as (micro scratch), but also the metal mechanical polishing that can be used as interlayer hole 224 connectors stops layer, and in the mechanical polishing process of follow-up metal plug, be removed in the lump.
In addition, what the present invention also can be used in process for copper (copper process) singly inlays (singledamascene) or dual damascene (dual damascene) technology, in order to form required copper interlayer connector (via plug) and copper conductor.See also Fig. 5, Fig. 5 is the schematic diagram that the present invention is applied in a preferred embodiment of dual damascene (dual damascene) technology.Semiconductor chip 300 comprises substrate 301, one dielectric layer 302, at least one conductive structure, for example conducting wire such as metal plug or metal pattern 304 is located in the dielectric layer 302, and dielectric layer 302 and 304 tops, conducting wire deposit the dielectric layer 308 of a dielectric layer 306, a patterning in addition.Wherein, the dielectric layer 308 of patterning can be the oxide layer (PE oxide) that plasma auxiliary chemical vapor deposition (PECvD) goes out, it is to utilize a photoresist layer (not shown) earlier and via after the pattern transfer steps such as gold-tinted etching, with generation a plurality of opening 310 patterns are arranged, be used for defining the position of the copper conductor of metal interconnecting.Then, the conductive mask 314 that forms a patterning is in dielectric layer 306,308 tops, this conductive mask 314 extend to always semiconductor chip 300 the edge and and substrate 301 contact, and the conductive mask 314 of patterning has at least one opening 316, be used for defining the position of the copper interlayer connector of metal interconnecting, via dry etching process, can in dielectric layer 306, form the interlayer hole (not shown) subsequently.Remove the conductive mask 314 of patterning then, and utilize the dielectric layer 308 of patterning to carry out etching again, just required shallow ridges (trench) pattern (not shown) be can in dielectric layer 306, form, copper interlayer connector and copper conductor in dual damascene opening, formed at last more simultaneously.And dual damascene (dual damascene) processing step of shallow ridges elder generation's system (trench first), interlayer elder generation's system (via first) or no-etch stop layer etc. is similar, its shallow ridges mask and interlayer mask all can use conductive mask of the present invention to come define pattern and avoid the metal explosion, do not add to give unnecessary details at this.
Because, the material of conductive mask 314 can be the conduction photoresist that large tracts of land covers dielectric layer 306,308 tops, and contact with substrate 301 again, so when dry etching process carries out, electric charge can not be accumulated in dielectric layer 306, the 308 etched blocks in prior art in a large number, but be distributed on the large-area conduction photoresist, and import in the substrate 301, so touch conducting wire 304 soon when being etched to, or when having touched conducting wire 304, can be because of a large amount of electric charge accumulations, and cause the metal explosion.Certainly, as previously mentioned, in the present embodiment, conductive mask 314 also can utilize the stacked structure of a metal level and a photoresist layer to constitute, just after forming opening 310, can deposit a layer of metal layer and a photoresist layer earlier as conductive mask, after this metal level and the photoresist layer patternization on it, carry out the dry ecthing of interlayer hole again.Certainly, before carrying out the interlayer hole dry ecthing, can select first flush away photoresist layer or stay the dry etching process that the photoresist layer carries out interlayer hole again.
What deserves to be mentioned is, the present invention also can be applicable in single mosaic technology, promptly utilize conductive mask and gold-tinted etch process to form interlayer hole opening or shallow ridges opening earlier, utilize conductive mask and gold-tinted etch process in dielectric layer, to form the opening of metal level again, deposition goes up the copper metal and forms copper connector or copper conductor again, because electric charge is to contact with large-area conductive mask, so stored charge in a large number not, when etching dielectric layer, the situation of metal explosion can not take place.
In the prior art, because electric charge is accumulated in a large number, so the dry ecthing dielectric layer is several to metal plug, the conducting wire, during element such as doped region or grid, the situation of metal explosion even gate dielectric puncture (breakdown) can take place in prior art, influence quality, yield, and seriously reduce production capacity, and the present invention utilizes conductive mask, make the electric charge that dry ecthing produced, conducted and be distributed on the large-area conductive mask, and imported in the substrate, so can not accumulate electric charge in a large number in the etched regional area of dielectric layer, the metal explosion situation of metal interconnecting and element etc. just can not take place yet, and the yield of semiconductor wafer can improve.And, conductive mask is except can directly adopting conduction photoresist material, outside the advantage of avoiding the metal explosion, the present invention can also use the composite construction of metal level and photoresist layer, can increase again with KLA-TencorAIT model chip detection system with the metal level that utilizes specific materials dielectric layer is measured defective and particulate on the line, for example residual (residues), scratch the recall rate of defectives such as (micro scratch), and can be used as follow-up interlayer connector chemico-mechanical polishing stop layer, and in this mechanical polishing process, be removed in the lump, reach and simplify the purpose that technology reduces cost.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (32)
1. the method for an etching dielectric layer, this dielectric layer is positioned at substrate top, this method is that the conductive mask that forms a patterning earlier contacts on this dielectric layer and with this substrate, utilize the conductive mask of this patterning that this dielectric layer is carried out a dry etching process again, the electric charge that wherein this dry etching process produced imports in this substrate via the conductive mask of this patterning.
2. the method for claim 1, wherein this dry etching process comprises that a contact hole etching technology, an interlayer hole etch process or singly inlay the opening etch process.
3. method as claimed in claim 2, wherein the conductive mask of this patterning is a conduction photoresist, is used in this dielectric layer this contact hole of definition, this interlayer hole or this singly to inlay the position of opening.
4. method as claimed in claim 3, wherein this conduction photoresist comprises:
One electroconductive resin;
One solvent; And
One sensitizer.
5. method as claimed in claim 4, wherein this electroconductive resin comprises 3-hexyl thiophene-3-thiophene-ethane-methacrylate copolymer.
6. method as claimed in claim 4, wherein this solvent is the acetonitrile solution that comprises chlorauride.
7. method as claimed in claim 4, wherein this sensitizer comprises chlorauride.
8. method as claimed in claim 2, wherein the conductive mask of this patterning is the stacked structure that comprises a metal level and a photoresist layer, is used for defining the position of this interlayer hole in this dielectric layer.
9. method as claimed in claim 8, wherein this metal level comprises titanium nitride.
10. method as claimed in claim 8, wherein the conductive mask of this patterning also comprises an anti-reflecting layer, is located between this metal level and this photoresist layer.
11. the method for claim 1, wherein the conductive mask of this patterning contacts the edge of this substrate.
12. a method that forms contact hole comprises:
Provide a substrate, and this substrate is provided with at least one element;
Forming a dielectric layer is covered on this element and this substrate;
Forming a conductive mask contacts on this dielectric layer and with this substrate; And
Utilize this conductive mask to carry out an etch process, to etch a contact hole until this element surface in this dielectric layer, the electric charge that wherein this etch process produced is to import in this substrate via this conductive mask.
13. method as claimed in claim 12, wherein those elements comprise a grid or a doped region.
14. method as claimed in claim 12, wherein this conductive mask is the conduction photoresist of a patterning, and it comprises an electroconductive resin, a solvent and a sensitizer, is used for defining the position of this contact hole in this dielectric layer.
15. method as claimed in claim 12, wherein the conductive mask of this patterning is the stacked structure that comprises a metal level and a photoresist layer, is used for defining the position of this interlayer hole in this dielectric layer.
16. method as claimed in claim 15, wherein this metal level comprises titanium nitride.
17. method as claimed in claim 15, wherein the conductive mask of this patterning also comprises an anti-reflecting layer, is located between this metal level and this photoresist layer.
18. method as claimed in claim 12, wherein this conductive mask contacts the edge of this substrate.
19. a method that forms interlayer hole comprises:
One substrate is provided, is formed with one first dielectric layer on this substrate, and this first dielectric layer is provided with at least one metal interconnecting layer;
Form one second dielectric layer, be covered on this metal interconnecting layer and on this first dielectric layer;
The conductive mask that forms a patterning contacts on this second dielectric layer and with this substrate; And
Utilize the conductive mask of this patterning to carry out an etch process, etching at least one interlayer hole until this metal interconnecting laminar surface in this second dielectric layer, the electric charge that wherein this etch process produced is that the conductive mask via this patterning imports in this substrate.
20. method as claimed in claim 19, wherein the conductive mask of this patterning is a conduction photoresist, and it comprises an electroconductive resin, a solvent and a sensitizer, is used for defining the position of this interlayer hole in this second dielectric layer.
21. method as claimed in claim 19, wherein the conductive mask of this patterning is the stacked structure that comprises a metal level and a photoresist layer, is used for defining the position of this interlayer hole in this second dielectric layer.
22. method as claimed in claim 21, wherein this metal level comprises titanium nitride.
23. method as claimed in claim 21, wherein the conductive mask of this patterning also comprises an anti-reflecting layer, is located between this metal level and this photoresist layer.
24. method as claimed in claim 19, wherein the conductive mask of this patterning contacts the edge of this substrate.
25. a mosaic technology method comprises:
Provide a substrate, and this substrate is provided with at least one conducting wire;
Form a dielectric layer on this conducting wire;
The conductive mask that forms a patterning contacts on this dielectric layer and with this substrate;
Utilize the conductive mask of this patterning to carry out an etch process, forming at least one opening in this dielectric layer until this surface, conducting wire, the electric charge that this etch process produced is that the conductive mask via this patterning imports in this substrate; And
Fill a bronze medal metal in this opening.
26. method as claimed in claim 25, wherein this conducting wire is a contact plunger, and this opening is one singly to inlay opening.
27. method as claimed in claim 25, wherein this conducting wire is a metal interconnecting, and this opening is a dual damascene opening.
28. method as claimed in claim 25, wherein the conductive mask of this patterning is a conduction photoresist, and it comprises an electroconductive resin, a solvent and a sensitizer, is used for defining this and is opened on position in this dielectric layer.
29. method as claimed in claim 28, wherein this electroconductive resin is 3-hexyl thiophene-3-thiophene-ethane-methacrylate copolymer.
30. method as claimed in claim 28, wherein this solvent is the acetonitrile solution of chlorauride.
31. method as claimed in claim 28, wherein this sensitizer is a chlorauride.
32. method as claimed in claim 25, wherein the conductive mask of this patterning contacts the edge of this substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510120487 CN1967785A (en) | 2005-11-18 | 2005-11-18 | Method for forming contact window and via by etching dielectric layer and inlay technics |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510120487 CN1967785A (en) | 2005-11-18 | 2005-11-18 | Method for forming contact window and via by etching dielectric layer and inlay technics |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1967785A true CN1967785A (en) | 2007-05-23 |
Family
ID=38076472
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510120487 Pending CN1967785A (en) | 2005-11-18 | 2005-11-18 | Method for forming contact window and via by etching dielectric layer and inlay technics |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1967785A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110021559A (en) * | 2018-01-09 | 2019-07-16 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
-
2005
- 2005-11-18 CN CN 200510120487 patent/CN1967785A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110021559A (en) * | 2018-01-09 | 2019-07-16 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN202930362U (en) | Semiconductor device | |
| CN103137554B (en) | The method forming semiconductor device | |
| CN1265458C (en) | Semiconductor having formed capacitor in multi-layer wire distributing structure | |
| US9818689B1 (en) | Metal-insulator-metal capacitor and methods of fabrication | |
| CN1761056A (en) | Interconnection structure and forming method thereof | |
| CN107895721B (en) | Memory and forming method thereof | |
| CN1815714A (en) | Semiconductor device and method for fabricating the same | |
| CN108074911B (en) | Jumping hole structure | |
| CN101030552A (en) | Processing method of integrated circuit, metal-insulator-metal capacitor formation method | |
| CN1181549C (en) | Semiconductor device and mfg. method thereof | |
| CN101290941B (en) | Image sensor and method for manufacturing the same | |
| CN1300850C (en) | Semiconductor device and method for fabricating the same | |
| CN1466190A (en) | Method for forming copper metal line | |
| CN1832177A (en) | Picture element structure and liquid crystal display and manufacturing method thereof | |
| CN110858562A (en) | Semiconductor element manufacturing method and semiconductor element manufactured by same | |
| CN1684244A (en) | Method of manufacturing a semiconductor device having damascene structures with air gaps | |
| CN102194834B (en) | Apparatus having thinner interconnect line for photodetector array and thicker interconnect line for periphery region | |
| CN1284243C (en) | Semiconductor device and its manufacturing method | |
| CN1635625A (en) | Method and structure for manufacturing high-capacitance capacitor by using copper | |
| US20040121584A1 (en) | Method of manufacturing a semiconductor device | |
| CN1967785A (en) | Method for forming contact window and via by etching dielectric layer and inlay technics | |
| US7704882B2 (en) | Semiconductor devices using fine patterns and methods of forming fine patterns | |
| CN1897222A (en) | Method for manufacturing capacitor for semiconductor device | |
| CN1574321A (en) | Bond pad scheme for cu process | |
| KR100977924B1 (en) | Stacted structure of MIM capacitor for high density and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20070523 |