US20190181862A1 - Circuit and system implementing a smart fuse for a power supply - Google Patents
Circuit and system implementing a smart fuse for a power supply Download PDFInfo
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- US20190181862A1 US20190181862A1 US16/202,573 US201816202573A US2019181862A1 US 20190181862 A1 US20190181862 A1 US 20190181862A1 US 201816202573 A US201816202573 A US 201816202573A US 2019181862 A1 US2019181862 A1 US 2019181862A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3243—Power saving in microcontroller unit
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/02—Details
- H02H3/06—Details with automatic reconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
- H02H3/087—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current for dc applications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1731—Optimisation thereof
- H03K19/1732—Optimisation thereof by limitation or reduction of the pin/gate ratio
Definitions
- FIG. 6 is zoomed in section of the timing diagram of FIG. 5 .
- the latch signal is maintained in the hardware latch even if the load current falls again to a safe value, or to zero.
- the latch signal is maintained until the hardware latch signal receives a rearm signal.
- a logic circuit is fed with the latch signal from the hardware latch and with a software command intended to control turning on and off of the circuit.
- the logic circuit converts the software command to a control voltage for application at the gate of the transistor when the latch signal is not set.
- the transistor is thus a “smart fuse” that is turned off to cut the flow of current into the load in case of a fault and that can be modulated by the software command to control a level of the current into the load in normal operation.
- a primary transistor 56 for example a metal oxide semiconductor field effect transistor (MOSFET), such as an n-channel MOSFET (NMOS) having a drain 58 , a gate 60 and a source 62 , is connected to the primary voltage source 52 and to a connector 64 having a pair of ports for eventually connecting a load 66 .
- a top resistor 68 is connected to the secondary voltage source 54 , to the gate 60 of the primary transistor 56 , and to a collector (C) 70 of a secondary transistor 72 , for example a bipolar transistor.
- the secondary transistor 72 also has a base (B) 74 and an emitter (E) 76 .
- the emitter 76 of the secondary transistor 72 is connected to a bottom resistor 78 , to the source 62 of the primary transistor 56 , and to a positive end of the connector 64 .
- An output 166 of the NAND gate 160 is determined as follows: If the NAND-gate latch is latched to provide a logical 0, resulting from V out having exceeded the trigger voltage of the NAND gate 136 , the output 166 of the NAND gate 160 is a logical 1 and will remain as such until the rearm signal is set to a logical 0, at least temporarily. Otherwise, if the NAND-gate latch is latched to provide a logical 1, which is a normal circumstance, the NAND gate 160 translates the software command Q0, providing a logical inverse of the software command Q0 at its the output 166 , so that the output 166 is a logical 0 when the software command Q0 is a logical 1, and vice-versa. The NAND gate 160 therefore combines effects of the software command Q0 and of the status of the circuit 100 .
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Electronic Switches (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
Description
- The present application claims priority from European Patent Application No. 17315014.5, filed on Dec. 13, 2017, the entirety of which being incorporated herein by reference.
- The present disclosure relates to the field of electronic power supplies. More specifically, the present disclosure relates to a circuit and a system implementing a smart fuse for a power supply.
- Large scale networks used for cloud computing, search engines, and similar applications, typically include tens or hundreds of servers for load sharing and for redundancy. These networks need to be highly scalable, so there is a need to frequently add more servers to the network infrastructure.
- Large scale server networks consume very large amounts of electric power and generate a lot of heat. Any manner of reducing power consumption is desirable.
- Fuses and/or relays may be used to cut delivery of power to a server in case of a fault, for example in the occurrence of a short-circuit. However fuses are typically slow to react and must be replaced after a short-circuit. Relays may protect a server from a short-circuit, and may be rearmed, but are very slow to react. Additionally, current that is provided to a server must flow through contacts of a relay, causing important power losses. Measurements have shown that, typically up to 4% of the power delivered to a server may be lost in a relay. The energy wasted in the relay causes heat accumulation in the power supply that, for a large server bank, translates into important cooling needs.
- Availability requirements for large scale server networks are extremely high, so maintenance activities, including connection of additional servers and replacement of failed units must be done without delay and without service disruption.
- One particularly disturbing circumstance to personnel who install servers is that inrush of electrical current into a server when initially plugged into a power supply oftentimes causes sparks at the level of a plug-in connection. Such sparks can be quite disturbing to the operators who install the servers and may also cause the accumulation of carbon deposits on connectors. The carbon deposits create undesired impedance on the connectors, causing of power losses and eventually causing failed connections to some servers. These carbon deposits may eventually lead to fire hazards.
- Thus, there is a desire for power supplies that address the aforementioned drawbacks.
- According to one aspect of the present technology, there is provided a circuit for powering a load, comprising: a voltage source; a transistor connected in series with the voltage source, the transistor further having a gate for turning on and off the transistor, the transistor being connectable in series with the load; a sensor of a load current, the sensor being adapted to emit a fault signal when the load current exceeds a first predetermined current value; a hardware latch adapted to set a latch signal when it receives the fault signal and to maintain the latch signal until it receives a rearm signal; and a logic circuit adapted to receive the latch signal from the hardware latch and to receive a software command for controlling turning on and off of the circuit, the logic circuit converting the software command to a control voltage for application at the gate of the transistor when the latch signal is not set.
- In some implementations of the present technology, the sensor of the load current comprises: a sense resistor connected in series with the transistor; and a current monitor emitting an output voltage proportional to a current flowing through the sense resistor.
- In some implementations of the present technology, the output voltage is sufficient to latch the hardware latch when the load current exceeds the first predetermined current value.
- In some implementations of the present technology, the latch signal is a status of the circuit, the latch signal being not set when the circuit has a normal status.
- In some implementations of the present technology, the logic circuit comprises: a combiner of the status of the circuit and of the software command; and a coupler of the logic circuit and of the transistor, the coupler being configured to cause the control voltage to be applied at the gate of the transistor.
- In some implementations of the present technology, the control voltage is a positive voltage to turn on the transistor, the circuit further comprising: a boost voltage source, a boost voltage of the boost voltage source being greater than a voltage of the voltage source; and a resistive divider connected to the boost voltage source, to the gate of the transistor, and to the coupler; wherein deactivation of the coupler causes the boost voltage to be applied at the gate of the transistor and turning on of the transistor; and wherein activation of the coupler causes a voltage applied at the gate to be less than the boost voltage and turning off of the transistor.
- In some implementations of the present technology, the circuit further comprises a microcontroller adapted to provide the software command for controlling turning on and off of the circuit.
- In some implementations of the present technology, the microcontroller is further adapted to provide the rearm signal.
- In some implementations of the present technology, the microcontroller is operatively connected to the sensor of the load current and is adapted to control turning off of the circuit when load current exceeds a second predetermined value, the second predetermined value being less than the first predetermined value.
- According to another aspect of the present technology, there is provided a system for powering multiple loads, comprising: a voltage source; one or more channels, each channel being configured for powering a respective load, each channel comprising: a transistor connected in series with the voltage, the transistor further having a gate for turning on and off the transistor, the transistor being connectable in series with the respective load, a sensor of a load current, the sensor being adapted to emit a fault signal when the load current exceeds a first predetermined current value, a hardware latch adapted to set a latch signal when it receives the fault signal and to maintain the latch signal until it receives a rearm signal, and a logic circuit adapted to receive the latch signal from the hardware latch and to receive a software command for controlling turning on and off of the transistor, the logic circuit converting the software command to a control voltage for application at the gate of the transistor when the latch signal is not set; and a microcontroller operatively connected to the hardware latch and to the logic circuit of each channel, the microcontroller being adapted to provide software commands for individually turning on and off the transistor of each channel and to provide rearm signals for individually resetting the hardware latch of each channel.
- In some implementations of the present technology, the microcontroller is adapted to individually receive the latch signal of each channel, the microcontroller interpreting the latch signal from a given channel as a normal status of the given channel when the latch signal is not set; the microcontroller is adapted to individually receive a measurement of a load voltage for each channel; and the microcontroller is adapted to individually receive a measurement of the load current for each channel
- In some implementations of the present technology, the one or more channels comprise a plurality of channels, the system further comprising: a first demultiplexer adapted to individually transmit the software commands to the logic circuit of each channel; and a second demultiplexer adapted to individually transmit the rearm signals to the hardware latches of each channel.
- In some implementations of the present technology, the system further comprises a first multiplexer adapted to individually receive the latch signal from each of the plurality of channels; a second multiplexer adapted to individually receive the measurement of the load voltage from each of the plurality of channels; and a third multiplexer adapted to individually receive the measurement of the load current from each of the plurality of channels.
- In some implementations of the present technology, the microcontroller is adapted to: detect the status of each individual channel; conditionally forward a software command to the logic circuit of a given channel for turning on the transistor of the given channel when the status of the given individual channel is normal.
- In some implementations of the present technology, the system further comprises a momentary switch operatively connected to the microcontroller, wherein the microcontroller is further adapted to: detect a rearm command form the momentary switch; detect that statuses of one or more of the plurality of channel are not normal; and forward a rearm signal to the one or more of the plurality of channels.
- The foregoing and other features will become more apparent upon reading of the following non-restrictive description of illustrative embodiments thereof, given by way of example only with reference to the accompanying drawings.
- Embodiments of the disclosure will be described by way of example only with reference to the accompanying drawings, in which:
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FIG. 1 is a highly schematic diagram of a circuit for switching on an off electrical supply to a load; -
FIG. 2 is a highly schematic diagram of a circuit for detecting attachment of a load and for gradually applying current to the load; -
FIG. 3 is an electrical diagram of a circuit for switching on and off electrical supply to a load, for example a computer or a server; -
FIG. 4 is schematic diagram of system for switching on and off electrical supply to a server of a server bank; -
FIG. 5 is timing diagram showing a variation of a voltage when the load is connected to the load connector; and -
FIG. 6 is zoomed in section of the timing diagram ofFIG. 5 . - Like numerals represent like features on the various drawings.
- Various aspects of the present disclosure generally address one or more of the problems found in conventional power supplies for large scale server networks. To this end, the present disclosure introduces a circuit for powering a load, this circuit being adapted for integration into a power supply.
- In a first embodiment, the circuit comprises a voltage source, a sense resistor, and a transistor connected in series with the voltage source and with the sense resistor. The load may be connected in series with the transistor. The transistor can be turned on and off by the application of a control voltage on its gate. A voltage across the sense resistor is sensed. Because the sense resistor is in series with the load, this voltage provides a direct indication of a level of current flowing in the load. The sensor emits a fault signal when the voltage across the sense resistor exceeds a predetermined value or, equivalently, then the current load exceeds a safe level, for example in the case of a short circuit at the load. The circuit includes a hardware latch that issues a latch signal when it receives the fault signal. The latch signal is maintained in the hardware latch even if the load current falls again to a safe value, or to zero. The latch signal is maintained until the hardware latch signal receives a rearm signal. A logic circuit is fed with the latch signal from the hardware latch and with a software command intended to control turning on and off of the circuit. The logic circuit converts the software command to a control voltage for application at the gate of the transistor when the latch signal is not set. In the circuit of this embodiment, the transistor is thus a “smart fuse” that is turned off to cut the flow of current into the load in case of a fault and that can be modulated by the software command to control a level of the current into the load in normal operation.
- In the same or another embodiment, the circuit for powering a load comprises a primary voltage source and a secondary voltage source. A primary transistor connects the primary voltage source to a load connector. A top resistor connects the secondary voltage source to a gate of the primary transistor while a bottom resistor is connected in parallel to the load connector. A secondary transistor is connected between the top resistor and the bottom resistor so that a drain of the secondary transistor is connected to the gate of the primary transistor. The circuit includes a translator of commands for turning on and off the circuit. The translator applies a high voltage at a gate of the secondary transistor when receiving an off command and a low voltage at the gate of the secondary transistor when receiving an on command. In the circuit, a microcontroller initially issues the off command, which is received at the translator, causing turning on of the secondary transistor and turning off of the primary transistor. The microcontroller receives a measurement of a voltage at the load connector. Initially, the voltage is defined by a resistive divider of the secondary voltage source, the resistive divider being formed by the top and bottom resistor. The microcontroller detects that the load is not connected to the load connector when the voltage at the load connector is at a high level while the off command is being issued. When the load is connected to the load detector, because its impedance is much lower than that of the bottom resistor, the microcontroller detects that the voltage at the load connector falls to a low level while the off command is being issued. The microcontroller may then issue the on command in response to the detection of the connection of the load. The on command may be issued in the form of an impulse, followed again by the off command, so that the primary transistor is only briefly turned on. The microcontroller may issue a sequence of such on command impulses so that the flow of current gradually increases in the load.
- Referring now to the drawings,
FIG. 1 is a highly schematic diagram of a circuit for switching on an off electrical supply to a load. Acircuit 10 includes avoltage source 12, aload 14, atransistor 16 having a drain (D) 18, a gate (G) 20 and a source (S) 22, and asense resistor 24. In thecircuit 10, thesense resistor 24, thetransistor 16 and theload 14 are connected in series between thevoltage source 12 and the ground (GND). Thetransistor 16 is turned on (i.e. closed) to allow current to flow from thevoltage source 12 through thesense resistor 24 and thedrain 18 and thesource 22 of thetransistor 16, reaching theload 14. Thetransistor 16 is turned on by the application at itsgate 20 of a voltage higher than a voltage at thesource 22, this voltage being an “ON” command for thetransistor 16. In more detail, thetransistor 16 is turned on when its gate to source voltage VGS is greater than a threshold voltage Vth for thetransistor 16. Application of a low voltage (an “OFF” command) at thegate 20, VGS being lower than Vth for thetransistor 16, turns off (i.e. opens) thetransistor 16 to prevent delivery of current to theload 14. - The ON/OFF command is applied at the
gate 20 by alogic circuit 26. Thelogic circuit 26 has two (2) inputs, i.e. a software ON/OFF command 28 from a microcontroller (shown in a later Figure) and alatch command 30. When thelatch command 30 is not set, thelogic circuit 26 converts the software ON/OFF command 28 into the high (ON) or low (OFF) voltage applied at thegate 20. - A voltage across the
sense resistor 24 is sensed by asensor 32. The sensed voltage is directly proportional to the current flowing through thesense resistor 24, thetransistor 16 and theload 14. When this current exceeds a predetermined safe value, the sensed voltage also exceeds a corresponding predetermined value. In that event, thesensor 32 sends afault signal 34 to ahardware latch 36. Thehardware latch 36 in turn provides thelatch command 30 to thecontrol logic circuit 26. As thelatch command 30 is set, thelogic circuit 26 ignores the software ON/OFF command 28 and applies a low (OFF) voltage at thegate 20, turning off thetransistor 16. - Although current no longer flows through the
sense resistor 24, thetransistor 16 and theload 14 when thetransistor 16 is turned off, thehardware latch 36 maintains thelatch command 30 until it receives a rearmcommand 38. Thelatch command 30 is removed when the rearmcommand 38 is received at thehardware latch 36, following which thelogic circuit 26 can once again convert the software ON/OFF command 28 into the high (ON) or low (OFF) voltage applied at thegate 20. - The
circuit 10 therefore implements a smart fuse in the sense that thetransistor 16 can rapidly react, under hardware control, in case of excessive current flowing through theload 14, for example in case of a short circuit. This smart fuse can be rearmed by the rearmsignal 38. In normal operation of thecircuit 10, when thelatch command 30 is not set, the ON/OFF command 28 from the microcontroller may be used to turn on or off the delivery of power to theload 14 and may further be used to control the amount of current into theload 14 by turning on and off thetransistor 16 in rapid cycles. -
FIG. 2 is a highly schematic diagram of a circuit for detecting attachment of a load and for gradually applying current to the load. A circuit 50 may optionally be combined in a same implementation with thecircuit 10 ofFIG. 1 , but is shown in isolation in order to simplify the illustration ofFIG. 2 . The circuit 50 includes aprimary voltage source 52 and asecondary voltage source 54, also called a boost voltage source because its voltage is higher than that of theprimary voltage source 52. Aprimary transistor 56, for example a metal oxide semiconductor field effect transistor (MOSFET), such as an n-channel MOSFET (NMOS) having adrain 58, agate 60 and asource 62, is connected to theprimary voltage source 52 and to aconnector 64 having a pair of ports for eventually connecting aload 66. Atop resistor 68 is connected to thesecondary voltage source 54, to thegate 60 of theprimary transistor 56, and to a collector (C) 70 of asecondary transistor 72, for example a bipolar transistor. Thesecondary transistor 72 also has a base (B) 74 and an emitter (E) 76. Theemitter 76 of thesecondary transistor 72 is connected to abottom resistor 78, to thesource 62 of theprimary transistor 56, and to a positive end of theconnector 64. - A
microcontroller 80 applies a software ON/OFF command 82 to atranslator 84. Thesoftware command 82 is a logical 1 to turn ON the circuit 50 and a logical 0 to turn OFF the circuit 50. - The
translator 84 outputs a negative version of the software ON/OFF command, the ON command being translated into a low voltage applied on thebase 74 of thesecondary transistor 72 and the OFF command being translated into a high voltage applied on thebase 74 of thesecondary transistor 72. - When the software ON/
OFF command 82 requires turning off of the circuit 50, a high voltage is applied at thebase 74 of thesecondary transistor 72. This high voltage turns on thesecondary transistor 72, whereby the voltage at itscollector 70 and at thegate 60 of theprimary transistor 56 becomes substantially equal to the voltage at thesource 62 of theprimary transistor 56, neglecting a small voltage drop between thecollector 70 and theemitter 76 of thesecondary transistor 72. The voltages at thegate 60 and at thesource 62 of theprimary transistor 56 being substantially equal, VGS is near zero and is less than Vth for theprimary transistor 56. Theprimary transistor 56 is therefore turned off. At the time, if theload 66 is not connected, the voltage at thesource 62 of theprimary transistor 56, which is also the voltage at theload connector 64, is defined by the voltage of thesecondary voltage source 54 and a resistive divider formed by thetop resistor 68 and thebottom resistor 78. If theload 66 is then connected, because it usually has a much lower impedance than that of thetop resistor 68 and of thebottom resistor 78, the voltage at theload connector 64 falls to nearly zero volt. - Conversely, when the software ON/
OFF command 82 requires turning on the circuit 50, this command is translated by thetranslator 84 into the low voltage applied at thebase 74 of thesecondary transistor 72. This low voltage turns off thesecondary transistor 72, whereby the voltage at itscollector 70, which is also the voltage at thegate 60 of theprimary transistor 56, becomes equal to the voltage of thesecondary voltage source 54. The voltage of thesecondary voltage source 54 being higher than the voltage of theprimary voltage source 52, the gate to source voltage VGS of theprimary transistor 56 is positive, no matter the voltage at thesource 62 of theprimary transistor 56 at that time. In the example as shown, theprimary transistor 56 is an NMOS transistor so the positive gate to source voltage VGS causes turning on of thetransistor 56, whereby the voltage at itssource 62 becomes substantially equal to the voltage of theprimary voltage source 52. It will be understood that the voltage of thesecondary voltage source 54 is selected to be higher than the voltage of theprimary voltage source 52 by a sufficient amount to ensure that VGS will be greater than Vth for theprimary transistor 56 when thesecondary transistor 72 is turned off. - When the software ON/
OFF command 82 is “OFF”, the high voltage applied at the base 74 causes closing (turning on) of thesecondary transistor 72. If theload 66 is not connected to theconnector 64, the voltage of thegate 60 and thesource 62 of theprimary transistor 56 is an intermediate voltage defined by thesecondary voltage source 54 and by the resistive divider formed by theresistors primary transistor 56 being near zero, theprimary transistor 56 is open. Avoltage measurement 86 taken between theresistors microcontroller 80. Connecting theload 66 to theconnector 64 at that time causes the voltage at thegate 60 and thesource 62 of theprimary transistor 56 to decrease significantly to a low voltage because theload 66 has a much lower impedance than that of theresistor 78. This drop of thevoltage measurement 86 is detected at themicrocontroller 80 as an indication that theload 66 is now connected to the circuit 50. - Thereafter, the
microcontroller 80 changes the software ON/OFF command 82 to “ON”, causing a low voltage to be applied at the base and causing opening of thesecondary transistor 72. The voltage of thesecondary voltage source 54 is now directly applied at thegate 60 of theprimary transistor 56. Thegate 60 of theprimary transistor 56 now being at a high voltage, thetransistor 56 becomes conductive because VGS is now greater than Vth. Current may flow from theprimary voltage source 52 though theprimary transistor 56 and into theload 66. The voltage at thesource 62 of theprimary transistor 56 is now substantially equal to the voltage of theprimary voltage source 52, neglecting for a minor voltage drop between thedrain 58 and thesource 62 of the primary transistor. VGS is substantially equal to the voltage of the secondary (boost)voltage source 54 minus the voltage of theprimary voltage source 52. As will be expressed hereinbelow, themicrocontroller 80 may rapidly cycle the software ON/OFF command 82 between the ON and OFF positions, at least for a brief initial period after the connection of theload 66, to control the inrush of current into theload 66 when theload 66 is initially plugged in at theconnector 64. Themicrocontroller 80 may continuously monitor thevoltage measurement 86 on theload 66. - A practical implementation of the
circuits 10 and 50 ofFIGS. 1 and 2 is shown onFIG. 3 , which is an electrical diagram of a circuit for switching on and off electrical supply to a load, for example a computer or a server. Acircuit 100 includes a high sidecurrent monitor 110, a quad 2-inputNAND Schmitt trigger 130, anoptocoupler 210, which is a secondary transistor for thecircuit 100, aMOSFET switch 220, which is a primary transistor for thecircuit 100, a 5-volt source 180, aload voltage source 182 providing for example 19 volts, aboost voltage source 184 providing for example 31 volts, which translates into a 12-volt boost over the voltage of theload voltage source 182, and aload connector 230. Thecircuit 100 also comprises various signal input ports, resistors, diodes, Zener diodes and capacitors that are described in the following paragraphs. Values shown onFIG. 3 for the various resistors, capacitors, including their tolerances, and for illustration purposes and do not limit the present disclosure. TheMOSFET switch 220 operates as a smart fuse, as will be explained hereinbelow. Afreewheeling diode 221 is mounted in parallel to theMOSFET switch 221 to eliminate any eventual voltage spikes that might occur when turning on and off theMOSFET switch 220, for example when an inductive load is plugged in theload connector 230. - In normal operation of the
circuit 100, the load, for example the server or computer, is connected to theload connector 230. Power to the load is from theload voltage source 182 and transmitted via theMOSFET switch 220, which may also be called a high side switch, to ports 3 and/or 4 of theload connector 230,ports 1 and/or 2 of theload connector 230 providing a ground connection for the server. - Current flowing from the
load voltage source 182 through theMOSFET switch 220 and through the server also flows through asense resistor 112. Thesense resistor 112 has a very low impedance, for example 10−3 ohm to maintain power consumed in thesense resistor 112 at a negligible level. A voltage Vsense across thesense resistor 112 is detected by the high sidecurrent monitor 110, between its input 114 (marked “IN”) and its sense amplifier input 116 (marked “LOAD”). The high sidecurrent monitor 110 has a gain defined by atransconductance resistor 118 connected between the higher voltage side of the sense resistor 112 (marked “+”) and a transconductance input 120 (marked “RA”) of the high sidecurrent monitor 110. Without limitation, thetransconductance resistor 118 has an impedance of 100 ohms, the transconductance gain of the high sidecurrent monitor 110 being 10−2 mho. The high sidecurrent monitor 110 has aground connection 122 and anoutput 124. A current Iout flowing from theoutput 124 is equal to the voltage across thesense resistor 112 multiplied by the transconductance gain of the high sidecurrent monitor 110. For example, when a load current of 10 amperes flows through the sense resistor 112 (as well as through theMOSFET switch 220 and the server connected to the connector 230), Vsense is equal to 10−2 volt the current Iout is at 10−4 ampere. The current Iout generates a voltage Vout across a resistor RB formed of a series combination ofresistors - The quad 2-input
NAND Schmitt trigger 130 is powered by the 5-volt source 180 and is also connected to the ground.Capacitors volt source 180, which might otherwise vary in operation of the quad 2-inputNAND Schmitt trigger 130. The quad 2-inputNAND Schmitt trigger 130 includes four (4)NAND gates - The voltage Vout is also present at an
input 138 of theNAND gate 136, being filtered by aresistor 168 and acapacitor 169. When Vout exceeds a trigger voltage for theNAND gate 136, for example in case of a fault such as a short circuit in the load connected to theload connector 230, Vout becomes a logical 1 applied at theinput 138. Vout can therefore be understood as a logical signal for indicating that the load current exceeds a predetermined value when Vout exceeds that trigger voltage. It may be noted that because theNAND gate 136 is a Schmitt-Trigger, slight variations of Vout will not cause oscillations at theoutput 142 of theNAND gate 136. The values of thesense resistor 112, of thetransconductance resistor 118, and of the resistor RB formed of the series combination ofresistors NAND gate 136 when the load current reaches a maximum desired value. In an implementation, these elements may be selected so that Vout only reaches the trigger voltage for theNAND gate 136 in case of a severe fault, for example in case of a short-circuit at the load. - Another
input 140 of theNAND gate 136 is aninput port 170 on which a rearm signal may be received for rearming thecircuit 100. When the ream signal is a logical 1 while Vout exceeds the trigger voltage for theNAND gate 136, anoutput 142 of theNAND gate 136 is a logical 0. Theoutput 142 of theNAND gate 126 is a logical 1 when Vout does not exceed the trigger voltage (the load current being within the intended range) and/or when the rearm signal is a logical 0. - The
NAND gates 144 and 152 are combined into a NAND-gate latch. A first input of the NAND-gate latch is theoutput 142 of theNAND gate 136, applied to aninput 146 of the NAND gate 144. A second input of the NAND-gate latch is the rearm signal from theinput port 170, applied to aninput 156 of theNAND gate 152. Anoutput 150 of the NAND gate 144 is applied at aninput 154 of theNAND gate 152 while anoutput 158 of theNAND gate 152 is applied to aninput 148 of the NAND gate 144, completing the NAND-gate latch. Theoutput 158 of theNAND gate 152 is the overall output of the NAND-gate latch and, at the same time, represents a status of thecircuit 100. This status is a logical 1 under normal conditions, when the current flowing through the load is within the intended range, Vout not exceeding the trigger voltage. At that time, the value of the rearm signal from theinput port 170 has no impact on theoutput 158. When Vout increases and becomes a logical 1, the status of thecircuit 100 becomes a logical 0, as long as the rearm signal is also a logical 1. The status of thecircuit 100 may be reset to become a logical 1 again by temporarily setting the rearm signal to a logical 0. - A software command Q0 from an
input port 172 is set to a logical 1 to turn on theMOSFET switch 220 or to a logical 0 to turn off theMOSFET switch 220. The software command Q0 provides ON and OFF commands to thecircuit 100, to control the application of current to the load on theload connector 230. The software command Q0 is applied to aninput 164 of theNAND gate 160. Theoutput 158 from the NAND gate 152 (which is also the output from the NAND-gate latch, i.e. the status of the circuit 100) is applied to aninput 162 of theNAND gate 160. Anoutput 166 of theNAND gate 160 is determined as follows: If the NAND-gate latch is latched to provide a logical 0, resulting from Vout having exceeded the trigger voltage of theNAND gate 136, theoutput 166 of theNAND gate 160 is a logical 1 and will remain as such until the rearm signal is set to a logical 0, at least temporarily. Otherwise, if the NAND-gate latch is latched to provide a logical 1, which is a normal circumstance, theNAND gate 160 translates the software command Q0, providing a logical inverse of the software command Q0 at its theoutput 166, so that theoutput 166 is a logical 0 when the software command Q0 is a logical 1, and vice-versa. TheNAND gate 160 therefore combines effects of the software command Q0 and of the status of thecircuit 100. - The
output 166 of theNAND gate 160 is connected to a resistive divider formed ofresistors 174 and 176 that connect the 5-volt source 180 to aninput 212 of theoptocoupler 210. Provided that the NAND-gate latch provides a logical 1 while the software command Q0 is set to 1, theoutput 166 of theNAND gate 160 is set to 0, which translates into a low voltage present within between theresistors 174 and 176. Current flowing through the resistor 174 and theNAND gate 160 turns on a light emitting diode (LED) 175 to provide a visual indication that thecircuit 100 is turned on. ALED 214 integrated in theoptocoupler 210 is de-energized, whereby aphototransistor 216 of theoptocoupler 210 is turned off and becomes an open circuit. A voltage from theboost voltage source 184 is substantially present at a gate 222 of theMOSFET switch 220. This boost voltage being selected to be higher by at least a threshold voltage of theMOSFET source 220 than any voltage present at thesource 226 of theMOSFET switch 220 at that time, theMOSFET switch 220 becomes conductive. Current may flow from theload voltage source 182 through thesense resistor 112, theMOSFET switch 220 and the load connected to theload connector 230. It may be observed that a resistance between adrain 224 and asource 226 of theMOSFET switch 220 is very low, typically in the order of 10−2 ohm when theMOSFET switch 220 is turned-on, so any amount of power consumed in theMOSFET switch 220 is negligible. - When, however, the
output 166 of theNAND gate 160 is set to 1, whether because the software command Q0 is set to 0 or because the NAND-gate latch provides a logical 0, a high voltage is present at theoutput 166 of theNAND gate 160, between theresistors 174 and 176. Current no longer flows through theLED 175, which is turned off to provide a visual indication that thecircuit 100 is no longer providing power to the load. TheLED 214 of theoptocoupler 210 is energized, whereby thephototransistor 216 is turned on and becomes conductive. The gate 222 and thesource 226 of theMOSFET switch 220 are now connected via aresistor 190. No significant current flows through theresistor 190, which means that the voltage at the gate 222 is essentially the same as the voltage at thedrain 226. Its gate to source voltage being about zero, theMOSFET switch 220 is then turned off and non-conductive, preventing the flow of current between theload voltage source 182 and theload connector 230. - It may be observed that while another type of secondary transistor may be used, the
optocoupler 210 provides voltage isolation components of thecircuit 100 powered by the 5-volt source 180 and other components of thecircuit 100 powered by theload voltage source 182 and theboost voltage source 184. - Overvoltage protection for the load and the
MOSFET switch 220 is implemented as follows. A voltage on the load connected to theconnector 230 is limited by aZener diode 192, for example a 60-volt diode, that will become conductive if that voltage becomes excessive. Likewise, regardless of the voltage at theboost voltage source 182 and the voltage at thesource 226 of theMOSFET switch 220 at any given time, the gate 222 to source 226 voltage of theMOSFET switch 220 is limited by the presence of aZener diode 194, for example a 10-volt diode, placed between the gate 222 and thesource 226. - A measure of a voltage applied on the load when the
MOSFET switch 220 is conductive is available at anoutput port 196. This measure is not a direct value of the voltage applied on the load because it is obtained from a voltage divider formed of theresistors load voltage source 182 is a 48-volt source, theresistors output port 196 is about 4.5 volts. The measure applied at theoutput port 196 is in any case directly proportional to the actual load voltage. Likewise, a measure of the current flowing through the load is available at anoutput port 198. The load current is sensed by reading a fraction of Vout, sensed betweenresistors resistors output port 198 within a safe voltage range for equipment connected to theoutput port 198. A status of thecircuit 100, which is theoutput 158 of theNAND gate 152, is available and anoutput port 200. Signals from theoutput ports circuit 100 to a microcontroller (shown in a later Figure), the microcontroller providing the software command Q0 available at theinput port 172. -
FIG. 4 is schematic diagram of system for switching on and off electrical supply to a server of a server bank. Asystem 250 is adapted to provide power to a bank of 24 servers over 24 distinct channels. Variants of thesystem 250 may provide power to a single server over a single channel or to any other number of servers over any number of channels. Each channel includes a copy of thecircuit 100 ofFIG. 3 . Each channel operates independently from the other channels. Within thecircuit 100, theZener diodes voltage protection module 240. Control applied at the gate 222 of theMOSFET switch 220 is schematically represented as an ON/OFF command 242. The various other components of thecircuit 100 are schematically represented as a converter andlogic module 244. - The
load voltage source 182 is supplied by apower bus bar 252 that is, in turn, connected to an AC to DC converter (not shown) and to batteries (not shown). The 5-volt source 180 and boostvoltage source 184 are supplied by asupply bus 254, which is connected to a DC to DC converter (not shown) that converts the load voltage to a 5-volt supply and to a boost-voltage supply. Theinput ports output ports control bus 256. - The
system 250 includes amicrocontroller 270 that is indirectly powered by the 5-volt source 180 via avoltage converter 271 that supplies 3.3 volts to themicrocontroller 270. Themicrocontroller 270 communicates with the 24 instances of thecircuit 100 via multiplexers and 272, 274 and 276 and viademultiplexers volt source 180. Each multiplexer and demultiplexer has 24 distinct ports configured to communicate with each of the 24 instances of thecircuit 100. In an embodiment having a single channel and asingle circuit 100, themicrocontroller 270 may communicate directly with the ports of thecircuit 100 without using any multiplexer or demultiplexer. - A
momentary switch 258 is connected to thecontrol bus 256 and may be manually actuated to provide a rearmcommand 260 that is directly applied to themicrocontroller 270. Themicrocontroller 270 is aware of the status of allcircuits 100, the status of eachcircuit 100 being transmitted by theoutput port 200 and received at themicrocontroller 270 via themultiplexer 276. Themicrocontroller 270 translates the rearmcommand 260 into the rearm signal applied at a givencircuit 100 whose status indicates a fault. The rearm signal is sent by themicrocontroller 270 via thedemultiplexer 280 and via theinput port 170 of the givencircuit 100. Themicrocontroller 270 may also initiate sending of the rearm signal without manual action of themomentary switch 258, based for example on its internal programming or based a command received at aninput 282 of themicrocontroller 70 from an external source (not shown). - Programming and monitoring of the
microcontroller 270 is made by external components (not shown) connected to theinput 282 of themicrocontroller 70. Themicrocontroller 270 may communicate with the same or other external components via anoutput 284. Details of programming and monitoring of themicrocontroller 270 are outside the scope of the present disclosure. - Considering a
first channel 1 of 24 and itscircuit 100, the measured voltage available at theoutput port 196, which is representative of the voltage applied to the load of thecircuit 100, is received at themultiplexer 272. The measured load current available at theoutput port 198 is received at themultiplexer 274. The status of thecircuit 100 available at theoutput port 200 is received at themultiplexer 276. These signals from thecircuit 100 are provided by themultiplexers - The
microcontroller 270 issues the ON/OFF commands and the rearm signal, via thedemultiplexers input ports circuit 100, respectively. - The
system 250 has various modes of operation. - When a computer, a server or a similar load is connected to, and energized by, the
circuit 100 of a given channel via theload connector 230, in normal operation, themicrocontroller 270 may issue a continuous ON command via thedemultiplexer 278, this ON command being available at theinput port 172 of thecircuit 100. The status of thecircuit 100 being normal (a logical 1 is present at theoutput 158 of the NAND gate 152), theoptocoupler 210 is turned off and theMOSFET switch 220 is turned on, allowing current to be delivered to the load. The current load is constantly monitored by the high sidecurrent monitor 110. If the current exceeds a first predetermined value, for example in case of a short circuit on the load, the voltage Vout increases and causes the NAND-gate latch to change its output—which is also the status of thecircuit 100—to a logical 0, causing the opening of theMOSFET switch 220, effectively removing power from the server or other load connected to theload connector 230. This disconnection is made via hardware only, without intervention from themicrocontroller 270, and is therefore extremely quick, for example in the order of 100 nanoseconds (ns). Thereafter, the NAND-gate latch remains in the same state until the rearm signal is received at theinput port 170. - When the server or other load is connected to, and energized by, the
circuit 100, themicrocontroller 270 may continuously monitor the load voltage and/or the load current via the signals available at theoutput ports microcontroller 270 by themultiplexers microcontroller 270 may detect that the load current is reaching a critical level, exceeding a second predetermined value that, while lower than the first predetermined value, may still be considered as a warning by themicrocontroller 270. Themicrocontroller 270 may cause thedemultiplexer 278 to send ON and OFF commands in rapid cycles, causing the opening and closing of theMOSFET switch 220, in turn causing a reduction of the effective voltage and current flowing through the load. Themicrocontroller 270 may alternatively initiate sending of a continuous OFF command in order to remove all power from the server or other load. - When the load is initially connected by plugging a jack (not shown) into the
load connector 230, current flowing through theload connector 230 and the load might increase very rapidly and cause a spark between the jack and theload connector 230. This spark can be quite disturbing to the operator who connects the jack to theload connector 230 and may also cause the accumulation of carbon deposits on the ports of theload connector 230. In an aspect, thesystem 250 may implement an anti-sparking mechanism to control an initial level of current flowing through theload connector 230 when a load is initially connected. The following paragraphs describe an anti-sparking mechanism. - When the
circuit 100 of a given channel is initially energized while no load is connected to theload connector 230, themicrocontroller 270 causes the application of an OFF command on theinput port 172 of thecircuit 100, causing the turning on of theoptocoupler 210 and the turning off of theMOSFET switch 220. Theoutput ports circuit 100 respectively indicate to themicrocontroller 270 that the load current is null, and that the status of thecircuit 100 is normal. Theoutput port 196 indicates to themicrocontroller 270 that the voltage available at theload connector 230 is defined by theboost voltage source 184 and by a resistive divider formed by theresistors load connector 230 is slightly lower than the voltage of the boost voltage source. Respective values of theresistors output port 196 within a safe voltage range for themultiplexer 272. - Thereafter, when the load is initially connected by plugging a jack into the
load connector 230, because the load has a much lower impedance than that of theresistors load connector 230 falls almost to zero volt. This information is detected at themicrocontroller 270 via theoutput port 196 and themultiplexer 272, themicrocontroller 270 being thus informed of the connection of a load to thecircuit 100. Themicrocontroller 270 causes sending of a very brief ON command, or impulse, via thedemultiplexer 278 to theinput port 172 of thecircuit 100, this very brief ON command being immediately followed by an OFF command. For this brief period, theoptocoupler 210 is turned off, leading to turning on of theMOSFET switch 220, the appearance of the voltage from theload voltage source 182 at thesource 226 of theMOSFET switch 220 and the application of the same voltage to theload connector 230 and to the load. These initial brief ON and OFF commands are rapidly followed by a succession of other similar impulses applied by themicrocontroller 270 to theinput port 172 of thecircuit 100, whereby current is progressively and increasingly applied to the load. In a non-limiting example, the first and second such impulses may be separated in time by a 100 millisecond (ms) delay, following which up to 20 impulses may be applied in an eight (8) ms period. As soon as themicrocontroller 270 detects that the voltage at theload connector 230 reaches the value of theload voltage source 182 while the load current reaches the expected value for the load, the ON command becomes a continuous command. -
FIG. 5 is a timing diagram showing a variation of a voltage when the load is connected to the load connector. Achart 300 shows a variation of the voltage between the ports 3 and/or 4 of theload connector 230 and theports 1 and/or 2 of theload connector 230, the latter ports being connected to the ground. Voltage values and timing values shown onFIG. 5 are solely for illustration purposes and do not limit the present disclosure. Initially, at 0 ms, no load is connected to theload connector 230. Aninitial voltage 310 at theload connector 230 is defined at least in part by the voltage of theboost voltage source 184 and by a resistive divider formed on one hand by theresistor 178 and on the other hand by a sum of theresistors voltage 310, sampled between theresistors output port 196. - At 100 ms, a load is plugged in the
load connector 230. The load being placed in parallel with theresistor 186 placed in series with theresistor 188, the load having a much lower impedance than the sum of theresistors resistor 178 and the load causes the voltage at theload connector 230 to fall to a muchlower value 320. A sample of thatvalue 320 is provided at theoutput port 196. - The
microcontroller 270 detects the voltage drop at theoutput port 196. After a delay to ensure that the load remains connected, for example about 840 ms, themicrocontroller 270 starts issuing software commands Q0, received at theinput port 172 of thecircuit 100, causing the closing of theMOSFET switch 220. -
FIG. 6 is zoomed in section of the timing diagram ofFIG. 5 . Asection 330 of the diagram 300 extends from about 838 ms to about 851 ms. At 840 ms, themicrocontroller 270 causes the application of very brief software command Q0, which is set to 1, causing the closing of theMOSFET switch 220 for a very brief moment (much like a Dirac impulse 340). A number of successivesimilar impulses 340, for example three (3) additional impulses, are issued by themicrocontroller 270, for example at about 0.7 ms intervals. In the illustration ofFIGS. 5 and 6 , the load has a large capacitive component, so each brief instances of closing theMOSFET switch 220 causes the accumulation of charges in the load, whereby the voltage at theload connector 230 increases gradually to avalue 350. Themicrocontroller 270 detects a corresponding increase of the voltage sampled at theoutput port 196. Because the voltage at theload connector 230 is increasing normally, themicrocontroller 270 issues a number ofadditional impulses 360 that are applied to thecircuit 100 to close theMOSFET switch 220 in rapid succession, for example at about 0.2 ms intervals. The voltage at theload connector 230 eventually reaches anominal value 370 that is interpreted by themicrocontroller 270 as an indication that the voltage and current are building normally in the load. Themicrocontroller 270 now issues a continuous software command Q0, which is set to 1, causing theMOSFET switch 220 to remain closed. The voltage at theload connector 230 eventually reaches a nominal value 380 (FIG. 5 ), which is substantially equal to the voltage of theload voltage source 182. - Those of ordinary skill in the art will realize that the description of the circuit and system implementing the smart fuse and the power supply configured for preventing sparks are illustrative only and are not intended to be in any way limiting. Other embodiments will readily suggest themselves to such persons with ordinary skill in the art having the benefit of the present disclosure. Furthermore, the disclosed circuit and system may be customized to offer valuable solutions to existing needs and problems related to power consumption and sparking found in conventional power supplies. In the interest of clarity, not all of the routine features of the implementations of the circuit and system are shown and described. In particular, combinations of features are not limited to those presented in the foregoing description as combinations of elements listed in the appended claims form an integral part of the present disclosure. It will, of course, be appreciated that in the development of any such actual implementation of the circuit and system, numerous implementation-specific decisions may need to be made in order to achieve the developer's specific goals, such as compliance with application-, system-, and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the field of electronic power supplies having the benefit of the present disclosure.
- In accordance with the present disclosure, the components, process operations, and/or data structures described herein may be implemented using various types of operating systems, computing platforms, network devices, computer programs, and/or general purpose machines. In addition, those of ordinary skill in the art will recognize that devices of a less general purpose nature, such as hardwired devices, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), or the like, may also be used.
- Systems and modules described herein may comprise software, firmware, hardware, or any combination(s) of software, firmware, or hardware suitable for the purposes described herein. Software and other modules may be executed by a processor and reside on a memory of servers, workstations, personal computers, computerized tablets, personal digital assistants (PDA), and other devices suitable for the purposes described herein. Software and other modules may be accessible via local memory, via a network, via a browser or other application or via other means suitable for the purposes described herein. Data structures described herein may comprise computer files, variables, programming arrays, programming structures, or any electronic information storage schemes or methods, or any combinations thereof, suitable for the purposes described herein.
- The circuit and system implementing the smart fuse implemented in accordance with some non-limiting embodiments of the present technology can be represented as follows, presented in numbered clauses.
-
- [Clause 1] A circuit for powering a load, comprising:
- a voltage source;
- a transistor connected in series with the voltage source, the transistor further having a gate for turning on and off the transistor, the transistor being connectable in series with the load;
- a sensor of a load current, the sensor being adapted to emit a fault signal when the load current exceeds a first predetermined current value;
- a hardware latch adapted to set a latch signal when it receives the fault signal and to maintain the latch signal until it receives a rearm signal; and
- a logic circuit adapted to receive the latch signal from the hardware latch and to receive a software command for controlling turning on and off of the circuit, the logic circuit converting the software command to a control voltage for application at the gate of the transistor when the latch signal is not set.
- [Clause 2] The circuit of
clause 1, wherein the sensor of the load current comprises:- a sense resistor connected in series with the transistor; and
- a current monitor emitting an output voltage proportional to a current flowing through the sense resistor.
- [Clause 3] The circuit of
clause 2, wherein the output voltage is sufficient to latch the hardware latch when the load current exceeds the first predetermined current value. - [Clause 4] The circuit of any one of
clauses 1 to 3, further comprising a microcontroller adapted to provide the software command for controlling turning on and off of the circuit. - [Clause 5] The circuit of clause 4, wherein the microcontroller is further adapted to provide the rearm signal.
- [Clause 6] The circuit of
clause 4 or 5, wherein the microcontroller is operatively connected to the sensor of the load current and is adapted to control turning off of the circuit when load current exceeds a second predetermined value, the second predetermined value being less than the first predetermined value. - [Clause 7] The circuit of any one of
clauses 1 to 6, wherein the latch signal is a status of the circuit, the latch signal being not set when the circuit has a normal status. - [Clause 8] The circuit of clause 7, wherein the logic circuit comprises:
- a combiner of the status of the circuit and of the software command; and
- a coupler of the logic circuit and of the transistor, the coupler being configured to cause the control voltage to be applied at the gate of the transistor.
- [Clause 9] The circuit of clause 8, wherein the control voltage is a positive voltage to turn on the transistor.
- [Clause 10] The circuit of clause 9, further comprising:
- a boost voltage source, a boost voltage of the boost voltage source being greater than a voltage of the voltage source; and
- a resistive divider connected to the boost voltage source, to the gate of the transistor, and to the coupler;
- wherein deactivation of the coupler causes the boost voltage to be applied at the gate of the transistor and turning on of the transistor; and
- wherein activation of the coupler causes a voltage applied at the gate to be less than the boost voltage and turning off of the transistor.
- [Clause 11] The circuit of
clause 10, wherein activation of the coupler effectively connects the gate of the transistor to a source of the transistor. - [Clause 12] The circuit of any one of clauses 8 to 11, wherein the coupler is an optocoupler
- [Clause 13] The circuit of any one of
clauses 1 to 12, wherein the transistor is a metal oxide semiconductor field effect transistor. - [Clause 14] A system for powering multiple loads, comprising:
- a voltage source;
- one or more channels, each channel being configured for powering a respective load, each channel comprising:
- a transistor connected in series with the voltage, the transistor further having a gate for turning on and off the transistor, the transistor being connectable in series with the respective load,
- a sensor of a load current, the sensor being adapted to emit a fault signal when the load current exceeds a first predetermined current value,
- a hardware latch adapted to set a latch signal when it receives the fault signal and to maintain the latch signal until it receives a rearm signal, and
- a logic circuit adapted to receive the latch signal from the hardware latch and to receive a software command for controlling turning on and off of the transistor, the logic circuit converting the software command to a control voltage for application at the gate of the transistor when the latch signal is not set; and
- a microcontroller operatively connected to the hardware latch and to the logic circuit of each channel, the microcontroller being adapted to provide software commands for individually turning on and off the transistor of each channel and to provide rearm signals for individually resetting the hardware latch of each channel.
- [Clause 15] The system of
clause 14, wherein the microcontroller is adapted to individually receive the latch signal of each channel, the microcontroller interpreting the latch signal from a given channel as a normal status of the given channel when the latch signal is not set. - [Clause 16] The system of
clause - [Clause 17] The system of any one of
clauses 14 to 16, wherein the microcontroller is adapted to individually receive a measurement of the load current for each channel - [Clause 18] The system of clause 17, wherein the one or more channels comprise a plurality of channels, the system further comprising:
-
- a first demultiplexer adapted to individually transmit the software commands to the logic circuit of each channel; and
- a second demultiplexer adapted to individually transmit the rearm signals to the hardware latches of each channel.
- [Clause 19] The system of
clause 18, further comprising:- a first multiplexer adapted to individually receive the latch signal from each of the plurality of channels;
- a second multiplexer adapted to individually receive the measurement of the load voltage from each of the plurality of channels; and
- a third multiplexer adapted to individually receive the measurement of the load current from each of the plurality of channels.
- [Clause 20] The system of clause 19, wherein the microcontroller is adapted to:
- detect the status of each individual channel;
- conditionally forward a software command to the logic circuit of a given channel for turning on the transistor of the given channel if the status of the given individual channel is normal.
- [Clause 21] The system of
clause 19 or 20, further comprising a momentary switch operatively connected to the microcontroller, wherein the microcontroller is further adapted to:- detect a rearm command form the momentary switch;
- detect that statuses of one or more of the plurality of channel are not normal; and
- forward a rearm signal to the one or more of the plurality of channels.
- The present disclosure has been described in the foregoing specification by means of non-restrictive illustrative embodiments provided as examples. These illustrative embodiments may be modified at will. The scope of the claims should not be limited by the embodiments set forth in the examples, but should be given the broadest interpretation consistent with the description as a whole.
Claims (15)
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EP17315014.5 | 2017-12-13 | ||
EP17315014.5A EP3499669A1 (en) | 2017-12-13 | 2017-12-13 | Circuit and system implementing a smart fuse for a power supply |
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US20190181862A1 true US20190181862A1 (en) | 2019-06-13 |
US10511307B2 US10511307B2 (en) | 2019-12-17 |
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FR3140720A1 (en) * | 2022-10-07 | 2024-04-12 | Stmicroelectronics (Rousset) Sas | Method and circuit for powering up an electrical circuit |
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Also Published As
Publication number | Publication date |
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EP3499669A1 (en) | 2019-06-19 |
CN110034534A (en) | 2019-07-19 |
CA3025548A1 (en) | 2019-06-13 |
US10511307B2 (en) | 2019-12-17 |
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