US20190164759A1 - Methods for controlling an end-to-end distance in semiconductor device - Google Patents
Methods for controlling an end-to-end distance in semiconductor device Download PDFInfo
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- US20190164759A1 US20190164759A1 US15/923,072 US201815923072A US2019164759A1 US 20190164759 A1 US20190164759 A1 US 20190164759A1 US 201815923072 A US201815923072 A US 201815923072A US 2019164759 A1 US2019164759 A1 US 2019164759A1
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- 238000000034 method Methods 0.000 title claims abstract description 211
- 239000004065 semiconductor Substances 0.000 title claims description 36
- 230000008569 process Effects 0.000 claims abstract description 147
- 238000000059 patterning Methods 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 234
- 239000000758 substrate Substances 0.000 claims description 106
- 238000010884 ion-beam technique Methods 0.000 claims description 73
- 239000011229 interlayer Substances 0.000 claims description 47
- 229920002120 photoresistant polymer Polymers 0.000 claims description 36
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000000605 extraction Methods 0.000 description 22
- 239000007789 gas Substances 0.000 description 22
- 239000003989 dielectric material Substances 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 229910052814 silicon oxide Inorganic materials 0.000 description 16
- 239000000463 material Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 230000009969 flowable effect Effects 0.000 description 12
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 9
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 9
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 7
- 239000011737 fluorine Substances 0.000 description 7
- 229910052731 fluorine Inorganic materials 0.000 description 7
- 238000002955 isolation Methods 0.000 description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 5
- WMIYKQLTONQJES-UHFFFAOYSA-N hexafluoroethane Chemical compound FC(F)(F)C(F)(F)F WMIYKQLTONQJES-UHFFFAOYSA-N 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- -1 spin-on glass (SOG)) Chemical compound 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- OJSVTCYWZNVKRV-UHFFFAOYSA-N [N].FC(F)(F)C(F)(F)F Chemical compound [N].FC(F)(F)C(F)(F)F OJSVTCYWZNVKRV-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 3
- 229910052801 chlorine Inorganic materials 0.000 description 3
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 3
- 239000002243 precursor Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910021324 titanium aluminide Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- YBMDPYAEZDJWNY-UHFFFAOYSA-N 1,2,3,3,4,4,5,5-octafluorocyclopentene Chemical compound FC1=C(F)C(F)(F)C(F)(F)C1(F)F YBMDPYAEZDJWNY-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 229910018503 SF6 Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910020776 SixNy Inorganic materials 0.000 description 2
- OQPDWFJSZHWILH-UHFFFAOYSA-N [Al].[Al].[Al].[Ti] Chemical compound [Al].[Al].[Al].[Ti] OQPDWFJSZHWILH-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- VOSJXMPCFODQAR-UHFFFAOYSA-N ac1l3fa4 Chemical compound [SiH3]N([SiH3])[SiH3] VOSJXMPCFODQAR-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 2
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 2
- 229910021334 nickel silicide Inorganic materials 0.000 description 2
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 2
- 239000004926 polymethyl methacrylate Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 2
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- DKCRDQKHMMPWPG-UHFFFAOYSA-N 3-methylpiperidine-2,6-dione Chemical compound CC1CCC(=O)NC1=O DKCRDQKHMMPWPG-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 235000010627 Phaseolus vulgaris Nutrition 0.000 description 1
- 244000046052 Phaseolus vulgaris Species 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- WRQGPGZATPOHHX-UHFFFAOYSA-N ethyl 2-oxohexanoate Chemical compound CCCCC(=O)C(=O)OCC WRQGPGZATPOHHX-UHFFFAOYSA-N 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000001900 extreme ultraviolet lithography Methods 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- ZQXQADNTSSMHJI-UHFFFAOYSA-N hafnium(4+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Hf+4] ZQXQADNTSSMHJI-UHFFFAOYSA-N 0.000 description 1
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- KUVFGOLWQIXGBP-UHFFFAOYSA-N hafnium(4+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Hf+4] KUVFGOLWQIXGBP-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 229920000592 inorganic polymer Polymers 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- QLOAVXSYZAJECW-UHFFFAOYSA-N methane;molecular fluorine Chemical compound C.FF QLOAVXSYZAJECW-UHFFFAOYSA-N 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 229920001709 polysilazane Polymers 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- FZHAPNGMFPVSLP-UHFFFAOYSA-N silanamine Chemical compound [SiH3]N FZHAPNGMFPVSLP-UHFFFAOYSA-N 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 125000000123 silicon containing inorganic group Chemical group 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
- G03F7/2002—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image
- G03F7/2004—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image characterised by the use of a particular light source, e.g. fluorescent lamps or deep UV light
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/36—Imagewise removal not covered by groups G03F7/30 - G03F7/34, e.g. using gas streams, using plasma
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70008—Production of exposure light, i.e. light sources
- G03F7/70033—Production of exposure light, i.e. light sources by plasma extreme ultraviolet [EUV] sources
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32422—Arrangement for selecting ions or species in the plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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Definitions
- Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
- FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.
- FIGS. 2A-2K are schematic sectional views of various stages of forming a semiconductor device according to one embodiment of the present disclosure.
- FIG. 3A is a schematic plan view of a reticle having a pattern with unidirectional features according to one embodiment of the present disclosure.
- FIG. 3B is a schematic plan view of unidirectional features after an angled etch process according to one embodiment of the present disclosure.
- FIG. 4 is a schematic plot of an angled etch process according to one embodiment of the present disclosure.
- FIG. 5 is a schematic sectional view of a process apparatus for performing the angled etch according to embodiment of the present disclosure.
- FIG. 6 is a schematic sectional view of a process apparatus for performing the angled etch according to embodiment of the present disclosure.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- an end-to-end distance or an end-to-end critical dimension may refer to the shortest distance separating two neighboring features in the pattern.
- a pattern includes two linear features positioned next two each other along the same axis, for example, the longitudinal axis
- a distance between the two nearest end points of the two features in the axial axis is referred to the end-to-end distance between the two features.
- the features may be openings/holes or islands in the pattern.
- the end-to-end distance in pattern features also shrinks.
- the end-to-end distance may be below 30 nm. It is challenging to achieve below 30 nm end-to-end distance using a single photolithographic process. Patterns with an end-to-end distance below 30 nm may be achieved through three lithographic processes and four etch processes in MD hard mask process.
- a first photolithographic process is used to form a first pattern with first features in a first photoresist structure.
- the first features may include lines along the x-direction.
- the width of the lines or the dimension of the lines along the y-direction represents a target end-to-end distance in the final pattern.
- the first photolithographic process may be an extreme ultraviolet (EUV) lithographic process.
- EUV extreme ultraviolet
- the first pattern is transferred to a first hard mask layer by a first etch process using the first photoresist as a mask. After the first photoresist structure from the first lithographic process is removed, a second photoresist structure is coated for a second photolithographic process.
- the second photolithographic process is performed to pattern a second pattern with second features in a second photoresist structure.
- the second features may include lines along the y-direction.
- the width of the lines or the dimension of the lines along the x-direction represents a target width of features in the final pattern.
- the second photolithographic process may be an immersion lithographic process.
- the second pattern is transferred to a second hard mask layer underneath the first hard mask layer by a second etch process using the second photoresist structure and the first hard mask layer as a mask.
- a third photoresist structure is coated for a third photolithographic process.
- the third photolithographic process is performed to pattern a third pattern with third features in the third photoresist structure.
- the third features may include lines along the y-direction.
- the second features and the third features may be identical but aligned at half a pitch apart to form lines along the y-direction.
- the width of the lines or the dimension of the lines along the x-direction represents a target width of features in the final pattern.
- the third photolithographic process may be an immersion lithographic process.
- the third pattern is transferred to the second hard mask by a third etch process using the third photoresist structure and the first hard mask layer as a mask.
- the final pattern is formed in a third hard mask layer by a fourth etch process using the first and second hard masks as a mask.
- the final pattern on the third mask reflects the overlay of the three patterns.
- it takes three lithographic processes and four etch processes to achieve the end-to-end distance below 30 nm.
- Embodiments of the present disclosure provides a method for forming a pattern having an end-to-end distance below 30 nm using one photolithographic process and one pattern.
- FIG. 1 is a flow chart of a method 100 for manufacturing a semiconductor device according to one embodiment of the present disclosure.
- the method 100 can be used to pattern a layer in a semiconductor substrate with unidirectional features.
- the method 100 uses one photolithographic operation to form unidirectional features with an end-to-end critical dimension of less than about 30 nm.
- the method 100 can be used to pattern various layers in manufacturing semiconductor devices.
- the method 100 can be used to pattern an interlayer dielectric layer, to form metal gate structures, to pattern active regions, and to pattern a polysilicon layer in a semiconductor device, such as a FinFET device.
- FIGS. 2A-2K are schematic cross sectional views of various stages of forming a semiconductor device 200 according to the method 100 .
- FIG. 2A is a schematic perspective cross sectional view of the semiconductor device 200 .
- the semiconductor device 200 includes one or more FinFET device structures 204 formed on a substrate 202 .
- the substrate 202 may be made of silicon or other semiconductor materials. Alternatively or additionally, the substrate 202 may include other elementary semiconductor materials such as germanium.
- the substrate 202 is made of a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide.
- the substrate 202 is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.
- the substrate 202 includes an epitaxial layer.
- the substrate 202 has an epitaxial layer overlying a bulk semiconductor.
- the FinFET device structure 204 includes one or more fin structures 206 (e.g., Si fins) that extend from the substrate 202 .
- the fin structures 206 may optionally include germanium.
- the fin structures 206 may be formed by using suitable processes such as photolithographic and etching processes. In some embodiments, the fin structures 206 are etched from the substrate 202 using dry etch or plasma processes.
- An isolation structure 208 such as a shallow trench isolation (STI) structure, is formed to surround the fin structures 206 .
- a lower portion of the fin structures 206 is surrounded by the isolation structure 208 , and an upper portion of the fin structures 206 protrudes from the isolation structure 208 .
- a portion of the fin structures 206 is embedded in the isolation structure 208 .
- the isolation structure 208 prevents electrical interference or crosstalk.
- the FinFET device structure 204 further includes gate stack structures 214 surrounded by an interlayer dielectric layer 212 .
- the interlayer dielectric layer 212 may include multilayers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other applicable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide.
- the interlayer dielectric layer 212 may be formed by chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), spin-on coating, Flow-able CVD, or other applicable processes.
- the gate stack structure 214 includes spacers 216 , gate stack layers 218 , and an electrode 220 .
- the gate structure 214 is formed over a central portion of the fin structures 206 .
- multiple gate stack structures 214 are formed over the fin structures 206 .
- the gate stack layers 218 may include multiple layers, such as high-k dielectric layers, capping layers, high-k metal layers, interface layers, and/or other suitable features.
- the gate stack layers 218 may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, dielectric material(s) with high dielectric constant (high-k), or combinations thereof.
- high-k dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, the like, or combinations thereof.
- the gate electrode 220 may include polysilicon or metal.
- Metal includes tantalum nitride (TaN), nickel silicon (NiSi), cobalt silicon (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), alumina (Al), cobalt (Co), zirconium (Zr), platinum (Pt), or other applicable materials.
- the gate electrode 220 may be formed in a gate last process (or gate replacement process).
- FIG. 2A illustrates gate cut regions 213 disposed between and separating longitudinally aligned gate stack structures 214 .
- the gate stack structures 214 can be formed separated by gate cut regions 213 by any method.
- dummy gate structures which are to be removed and replaced by the gate stack structures 214 , can be formed and patterned being separated by the gate cut regions 213 .
- spacers 216 may be formed along the gate stack structures 214 at the gate cut regions 213 .
- the dummy gate structures may be cut after the interlayer dielectric layer 212 is formed, such as by etching the dummy gate structures and filling the etched recesses with a dielectric material to form the gate cut regions 213 .
- the gate stack structures 214 may be cut after forming the interlayer dielectric layer 212 and the gate stack structures 214 , such as by etching the gate stack structures 214 and filling the etched recesses with a dielectric material to form the gate cut regions 213 .
- the fin structures 206 includes a channel region 222 surrounded or wrapped by the gate structures 214 .
- the fin structures 206 may be doped to provide a suitable channel for an n-type FinFET (NMOS device) or a p-type FinFET (PMOS device).
- the fin structures 206 may be doped using a suitable process, such as an ion implantation process, diffusion process, annealing process, other applicable processes, or combinations thereof.
- the fin structures 206 include source/drain regions 210 and channel regions 222 between the source/drain regions 210 .
- the FinFET device structure 204 may be a device included in a microprocessor, memory cell (e.g., Static Random-Access Memory (SRAM), and/or other integrated circuits.
- SRAM Static Random-Access Memory
- the FinFET device structure 204 includes multiple fin structures 206 and multiple gate structures 214 .
- the gate structures 214 traverse over the fin structures 206 .
- the fin structures 206 may be substantially parallel to each other.
- the gate structures 214 may also be parallel to each other and substantially perpendicular to the fin structures 206 . As shown in FIG. 2A , the fin structures 206 are along the x-direction and the gate structures 214 are along the y-direction.
- FIG. 2A is an example structure on which patterning with reduced end-to-end distances, such as described with respect to FIG. 1 , may be performed.
- FIGS. 2B-2K are partial cross sectional views of the semiconductor device 200 .
- Each of the FIGS. 2B-2K includes a 1D (X-cut) view that is a cross sectional view of the semiconductor device 200 along a XX-XX plane that is parallel to the x-z plane, and a 2D (Y-cut) view that is a cross sectional view of the semiconductor device 200 along a YY-YY plane that is parallel to the y-z plane.
- the x-y-z coordinates are selected where the x-y plane is parallel to a top surface of the substrate 200 , and the z-axis is perpendicular to the top surface of the substrate 200 .
- an etch stop layer 224 is formed over the gate structures 214 and the interlayer dielectric layer 212 .
- the etch stop layer 224 may be a single layer or multiple layers.
- the etch stop layer 224 is made of silicon oxide (SiOx), silicon carbide (SiC), silicon nitride (SixNy), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN), or another applicable material.
- the etch stop layer 224 has a bi-layer structure which includes a silicon oxide (SiOx) layer formed on a SiC layer, and silicon oxide layer is formed from tetraethyl orthosilicate (TEOS).
- SiOx silicon oxide
- TEOS tetraethyl orthosilicate
- the SiC layer is used as a glue layer to improve adhesion between the underlying layer and the silicon oxide layer.
- the etch stop layer 224 has a thickness of between about 2 nm and 10 nm, for example about 5 nm.
- the etch stop layer 224 includes a silicon nitride (Si x N y ) formed by a plasma enhanced chemical vapor deposition (PECVD) process.
- an interlayer dielectric layer 226 is formed over the etch stop layer 224 as shown in FIG. 2B .
- the interlayer dielectric layer 226 is configured to electrically isolate contact structures connecting the FinFET device structure 204 from each other.
- the interlayer dielectric layer 226 is formed from physically densifying and/or chemically converting flowable dielectric material(s) into dielectric materials, such as silicon oxide and silicon nitride.
- the interlayer dielectric layer 226 includes flowable dielectric materials formed in a flowable CVD (FCVD) process.
- FCVD flowable CVD
- flowable dielectric materials may primarily include silicon nitride, silicon oxynitride, silicon carbide, or silicon oxycarbide.
- FCVD flowable CVD
- flowable dielectric materials may primarily include silicon nitride, silicon oxynitride, silicon carbide, or silicon oxycarbide.
- Flowable dielectric materials as their name suggest, can “flow” during deposition to fill gaps or spaces with a high aspect ratio. Usually, various chemistries are added to silicon-containing precursors to allow the deposited film to flow.
- flowable dielectric precursors particularly flowable silicon oxide precursors
- examples of flowable dielectric precursors include a silicate, a siloxane, a methyl silsesquioxane (MSQ), a hydrogen silsesquioxane (HSQ), an MSQ/HSQ, a perhydrosilazane (TCPS), a perhydro-polysilazane (PSZ), a tetraethyl orthosilicate (TEOS), or a silyl-amine, such as trisilylamine (TSA).
- silicate a siloxane
- MSQ methyl silsesquioxane
- HSQ hydrogen silsesquioxane
- MSQ/HSQ an MSQ/HSQ
- TCPS perhydrosilazane
- PSZ perhydro-polysilazane
- TEOS tetraethyl orthosilicate
- silyl-amine such as trisilylamine (
- the interlayer dielectric layer 226 is formed from annealing and high temperature (HT) doping flowable dielectric materials into silicon oxide.
- annealing and/or HT doping of deposited flowable dielectric materials helps to remove undesired element(s) to densify the deposited flowable dielectric material.
- Materials used for doping these flowable dielectric materials may include silicon, germanium, oxygen, nitrogen, or any combination thereof, or any element(s) that does not alter and/or degrade the dielectric properties of the interlayer dielectric layer 226 .
- the HT doping process to form the interlayer dielectric layer 226 improves structural density of the dielectric material of the interlayer dielectric layer 226 . For example, such improvement in structural density substantially reduces the wet etch rate (WER) of the interlayer dielectric layer 226 by about 30% to about 50% compared to the interlayer dielectric layers used formed without the HT doping process.
- WER wet etch rate
- the interlayer dielectric layer 226 includes silicon oxide formed from FCVD.
- the interlayer dielectric layer 226 may have a thickness between about 30 nm and 100 nm, for example, about 65 nm.
- a first hard mask layer 228 is formed over the interlayer dielectric layer 226 , as shown in FIG. 2B .
- the first hard mask layer 228 is configured to provide a high etching selectivity relative to the interlayer dielectric layer 226 during a dry etch process.
- the first hard mask layer 228 is made of a metal material, such as tungsten carbide (WC), titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN).
- the first hard mask layer 228 has a thickness between about 10 nm and 50 nm, for example, about 20 nm.
- a second hard mask layer 230 is formed over the first hard mask layer 228 as shown in FIG. 2B .
- the second hard mask layer 230 is configured to provide a high etching selectivity relative to the first hard mask layer 228 during a dry etch process.
- the second hard mask layer 230 may include a silicon oxide layer, or other suitable material.
- the second hard mask layer 230 is a silicon oxide layer formed by PECVD.
- the second hard mask layer 230 has a thickness between about 20 nm and 80 nm, for example, about 40 nm.
- a tri-layer photoresist structure 232 is formed on the second hard mask layer 230 as shown in FIG. 2C .
- the tri-layer photoresist structure 232 includes a bottom layer 234 , a middle layer 236 , and a top layer 238 .
- the tri-layer photoresist 232 may be selected to be suitable for an extreme ultraviolet (EUV) photolithography.
- EUV extreme ultraviolet
- the bottom layer 234 contains a material that is patternable and/or has a composition tuned to provide anti-reflection properties.
- the bottom layer 234 is a bottom anti-reflective coating (BARC) layer configured to reduce reflection during the photolithography process.
- the bottom layer 234 includes monomers or polymers that are not cross-linked, for example a carbon backbone polymer.
- the bottom layer 234 is made of nitrogen-free material, such as silicon rich oxide, or silicon oxycarbide (SiOC).
- the bottom layer 234 may be formed by a spin coating process.
- the underlayer may be formed by another suitable deposition process.
- the bottom layer 234 includes spin-on-carbon (SOC).
- the bottom layer 234 may have a thickness between about 60 nm and 300 nm, for example, about 200 nm.
- the middle layer 236 may have a composition that provides an anti-reflective properties and/or hard mask properties for the lithography process.
- the middle layer 236 includes a silicon containing layer (e.g., silicon hard mask material).
- the middle layer 236 may include a silicon-containing inorganic polymer.
- the middle layer 236 includes a siloxane polymer (e.g., a polymer having a backbone of O—Si—O—Si— etc.).
- the silicon ratio of the middle layer 236 may be selected to control the etch rate.
- the middle layer 236 may include silicon oxide (e.g., spin-on glass (SOG)), silicon nitride, silicon oxynitride, polycrystalline silicon, a metal-containing organic polymer material that contains metal such as titanium, titanium nitride, aluminum, and/or tantalum; and/or other suitable materials.
- the middle layer 236 may have a thickness between about 15 nm and 50 nm, for example, about 30 nm.
- the top layer 238 may be a positive photoresist layer or a negative photoresist layer.
- the top layer 238 is made of Poly (methyl methacrylate) (PMMA), Poly (methyl glutarimide) (PMGI), Phenol formaldehyde resin (DNQ/Novolac) or SU-8.
- the top layer 238 may have a thickness between about 30 nm and 85 nm, for example, about 65 nm.
- the top layer 238 is patterned using a photolithography process.
- the top layer 238 may be formed using an EUV lithography process, which uses extreme ultraviolet (EVU) radiation or soft x-ray, i.e. radiation with wavelength shorter than 130 nm, has become one of the lithography methods for forming smaller semiconductor devices.
- EUV extreme ultraviolet
- each feature 240 may be an opening having a width 242 along the x-direction and a length 244 along the y-direction.
- the width 242 may be between about 10 nm and 15 nm.
- the length 244 may be between about 20 nm to 100 nm.
- the features 240 may be aligned along the y-direction with an end-to-end distance 246 between the neighboring features 240 . In other words, the features 240 are uni-directionally arranged such that a longitudinal axis of each feature 240 is parallel to the y-axis.
- the end-to-end distance 246 may be less than about 65 nm.
- the end-to-end distance 246 may be less than 55 nm.
- the end-to-end distance 246 is between about 40 nm to about 50 nm.
- the length 244 of the features 240 is shorter than a target length of an opening to be formed in the interlayer dielectric layer 226 .
- the end-to-end distance 246 is longer than a target end-to-end distance to be achieved in the interlayer dielectric layer 226 .
- the length 244 may be between about 20 nm and 30 nm shorter than a target length of features to be formed in the interlayer dielectric layer 226 .
- FIG. 3A is a schematic plan view of a pattern 300 a used to pattern the top layer 238 .
- the pattern 300 a reflects a pattern in a reticle used to pattern the top layer 238 .
- the pattern 300 a includes the plurality of unidirectional features 240 .
- the plurality of features 240 are arranged in multiple lines along the y-direction and have substantially the same widths 242 along the x-direction.
- the lengths 244 of the plurality of features 240 along the y-direction may be similar or different depending on the design of the integrated circuit.
- features 240 includes features 240 Vss, 240 Vcc, 240 BL, 240 n N which are intended to provide openings for electrically contacts to source/drain regions, gate electrode, and interconnects for FinFET devices.
- the features 240 Vss, 240 Vcc, 240 BL, 240 n N have substantially similar width along the x-direction and various lengths along the longitudinal direction or the y-direction.
- the features 240 Vss, 240 Vcc, 240 BL are linearly arranged along the same line in the y-direction.
- the features 240 Vss, 240 Vcc, 240 BL may have a length of about 80 nm, 35 nm, and 15 nm respectively. End-to-end distances between neighboring features 240 Vss, 240 Vcc, 240 BL may be about 55 nm.
- a plurality of features 240 n N are linearly arranged along the same line in the y-direction. The features 240 n N may have a length of about 55 nm. End-to-end distances between neighboring features 240 n N may be about 55 nm.
- the middle layer 236 is patterned using the patterned top layer 238 as a mask. As a result, the pattern of the top layer 238 is transferred to the middle layer 236 forming a patterned middle layer 236 .
- the bottom layer 234 is patterned using the patterned middle layer 236 as a mask as shown. The middle layer 236 and the bottom layer 234 may be patterned using a plasma process.
- the second hard mask layer 230 is patterned using the patterned photoresist structure 232 as a mask, as shown in FIG. 2E .
- a dry etch process may be used in operation 135 to pattern the second mask layer 230 .
- the features 240 are transferred from the patterned photoresist structure 232 to the second mask layer 230 .
- the second mask layer 230 is patterned using an etch gas comprising fluorine-containing gas, nitrogen (N 2 ), oxygen (O 2 ) or combinations thereof.
- the fluorine-containing gas includes nitrogen hexafluoroethane (C 2 F 6 ), tetrafluoromethane (CF 4 ), trifluoromethane (CHF 3 ), difluoromethane (CH 2 F 2 ), octofluoropropane (C 3 F 8 ), octofluorocyclobutane (C 4 F 8 ), or combinations thereof.
- a dry etching process may be performed to remove the top layer 238 and the middle layer 236 . As shown in FIG. 2E , only the bottom layer 234 of the tri-layer photoresist structure 232 is left after the dry etching process in operation 140 .
- an angled etch process is performed to modify the patterned second hard mask layer 230 along one direction as shown in FIGS. 2F and 2G .
- Ion beams 254 a and/or ion beam 254 b are directed to the substrate 200 at an angle relative to the z-axis to modify sidewalls 258 a , 258 b of the features 240 in the y-direction without affecting sidewalls 260 of the features 240 .
- FIG. 4 is a schematic plot of an angled etch process used in the operation 145 .
- the substrate 202 having features 240 is positioned in the x-y plane.
- the substrate 202 may be rotated about the z-axis so that sidewalls 260 are along the y-direction or the longitudinal axis of the features 240 is parallel to the y-axis.
- Ion beams 254 a , 254 b are directed towards substrate 202 in a plane substantially parallel to the y-z plane so that the ion beans 254 a , 254 b are parallel to the sidewalls 260 of the features 240 .
- Ion beams 254 a may have an angel 404 relative to the z-axis in the y-z plane.
- Ion beams 254 a may have an angel 406 relative to the z-axis.
- ion beams 254 a , 254 b may be a ribbon of ion beams in a plane 402 scanning across the substrate along the x-direction.
- ion beams 254 a , 254 b may be bulk ion beams directed to the entire surface of the substrate 202 simultaneously.
- the angles 404 , 406 may be selected according to an aspect ratio along the y-direction (a depth over length 244 ) of the features 240 to achieve a target etch rate along the y-direction.
- the angles 404 , 406 may be between 10 degrees and 30 degrees when the maximum aspect ratio along the y-direction of the features 240 (depth of the feature 240 over the minimum length 244 ) is between about 1.0 to 10, for example about 5.0.
- the angles 404 , 406 may be about 20 degrees when the maximum aspect ratio along the y-direction of the features 240 (depth of the feature 240 over the minimum length 244 ) is between about 1.0 to 10, for example about 5.0.
- angles 404 , 406 may be selected to adjust an etch rate along the y-direction.
- a larger angel 404 , 406 corresponds to a faster etch rate along the bottom of hard mask 230 y-direction.
- etching time and etch rate may be selected to achieve a desired increase in length of the features 240 .
- one or both of angles 404 , 406 can be spread in a range of angles.
- one or both of angles 404 , 406 are spread in a range of about 10°.
- one or both of angles 404 , 406 are spread in a range of about 5°.
- the ion beams 254 a are directed to the substrate 202 at the angle 404 so that the ion beams 254 a impinge the second mask layer 230 on the sidewall 258 a of the feature 240 as shown in FIG. 2F .
- the ion beams 254 a do not directly impinge the sidewalls 260 of the features 240 .
- the features 240 obtain a length increase 256 along the y-direction while the width 242 of the features 240 remains unchanged.
- the ion beams 254 b are directed to the substrate 202 at the angle 406 so that the ion beams 254 b impinge the second mask layer 230 on the sidewall 258 b of the features 240 as shown in FIG. 2G .
- the ion beams 254 b do not directly impinge the sidewalls 260 of the feature 240 .
- the features 240 obtain a length increase 262 along the y-direction while the width 242 of the features 240 remains unchanged.
- Ion beams 254 a , 254 b may be applied. Ion beams 254 a , 254 b may be applied at sequentially or simultaneously depending on the apparatus used in operation 145 .
- the ion beam 254 a , 254 b may be generated from a plasma of an etch gas.
- the etch gas may include fluorine-containing gas, nitrogen (N 2 ), oxygen (O 2 ) or an inert gas, such as argon (Ar), or combinations thereof.
- the fluorine-containing gas includes tetrafluoromethane (CF 4 ), nitrogen hexafluoroethane (C 2 F 6 ), trifluoromethane (CHF 3 ), difluoromethane (CH 2 F 2 ), octofluoropropane (C 3 F 8 ), octofluorocyclobutane (C 4 F 8 ), Octafluorocyclopentene (C 5 F 8 ), or combinations thereof.
- a carrier gas such as argon, may be included in the etch gas to generate to the ion beams 254 a , 254 b.
- the bottom layer 234 of the tri-layer photoresist structure 232 is removed as shown in FIG. 2H .
- the bottom layer 234 may be removed by a strip process, such as an ashing process.
- a wet cleaning process may be performed following the strip process.
- the features 240 have been modified to features 240 ′.
- the features 240 ′ has a length 250 that is increased by the angled etch process in the operation 145 , and a width 248 that is substantially the same as the width 242 of the features 240 .
- An end-to-end distance 252 between the features 240 ′ is reduced from the end-to-end distance 246 between the features 240 .
- the dimension of the features 240 ′ and the end-to-end distance 252 correspond to target dimensions to be formed in the interlayer dielectric layer 226 .
- FIG. 3B is a schematic plan view of a pattern 300 b formed in the second hard mask layer 230 after the angled etch process according to one embodiment of the present disclosure.
- the pattern 300 b reflects a target pattern to be formed in the interlayer dielectric layer 226 .
- the pattern 300 b includes the plurality of unidirectional features 240 ′ modified from the plurality of unidirectional features 240 in the pattern 300 a .
- the plurality of features 240 ′ are arranged in multiple lines along the y-direction and have substantially the same widths 248 along the x-direction.
- the lengths 250 of the plurality of features 240 ′ along the y-direction are similar or different depending on the design of the integrated circuit.
- the width 248 of the features 240 ′ may be between about 10 nm and 15 nm. According to embodiments of the present disclosure, the difference between the width 248 and the width 242 is less than 3 nm, for example, nearly 0 nm. In one embodiment, the length 250 of the features 240 ′ may be between about 35 nm to 130 nm. In one embodiment, the end-to-end distance 252 between the neighboring features 240 ′ may be less than about 35 nm. For example, the end-to-end distance 252 may be less than 25 nm. In one embodiment, the end-to-end distance 252 is between about 20 nm and about 25 nm.
- the features 240 ′Vss, 240 ′Vcc, 240 ′BL may have a length of about 110 nm, 65 nm, and 45 nm respectively.
- End-to-end distance between neighboring features 240 ′Vss, 240 ′Vcc, 240 ′BL may be about 20 nm to 30 nm.
- the features 240 ′nN may have a length of about 85 nm.
- End-to-end space between neighboring features 240 ′nN may be about 20 nm to 30 nm. Comparing the patterns 300 a and 300 b , the end-to-end distance between the features has been reduced for about 20 nm to 30 nm. In the pattern 300 b , the end-to-end distance 252 is less than 35 nm.
- an etch process is performed to transfer the pattern 300 b from the second hard mask layer 230 to the first hard mask layer 228 as shown in FIG. 2I .
- Operation 160 may be performed by a dry etch process using a plasma of an etch gas.
- the etch gas includes chlorine or fluorine based gas when the first hard mask layer 228 includes metals, such as titanium nitride, tungsten carbide.
- the etch gas may include Sulfur hexafluoride (SF 6 ), nitrogen tri-fluoride (NF 3 ) combined with chlorine (Cl 2 ), carbon tetrafluoride (CF 4 ), hexafluoroethane (C 2 F 6 ), chlorine (Cl 2 ), Boron tri-chloride (BCl 3 ), and a combination thereof.
- operation 160 includes a wet cleaning process following the dry etch to remove residues from the substrate. After operation 160 , the pattern 300 b is transferred to the first hard mask layer 228 .
- a below 35 nm end-to-end distance may be achieved using three photolithographic processes with three different patterns and four etch processes.
- the method 100 achieves a below 35 nm end-to-end distance with one photolithographic process, operation 130 , and three etch processes, operations 135 , 145 , 160 .
- the method 100 reduces production time and cost by eliminating two photolithographic processes and one etch process.
- the interlayer dielectric layer 226 is patterned by an etch process using the first hard mask layer 228 as a mask as shown in FIG. 2J .
- the etch process may be a dry etch process using a plasma of an etch gas.
- the etch gas may include fluorine-containing gas, nitrogen (N 2 ), oxygen (O 2 ) or combinations thereof.
- the fluorine-containing gas includes tetrafluoromethane (CF 4 ), nitrogen hexafluoroethane (C 2 F 6 ), trifluoromethane (CHF 3 ), difluoromethane (CH 2 F 2 ), octofluoropropane (C 3 F 8 ), octofluorocyclobutane (C 4 F 8 ), Octafluorocyclopentene (C 5 F 8 ), or combinations thereof.
- CF 4 tetrafluoromethane
- C 2 F 6 nitrogen hexafluoroethane
- CHF 3 trifluoromethane
- difluoromethane CH 2 F 2
- octofluoropropane C 3 F 8
- octofluorocyclobutane C 4 F 8
- Octafluorocyclopentene C 5 F 8
- the etch process in operation 165 also etches through the etch stop layer 224 and the interlayer dielectric layer 212 to form features 264 .
- the features 264 may be trenches or vias opening to the source/drain regions, gate electrodes, or other regions of the FinFET device structure 204 for forming electrical contacts to the FinFET device structure 204 .
- a metallization process is performed to fill the features 264 with electrically conductive material to make contacts 266 , as shown in FIG. 2K .
- a planization process such as a chemical mechanical polishing (CMP) process is performed after the metal fill.
- the conductive material used to make contact 266 includes aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantulum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), tantulum carbide (TaC), tantulum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAI), titanium aluminide nitride (TiAIN), other applicable conductive materials, or a combination thereof.
- the contacts 266 include a titanium nitride layer and tungsten formed over the titanium nitride layer.
- the contacts 266 may further include a liner and/or a barrier layer.
- a liner (not shown) may be formed on the sidewalls and bottom of the contact trench 264 .
- the liner may be either tetraethylorthosilicate (TEOS) or silicon nitride, although any other applicable dielectric may alternatively be used.
- the liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other applicable processes, such as physical vapor deposition or a thermal process, may alternatively be used.
- PECVD plasma enhanced chemical vapor deposition
- the barrier layer (not shown) may be formed over the liner (if present) and may cover the sidewalls and bottom of the opening.
- the barrier layer may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition processes.
- CVD chemical vapor deposition
- PVD physical vapor deposition
- PECVD plasma enhanced CVD
- PEPVD plasma enhanced physical vapor deposition
- ALD atomic layer deposition
- the barrier layer may be made of tantalum nitride, although other materials, such as tantalum, titanium, titanium nitride, or the like, may also be used.
- the contacts 266 are formed through the interlayer dielectric layer 226 .
- the end-to-end distance between the metal contacts 266 is less than 35 nm. In one embodiment, the end-to-end distance between the metal contacts 266 is between about 20 nm and about 25 nm.
- the angled etch process according to the present disclosure may be performed in a plasma chamber where ion beams can be directed to a substrate being processed at an angle.
- FIG. 5 is a schematic sectional view of a process apparatus 500 for performing the angled etch according to embodiment of the present disclosure.
- the process apparatus 500 generates and directs an ion beam ribbon towards a substrate at an angle.
- the process apparatus 500 may include a process chamber 502 and a plasma chamber 504 .
- the process apparatus 500 may include an antenna 506 .
- the antenna 506 may be disposed outside the plasma chamber 504 .
- the antenna 506 may be electrically connected to a RF power supply (not shown), which supplies an alternating voltage to the antenna 506 .
- the voltage may be at a frequency of, for example, 2 MHz or more, to generate a plasma in the plasma chamber 504 .
- the antenna 506 is powered using a RF signal to inductively couple energy into the plasma chamber 504 .
- the inductively coupled energy excites a process gas, such as the etch gas in operation 145 , introduced the plasma chamber, thus generating a plasma.
- the plasma chamber 504 includes a chamber wall 508 having an extraction aperture 510 .
- the chamber wall 508 may be disposed on the side of the process chamber 502 facing a substrate carrier 512 disposed in the process chamber 502 .
- the extract aperture 510 is configured to direct a ribbon of ion beams 520 towards the substrate carrier 512 .
- the aperture 510 may be configured to direct the ribbon of ion beam 520 at various angels and combinations towards the substrate 514 .
- the substrate carrier 512 is configured to secure and move a substrate 514 in the process chamber 512 .
- the substrate carrier 512 may translate the along the x direction in the process chamber 502 so that the ribbon of ion beam 520 scan through the entire surface of the substrate 514 on the substrate carrier 512 .
- the substrate 514 may be grounded during operation.
- An extraction power supply 516 may be used to apply an extraction voltage between the substrate 514 and the chamber wall 508 .
- the extraction voltage may be between about 800 Volt and about 1200 volt, for example, about 1000 volt, although other voltages are within the scope of the disclosure.
- the extraction voltage may be a square wave, having a frequency of between about 1 kHz and 50 kHz, although other frequencies are within the scope of the disclosure.
- the extraction voltage When the extraction voltage is applied between the chamber wall 508 of the plasma chamber 504 and the substrate 514 , and the plasma within the plasma chamber 504 is biased by the extraction voltage relative to the substrate 514 .
- the difference in potential between the plasma and the substrate 514 causes positively charged ions in the plasma to be accelerated through the extraction aperture 510 in the form of the ribbon of ion beam 520 and toward the substrate 514 .
- the substrate 514 is disposed proximate and opposite the chamber wall 508 having the extraction aperture 510 .
- the substrate 514 may be positioned between about 5 mm and 15 mm away from the aperture 510 , for example, about 12 mm.
- the substrate 514 may be positioned relative to the extraction aperture 510 to align features on the substrate 514 to the ribbon of ion beams 520 to achieve the angled etch according to the present disclosure.
- the substrate 514 may be pre-aligned before secured to the substrate carrier 512 .
- the substrate 514 may be rotated about the z-axis by the substrate carrier 512 .
- the extraction aperture 510 may be rotated about the z-axis.
- both the substrate carrier 512 and the extraction aperture 510 may rotate about the z-axis.
- the ribbon of ion beam 520 may be at least as wide as the substrate 514 in one direction, such as the y-direction, and may be much narrower than the substrate 514 in the orthogonal direction (or x-direction).
- the substrate 514 may be translated relative to the extraction aperture 510 such that different portions of the substrate 514 are exposed to the ribbon of ion beam 520 .
- the plasma chamber 504 may be translated while the substrate 514 remains stationary.
- both the plasma chamber 504 and the substrate 514 may be translated.
- the substrate 514 moves at a constant workpiece scan velocity relative to the extraction aperture 510 in the x-direction, so that the entirety of the substrate 514 is exposed to the ribbon of ion beam 520 for the same amount of time.
- FIG. 6 is a schematic sectional view of a process apparatus 600 for performing the angled etch according to embodiment of the present disclosure.
- the process apparatus 600 generates and directs a bulk ion beam 620 towards a substrate at an angle.
- the process apparatus 600 may include a process chamber 602 and a plasma chamber 604 .
- the process apparatus 600 may include an antenna 606 .
- the antenna 606 may be disposed outside the plasma chamber 604 .
- the antenna 606 may be electrically connected to a RF power supply (not shown), which supplies an alternating voltage to the antenna 606 .
- the voltage may be at a frequency of, for example, 2 MHz or more, to generate a plasma in the plasma chamber 604 .
- the antenna 606 is powered using a RF signal to inductively couple energy into the plasma chamber 604 .
- the inductively coupled energy excites a process gas, such as the etch gas in operation 145 , which is introduced into the plasma chamber 604 , thus generating a plasma.
- the plasma chamber 604 includes a plasm grill 608 having a plurality of apertures 610 .
- the plasm grill 608 may be disposed over the process chamber 602 facing a substrate carrier 612 disposed in the process chamber 602 .
- the plurality of apertures 610 are configured to direct the bulk ion beam 620 along the z-direction.
- the bulk ion beam 620 may be directed towards the substrate 614 on the substrate carrier 612 at various impinging angles.
- the impinging angle of the bulk ion beam 620 is controlled by rotating the substrate carrier about the x-direction.
- the substrate carrier 612 is configured to secure and move a substrate 614 in the process chamber 602 .
- the substrate carrier 612 may translate the along the z direction in the process chamber 602 to adjust the distance between the substrate 614 and the plasma grill 608 .
- the substrate carrier 612 may also rotate about the x-axis, y-axis, and z-axis to align the substrate 614 with the bulk ion beam 620 and to adjust the impinging angle of the bulk ion beam 620 at the substrate 614 .
- the x-y-z coordinate system is selected where the z-axis passes through a center axis 618 of the substrate carrier 612 .
- the substrate 614 may be grounded during operation.
- An extraction power supply 616 may be used to apply an extraction voltage between the substrate 614 and the plasma grill 608 .
- the extraction voltage may be a constant voltage.
- the extraction voltage may be a square wave, having a frequency of between about 1 kHz and 50 kHz, although other frequencies are within the scope of the disclosure.
- the extraction voltage When the extraction voltage is applied between the plasma grill 608 and the substrate 614 , and the plasma within the plasma chamber 604 is biased by the extraction voltage relative to the substrate 614 .
- the difference in potential between the plasma and the substrate 614 causes positively charged ions in the plasma to be accelerated through the plurality of apertures 610 in the plasma grill 608 the bulk ion beam 620 toward the substrate 614 .
- the substrate 614 may be secured to the substrate carrier 612 .
- the substrate carrier 612 may rotate about the z-axis to align longitudinal axis of features on the substrate 614 , such as the features 240 .
- the substrate 614 may be rotated so that the lengths 244 of the features 240 are parallel to the y-axis.
- the substrate 614 may be rotated about the x-axis by the substrate carrier 612 to select an angle for the angled etch as disclosed in the present disclosure.
- the substrate remains stationary.
- the substrate 614 may be rotated for 180 degrees about the z-axis at half time to balance the distance differences between the plasma grill 608 and different portions of the substrate 614 .
- the method 100 of the present disclosure is performed using a process apparatus similar to the process apparatus 500 of FIG. 5 to perform the angled etch in operation 145 of the method 100 .
- a first pattern is formed in a tri-layer photoresist layer.
- the pattern includes a Vss feature, a Vcc feature, and a BL feature arranged repeatedly and sequentially lengthwise in a line.
- the Vss feature has a length of about 100 nm
- the Vcc feature has a length of about 55 nm
- the BL feature has a length of about 35 nm.
- the end-to-end distance between the BL feature and the Vss feature is about 30 nm.
- the end-to-end distance between the Vss feature and the Vcc feature is about 30 nm.
- the end-to-end distance between the Vcc feature and the BL feature is about 30 nm.
- the pattern includes a Vss feature, a Vcc feature, and a BL feature arranged repeatedly and sequentially lengthwise in a line.
- the Vss feature has a length of about 80 nm
- the Vcc feature has a length of about 35 nm
- the BL feature has a length of about 15 nm.
- the end-to-end distance between the BL feature and the Vss feature is about 50 nm.
- the end-to-end distance between the Vss feature and the Vcc feature is about 50 nm.
- the end-to-end distance between the Vcc feature and the BL feature is about 50 nm.
- An angled etch process is performed to the first pattern using a process apparatus similar to the process apparatus 500 .
- a 1000 Walt power is applied to the plasma source to generate a plasma of an etch gas.
- a 1000 volt extraction voltage is applied to extract a ribbon of ion beam.
- the etch gas includes 10 sccm of CF 4 , 5 sccm of CH 3 F and 9 sccm of Argon.
- the impinging angle of the ribbon of ion beam is about 21 degrees.
- the distance between the substrate and the extraction aperture is about 12 mm.
- the angled process is performed for 10-30 minutes.
- the Vss feature has a length of about 110 nm, increased by 30 nm from the original length 80 nm.
- the Vcc feature has a length of about 65 nm, increased by 30 nm from the original length 35 nm.
- the BL feature has a length of about 45 nm, increased by 30 nm from the original length 15 nm.
- the variation in length change between long openings and short openings are less than 2 nm.
- the changes in width of the features are not detectable or less than 3 nm.
- the end-to-end distance between the BL feature and the Vss feature is about 25 nm.
- the end-to-end distance between the Vss feature and the Vcc feature is about 25 nm.
- the end-to-end distance between the Vcc feature and the BL feature is about 25 nm.
- embodiments of the present disclosure may be used for patterning layers to form unidirectional features with an end-to-end distance lower than 35 nm.
- embodiments of the present disclosure may be used to pattern an active region with line features, for example to form fin in the active region, pattern a polysilicon layer, for example to form dummy gates in the polysilicon layer, or pattern a metal gate structure, for example to form isolation structures in metal gates.
- device elements include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high-voltage transistors, high-frequency transistors, p-channel and/or n channel field effect transistors (PFETs/NFETs), etc.), diodes, and/or other applicable elements.
- MOSFET metal oxide semiconductor field effect transistors
- CMOS complementary metal oxide semiconductor
- BJT bipolar junction transistors
- PFETs/NFETs p-channel and/or n channel field effect transistors
- Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond 5 nm node fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.
- One embodiment of the present disclosure provides a method of processing a substrate.
- the method includes patterning a hard mask layer on the substrate to form a feature in the hard mask layer, and performing an angled etch process to modify the feature by increasing a length of the feature while maintaining a width of the feature.
- performing the angled etch process includes directing an ion beam towards a top surface of the substrate, wherein a plane including the ion beam is parallel to a plane of a sidewall of the feature along the length of the feature.
- the ion beam is at an impinging angle relative to a z-axis perpendicular to the top surface of the substrate. In some embodiments, the impinging angle is between about 10 degrees to about 30 degrees.
- the method further includes selecting the impinging angle according to an aspect ratio of the feature.
- the ion beam is a ribbon of ion beam covering a width of the substrate.
- the ion beam is a bulk ion beam covering the entire top surface of the substrate.
- the length of the feature is increased by about 20 nm to about 30 nm.
- patterning the mask layer is performed by an extreme ultraviolet (EUV) lithographic process.
- the method further includes removing a photoresist layer used in patterning the mask layer after performing the angled etch process.
- EUV extreme ultraviolet
- Another embodiment of the present disclosure provides a method of patterning a layer on a substrate.
- the method includes forming a first hard mask layer over the layer, forming a second mask layer over the first mask layer, forming a photoresist layer over the second mask layer, patterning the photoresist layer using a photolithographic process, etching the second mask layer using the photoresist layer as a mask to form a feature in the second mask layer, performing an angled etch to modify the feature by increasing a length of the feature without changing a width of the feature, and etching the first mask layer using the second mask layer as a mask.
- the photolithographic process is an extreme ultraviolet (EUV) lithographic process.
- performing the angled etch process includes directing an ion beam towards a top surface of the substrate, wherein a plane including the ion beam is parallel to a plane of a sidewall of the feature along the length of the feature.
- the ion beam is at an impinging angle relative to a z-axis perpendicular to the top surface of the substrate. In some embodiments, the impinging angle is between about 10 degrees to about 30 degrees.
- the ion beam is a ribbon of ion beam covering a width of the substrate.
- the ion beam is a bulk ion beam covering the entire top surface of the substrate. In some embodiments, wherein the length of the feature is increased by about 20 nm to about 30 nm.
- the semiconductor layer is one of an interlayer dielectric layer formed over FinFET device structures.
- Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device.
- the method includes patterning a hard mask layer on a substrate to form a first pattern in the hard mask layer, wherein the first pattern includes two or more unidirectional features aligned along a line having an end-to-end distance at a first value, and performing an angled etch process to reduce the end-to-end distance between two features from the first value to a second value without changing a width of the two or more features.
- the second value of the end-to-end distance is less than 35 nm.
- performing the angled etch process includes directing an ion beam towards a top surface of the substrate, wherein a plane including the ion beam is parallel to a plane of a sidewall of the feature along the length of the feature.
- the ion beam is at an impinging angle relative to a z-axis perpendicular to the top surface of the substrate.
- the ion beam is a bulk ion beam covering the entire top surface of the substrate.
- the length of the feature is increased by about 20 nm to about 30 nm.
- Another embodiment of the present disclosure provides a method for forming a semiconductor device.
- the method includes forming an interlayer dielectric layer over gate structures of a FinFET structure, and patterning the interlayer dielectric layer to form a contact opening in the interlayer dielectric layer, including forming a first hard mask layer over the interlayer dielectric layer, forming a second hard mask layer over the first hard mask layer, patterning the second hard mask layer to form a first opening in the first hard mask layer, wherein a length of the first opening is shorter than a length of the contact opening, performing an angled etch process to increase the length of first opening without changing a width of the first opening, etching the first hard mask layer using the second hard mask as a mask, thereby, transferring the modified first opening to the first hard mask layer, and etching the interlayer dielectric layer to form the contact opening using the modified first opening in the first hard mask as a mask.
- performing the angled etch process includes directing an ion beam towards a top surface of the substrate, wherein
- Another embodiment of the present disclosure provides a method of forming a semiconductor device.
- the method includes forming an interlayer dielectric layer over gate structures of a FinFET structure, and patterning the interlayer dielectric layer to form a contact opening in the interlayer dielectric layer, including patterning a hard mask layer over the interlayer dielectric layer to form a first pattern in the hard mask layer, wherein the first pattern includes two or more unidirectional features aligned along a line having an end-to-end distance at a first value, and performing an angled etch process to increase a length of the two or more features without changing a width of the two or more features, thereby, reducing the end-to-end distance from the first value to a second value.
- the method includes forming a first pattern in a photoresist layer, wherein the first pattern includes unidirectional features, etching a mask layer below the photoresist layer using the photoresist layer as a mask to the first pattern in the mask layer, an directing an ion beam at an angle to increase lengths of the unidirectional features without enlarging a width of the unidirectional features.
- the ion beam is directed along a plane parallel to a plane of sidewalls of the unidirectional features along the length of the unidirectional features.
Abstract
Description
- Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
- As the semiconductor industry has progressed into nanometer technology process nodes, such as 5 nm nodes, in pursuit of higher device density, higher performance, and lower costs. The shrinking dimension of the semiconductor devices presents challenges in semiconductor processing steps. There is a need to improve efficiency and reduce cost for various semiconductor processing steps.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. -
FIGS. 2A-2K are schematic sectional views of various stages of forming a semiconductor device according to one embodiment of the present disclosure. -
FIG. 3A is a schematic plan view of a reticle having a pattern with unidirectional features according to one embodiment of the present disclosure. -
FIG. 3B is a schematic plan view of unidirectional features after an angled etch process according to one embodiment of the present disclosure. -
FIG. 4 is a schematic plot of an angled etch process according to one embodiment of the present disclosure. -
FIG. 5 is a schematic sectional view of a process apparatus for performing the angled etch according to embodiment of the present disclosure. -
FIG. 6 is a schematic sectional view of a process apparatus for performing the angled etch according to embodiment of the present disclosure. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- Embodiments of the present disclosure relates to methods for forming a pattern with reduced an end-to-end distance. During semiconductor processing, an end-to-end distance or an end-to-end critical dimension may refer to the shortest distance separating two neighboring features in the pattern. For example, when a pattern includes two linear features positioned next two each other along the same axis, for example, the longitudinal axis, a distance between the two nearest end points of the two features in the axial axis is referred to the end-to-end distance between the two features. The features may be openings/holes or islands in the pattern.
- As the dimension of devices shrink, the end-to-end distance in pattern features also shrinks. For the node 5 nm process, the end-to-end distance may be below 30 nm. It is challenging to achieve below 30 nm end-to-end distance using a single photolithographic process. Patterns with an end-to-end distance below 30 nm may be achieved through three lithographic processes and four etch processes in MD hard mask process.
- For example, a first photolithographic process is used to form a first pattern with first features in a first photoresist structure. The first features may include lines along the x-direction. The width of the lines or the dimension of the lines along the y-direction represents a target end-to-end distance in the final pattern. The first photolithographic process may be an extreme ultraviolet (EUV) lithographic process. The first pattern is transferred to a first hard mask layer by a first etch process using the first photoresist as a mask. After the first photoresist structure from the first lithographic process is removed, a second photoresist structure is coated for a second photolithographic process.
- The second photolithographic process is performed to pattern a second pattern with second features in a second photoresist structure. The second features may include lines along the y-direction. The width of the lines or the dimension of the lines along the x-direction represents a target width of features in the final pattern. The second photolithographic process may be an immersion lithographic process. The second pattern is transferred to a second hard mask layer underneath the first hard mask layer by a second etch process using the second photoresist structure and the first hard mask layer as a mask. After the second photoresist structure from the second lithographic process is removed, a third photoresist structure is coated for a third photolithographic process.
- The third photolithographic process is performed to pattern a third pattern with third features in the third photoresist structure. The third features may include lines along the y-direction. The second features and the third features may be identical but aligned at half a pitch apart to form lines along the y-direction. The width of the lines or the dimension of the lines along the x-direction represents a target width of features in the final pattern. The third photolithographic process may be an immersion lithographic process. The third pattern is transferred to the second hard mask by a third etch process using the third photoresist structure and the first hard mask layer as a mask.
- After the third photoresist structure from the third lithographic process is removed, the final pattern is formed in a third hard mask layer by a fourth etch process using the first and second hard masks as a mask. The final pattern on the third mask reflects the overlay of the three patterns. Thus, in the existing technology, it takes three lithographic processes and four etch processes to achieve the end-to-end distance below 30 nm.
- Embodiments of the present disclosure provides a method for forming a pattern having an end-to-end distance below 30 nm using one photolithographic process and one pattern.
-
FIG. 1 is a flow chart of amethod 100 for manufacturing a semiconductor device according to one embodiment of the present disclosure. Themethod 100 can be used to pattern a layer in a semiconductor substrate with unidirectional features. Themethod 100 uses one photolithographic operation to form unidirectional features with an end-to-end critical dimension of less than about 30 nm. Themethod 100 can be used to pattern various layers in manufacturing semiconductor devices. For example, themethod 100 can be used to pattern an interlayer dielectric layer, to form metal gate structures, to pattern active regions, and to pattern a polysilicon layer in a semiconductor device, such as a FinFET device.FIGS. 2A-2K are schematic cross sectional views of various stages of forming asemiconductor device 200 according to themethod 100. -
FIG. 2A is a schematic perspective cross sectional view of thesemiconductor device 200. In one embodiment, thesemiconductor device 200 includes one or moreFinFET device structures 204 formed on asubstrate 202. Thesubstrate 202 may be made of silicon or other semiconductor materials. Alternatively or additionally, thesubstrate 202 may include other elementary semiconductor materials such as germanium. In some embodiments, thesubstrate 202 is made of a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide. In some embodiments, thesubstrate 202 is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, thesubstrate 202 includes an epitaxial layer. For example, thesubstrate 202 has an epitaxial layer overlying a bulk semiconductor. - The
FinFET device structure 204 includes one or more fin structures 206 (e.g., Si fins) that extend from thesubstrate 202. Thefin structures 206 may optionally include germanium. Thefin structures 206 may be formed by using suitable processes such as photolithographic and etching processes. In some embodiments, thefin structures 206 are etched from thesubstrate 202 using dry etch or plasma processes. - An
isolation structure 208, such as a shallow trench isolation (STI) structure, is formed to surround thefin structures 206. In some embodiments, a lower portion of thefin structures 206 is surrounded by theisolation structure 208, and an upper portion of thefin structures 206 protrudes from theisolation structure 208. In other words, a portion of thefin structures 206 is embedded in theisolation structure 208. Theisolation structure 208 prevents electrical interference or crosstalk. - The
FinFET device structure 204 further includesgate stack structures 214 surrounded by aninterlayer dielectric layer 212. Theinterlayer dielectric layer 212 may include multilayers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other applicable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. Theinterlayer dielectric layer 212 may be formed by chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), spin-on coating, Flow-able CVD, or other applicable processes. - The
gate stack structure 214 includesspacers 216, gate stack layers 218, and anelectrode 220. Thegate structure 214 is formed over a central portion of thefin structures 206. In some embodiments, multiplegate stack structures 214 are formed over thefin structures 206. The gate stack layers 218 may include multiple layers, such as high-k dielectric layers, capping layers, high-k metal layers, interface layers, and/or other suitable features. - The gate stack layers 218 may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, dielectric material(s) with high dielectric constant (high-k), or combinations thereof. Examples of high-k dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, the like, or combinations thereof.
- The
gate electrode 220 may include polysilicon or metal. Metal includes tantalum nitride (TaN), nickel silicon (NiSi), cobalt silicon (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), alumina (Al), cobalt (Co), zirconium (Zr), platinum (Pt), or other applicable materials. Thegate electrode 220 may be formed in a gate last process (or gate replacement process). -
FIG. 2A illustrates gate cut regions 213 disposed between and separating longitudinally alignedgate stack structures 214. Thegate stack structures 214 can be formed separated by gate cut regions 213 by any method. For example, in the context of a replacement gate process, dummy gate structures, which are to be removed and replaced by thegate stack structures 214, can be formed and patterned being separated by the gate cut regions 213. In such a case,spacers 216 may be formed along thegate stack structures 214 at the gate cut regions 213. In other examples, the dummy gate structures may be cut after theinterlayer dielectric layer 212 is formed, such as by etching the dummy gate structures and filling the etched recesses with a dielectric material to form the gate cut regions 213. In further examples, thegate stack structures 214 may be cut after forming theinterlayer dielectric layer 212 and thegate stack structures 214, such as by etching thegate stack structures 214 and filling the etched recesses with a dielectric material to form the gate cut regions 213. - The
fin structures 206 includes achannel region 222 surrounded or wrapped by thegate structures 214. Thefin structures 206 may be doped to provide a suitable channel for an n-type FinFET (NMOS device) or a p-type FinFET (PMOS device). Thefin structures 206 may be doped using a suitable process, such as an ion implantation process, diffusion process, annealing process, other applicable processes, or combinations thereof. Thefin structures 206 include source/drain regions 210 andchannel regions 222 between the source/drain regions 210. TheFinFET device structure 204 may be a device included in a microprocessor, memory cell (e.g., Static Random-Access Memory (SRAM), and/or other integrated circuits. - The
FinFET device structure 204 includesmultiple fin structures 206 andmultiple gate structures 214. Thegate structures 214 traverse over thefin structures 206. Thefin structures 206 may be substantially parallel to each other. Thegate structures 214 may also be parallel to each other and substantially perpendicular to thefin structures 206. As shown inFIG. 2A , thefin structures 206 are along the x-direction and thegate structures 214 are along the y-direction. -
FIG. 2A is an example structure on which patterning with reduced end-to-end distances, such as described with respect toFIG. 1 , may be performed. -
FIGS. 2B-2K are partial cross sectional views of thesemiconductor device 200. Each of theFIGS. 2B-2K includes a 1D (X-cut) view that is a cross sectional view of thesemiconductor device 200 along a XX-XX plane that is parallel to the x-z plane, and a 2D (Y-cut) view that is a cross sectional view of thesemiconductor device 200 along a YY-YY plane that is parallel to the y-z plane. As shown inFIG. 2A , the x-y-z coordinates are selected where the x-y plane is parallel to a top surface of thesubstrate 200, and the z-axis is perpendicular to the top surface of thesubstrate 200. - In
operation 105 of themethod 100, anetch stop layer 224 is formed over thegate structures 214 and theinterlayer dielectric layer 212. Theetch stop layer 224 may be a single layer or multiple layers. Theetch stop layer 224 is made of silicon oxide (SiOx), silicon carbide (SiC), silicon nitride (SixNy), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN), or another applicable material. In some embodiments, theetch stop layer 224 has a bi-layer structure which includes a silicon oxide (SiOx) layer formed on a SiC layer, and silicon oxide layer is formed from tetraethyl orthosilicate (TEOS). The SiC layer is used as a glue layer to improve adhesion between the underlying layer and the silicon oxide layer. - In one embodiment, the
etch stop layer 224 has a thickness of between about 2 nm and 10 nm, for example about 5 nm. Theetch stop layer 224 includes a silicon nitride (SixNy) formed by a plasma enhanced chemical vapor deposition (PECVD) process. - In
operation 110 of themethod 100, aninterlayer dielectric layer 226 is formed over theetch stop layer 224 as shown inFIG. 2B . Theinterlayer dielectric layer 226 is configured to electrically isolate contact structures connecting theFinFET device structure 204 from each other. - In some embodiments, the
interlayer dielectric layer 226 is formed from physically densifying and/or chemically converting flowable dielectric material(s) into dielectric materials, such as silicon oxide and silicon nitride. In some embodiment, theinterlayer dielectric layer 226 includes flowable dielectric materials formed in a flowable CVD (FCVD) process. In some embodiments, flowable dielectric materials may primarily include silicon nitride, silicon oxynitride, silicon carbide, or silicon oxycarbide. Flowable dielectric materials, as their name suggest, can “flow” during deposition to fill gaps or spaces with a high aspect ratio. Usually, various chemistries are added to silicon-containing precursors to allow the deposited film to flow. In some embodiments, nitrogen hydride bonds are added. Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include a silicate, a siloxane, a methyl silsesquioxane (MSQ), a hydrogen silsesquioxane (HSQ), an MSQ/HSQ, a perhydrosilazane (TCPS), a perhydro-polysilazane (PSZ), a tetraethyl orthosilicate (TEOS), or a silyl-amine, such as trisilylamine (TSA). - In one embodiment, the
interlayer dielectric layer 226 is formed from annealing and high temperature (HT) doping flowable dielectric materials into silicon oxide. In some embodiments, annealing and/or HT doping of deposited flowable dielectric materials helps to remove undesired element(s) to densify the deposited flowable dielectric material. Materials used for doping these flowable dielectric materials may include silicon, germanium, oxygen, nitrogen, or any combination thereof, or any element(s) that does not alter and/or degrade the dielectric properties of theinterlayer dielectric layer 226. The HT doping process to form theinterlayer dielectric layer 226 improves structural density of the dielectric material of theinterlayer dielectric layer 226. For example, such improvement in structural density substantially reduces the wet etch rate (WER) of theinterlayer dielectric layer 226 by about 30% to about 50% compared to the interlayer dielectric layers used formed without the HT doping process. - In one embodiment, the
interlayer dielectric layer 226 includes silicon oxide formed from FCVD. Theinterlayer dielectric layer 226 may have a thickness between about 30 nm and 100 nm, for example, about 65 nm. - In
operation 115 of themethod 100, a firsthard mask layer 228 is formed over theinterlayer dielectric layer 226, as shown inFIG. 2B . The firsthard mask layer 228 is configured to provide a high etching selectivity relative to theinterlayer dielectric layer 226 during a dry etch process. In some embodiments, the firsthard mask layer 228 is made of a metal material, such as tungsten carbide (WC), titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). In one embodiment, the firsthard mask layer 228 has a thickness between about 10 nm and 50 nm, for example, about 20 nm. - In
operation 120 of themethod 100, a secondhard mask layer 230 is formed over the firsthard mask layer 228 as shown inFIG. 2B . The secondhard mask layer 230 is configured to provide a high etching selectivity relative to the firsthard mask layer 228 during a dry etch process. The secondhard mask layer 230 may include a silicon oxide layer, or other suitable material. In one embodiment, the secondhard mask layer 230 is a silicon oxide layer formed by PECVD. In one embodiment, the secondhard mask layer 230 has a thickness between about 20 nm and 80 nm, for example, about 40 nm. - In
operation 125 of themethod 100, atri-layer photoresist structure 232 is formed on the secondhard mask layer 230 as shown inFIG. 2C . Thetri-layer photoresist structure 232 includes abottom layer 234, amiddle layer 236, and a top layer 238. In one embodiment, thetri-layer photoresist 232 may be selected to be suitable for an extreme ultraviolet (EUV) photolithography. - The
bottom layer 234 contains a material that is patternable and/or has a composition tuned to provide anti-reflection properties. In one embodiment, thebottom layer 234 is a bottom anti-reflective coating (BARC) layer configured to reduce reflection during the photolithography process. In one embodiment, thebottom layer 234 includes monomers or polymers that are not cross-linked, for example a carbon backbone polymer. In other embodiments, thebottom layer 234 is made of nitrogen-free material, such as silicon rich oxide, or silicon oxycarbide (SiOC). Thebottom layer 234 may be formed by a spin coating process. In other embodiments, the underlayer may be formed by another suitable deposition process. In one embodiment, thebottom layer 234 includes spin-on-carbon (SOC). Thebottom layer 234 may have a thickness between about 60 nm and 300 nm, for example, about 200 nm. - The
middle layer 236 may have a composition that provides an anti-reflective properties and/or hard mask properties for the lithography process. In one embodiment, themiddle layer 236 includes a silicon containing layer (e.g., silicon hard mask material). Themiddle layer 236 may include a silicon-containing inorganic polymer. In other embodiment, themiddle layer 236 includes a siloxane polymer (e.g., a polymer having a backbone of O—Si—O—Si— etc.). The silicon ratio of themiddle layer 236 may be selected to control the etch rate. In other embodiments themiddle layer 236 may include silicon oxide (e.g., spin-on glass (SOG)), silicon nitride, silicon oxynitride, polycrystalline silicon, a metal-containing organic polymer material that contains metal such as titanium, titanium nitride, aluminum, and/or tantalum; and/or other suitable materials. In one embodiment, themiddle layer 236 may have a thickness between about 15 nm and 50 nm, for example, about 30 nm. - The top layer 238 may be a positive photoresist layer or a negative photoresist layer. In some embodiments, the top layer 238 is made of Poly (methyl methacrylate) (PMMA), Poly (methyl glutarimide) (PMGI), Phenol formaldehyde resin (DNQ/Novolac) or SU-8. In one embodiment, the top layer 238 may have a thickness between about 30 nm and 85 nm, for example, about 65 nm.
- In
operation 130 of themethod 100, the top layer 238 is patterned using a photolithography process. The top layer 238 may be formed using an EUV lithography process, which uses extreme ultraviolet (EVU) radiation or soft x-ray, i.e. radiation with wavelength shorter than 130 nm, has become one of the lithography methods for forming smaller semiconductor devices. - After the photolithography process, features 240 are formed in the top layer 238 as shown in
FIG. 2D . In one embodiment, eachfeature 240 may be an opening having awidth 242 along the x-direction and alength 244 along the y-direction. Thewidth 242 may be between about 10 nm and 15 nm. In one embodiment, thelength 244 may be between about 20 nm to 100 nm. Thefeatures 240 may be aligned along the y-direction with an end-to-end distance 246 between the neighboring features 240. In other words, thefeatures 240 are uni-directionally arranged such that a longitudinal axis of eachfeature 240 is parallel to the y-axis. In one embodiment, the end-to-end distance 246 may be less than about 65 nm. For example, the end-to-end distance 246 may be less than 55 nm. In one embodiment, the end-to-end distance 246 is between about 40 nm to about 50 nm. - In one embodiment, the
length 244 of thefeatures 240 is shorter than a target length of an opening to be formed in theinterlayer dielectric layer 226. In other words, the end-to-end distance 246 is longer than a target end-to-end distance to be achieved in theinterlayer dielectric layer 226. In one embodiment, thelength 244 may be between about 20 nm and 30 nm shorter than a target length of features to be formed in theinterlayer dielectric layer 226. -
FIG. 3A is a schematic plan view of apattern 300 a used to pattern the top layer 238. Thepattern 300 a reflects a pattern in a reticle used to pattern the top layer 238. Thepattern 300 a includes the plurality ofunidirectional features 240. Particularly, the plurality offeatures 240 are arranged in multiple lines along the y-direction and have substantially thesame widths 242 along the x-direction. Thelengths 244 of the plurality offeatures 240 along the y-direction may be similar or different depending on the design of the integrated circuit. - In the exemplary design of
FIG. 3A , features 240 includes features 240Vss, 240Vcc, 240BL, 240 nN which are intended to provide openings for electrically contacts to source/drain regions, gate electrode, and interconnects for FinFET devices. The features 240Vss, 240Vcc, 240BL, 240 nN have substantially similar width along the x-direction and various lengths along the longitudinal direction or the y-direction. For example, the features 240Vss, 240Vcc, 240BL are linearly arranged along the same line in the y-direction. The features 240Vss, 240Vcc, 240BL may have a length of about 80 nm, 35 nm, and 15 nm respectively. End-to-end distances between neighboring features 240Vss, 240Vcc, 240BL may be about 55 nm. A plurality offeatures 240 nN are linearly arranged along the same line in the y-direction. Thefeatures 240 nN may have a length of about 55 nm. End-to-end distances between neighboringfeatures 240 nN may be about 55 nm. - Referring back to
FIG. 2D , after the top layer 238 is patterned, themiddle layer 236 is patterned using the patterned top layer 238 as a mask. As a result, the pattern of the top layer 238 is transferred to themiddle layer 236 forming a patternedmiddle layer 236. After themiddle layer 236 is patterned, thebottom layer 234 is patterned using the patternedmiddle layer 236 as a mask as shown. Themiddle layer 236 and thebottom layer 234 may be patterned using a plasma process. - In
operation 135 of themethod 100, the secondhard mask layer 230 is patterned using the patternedphotoresist structure 232 as a mask, as shown inFIG. 2E . A dry etch process may be used inoperation 135 to pattern thesecond mask layer 230. During operation, thefeatures 240 are transferred from the patternedphotoresist structure 232 to thesecond mask layer 230. - In one embodiment, the
second mask layer 230 is patterned using an etch gas comprising fluorine-containing gas, nitrogen (N2), oxygen (O2) or combinations thereof. The fluorine-containing gas includes nitrogen hexafluoroethane (C2F6), tetrafluoromethane (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), octofluoropropane (C3F8), octofluorocyclobutane (C4F8), or combinations thereof. - In
operation 140 of themethod 100, a dry etching process may be performed to remove the top layer 238 and themiddle layer 236. As shown inFIG. 2E , only thebottom layer 234 of thetri-layer photoresist structure 232 is left after the dry etching process inoperation 140. - In
operation 145 of themethod 100, an angled etch process is performed to modify the patterned secondhard mask layer 230 along one direction as shown inFIGS. 2F and 2G . Ion beams 254 a and/orion beam 254 b are directed to thesubstrate 200 at an angle relative to the z-axis to modifysidewalls features 240 in the y-direction without affectingsidewalls 260 of thefeatures 240. -
FIG. 4 is a schematic plot of an angled etch process used in theoperation 145. Thesubstrate 202 havingfeatures 240 is positioned in the x-y plane. Thesubstrate 202 may be rotated about the z-axis so thatsidewalls 260 are along the y-direction or the longitudinal axis of thefeatures 240 is parallel to the y-axis. Ion beams 254 a, 254 b are directed towardssubstrate 202 in a plane substantially parallel to the y-z plane so that theion beans sidewalls 260 of thefeatures 240. Ion beams 254 a may have anangel 404 relative to the z-axis in the y-z plane. Ion beams 254 a may have anangel 406 relative to the z-axis. In one embodiment, ion beams 254 a, 254 b may be a ribbon of ion beams in aplane 402 scanning across the substrate along the x-direction. In other embodiments, ion beams 254 a, 254 b may be bulk ion beams directed to the entire surface of thesubstrate 202 simultaneously. - The
angles features 240 to achieve a target etch rate along the y-direction. In one embodiment, theangles feature 240 over the minimum length 244) is between about 1.0 to 10, for example about 5.0. In one embodiment, theangles feature 240 over the minimum length 244) is between about 1.0 to 10, for example about 5.0. - The
angles larger angel features 240. In one embodiment, one or both ofangles angles angles - In
operation 145, the ion beams 254 a are directed to thesubstrate 202 at theangle 404 so that the ion beams 254 a impinge thesecond mask layer 230 on thesidewall 258 a of thefeature 240 as shown inFIG. 2F . On the other hand, the ion beams 254 a do not directly impinge thesidewalls 260 of thefeatures 240. As a result, thefeatures 240 obtain alength increase 256 along the y-direction while thewidth 242 of thefeatures 240 remains unchanged. Similarly, the ion beams 254 b are directed to thesubstrate 202 at theangle 406 so that the ion beams 254 b impinge thesecond mask layer 230 on thesidewall 258 b of thefeatures 240 as shown inFIG. 2G . On the other hand, the ion beams 254 b do not directly impinge thesidewalls 260 of thefeature 240. As a result, thefeatures 240 obtain alength increase 262 along the y-direction while thewidth 242 of thefeatures 240 remains unchanged. - Depending on the recipe used in the
operation 145, one or bothion beams operation 145. - In one embodiment, the
ion beam - At
operation 155 of themethod 100, thebottom layer 234 of thetri-layer photoresist structure 232 is removed as shown inFIG. 2H . Thebottom layer 234 may be removed by a strip process, such as an ashing process. A wet cleaning process may be performed following the strip process. - The
features 240 have been modified tofeatures 240′. Thefeatures 240′ has alength 250 that is increased by the angled etch process in theoperation 145, and awidth 248 that is substantially the same as thewidth 242 of thefeatures 240. An end-to-end distance 252 between thefeatures 240′ is reduced from the end-to-end distance 246 between thefeatures 240. The dimension of thefeatures 240′ and the end-to-end distance 252 correspond to target dimensions to be formed in theinterlayer dielectric layer 226. -
FIG. 3B is a schematic plan view of apattern 300 b formed in the secondhard mask layer 230 after the angled etch process according to one embodiment of the present disclosure. Thepattern 300 b reflects a target pattern to be formed in theinterlayer dielectric layer 226. Thepattern 300 b includes the plurality ofunidirectional features 240′ modified from the plurality ofunidirectional features 240 in thepattern 300 a. Particularly, the plurality offeatures 240′ are arranged in multiple lines along the y-direction and have substantially thesame widths 248 along the x-direction. Thelengths 250 of the plurality offeatures 240′ along the y-direction are similar or different depending on the design of the integrated circuit. - The
width 248 of thefeatures 240′ may be between about 10 nm and 15 nm. According to embodiments of the present disclosure, the difference between thewidth 248 and thewidth 242 is less than 3 nm, for example, nearly 0 nm. In one embodiment, thelength 250 of thefeatures 240′ may be between about 35 nm to 130 nm. In one embodiment, the end-to-end distance 252 between the neighboringfeatures 240′ may be less than about 35 nm. For example, the end-to-end distance 252 may be less than 25 nm. In one embodiment, the end-to-end distance 252 is between about 20 nm and about 25 nm. - In the exemplary pattern of
FIG. 3B , thefeatures 240′Vss, 240′Vcc, 240′BL may have a length of about 110 nm, 65 nm, and 45 nm respectively. End-to-end distance between neighboringfeatures 240′Vss, 240′Vcc, 240′BL may be about 20 nm to 30 nm. Thefeatures 240′nN may have a length of about 85 nm. End-to-end space between neighboringfeatures 240′nN may be about 20 nm to 30 nm. Comparing thepatterns pattern 300 b, the end-to-end distance 252 is less than 35 nm. - In
operation 160 of themethod 100, an etch process is performed to transfer thepattern 300 b from the secondhard mask layer 230 to the firsthard mask layer 228 as shown inFIG. 2I .Operation 160 may be performed by a dry etch process using a plasma of an etch gas. In one embodiment, the etch gas includes chlorine or fluorine based gas when the firsthard mask layer 228 includes metals, such as titanium nitride, tungsten carbide. For example, the etch gas may include Sulfur hexafluoride (SF6), nitrogen tri-fluoride (NF3) combined with chlorine (Cl2), carbon tetrafluoride (CF4), hexafluoroethane (C2F6), chlorine (Cl2), Boron tri-chloride (BCl3), and a combination thereof. - In one embodiment,
operation 160 includes a wet cleaning process following the dry etch to remove residues from the substrate. Afteroperation 160, thepattern 300 b is transferred to the firsthard mask layer 228. - As discussed above, a below 35 nm end-to-end distance may be achieved using three photolithographic processes with three different patterns and four etch processes. The
method 100 achieves a below 35 nm end-to-end distance with one photolithographic process,operation 130, and three etch processes,operations method 100 reduces production time and cost by eliminating two photolithographic processes and one etch process. - In
operation 165 of themethod 100, theinterlayer dielectric layer 226 is patterned by an etch process using the firsthard mask layer 228 as a mask as shown inFIG. 2J . The etch process may be a dry etch process using a plasma of an etch gas. The etch gas may include fluorine-containing gas, nitrogen (N2), oxygen (O2) or combinations thereof. The fluorine-containing gas includes tetrafluoromethane (CF4), nitrogen hexafluoroethane (C2F6), trifluoromethane (CHF3), difluoromethane (CH2F2), octofluoropropane (C3F8), octofluorocyclobutane (C4F8), Octafluorocyclopentene (C5F8), or combinations thereof. - In one embodiment, the etch process in
operation 165 also etches through theetch stop layer 224 and theinterlayer dielectric layer 212 to form features 264. Thefeatures 264 may be trenches or vias opening to the source/drain regions, gate electrodes, or other regions of theFinFET device structure 204 for forming electrical contacts to theFinFET device structure 204. - In
operation 170 of themethod 100, a metallization process is performed to fill thefeatures 264 with electrically conductive material to makecontacts 266, as shown inFIG. 2K . In one embodiment, a planization process, such as a chemical mechanical polishing (CMP) process is performed after the metal fill. - In some embodiments, the conductive material used to make
contact 266 includes aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantulum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), tantulum carbide (TaC), tantulum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAI), titanium aluminide nitride (TiAIN), other applicable conductive materials, or a combination thereof. In some embodiments, thecontacts 266 include a titanium nitride layer and tungsten formed over the titanium nitride layer. - In some embodiments, the
contacts 266 may further include a liner and/or a barrier layer. For example, a liner (not shown) may be formed on the sidewalls and bottom of thecontact trench 264. The liner may be either tetraethylorthosilicate (TEOS) or silicon nitride, although any other applicable dielectric may alternatively be used. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other applicable processes, such as physical vapor deposition or a thermal process, may alternatively be used. The barrier layer (not shown) may be formed over the liner (if present) and may cover the sidewalls and bottom of the opening. The barrier layer may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition processes. The barrier layer may be made of tantalum nitride, although other materials, such as tantalum, titanium, titanium nitride, or the like, may also be used. - As shown in
FIG. 2K , thecontacts 266 are formed through theinterlayer dielectric layer 226. The end-to-end distance between themetal contacts 266 is less than 35 nm. In one embodiment, the end-to-end distance between themetal contacts 266 is between about 20 nm and about 25 nm. - The angled etch process according to the present disclosure, as discussed in
operation 145 of themethod 100, may be performed in a plasma chamber where ion beams can be directed to a substrate being processed at an angle. -
FIG. 5 is a schematic sectional view of aprocess apparatus 500 for performing the angled etch according to embodiment of the present disclosure. Theprocess apparatus 500 generates and directs an ion beam ribbon towards a substrate at an angle. - As shown in
FIG. 5 , theprocess apparatus 500 may include aprocess chamber 502 and a plasma chamber 504. Theprocess apparatus 500 may include anantenna 506. Theantenna 506 may be disposed outside the plasma chamber 504. Theantenna 506 may be electrically connected to a RF power supply (not shown), which supplies an alternating voltage to theantenna 506. The voltage may be at a frequency of, for example, 2 MHz or more, to generate a plasma in the plasma chamber 504. In operation, theantenna 506 is powered using a RF signal to inductively couple energy into the plasma chamber 504. The inductively coupled energy excites a process gas, such as the etch gas inoperation 145, introduced the plasma chamber, thus generating a plasma. - The plasma chamber 504 includes a chamber wall 508 having an
extraction aperture 510. The chamber wall 508 may be disposed on the side of theprocess chamber 502 facing a substrate carrier 512 disposed in theprocess chamber 502. Theextract aperture 510 is configured to direct a ribbon ofion beams 520 towards the substrate carrier 512. As shown in circle 518, theaperture 510 may be configured to direct the ribbon ofion beam 520 at various angels and combinations towards thesubstrate 514. - The substrate carrier 512 is configured to secure and move a
substrate 514 in the process chamber 512. The substrate carrier 512 may translate the along the x direction in theprocess chamber 502 so that the ribbon ofion beam 520 scan through the entire surface of thesubstrate 514 on the substrate carrier 512. - The
substrate 514 may be grounded during operation. An extraction power supply 516 may be used to apply an extraction voltage between thesubstrate 514 and the chamber wall 508. The extraction voltage may be between about 800 Volt and about 1200 volt, for example, about 1000 volt, although other voltages are within the scope of the disclosure. In addition, the extraction voltage may be a square wave, having a frequency of between about 1 kHz and 50 kHz, although other frequencies are within the scope of the disclosure. - When the extraction voltage is applied between the chamber wall 508 of the plasma chamber 504 and the
substrate 514, and the plasma within the plasma chamber 504 is biased by the extraction voltage relative to thesubstrate 514. The difference in potential between the plasma and thesubstrate 514 causes positively charged ions in the plasma to be accelerated through theextraction aperture 510 in the form of the ribbon ofion beam 520 and toward thesubstrate 514. - During operation, the
substrate 514 is disposed proximate and opposite the chamber wall 508 having theextraction aperture 510. In some embodiments, thesubstrate 514 may be positioned between about 5 mm and 15 mm away from theaperture 510, for example, about 12 mm. - In one embodiment, the
substrate 514 may be positioned relative to theextraction aperture 510 to align features on thesubstrate 514 to the ribbon ofion beams 520 to achieve the angled etch according to the present disclosure. In one embodiment, thesubstrate 514 may be pre-aligned before secured to the substrate carrier 512. In one embodiment, thesubstrate 514 may be rotated about the z-axis by the substrate carrier 512. In other embodiment, theextraction aperture 510 may be rotated about the z-axis. In other embodiment, both the substrate carrier 512 and theextraction aperture 510 may rotate about the z-axis. - The ribbon of
ion beam 520 may be at least as wide as thesubstrate 514 in one direction, such as the y-direction, and may be much narrower than thesubstrate 514 in the orthogonal direction (or x-direction). Thesubstrate 514 may be translated relative to theextraction aperture 510 such that different portions of thesubstrate 514 are exposed to the ribbon ofion beam 520. In another embodiment, the plasma chamber 504 may be translated while thesubstrate 514 remains stationary. In other embodiments, both the plasma chamber 504 and thesubstrate 514 may be translated. In some embodiments, thesubstrate 514 moves at a constant workpiece scan velocity relative to theextraction aperture 510 in the x-direction, so that the entirety of thesubstrate 514 is exposed to the ribbon ofion beam 520 for the same amount of time. -
FIG. 6 is a schematic sectional view of aprocess apparatus 600 for performing the angled etch according to embodiment of the present disclosure. Theprocess apparatus 600 generates and directs abulk ion beam 620 towards a substrate at an angle. - As shown in
FIG. 6 , theprocess apparatus 600 may include aprocess chamber 602 and aplasma chamber 604. Theprocess apparatus 600 may include anantenna 606. Theantenna 606 may be disposed outside theplasma chamber 604. Theantenna 606 may be electrically connected to a RF power supply (not shown), which supplies an alternating voltage to theantenna 606. The voltage may be at a frequency of, for example, 2 MHz or more, to generate a plasma in theplasma chamber 604. In operation, theantenna 606 is powered using a RF signal to inductively couple energy into theplasma chamber 604. The inductively coupled energy excites a process gas, such as the etch gas inoperation 145, which is introduced into theplasma chamber 604, thus generating a plasma. - The
plasma chamber 604 includes aplasm grill 608 having a plurality ofapertures 610. Theplasm grill 608 may be disposed over theprocess chamber 602 facing asubstrate carrier 612 disposed in theprocess chamber 602. The plurality ofapertures 610 are configured to direct thebulk ion beam 620 along the z-direction. Thebulk ion beam 620 may be directed towards thesubstrate 614 on thesubstrate carrier 612 at various impinging angles. The impinging angle of thebulk ion beam 620 is controlled by rotating the substrate carrier about the x-direction. - The
substrate carrier 612 is configured to secure and move asubstrate 614 in theprocess chamber 602. Thesubstrate carrier 612 may translate the along the z direction in theprocess chamber 602 to adjust the distance between thesubstrate 614 and theplasma grill 608. Thesubstrate carrier 612 may also rotate about the x-axis, y-axis, and z-axis to align thesubstrate 614 with thebulk ion beam 620 and to adjust the impinging angle of thebulk ion beam 620 at thesubstrate 614. As shown inFIG. 6 , the x-y-z coordinate system is selected where the z-axis passes through acenter axis 618 of thesubstrate carrier 612. - The
substrate 614 may be grounded during operation. Anextraction power supply 616 may be used to apply an extraction voltage between thesubstrate 614 and theplasma grill 608. The extraction voltage may be a constant voltage. Alternatively, the extraction voltage may be a square wave, having a frequency of between about 1 kHz and 50 kHz, although other frequencies are within the scope of the disclosure. - When the extraction voltage is applied between the
plasma grill 608 and thesubstrate 614, and the plasma within theplasma chamber 604 is biased by the extraction voltage relative to thesubstrate 614. The difference in potential between the plasma and thesubstrate 614 causes positively charged ions in the plasma to be accelerated through the plurality ofapertures 610 in theplasma grill 608 thebulk ion beam 620 toward thesubstrate 614. - Prior to performing an angled etch process according to the present disclosure, the
substrate 614 may be secured to thesubstrate carrier 612. Thesubstrate carrier 612 may rotate about the z-axis to align longitudinal axis of features on thesubstrate 614, such as thefeatures 240. For example, thesubstrate 614 may be rotated so that thelengths 244 of thefeatures 240 are parallel to the y-axis. Thesubstrate 614 may be rotated about the x-axis by thesubstrate carrier 612 to select an angle for the angled etch as disclosed in the present disclosure. - During the angled etch as described in
operation 145, the substrate remains stationary. In one embodiment, thesubstrate 614 may be rotated for 180 degrees about the z-axis at half time to balance the distance differences between theplasma grill 608 and different portions of thesubstrate 614. - In one example, the
method 100 of the present disclosure is performed using a process apparatus similar to theprocess apparatus 500 ofFIG. 5 to perform the angled etch inoperation 145 of themethod 100. - Prior to
operation 145, a first pattern is formed in a tri-layer photoresist layer. After a photolithographic process, the pattern includes a Vss feature, a Vcc feature, and a BL feature arranged repeatedly and sequentially lengthwise in a line. The Vss feature has a length of about 100 nm, the Vcc feature has a length of about 55 nm, and the BL feature has a length of about 35 nm. The end-to-end distance between the BL feature and the Vss feature is about 30 nm. The end-to-end distance between the Vss feature and the Vcc feature is about 30 nm. The end-to-end distance between the Vcc feature and the BL feature is about 30 nm. After etching a second hard mask, such as thehard mark 230, the pattern includes a Vss feature, a Vcc feature, and a BL feature arranged repeatedly and sequentially lengthwise in a line. The Vss feature has a length of about 80 nm, the Vcc feature has a length of about 35 nm, and the BL feature has a length of about 15 nm. The end-to-end distance between the BL feature and the Vss feature is about 50 nm. The end-to-end distance between the Vss feature and the Vcc feature is about 50 nm. The end-to-end distance between the Vcc feature and the BL feature is about 50 nm - An angled etch process is performed to the first pattern using a process apparatus similar to the
process apparatus 500. During operation, a 1000 Walt power is applied to the plasma source to generate a plasma of an etch gas. A 1000 volt extraction voltage is applied to extract a ribbon of ion beam. The etch gas includes 10 sccm of CF4, 5 sccm of CH3F and 9 sccm of Argon. The impinging angle of the ribbon of ion beam is about 21 degrees. The distance between the substrate and the extraction aperture is about 12 mm. The angled process is performed for 10-30 minutes. - After the angled etch process, the Vss feature has a length of about 110 nm, increased by 30 nm from the original length 80 nm. The Vcc feature has a length of about 65 nm, increased by 30 nm from the original length 35 nm. The BL feature has a length of about 45 nm, increased by 30 nm from the original length 15 nm. The variation in length change between long openings and short openings are less than 2 nm. The changes in width of the features are not detectable or less than 3 nm. The end-to-end distance between the BL feature and the Vss feature is about 25 nm. The end-to-end distance between the Vss feature and the Vcc feature is about 25 nm. The end-to-end distance between the Vcc feature and the BL feature is about 25 nm.
- Even though a process for patterning an interlayer metal dielectric layer is described above, embodiments of the present disclosure may be used for patterning layers to form unidirectional features with an end-to-end distance lower than 35 nm. For example, embodiments of the present disclosure may be used to pattern an active region with line features, for example to form fin in the active region, pattern a polysilicon layer, for example to form dummy gates in the polysilicon layer, or pattern a metal gate structure, for example to form isolation structures in metal gates.
- Even though a method for manufacturing FinFET devices is described above, embodiments of the present disclosure may be used in manufacturing of any suitable devices where there is a need to form a pattern with an end-to-end distance lower than 35 nm. For example, device elements include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high-voltage transistors, high-frequency transistors, p-channel and/or n channel field effect transistors (PFETs/NFETs), etc.), diodes, and/or other applicable elements.
- Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond 5 nm node fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.
- One embodiment of the present disclosure provides a method of processing a substrate. The method includes patterning a hard mask layer on the substrate to form a feature in the hard mask layer, and performing an angled etch process to modify the feature by increasing a length of the feature while maintaining a width of the feature. In some embodiments, performing the angled etch process includes directing an ion beam towards a top surface of the substrate, wherein a plane including the ion beam is parallel to a plane of a sidewall of the feature along the length of the feature. In some embodiments, the ion beam is at an impinging angle relative to a z-axis perpendicular to the top surface of the substrate. In some embodiments, the impinging angle is between about 10 degrees to about 30 degrees. In some embodiments, the method further includes selecting the impinging angle according to an aspect ratio of the feature. In some embodiments, the ion beam is a ribbon of ion beam covering a width of the substrate. In some embodiments, the ion beam is a bulk ion beam covering the entire top surface of the substrate. In some embodiments, the length of the feature is increased by about 20 nm to about 30 nm. In some embodiments, patterning the mask layer is performed by an extreme ultraviolet (EUV) lithographic process. In some embodiments, the method further includes removing a photoresist layer used in patterning the mask layer after performing the angled etch process.
- Another embodiment of the present disclosure provides a method of patterning a layer on a substrate. The method includes forming a first hard mask layer over the layer, forming a second mask layer over the first mask layer, forming a photoresist layer over the second mask layer, patterning the photoresist layer using a photolithographic process, etching the second mask layer using the photoresist layer as a mask to form a feature in the second mask layer, performing an angled etch to modify the feature by increasing a length of the feature without changing a width of the feature, and etching the first mask layer using the second mask layer as a mask. In some embodiments, the photolithographic process is an extreme ultraviolet (EUV) lithographic process. In some embodiments, performing the angled etch process includes directing an ion beam towards a top surface of the substrate, wherein a plane including the ion beam is parallel to a plane of a sidewall of the feature along the length of the feature. In some embodiments, the ion beam is at an impinging angle relative to a z-axis perpendicular to the top surface of the substrate. In some embodiments, the impinging angle is between about 10 degrees to about 30 degrees. In some embodiments, the ion beam is a ribbon of ion beam covering a width of the substrate. In some embodiments, the ion beam is a bulk ion beam covering the entire top surface of the substrate. In some embodiments, wherein the length of the feature is increased by about 20 nm to about 30 nm. In some embodiments, the semiconductor layer is one of an interlayer dielectric layer formed over FinFET device structures.
- Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device. The method includes patterning a hard mask layer on a substrate to form a first pattern in the hard mask layer, wherein the first pattern includes two or more unidirectional features aligned along a line having an end-to-end distance at a first value, and performing an angled etch process to reduce the end-to-end distance between two features from the first value to a second value without changing a width of the two or more features. In some embodiments, the second value of the end-to-end distance is less than 35 nm. In some embodiments, performing the angled etch process includes directing an ion beam towards a top surface of the substrate, wherein a plane including the ion beam is parallel to a plane of a sidewall of the feature along the length of the feature. In some embodiments, the ion beam is at an impinging angle relative to a z-axis perpendicular to the top surface of the substrate. In some embodiments, the ion beam is a bulk ion beam covering the entire top surface of the substrate. In some embodiments, the length of the feature is increased by about 20 nm to about 30 nm.
- Another embodiment of the present disclosure provides a method for forming a semiconductor device. The method includes forming an interlayer dielectric layer over gate structures of a FinFET structure, and patterning the interlayer dielectric layer to form a contact opening in the interlayer dielectric layer, including forming a first hard mask layer over the interlayer dielectric layer, forming a second hard mask layer over the first hard mask layer, patterning the second hard mask layer to form a first opening in the first hard mask layer, wherein a length of the first opening is shorter than a length of the contact opening, performing an angled etch process to increase the length of first opening without changing a width of the first opening, etching the first hard mask layer using the second hard mask as a mask, thereby, transferring the modified first opening to the first hard mask layer, and etching the interlayer dielectric layer to form the contact opening using the modified first opening in the first hard mask as a mask. In some embodiments, performing the angled etch process includes directing an ion beam towards a top surface of the substrate, wherein a plane including the ion beam is parallel to a plane of a sidewall of the first opening along the length of the first opening.
- Another embodiment of the present disclosure provides a method of forming a semiconductor device. The method includes forming an interlayer dielectric layer over gate structures of a FinFET structure, and patterning the interlayer dielectric layer to form a contact opening in the interlayer dielectric layer, including patterning a hard mask layer over the interlayer dielectric layer to form a first pattern in the hard mask layer, wherein the first pattern includes two or more unidirectional features aligned along a line having an end-to-end distance at a first value, and performing an angled etch process to increase a length of the two or more features without changing a width of the two or more features, thereby, reducing the end-to-end distance from the first value to a second value.
- Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The method includes forming a first pattern in a photoresist layer, wherein the first pattern includes unidirectional features, etching a mask layer below the photoresist layer using the photoresist layer as a mask to the first pattern in the mask layer, an directing an ion beam at an angle to increase lengths of the unidirectional features without enlarging a width of the unidirectional features. In some embodiments, the ion beam is directed along a plane parallel to a plane of sidewalls of the unidirectional features along the length of the unidirectional features.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/923,072 US10312089B1 (en) | 2017-11-29 | 2018-03-16 | Methods for controlling an end-to-end distance in semiconductor device |
DE102018124819.9A DE102018124819A1 (en) | 2017-11-29 | 2018-10-09 | A method of controlling an end-to-end distance in a semiconductor device |
CN201811247487.8A CN109841593B (en) | 2017-11-29 | 2018-10-25 | Method for manufacturing semiconductor device |
TW107141865A TWI770316B (en) | 2017-11-29 | 2018-11-23 | Method of patterning layer on substrate and method of forming semiconductor device |
KR1020180149524A KR102152758B1 (en) | 2017-11-29 | 2018-11-28 | Methods for controlling an end-to-end distance in semiconductor device |
US16/402,620 US10504729B2 (en) | 2017-11-29 | 2019-05-03 | Methods for controlling an end-to-end distance in semiconductor device |
US16/679,617 US10692720B2 (en) | 2017-11-29 | 2019-11-11 | Methods for controlling an end-to-end distance in semiconductor device |
Applications Claiming Priority (2)
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---|---|---|---|
US201762591890P | 2017-11-29 | 2017-11-29 | |
US15/923,072 US10312089B1 (en) | 2017-11-29 | 2018-03-16 | Methods for controlling an end-to-end distance in semiconductor device |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US16/402,620 Continuation US10504729B2 (en) | 2017-11-29 | 2019-05-03 | Methods for controlling an end-to-end distance in semiconductor device |
Publications (2)
Publication Number | Publication Date |
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US20190164759A1 true US20190164759A1 (en) | 2019-05-30 |
US10312089B1 US10312089B1 (en) | 2019-06-04 |
Family
ID=66442381
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
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US15/923,072 Active US10312089B1 (en) | 2017-11-29 | 2018-03-16 | Methods for controlling an end-to-end distance in semiconductor device |
US16/402,620 Active US10504729B2 (en) | 2017-11-29 | 2019-05-03 | Methods for controlling an end-to-end distance in semiconductor device |
US16/679,617 Active US10692720B2 (en) | 2017-11-29 | 2019-11-11 | Methods for controlling an end-to-end distance in semiconductor device |
Family Applications After (2)
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US16/402,620 Active US10504729B2 (en) | 2017-11-29 | 2019-05-03 | Methods for controlling an end-to-end distance in semiconductor device |
US16/679,617 Active US10692720B2 (en) | 2017-11-29 | 2019-11-11 | Methods for controlling an end-to-end distance in semiconductor device |
Country Status (5)
Country | Link |
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US (3) | US10312089B1 (en) |
KR (1) | KR102152758B1 (en) |
CN (1) | CN109841593B (en) |
DE (1) | DE102018124819A1 (en) |
TW (1) | TWI770316B (en) |
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Publication number | Publication date |
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US20200083046A1 (en) | 2020-03-12 |
CN109841593B (en) | 2021-05-11 |
KR20190063430A (en) | 2019-06-07 |
CN109841593A (en) | 2019-06-04 |
DE102018124819A1 (en) | 2019-05-29 |
TWI770316B (en) | 2022-07-11 |
KR102152758B1 (en) | 2020-09-08 |
TW201926415A (en) | 2019-07-01 |
US10692720B2 (en) | 2020-06-23 |
US10504729B2 (en) | 2019-12-10 |
US20190259613A1 (en) | 2019-08-22 |
US10312089B1 (en) | 2019-06-04 |
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