KR20130124149A - Method and system for modifying substrate patterned features using ion implantion - Google Patents

Abstract

A method of processing resist features includes positioning a substrate 112 having patterned resist features 114a on a first side of the substrate in the process chamber 302 and a substrate in the process chamber. Generating a plasma 306 having a plasma sheath 308b adjacent to the first side of the. The method uses a plasma sheath modifier 312 so that the portion in the form of a boundary is not parallel to the surface formed by the front surface of the substrate 112 facing the plasma. ) And modifying the boundary between the plasma sheath 308b, wherein ions 310 from the plasma during the first exposure are wide-angled on the patterned resist features 114a. Impinge to a wide angular range.

Description

METHOD AND SYSTEM FOR MODIFYING SUBSTRATE PATTERNED FEATURES USING ION IMPLANTION

Embodiments of the present invention relate to the field of device fabrication. More specifically, the present invention relates to methods, systems and structures for substrate patterning and implanting into a substrate for device fabrication.

Optical lithography is often used in the manufacture of electronic devices. This is a process that allows the substrate to be patterned so that a circuit can be formed on the substrate according to the pattern. 1A-1E, there are shown simplified diagrams of an optical lithographic process. Generally, substrate 112 is coated with a photocurable, polymeric photoresist 114 (FIG. 1A). Thereafter, a mask 142 having a desired opening pattern is deposited between the substrate 114 and a light source (not shown). Light 10 from the light source is irradiated onto the substrate 112 through the opening of the mask 142, and light transmitted through the opening (or image of the pattern) of the mask is projected onto the photoresist 114. The portion 114a of the photoresist is exposed to light 10 and cured, while the remaining portion 114b of the photoresist remains uncured (FIG. 1B). As a result, an image of the openings of the mask can be formed by the cured portion 114a of the photoresist.

As shown in FIG. 1C, the uncured portion 114b of the photoresist is removed and a three-dimensional photoresist feature or relief 114a corresponding to the opening pattern of the mask is removed from the substrate 112. ) May remain on. Thereafter, the substrate is etched, and trenches 116 corresponding to a negative image of the opening pattern of the mask can be formed (FIG. 1 d). After the remaining photoresist is removed, a circuit having the desired pattern can be formed on the substrate 112.

2, a conventional optical lithography system 200 for projecting an image of an opening pattern of a mask onto a substrate is shown. Optical lithography system 200 includes a light source 222, an optical integrator 232, and a condenser lens 234. In addition, the optical lithography system 200 may include a mask 142 and a projection lens 252 having a desired aperture pattern. As shown, light having a desired wavelength is emitted from the light source 222 to the optical integrator 232 and the condenser lens 234, which are collectively known as an illuminator 230. have. Within illumination system 230, light 10 is expanded, homogenized, focused, or adjusted. Light 10 is then irradiated onto the mask 142 with the desired opening pattern to be projected onto the substrate 112. Light 10 transmitted through the openings of the mask 142 may include information on the opening pattern of the mask. Light 10 is then captured by projection lens 252 which projects light 10 or an image of the opening pattern of the mask onto the photoresist deposited on substrate 112. In projecting an image, the projection lens 10 may reduce the image by four or five factors.

Several modifications can be implemented through the process to produce circuit patterns with smaller sized features (eg, the width of the trench). As is known in the art, the ability to project clear images of small features may, among other things, depend on the wavelength of light used in the process. Currently, ultraviolet light with wavelengths of 365 nm and 248 nm, and 193 nm is used. In particular, to produce circuits having a width of 13.5 nm, an argon fluoride (ArF) excimer laser having 193 nm has been proposed.

Although optical lithography is an efficient process with high throughput, the process is not without disadvantages. One of these drawbacks is line width roughness (LWR) or line edge roughness (LER) As is known in the art, LWR is an uncured photoresist from a substrate. Excessive changes in the width of the photoresist feature formed after the portion 114b has been removed If the changes occur on the side of the photoresist relief or feature, those changes are known as LERs.Rough due to LWR or LER Varnishes or changes can be disadvantageous in that they can be transferred onto trenches and ultimately into the circuit during etching, and changes become more important as the feature size of the photoresist relief or trenches is reduced. In the 193nm-based lithography process producing a 13.5nm feature size, more than 4nm changes were observed. Due to the geometry of the patterned resist features, including line roughness effects such as LWR and LER, transferred from the resist layer to the permanent lower layer of the device during patterning of the underlying layer, LWR and LER May limit the ability to form devices of acceptable quality for dimensions of about 100 nm or less These changes may result in non-uniform circuits and ultimately device degradation or failure. In addition, depending on design criteria, device performance may be more impacted by one of short, medium, or long range roughness.

Several treatments have been tried to address LWR and LER effects. In one example, a dry chemical etch process with the ability to remove resist was used, but unlike isolated features, removal in densely patterned areas should generally tolerate a pattern that is dependent on different loading effects. did. These dry chemical etching processes can also give the resist pattern unwanted defects that result in loss of yield. In addition, any process used to deal with LWR / LER effects in the resist may be applied to resist height, width, and, in order to maintain tight control of the critical dimesion (CD) of the underlying features to be patterned. It is important to leave fundamental resist properties such as profiles intact.

Another treatment used to address the LWR and LER effects is the deep ultraviolet (UDV) curing (extraviolet (UDV) curing) by exposing the rough pattern to a UV lamp where heating through radiation exposure removes the rough lines. curing). This approach has the undesirable side effect of causing pattern pullback at line segment corners and causing deformation of the lines in the same way as rendering the device useless.

In the case where the lines or other patterns have CD feature sizes below the diffraction limit of the illuminating radiation, to handle the diffraction limit of the UV lithography processing of the resist, double patterning lithography, DPL). In attempts to ensure the success of DPL, a number of processes have been used, including self aligned double patterning lithography and chemical freeze lithography. However, each of these processes may have both advantages and disadvantages with respect to cost and / or yield.

In addition to the challenges as described above with respect to resist patterning control, controlling the size and shape of patterned substrate features after their formation still remains a challenge. Control of etching conditions for the patterning of substrate features used to form devices such as polysilicon or metal gates, or silicon fins, in forming the final shape and size of these features after etching It can be important. In addition, processing steps, such as ion implantation, can affect the shape and size of these substrate features, especially if these features have dimensions of 100 nm or less. For example, ion implantation of substrates to provide doping of a device having silicon fins can result in inadvertent etching / sputtering of the fins. In some cases, silicon fins can result in firm faceting, which can significantly change the device characteristics of the pin-based devices to be formed.

In view of the above, processes such as resist lithography processes and device doping processes that affect device feature patterning, particularly for techniques that require very small feature sizes, such as CD devices below 100 nm, for example It will be appreciated that there is a need for improvement.

Embodiments of the present invention relate to methods and systems for improving substrate patterning, and more specifically, treatment of relief features, such as patterned resist features or permanent patterned substrate features. It is about. In one example, a resist feature processing method includes positioning, in a process chamber, a substrate having a set of patterned resist features on a first side of the substrate and adjacent to the first side of the substrate. Generating a plasma in a process chamber having a plasma sheath. The method comprises modifying the shape of the boundary between the plasma and the plasma sheath using a plasma sheath modifier such that the portion of the shape of the boundary is not parallel to the plane formed by the front surface of the substrate opposite the plasma. Wherein the ions from the plasma impinge on the patterned resist features in a wide angle range during the first exposure.

In another embodiment, a substrate patterning method includes providing a first set of patterned resist features on a substrate. The method includes exposing a first set of patterned resist features to a first exposure of ions extracted from a plasma sheath modifier operative to provide incidence of ions on a substrate in a wide angular range; And performing a lithographic patterning process on the substrate to form a second set of patterned resist features.

1A-1E are schematic cross sectional views of a substrate showing the steps of a conventional optical lithographic process.
2 is a schematic depiction of a conventional optical lithographic system for projecting an opening pattern of marks onto a substrate.
3A is a schematic depiction of a substrate processing system, in accordance with an embodiment of the present invention.
3B shows an exemplary angular distribution of incident particles on a substrate as provided by embodiments of the present invention.
4 shows a schematic cross-section of a plasma sheath modifier and resist feature showing exemplary features of the present invention.
5A-5D show exemplary results of an embodiment of three-dimensional resist pattern processing.
6 shows patterned silicon features after exposure of known ion implantation.
FIG. 7 shows exemplary wide-angle patterned silicon features after exposure of an ion flux. FIG.
8 illustrates an embodiment of three-dimensional processing.

In the following, the invention will be described in more detail with reference to the accompanying drawings in which preferred embodiments of the invention are shown. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In order to solve the drawbacks associated with the methods as described above, new and advanced techniques and systems for substrate patterning are introduced. In some embodiments, the method involves processing of temporary substrate features that will ultimately be removed, such as patterned photoresist features. In other embodiments, the methods relate to the processing of permanent device features such as semiconductor structures. Specifically, the present disclosure focuses on techniques related to ion implantation processes for improving the quality of resist features, such as LWR and LER improvement in resist features. The processes disclosed herein can be used in conjunction with processes for forming narrow features, including features incorporated into arrays with very small pitch, for example, pitches less than about 250 nm. have. Such processes include conventional DUV lithography, double patterned lithography, self-aligned double patterned lithography, and other lithography processes. However, those skilled in the art will appreciate that the techniques disclosed herein are not limited to being used with any range of dimensions in any particular lithography or resist characteristic.

Some embodiments of the present invention use plasma immersion implantation processes to process resist features with very small dimensions. Several embodiments are disclosed that include new techniques for processing three-dimensional (3D) structures. For clarity and simplicity, embodiments are described as techniques for photoresist processing with surfaces oriented at multiple angles. However, those skilled in the art will appreciate that the present disclosure is not so limited. The structure can be any type of structure with surfaces originated at different angles.

Embodiments are described as techniques using plasma based substrate processing systems. However, those skilled in the art are aware that other types of sub atomic, atomic, or molecular particle based substrate processing systems, including plasma sputtering as well as beam line ion implantation systems, are within the scope of the present invention. Will recognize.

Referring to FIG. 3A, a substrate processing system 300 for three-dimensional structure processing in accordance with one embodiment of the present invention is shown. 3B shows the angular distribution of the particles processing the photoresist. The drawings need not be drawn to scale.

As shown in FIG. 3A, the system 300 includes a process chamber 302 in which a substrate 112 and a platen 304 supporting the substrate 112 are deposited. In the present invention, the substrate 112 may be a metal material, a semiconductor material, or an insulating material based substrate. In the present invention, patterned photoresist may be deposited on a substrate. The patterned photoresist may be a cured portion of the photoresist that remains on the substrate after the uncured portion is removed.

System 300 may also include a plasma source (not shown) for generating plasma 306 included in processing chamber 302. The plasma source may be an in situ or remote, inductively coupled plasma source, capacitively coupled plasma source, helicon source, microwave source, or any other type of plasma source.

One or more plasma sheath modifiers 312 may be deposited between the plasma 306 and the substrate 112. In this example, the plasma sheath modifier 312 may include a pair of modifier parts 312a and 312b spaced apart from each other by a gap “y”. In other embodiments, the modifier 312 may include a single modifier. In still other embodiments, the modifier 312 may include three or more spaced correction parts that form a gap.

The plasma sheath corrector 312 may adjust the electric field of the plasma sheath. In some embodiments, the plasma sheath modifier 312 may be positively or negatively charged. The plasma sheath modifier 312 may be made from an electrically insulating (eg glass) or conductive (eg metal) material, or a combination thereof. If system 300 includes one or more correction units, the correction units may be made from the same or different materials. For example, system 300 may include a plasma sheath corrector 312, and the plasma sheath corrector 312 may include two rectifiers 312a and 312b. Corrections 312a and 312b may be made from the same or different material.

If the plasma sheath corrector 312 includes two or more correction parts, the correction parts may be deposited in the same plane or in different planes. For example, the plasma sheath modifier 312 included in the processing system 300 may include two rectifiers 312a and 312b. Corrections 312a and 312b may be deposited on the same plane such that the vertical spacings “z” between the substrate 112 and each correction portion may be the same. In another embodiment, the modifier 312 includes two correction portions 312a and 312b, each correction portion 312a and 312b spaced apart from the substrate 112 at different vertical spacings (z). May be A further description of a processing system with a plasma sheath corrector is described in US Patent Application No. 12 / 418,120, filed on Apr. 03, 2009 and concurrently incorporated by reference in its entirety; 12 / 417,929, and US Pat. No. 7,767,977; And 12/644103.

In operation, on-site or remotely generated plasma may be included in the processing chamber 302. The plasma 306 may include fragments containing electrons, protons, and radicals of atomic or molecular ions, neutrals, and preferred species. In the present invention, the plasma fragments 306 may be used for doping, etching, or depositing material on the substrate 112. The species included in the plasma 306 are not limited to one or more specific species. The species may include one or more elements from Groups I and 3A-8A. Examples of species contained within are hydrogen (H), helium (He) or other rare gases, carbon (C), oxygen (O), nitrogen (N), arsenic (As), boron (B) , Phosphorus (P), antimony, gallium (Ga), phosphorus (In), carborane (C ₂ B ₁₀ 0H ₁₂ ) or other molecular compounds. As shown in FIG. 3, the plasma 306 may also include a plasma sheath 308 adjacent to the periphery. In this embodiment, the plasma sheath 308 may include positively charged ions 310.

As shown in the figures, the sheath 308 is represented by the boundary of the sheath with the plasma 306. However, sheath 308 extends a finite distance from the edge of plasma 306 to the surfaces of objects around plasma 306, for example to the walls of chamber 302 and the surface of substrate 112. can do.

Ions 310 of plasma sheath 308 or plasma 306 may be directed to a substrate 112, such as substrate 112, biased by a DC or RF bias supply (not shown). The bias signal applied to the substrate 112, which is DC or RF, can be continuous or pulsed.

The plasma sheath modifier 312 may modify the shape of the plasma sheath 308 to control the angle of incidence distribution of the ions 310. For example, the plasma sheath modifier 312 may modify the electric field in the plasma sheath 242 and may modify the shape of the plasma sheath 308. In this embodiment, the plasma sheath modifier 312 corrects at least a portion of the sheath 308 with a plasma sheath 308b (modified sheath 308b) that is concave with respect to the bulk plasma 306. Or a dome shaped (convex) plasma relative to the bulk plasma. When the substrate 112 is biased, the ions 310 attracted to the substrate 112 may move over a large range of angles of incidence through the gap “y” between the rectifiers 312a and 312b. In conventional plasma based processing systems, the plasma sheath closest to the substrate lies parallel to the substrate. When the substrate is biased, the ions travel through a path that is generally perpendicular to the plasma sheath, and thus are generally perpendicular to the substrate. As a result, the ions in the conventional plasma processing system have an angle of incidence ranging from -3 ° to + 3 °. However, in this embodiment, the angle of incidence of the ions 310 can be modified using the modified sheath 308b. As shown in FIG. 3A, the modified sheath 308b is multi-angled with respect to the substrate. Thus, ions 310 moving perpendicular to the modified sheath 308b may move at a plurality of angles. Ions 310 moving from different portions of the modified sheath 308b toward the substrate 112 may have different angles of incidence, and the ions 310 will thus have a wide range of angles of incidence. As shown in FIG. 3B, the angles of incidence of ions 310 may range from about + 60 ° to −60 °, centered around 0 °. In some embodiments, the angles of incidence of the ions 310 may be further modified by the electric field generated by the plasma sheath modifier 312. Based on a number of factors, including but not limited to the configurations and characteristics of plasma sheath modifier 312, the angle of incidence of the ions may be further modified. Examples of such factors include the horizontal spacing Y between the correctors 312a and 312b, the vertical spacing Z between the modifier 312 and the substrate 112, the substrate 112 and the respective correctors 312a and The difference in the vertical spacing z between 312b) and the electrical properties of the modifier 312. Other plasma process parameters may also be adjusted to adjust the angle of incidence and / or angle of incidence of the ions. Further descriptions can be found in simultaneously pending US patent applications Nos. 12 / 418,120, 12/417929, 12/644103, which are incorporated herein by reference in their entirety.

By modifying the plasma sheath 312, a three-dimensional structure with surfaces originating at different angles can be processed conformally or isotropically. As mentioned below, the modified plasma sheath 312 can be used to treat multiple surfaces of three-dimensional structures, such as isotropically, for example, three-dimensional photoresist reliefs.

Referring to Fig. 4, a technique for three-dimensional structure processing in accordance with one embodiment of the present invention is shown. In this embodiment, the technique can be used to reduce the LER and LWR included in the three-dimensional photoresist relief 114a. As mentioned above, LER and LWR may occur in the three-dimensional photoresist relief 114a obtained during optical lithography after the uncured portion of the photoresist is removed. In this embodiment, LER and LWR included in photoresist relief 114a are plasma assisted doping (PLAD) or plasma immersion ion implantation using plasma sheath modifier 312 on different surfaces of relief 114a. By performing the PIII) processing, it can be reduced. Those skilled in the art will appreciate that features need not be scaled.

As shown in FIG. 4, a three-dimensional photoresist relief 114a having a side surface 114a-1 and an upper surface 114a-2 can be deposited on the substrate 112. Substrate 112 and photoresist relief 114a are deposited in a plasma processing system including plasma sheath modifier 312, and plasma is deposited near substrate 112. The ions 310 of the plasma may then be directed to the surfaces of the photoresist relief 114a through the gap between the plasma sheath corrections 312a and 312b. As shown in the figure, the ions 310 may be sent at a plurality of incident angles.

In this embodiment, ions 310 may be implanted into the side and top surfaces 114a-1 and 114a-2 of the photoresist relief 114a. Although various ionic species may be implanted, helium (He) or argon (Ar) ions may be implanted in the present invention. In embodiments of the present invention, the duration of exposure of the resist to ions may cover a wide range, and the exposure time may vary from about 1 second to several minutes.

Experiments were performed to determine the effect on the LER of a plasma processing system (PSM system) deployed in accordance with the present invention. As used hereinafter, the term “PSM system”, or “PSM plasma system,” utilizes a plasma sheath modifier to provide a wide range of angular distributions of ions directed to a substrate located adjacent to a portion of the plasma. Means a plasma processing system. The term "wide", "wide range", or "wide angular range", used with the angle of ion incidence, refers to a set of angles that span the total range of about 5 degrees or more. it means. Plasma sheath modifiers are used to provide exposure including doses of ions distributed over a wide angular range, as shown in FIG. 3B. In some cases, the term “extraction plate” includes a plate having an opening that leads to the formation of a modified plasma sheath (identifying component 308b), and also wherein the ions have a substrate over a wide angular range. It can be used to refer to a plasma sheath modifier that extracts ions from the plasma to impinge on.

Referring again to FIG. 4, a set of resist lines with a conventional CD of about 40 nm is exposed to a 3 kV helium plasma using an exemplary extraction plate. LER improved from 5.6 nm to 3.2 nm by implanting helium ions 310 at both 3-4 kV into both the top surface 114-2 and side surface 114a-1 of the photoresist relief 114a, and LER An improvement of about 40% was observed in and LWRs. By implanting helium ions using the plasma sheath modifier 312, these improvements are simultaneously isotropically on the plurality of surfaces 114a-1 and 114a-2 of the photoresist relief 114a. Occurred.

In addition, only minimal critical dimension shrinkage of the photoresist relief 114a has been observed. More specifically, the 39.1 nm CD measured before processing was reduced to only 37.6 nm after processing, which is only 4% when helium ions 310 are implanted into the resist relief 114a at multiple incidence angles. Reduction of Minimal faceting or sputtering is also observed. Since the PLAD or PIII process is a low energy process, the depth by the implanted ions 310 is very low. Thus, any change in photoresist relief 114a caused by ion implantation, such as, for example, resist shrinking and / or sputtering, can be minimized.

In various seals, the optimal line roughness for the patterned resist features can be based on the nature of the devices to be fabricated in the underlying substrate using the patterned resist. Thus, in embodiments of the present invention, the set of parameters can be tuned to bring about an optimal reduction in the desired roughness features. Such parameters may, among other things, include ion type, ion energy, resist type, resist feature size, as well as geometric features associated with the plasma sheath modifier. Referring again to FIG. 3A, the latter features include horizontal spacing (Y), vertical spacing (Z), and other factors disclosed in more detail in simultaneously pending US patent applications 12 / 418,120, 12/417929, and 12/644103. Include them.

Exemplary systems, methods, and components described above generally provide improved roughness results, such as reductions in LWR / LER, reductions in high, low, and intermediate frequency roughness variations, and similar. To provide patterned resist properties, it can be used in any combination.

In addition to reducing linewidth roughness, at the same time, isotropic hardening of a plurality of surfaces of photoresist features may be induced in accordance with some embodiments. Referring again to FIG. 4, after exposure to a wide angular range of ion flux, isotropic hardening is observed within the patterned resist features generally depicted as photoresist relief 114a. At the same time, isotropic curing of photoresist relief 114a may be advantageous when an additional optical lithographic process is performed to achieve a double patterned lithographic (DPL) or self-aligned double patterned lithographic (SADPL) process. For DPL or SADPL, a secondary lithographic process is performed to create additional photoresist reliefs between the two original photoresist reliefs formed during the first lithographic process. The formation of additional photoresist reliefs may reduce the distance between them, resulting in the substrate 112 with trenches of much smaller widths. During the secondary lithographic process, chemical treatment can be performed. If performed, the structure of the photoresist relief formed during the primary lithographic process can be negatively affected. In this embodiment, the isotropically cured photoresist relief 114a can withstand the chemical processing associated with the secondary lithographic process. Thus, additional lithographic processes may be enabled to achieve DPL or SADPL.

5A-5D show exemplary results of an embodiment of three-dimensional resist pattern processing. In this example, several different types of resist features, using an example extraction plate (plasma sheath modifier) to provide a wide angular range of ions, to clarify the operation of the example resist curing processes. Related to exposure. Referring to FIG. 5A, substrate 500 includes a portion 502 associated with example exposure to a wide angular distribution of ions using an example plasma sheath modifier, such as plate 312. In the example of FIG. 5A, a plate 312 having an opening 314 can be deposited on the substrate 500 to allow ions to impinge upon the substrate 500 through the opening 314. May be scanned along the y-direction with respect to the substrate 500. Referring also to FIG. 4, a view of the plate 312 shown in FIG. 4 follows the y-direction shown in FIG. 5D. 5B shows an enlarged view of portion 502, which includes patterned vertical resist lines 504 (long axes parallel to the y-direction) and a blanket portion 508. Substrate portion after exposure to exemplary wide angle ion flux 530 of resist features following exposure to liquid etchant used for the purpose of mimicking the resist development process ( 502 is shown. Although the structure of the resist features shown in the figure corresponds to their resulting structure after ion bombardment following exposure to the next liquid etchant, ion flux 530 is also shown in the figure.

As shown in the figures, in this example, the ions 530 are generally parallel to the y-direction (as formed in FIGS. 4 and 5) and as further shown in FIG. 5D. Impinges on the substrate portion 502, over a range of incidence angles. In FIG. 5D, each resist line 506 is bombarded by ions 520 on top of the resist line and along sidewalls 518. The etching results of the various resist features are shown at the top of FIG. 5B, and cross-sections along lines A-A 'and B-B' are shown in FIGS. 5C and 5D, respectively. As can be seen, selective etching of portions of resist features occurs, indicating the effect of exemplary wide angle ion bombardment on the etch resistance of patterned resist features.

More specifically, these portions of the resist features that are not subject to ion bombardment are very sensitive to etching. For example, the blanket region 508 is deposited parallel to the horizontal edge 516 and ions 530 exposed to the ions 530 and thus the vertical edge (not subjected to direct ion bombardment from the ions 530). 514). As shown in FIG. 5B, most of the resist etch occurs over a length L extending inwardly from the unprotected (ie, unimpacted) vertical edge 514. Similarly, vertical lines 504 each having a pair of unprotected vertical edges 510 are etched across their respective widths W, which are generally less than etch length L. Thus, the overall width of the lines 504 is largely invaded by etching. On the other hand, horizontal lines 506 that are subjected to ion bombardment along their entire sidewalls 518 are generally except for regions 540 immediately adjacent to small vertical notches that are not subjected to ion bombardment. Protected from etching.

Accordingly, embodiments of the present invention may utilize an exemplary plasma sheath modifier that allows patterned resist lines to be affected by a wide angle of ion flux to cure patterned resist features for subsequent processing. . This subsequent processing includes, for example, etchants that can easily invade the uncured resist. In some embodiments, patterned resist features can be arranged such that sidewalls and tops of the patterned resist features can be adapted to receive a wide angle of ion bombardment from an exemplary extraction plate. .

In one embodiment of the dual patterned lithographic process, in a first step, a first set of patterned resist features (reliefs) are formed using a first order lithographic process sequence. In a next step, the first set of patterned resist features is subjected to a first exposure that includes a wide angle of ion bombardment. The resist features may be arranged such that sidewalls and tops of the resist features are exposed to the ion flux. In this way, some or all of the resist surfaces that may be exposed to the next etchant may be cured to withstand the involvement of the etchant. Wide angle ion bombardment can be performed using a plasma sheath modifier provided for exposing sidewalls and tops of resist features to ions at the same time. In an additional step, a secondary lithographic process sequence is performed to form a second set of patterned resist features. In various embodiments, the first exposure resists in a manner that prevents or reduces resist features from being degraded, such as being etched or melted by chemical processing during a secondary lithographic processing sequence. Curing the first set of features.

In other various embodiments, additional substrate relief features, such as permanent features remaining on the substrate after final processing, may be exposed to a wide angle of ion flux. In some embodiments, semiconductor substrate features may be ion implanted with a wide angle of ion flux exposure using an extraction plate having a plasma sheath modifier. The semiconductor substrate features may be small semiconductor relief features, such as silicon-based materials including Si, SiGe alloys, or similar materials. This may be useful in the formation of devices using single crystal semiconductor features, such as known as FINFET double gate devices. For example, in some process sequences, a silicon structure, such as the channel region of a FINFET, may be affected by the ion implantation process. In conventional ion implantation procedures, the external shape of these silicon fins can be greatly altered by ion implantation, which can adversely affect device performance by final transistors formed using the FINFET process.

6 shows a profile of silicon relief features 602 after exposure to a conventional 1.4 kV argon ion implantation process. In this example, these features are 100 nm wide. As shown, the tops 604 show strong faceting and the sidewalls are generally inclined. In addition, the top of these features may be partially etched and the overall height of these features may be reduced.

In contrast, as shown in FIG. 7, a similar silicon relief feature 702 exposed at 4 kV to an exemplary wide angle argon ion implantation process shows minimal faceting in the top regions 704, and is generally alternative. As shown by the straight side walls. Thus, the exemplary wide angle ion implantation can result in a more ideal structure for a device fabricated from silicon relief features 702. This may in turn enable better device performance.

Although the embodiments of the present invention described above, overall, systems and processes that use ion bombardment to reduce the loss of critical dimensions that may occur in these smoothing processes and to reduce the roughness of surface features Even related to, other embodiments provide mechanisms that use ion bombardment to add material to surface patterned features. 8A and 8B, a simplified diagram of a technique for three-dimensional structure processing, in accordance with another embodiment of the present invention, is shown. In this embodiment, a technique for reducing the area of a hole is shown. In such an embodiment, the substrate 800 may be a metal substrate, a semiconductor substrate, or a dielectric substrate. The substrate 800 includes a hole 812. Although the present embodiment can be described in the processing context of a substrate having holes of the first radius R ₁ , the present invention is not limited thereto. Similar to the photoresist of the previous embodiments, the substrate 800 of this embodiment may simply be a structure having one or more vertically extending surfaces.

In this embodiment, the ions 310 are moved to the sidewall surface 814 of the hole 812 at a plurality of incident angles. As shown, sidewall 814 is formed and angled with respect to top surface 816 of substrate 800, and in some embodiments the angle may be about 90 degrees. Although ions are preferred, the present invention does not exclude other particles containing radicals or other neutrals. Ions 310 directed to the surface of the hole 812 may then be deposited on the surface of the hole 812, thereby forming a boundary layer 822 having a second radius R ₂ . By using the plasma sheath modifier 822, the ions 310 can be moved to the surface of the hole 812 at a plurality of incident angles. As a result, conformal and isotropic deposition may occur, and a boundary layer 822 having a uniform thickness may be formed. In addition, the radius of the original hole of the substrate 800 can be reduced from R ₁ to R ₂ isotropically and uniformly.

The methods disclosed herein may be automated, for example, by tangibly implementing a program of instructions on a computer readable storage medium that may be read by a machine capable of executing the instructions. A general purpose computer is one example of such a machine. A non-limiting and exemplary list of suitable storage media known in the art is readable or writable CDs, flash memory chips (eg, thumb drives), various magnetic storage media, and the like. And include such devices.

In summary, the present invention provides novel and advanced methods and systems for processing patterned features such as photoresist or permanent substrate relief structures. The present invention is effective in systems that use relatively low ion energy, such as plasma immersion systems that support the ability to provide ions and other species with only small penetration depth into patterned features. Can be used. This enables the ability to provide surface smoothing without significantly impacting resist pattern properties such as profile and CD. By providing a significant flux of ions at angles that are not at all common, the PSM architecture of the present invention provides for attacking resist features, ie resist sidewalls, in regions most directly affected by surface roughness. Is particularly efficient. Embodiments of the present invention, such as the use of an inert gas plasma, are not sensitive to pattern dependent effects that generally use dry chemical processes such as RIE. In addition, by using a plasma sheath modulator with plasma process systems such as an immersion injection system, the present invention provides great flexibility for tailoring resist processing processes. This is due to the variety of plasma parameters that can be conveniently and independently tuned, such as gas composition, ion energy, ion dose, and range of incidence angles of ions.

The invention is not limited by the specific embodiments described herein. Rather, in addition to the embodiments described herein, other various embodiments and modifications of the present invention will become apparent to those skilled in the art from the foregoing description and the accompanying drawings. Although the present invention can be used in plasma immersion ion implantation systems using low energy ions, ion bombardment effects can contribute to resist smoothing in addition to ion implantation and other or ion implantation, and the present invention provides low energy ions. This could be used for other possible plasma systems.

Also, in addition to implantation or deposition, the techniques disclosed herein can be used to perform etching on photoresist structures or other structures than photoresist structures. For example, the techniques disclosed in the present invention can be used in a photoresist trim process to reduce the critical dimensions of gates on transistors. In contrast to conventional trim processes in which the trim process is performed on one surface using O ₂ + HBr plasma simultaneously, the techniques of the present invention deliver an etching agent (eg, ions) at a plurality of angles, It can be used to perform the trimming process isotropically on a plurality of surfaces simultaneously. Thus, the trim process can be performed more efficiently and more uniformly. Accordingly, such other embodiments and modifications are intended to be within the scope of the present invention. Furthermore, although the invention has been described herein in the context of specific embodiments in specific circumstances for a particular purpose, those skilled in the art are not limited to the utility of the invention and the invention is not intended for any plurality of purposes. It will be appreciated that it may be usefully implemented in multiple environments. Accordingly, the subject matter of the present invention should be understood in view of the full breadth and spirit of the present invention as described herein.

Claims (20)

A method of treating resist features, the method comprising:
Generating a plasma having a plasma sheath adjacent the first surface of the substrate facing the plasma sheath in the process chamber; And
Modifying the shape of the boundary formed between the plasma and the plasma sheath using a plasma sheath modifier,
Wherein the portion in the form of the boundary is not parallel to the plane formed by the first surface of the substrate, and ions from the plasma impinge on the substrate over a range of angles with respect to the plane. . The method according to claim 1,
The modifying step creates a gap defined by a pair of parts, wherein the parts comprise one of insulators, semiconductors, and metals. Including,
The shape of the boundary around the gap is convex with respect to the plane. The method according to claim 1,
The modifying step comprises forming a gap in the plate, wherein the plate comprises one of an insulator, a conductor, and a semiconductor,
Wherein the shape of the boundary around the gap is convex with respect to the plane. The method according to claim 2,
Wherein said range of angles of incidence is between about + 60 ° and −60 ° centered about about 0 °. The method according to claim 1,
Wherein the energy and species of ions are arranged to significantly reduce the linewidth roughness of the patterned resist features on the substrate. The method according to claim 1,
The first exposure is sufficient to result in a significant reduction in low frequency line width roughness (LWR). The method according to claim 1,
The ions from the plasma are inert gas ions. In the substrate patterning method,
Providing a first set of patterned resist features on the substrate;
The first set of patterned resist features is subjected to a first exposure of ions extracted from a plasma sheath modifier operative to provide incidence of ions on the substrate over a range of angles relative to the substrate. Exposing; And
Performing a lithographic patterning process on the substrate to form a second set of patterned resist features. The method according to claim 8,
Wherein said first and second set of patterned resist features are formed using a dual patterning lithographic process. The method according to claim 8,
The first exposure hardens the first set of patterned resist features that remains intact during the lithographic patterning process used to form the second set of patterned resist features. And to operate. The method according to claim 8,
The plasma sheath modifier forms a gap therebetween, such that the shape of the boundary of the plasma adjacent to the gap becomes convex with respect to the plane of the substrate, the first insulator portion and the second insulation. Comprising a part. The method according to claim 8,
Wherein the first exposure comprises exposure to inert gas ions. The method according to claim 8,
Wherein the ion energy of the ions of the first exposure is less than about 20 keV. The method according to claim 8,
After the first exposure, the linewidth roughness of the first set of patterned resist features is greatly reduced. The method according to claim 8,
The first and second set of patterned resist features are subjected to a second exposure of ions extracted from a plasma sheath modifier operative to provide incidence of ions on the substrate over a wide range of angles. Further including exposing,
After the second exposure, the linewidth roughness of the second set of patterned resist features is reduced. A method of injecting patterned crystalline features into a substrate, the method comprising:
Generating a plasma having a plasma sheath adjacent a first side of a substrate positioned in said process chamber in a plasma chamber;
Modifying the shape of the boundary between the plasma and the plasma sheath using a plasma sheath modifier such that a portion of the shape of the boundary is not parallel to the plane formed by the front surface of the substrate opposite the plasma; And
Providing a bias between the substrate and the plasma,
Ions are implanted into the patterned crystalline features over a wide range of angles without causing faceting on the patterned crystalline features. And wherein said patterned crystalline features are silicon based features. In the method of processing a hole in a substrate,
Generating a plasma having a plasma sheath adjacent to a first surface of the substrate opposite the plasma sheath in the process chamber, the substrate comprising a hole sidewall surface angled with respect to the first surface; ; And
Using a plasma sheath corrector to modify the shape of the boundary formed between the plasma and the plasma sheath,
Said shape of said boundary is not parallel to the surface formed by said first surface of said substrate, wherein ions from said plasma impinge on said sidewall surface of said hole over a range of angles. 19. The method of claim 18,
Wherein the ions comprise species determined to be condensed on the surface of the hole. 19. The method of claim 18,
The modifying step comprises forming a gap in the plate, wherein the plate comprises one of an insulator, a metal and a semiconductor,
Wherein said shape of said boundary around said gap is convex with respect to the plane formed by said first surface of said substrate.

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