US20190148396A1 - Method of manufacturing three-dimensional stacked semiconductor structure and structure manufactured by the same - Google Patents
Method of manufacturing three-dimensional stacked semiconductor structure and structure manufactured by the same Download PDFInfo
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- US20190148396A1 US20190148396A1 US15/814,582 US201715814582A US2019148396A1 US 20190148396 A1 US20190148396 A1 US 20190148396A1 US 201715814582 A US201715814582 A US 201715814582A US 2019148396 A1 US2019148396 A1 US 2019148396A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 50
- 229920005591 polysilicon Polymers 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 230000002093 peripheral effect Effects 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 35
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims 1
- 239000000463 material Substances 0.000 description 5
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- SEOYNUHKXVGWFU-UHFFFAOYSA-N mu-oxidobis(oxidonitrogen) Chemical compound O=NON=O SEOYNUHKXVGWFU-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H01L21/02518—Deposited layers
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/02612—Formation types
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
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- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
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- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
Definitions
- the disclosure relates in general to a method of manufacturing a three-dimensional (3D) stacked semiconductor structure and a 3D stacked semiconductor structure manufactured by the same, and more particularly to a method of manufacturing a 3D stacked structure having thick conductive pads.
- the disclosure relates to a method of manufacturing a three-dimensional (3D) stacked semiconductor structure and a structure manufactured by the same.
- the structure provides the conductive pads with increased thickness for contact landing, thereby improving the reliability of electrical performance of the 3D stacked semiconductor structure.
- a three-dimensional (3D) stacked semiconductor structure comprising: a substrate, having an array area and a peripheral area; patterned multi-layered stacks formed in the array area and above the substrate, and the patterned multi-layered stacks spaced apart from each other, and channel holes between the patterned multi-layered stacks disposed adjacently; a charge trapping layer formed on the patterned multi-layered stacks and deposited in the channel holes as liners; a polysilicon channel layer deposited along the charge trapping layer; and conductive pads formed on the polysilicon channel layer and respectively corresponding to the patterned multi-layered stacks, wherein the polysilicon channel layer has a first thickness (t 1 ), one of the conductive pads has a second thickness (t 2 ), and the second thickness (t 2 ) is larger than the first thickness (t 1 ).
- patterned multi-layered stacks above a substrate and within above the substrate of the substrate, wherein the patterned multi-layered stacks are spaced apart from each other, and channel holes between the patterned multi-layered stacks disposed adjacently; forming a charge trapping layer on the patterned multi-layered stacks, and the charge trapping layer deposited in the channel holes as liners; depositing a polysilicon channel layer on the charge trapping layer and formed along the charge trapping layer; and forming conductive pads on the polysilicon channel layer and respectively corresponding to the patterned multi-layered stacks, wherein the polysilicon channel layer has a first thickness (t 1 ), one of the conductive pads has a second thickness (t 2 ), and the second thickness (t 2 ) is larger than the first thickness (t 1 ).
- FIG. 2 depicts a 3D stacked semiconductor structure according to an embodiment of the present disclosure.
- a method of manufacturing a three-dimensional (3D) stacked semiconductor structure and a 3D stacked semiconductor structure manufactured by the same are provided.
- the conductive pads above the patterned multi-layered stacks are thickened such as by a selective epitaxial growth process, and the structure having thicker conductive pads can be obtained for solving the problem of contact landing on the thin pads of the conventional structure.
- an embodied structure provides reliable conductive pads with increased thickness for landing the conductive contacts (ex: BL contacts), thereby improving the reliability of electrical performance of the 3D stacked semiconductor structure.
- the method of the embodiment causes no damage to the related layers and components of the structure, and the method of the embodiment is also suitable for manufacturing the 3D stacked semiconductor structure with large number of the stacking layers without affecting the configuration of structure of the embodiment.
- the embodiment of the present disclosure could be implemented in many different 3D stacked semiconductor structures in the applications.
- the embodiment could be applied to, but not limited to, the 3D vertical-channel (VC) semiconductor devices.
- the embodiment is provided hereinafter with reference to the accompanying drawings for elaborating the method of manufacturing the 3D stacked semiconductor structure of the disclosure and the structure manufactured by the same.
- the present disclosure is not limited thereto.
- the descriptions disclosed in the embodiments of the disclosure such as detailed structures, manufacturing procedures and material selections are for illustration only, not for limiting the scope of protection of the disclosure.
- FIG. 1A — FIG. 1H illustrate a method of manufacturing a 3D stacked semiconductor structure according to an embodiment of the present disclosure.
- a multi-layered stack 11 M is formed above a substrate 10 , and the multi-layered stack 11 M comprises a plurality of insulating layers 111 and a plurality of conductive layers 112 arranged alternately along a second direction D 2 (ex: Z-direction) vertical to the substrate 10 .
- the insulating layers 111 could be oxide layers
- the conductive layers 112 could be polysilicon layers (ex: heavily doped N+ polysilicon layers or heavily doped P+ polysilicon layers).
- a polysilicon channel layer 14 is deposited on the charge trapping layer 13 and formed along the charge trapping layer 13 (ex: the polysilicon channel layer 14 conformally deposited on the charge trapping layer 13 ), as shown in FIG. 1D .
- the charge trapping layer 13 deposited in the channel holes 12 is formed on the buried oxide layer 115 ′ and directly in contact with the buried oxide layer 115 ′ since the channel holes 12 are extended downwardly to stop on the buried oxide layer 115 ′.
- the polysilicon channel layer 14 and the buried oxide layer 115 ′ are separated by the charge trapping layer 13 .
- the dielectric medium layer 15 is recessed downwardly to expose at least a top portion 140 of the polysilicon channel layer 14 , as shown in FIG. 1F .
- the dielectric medium layer 15 is recessed by etching back step.
- conductive pads 16 are formed on the polysilicon channel layer 14 and respectively corresponding to the patterned multi-layered stacks 11 M′, as shown in FIG. 1G .
- a selective epitaxial growth process is applied to grow the conductive pads 16 on the polysilicon channel layer 14 , and the material of the conductive pads 16 and the polysilicon channel layer 14 would be the same.
- a selective epitaxial growth process is conducted at a temperature of about 800° C.
- the polysilicon channel layer 14 has a first thickness t 1
- one of the conductive pads 16 has a second thickness t 2 , wherein the second thickness t 2 is larger than the first thickness t 1 .
- the polysilicon channel layer 14 also covers a top surface 13 a of the charge trapping layer 13 , and the top portion 140 of the polysilicon channel layer 14 is formed on the top surface 13 a of the charge trapping layer 13 .
- the epi-polysilicon film only grows on the top portion 140 of the polysilicon channel layer 14 rather than on other material such as oxide (i.e. not grows on the dielectric medium layer 15 ).
- conductive contacts 17 are respectively formed on the conductive pads 16 , wherein the conductive contacts 17 are electrically connected to the conductive pads 16 correspondingly, as shown in FIG. 1H .
- the conductive layers 112 function as word lines (WLs), and the conductive pads 16 are bit line (BL) pads, and the conductive contacts 17 are BL contacts.
- FIG. 2 depicts a 3D stacked semiconductor structure according to an embodiment of the present disclosure.
- the polysilicon channel layer 14 has a first thickness t 1
- one of the conductive pads 16 has a second thickness t 2 , wherein the second thickness t 2 is larger than the first thickness t 1 .
- a length of the polysilicon channel layer 14 parallel to a first direction D 1 (ex: along X-direction) of FIG. 2 is determined as the first thickness t 1
- a length of the conductive pads 16 parallel to a second direction D 2 is determined as the second thickness t 2 herein, wherein the second direction D 2 is perpendicular to the first direction D 1 .
- a ratio of the second thickness t 2 to the first thickness t 1 is in a range of 2 to 10, such as in a range of 2 to 5.
- the first thickness t 1 is in a range of 50 ⁇ to 150 ⁇ .
- the second thickness t 2 is in a range of 200 ⁇ to 600 ⁇ .
- the second thickness t 2 is about 400 ⁇ when the adjacent conductive pads 16 are spaced apart from about 100 nm. It is noted that those numerical values described herein are provided for illustration, not for limitation.
- the conductive pads above the patterned multi-layered stacks are thickened such as by a selective epitaxial growth process, and the embodied structure provides reliable conductive pads with increased thickness for landing the conductive contacts (ex: BL contacts).
- the selective epitaxy since the selective epitaxy only grows films on the polysilicon material rather than oxide material, the neighboring conductive pads can keep in excellent isolation. Hence the contact etching can stop on the thicker conductive pads (ex: BL pads) without increasing the thickness of the polysilicon channel layer. Therefore, the reliability of electrical performance of the 3D stacked semiconductor structure can be improved.
- the method of the embodiment causes no damage to the related layers and components of the structure
- the method of the embodiment is also suitable for manufacturing the 3D stacked semiconductor structure with large number of the stacking layers without affecting the configuration of structure of the embodiment (i.e. structure possesses a solid construction, a complete profile of the related layers and components).
- the 3D stacked semiconductor structure of the embodiment is manufactured by adopting no time-consuming and expensive procedures, which is suitable for mass production.
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Abstract
Description
- The disclosure relates in general to a method of manufacturing a three-dimensional (3D) stacked semiconductor structure and a 3D stacked semiconductor structure manufactured by the same, and more particularly to a method of manufacturing a 3D stacked structure having thick conductive pads.
- A nonvolatile semiconductor memory device is typically designed to securely hold data even when power is lost or removed from the memory device. Various types of nonvolatile memory devices have been proposed in the related art. Also, manufactures have been looking for new developments or techniques combination for stacking multiple planes of memory cells, so as to achieve greater storage capacity. For example, several types of multi-layer stackable NAND-type flash memory structures have been proposed. However, the typical 3D stacked semiconductor structure still suffers from some problems.
- For example, for a single gate vertical channel 3D NAND flash, it is necessary to form thin channel for device performance. However contact landing will become a challenge when the channel polysilicon is too thin to land on, which is a problem for the manufacturers.
- The disclosure relates to a method of manufacturing a three-dimensional (3D) stacked semiconductor structure and a structure manufactured by the same. According to the embodiment, the structure provides the conductive pads with increased thickness for contact landing, thereby improving the reliability of electrical performance of the 3D stacked semiconductor structure.
- According to one embodiment of the present disclosure, a three-dimensional (3D) stacked semiconductor structure is provided, comprising: a substrate, having an array area and a peripheral area; patterned multi-layered stacks formed in the array area and above the substrate, and the patterned multi-layered stacks spaced apart from each other, and channel holes between the patterned multi-layered stacks disposed adjacently; a charge trapping layer formed on the patterned multi-layered stacks and deposited in the channel holes as liners; a polysilicon channel layer deposited along the charge trapping layer; and conductive pads formed on the polysilicon channel layer and respectively corresponding to the patterned multi-layered stacks, wherein the polysilicon channel layer has a first thickness (t1), one of the conductive pads has a second thickness (t2), and the second thickness (t2) is larger than the first thickness (t1).
- According to one embodiment of the present disclosure, is provided, comprising: forming patterned multi-layered stacks above a substrate and within above the substrate of the substrate, wherein the patterned multi-layered stacks are spaced apart from each other, and channel holes between the patterned multi-layered stacks disposed adjacently; forming a charge trapping layer on the patterned multi-layered stacks, and the charge trapping layer deposited in the channel holes as liners; depositing a polysilicon channel layer on the charge trapping layer and formed along the charge trapping layer; and forming conductive pads on the polysilicon channel layer and respectively corresponding to the patterned multi-layered stacks, wherein the polysilicon channel layer has a first thickness (t1), one of the conductive pads has a second thickness (t2), and the second thickness (t2) is larger than the first thickness (t1).
- The disclosure will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
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FIG. 1A —FIG. 1H illustrate a method of manufacturing a 3D stacked semiconductor structure according to an embodiment of the present disclosure. -
FIG. 2 depicts a 3D stacked semiconductor structure according to an embodiment of the present disclosure. - In the embodiments of the present disclosure, a method of manufacturing a three-dimensional (3D) stacked semiconductor structure and a 3D stacked semiconductor structure manufactured by the same are provided. According to a method of the embodiment, the conductive pads above the patterned multi-layered stacks are thickened such as by a selective epitaxial growth process, and the structure having thicker conductive pads can be obtained for solving the problem of contact landing on the thin pads of the conventional structure. Accordingly, an embodied structure provides reliable conductive pads with increased thickness for landing the conductive contacts (ex: BL contacts), thereby improving the reliability of electrical performance of the 3D stacked semiconductor structure. Moreover, the method of the embodiment causes no damage to the related layers and components of the structure, and the method of the embodiment is also suitable for manufacturing the 3D stacked semiconductor structure with large number of the stacking layers without affecting the configuration of structure of the embodiment.
- The embodiment of the present disclosure could be implemented in many different 3D stacked semiconductor structures in the applications. For example, the embodiment could be applied to, but not limited to, the 3D vertical-channel (VC) semiconductor devices. The embodiment is provided hereinafter with reference to the accompanying drawings for elaborating the method of manufacturing the 3D stacked semiconductor structure of the disclosure and the structure manufactured by the same. However, the present disclosure is not limited thereto. The descriptions disclosed in the embodiments of the disclosure such as detailed structures, manufacturing procedures and material selections are for illustration only, not for limiting the scope of protection of the disclosure.
- Also, it is noted that not all embodiments of the invention are shown. Modifications and variations can be made without departing from the spirit of the disclosure to meet the requirements of the practical applications. Thus, there may be other embodiments of the present disclosure which are not specifically illustrated. It is also important to point out that the illustrations may not be necessarily be drawn to scale. Thus, the specification and the drawings are to be regard as an illustrative sense rather than a restrictive sense.
- Moreover, use of ordinal terms such as “first”, “second”, “third” etc., in the specification and claims to describe an element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having the same name (but for use of the ordinal term) to distinguish the claim elements.
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FIG. 1A —FIG. 1H illustrate a method of manufacturing a 3D stacked semiconductor structure according to an embodiment of the present disclosure. As shown inFIG. 1A , amulti-layered stack 11M is formed above asubstrate 10, and themulti-layered stack 11M comprises a plurality ofinsulating layers 111 and a plurality ofconductive layers 112 arranged alternately along a second direction D2 (ex: Z-direction) vertical to thesubstrate 10. In one embodiment, theinsulating layers 111 could be oxide layers, and theconductive layers 112 could be polysilicon layers (ex: heavily doped N+ polysilicon layers or heavily doped P+ polysilicon layers). - In one exemplified (but not limited) example, the structure may further comprise a buried
oxide layer 115 formed on thesubstrate 10, a bottom gate layer (ex: an inversion gate) 114 formed on the buriedoxide layer 115, and a bottom oxide layer 113 (ex: an inversion oxide) is formed on thebottom gate layer 114, and themulti-layered stack 11M is formed on thebottom oxide layer 113, as shown inFIG. 1A . Also, in one exemplified (but not limited) example, a top polysilicon layer (ex: string select line (SSL) polysilicon layer) 116 is formed on themulti-layered stack 11M, a top oxide layer (ex: SSL oxide) 117 is formed on thetop polysilicon layer 116, and a cap layer (ex: SIN as a hard mask (HM)) 118 is formed on thetop oxide layer 117. - Then, the
multi-layered stack 11M is patterned, such as by etching, to formseveral channel holes 12 and patternedmulti-layered stack 11M′ vertically to thesubstrate 10. As shown inFIG. 1B , the patternedmulti-layered stack 11M′ above thesubstrate 10 are spaced apart from each other. Also, thechannel holes 12 penetrate thecap layer 118, thetop oxide layer 117, thetop polysilicon layer 116, themulti-layered stack 11M, thebottom oxide layer 113 and thebottom gate layer 114. Thechannel holes 12 are extended downwardly to stop on the buriedoxide layer 115′, and expose the sidewalls of theinsulating layers 111′ and theconductive layers 112′. - Afterward, a
charge trapping layer 13 is formed on the patternedmulti-layered stacks 11M′, and thecharge trapping layer 13 is deposited in thechannel holes 12 as liners, as shown inFIG. 1C . In one embodiment, the charge trappinglayer 13 functions as a memory layer and could be an ONO layer or an ONONO layer or an ONONONO layer. For example, thecharge trapping layer 13 may comprise a blocking oxide layer (adjacent to the sidewalls of theinsulating layers 111 and the sidewalls of the conductive layers 112), a trapping nitride layer and a tunneling oxide layer. In the exemplified drawings of the embodiment, one integrated layer is depicted as thecharge trapping layer 13 for clear illustration. - Then, a
polysilicon channel layer 14 is deposited on thecharge trapping layer 13 and formed along the charge trapping layer 13 (ex: thepolysilicon channel layer 14 conformally deposited on the charge trapping layer 13), as shown inFIG. 1D . In one embodiment, thecharge trapping layer 13 deposited in thechannel holes 12 is formed on the buriedoxide layer 115′ and directly in contact with the buriedoxide layer 115′ since thechannel holes 12 are extended downwardly to stop on the buriedoxide layer 115′. Thus, thepolysilicon channel layer 14 and the buriedoxide layer 115′ are separated by thecharge trapping layer 13. - After depositing the
polysilicon channel layer 14 on thecharge trapping layer 13, the method further comprises depositing a dielectric medium layer (such as oxide) 15 on the patternedmulti-layered stacks 11M′ for covering thepolysilicon channel layer 14 and filling up rest spaces inside thechannel holes 12, as shown inFIG. 1E . - Then, the
dielectric medium layer 15 is recessed downwardly to expose at least atop portion 140 of thepolysilicon channel layer 14, as shown inFIG. 1F . In one embodiment, thedielectric medium layer 15 is recessed by etching back step. - Afterward, several
conductive pads 16 are formed on thepolysilicon channel layer 14 and respectively corresponding to the patternedmulti-layered stacks 11M′, as shown inFIG. 1G . In one embodiment, a selective epitaxial growth process is applied to grow theconductive pads 16 on thepolysilicon channel layer 14, and the material of theconductive pads 16 and thepolysilicon channel layer 14 would be the same. In one example, a selective epitaxial growth process is conducted at a temperature of about 800° C. for about 6 minutes (process time of main step), under a DCS (diclolo-silane, SiH2Cl2)—HCl—H2 system (gas ratio=DCS/HCV H2=200 sccm/180 sccm/25 slm), wherein the silicon loss is about 200 A. According to the embodied structure, thepolysilicon channel layer 14 has a first thickness t1, and one of theconductive pads 16 has a second thickness t2, wherein the second thickness t2 is larger than the first thickness t1. - According to an embodiment, the
polysilicon channel layer 14 also covers atop surface 13 a of thecharge trapping layer 13, and thetop portion 140 of thepolysilicon channel layer 14 is formed on thetop surface 13 a of thecharge trapping layer 13. When a selective epitaxial growth process is applied, the epi-polysilicon film only grows on thetop portion 140 of thepolysilicon channel layer 14 rather than on other material such as oxide (i.e. not grows on the dielectric medium layer 15). - After forming the
conductive pads 16, several conductive contacts 17 (such as Bit line contacts) are respectively formed on theconductive pads 16, wherein theconductive contacts 17 are electrically connected to theconductive pads 16 correspondingly, as shown inFIG. 1H . In one embodiment of a VC type 3D semiconductor structure of the application, theconductive layers 112 function as word lines (WLs), and theconductive pads 16 are bit line (BL) pads, and theconductive contacts 17 are BL contacts. -
FIG. 2 depicts a 3D stacked semiconductor structure according to an embodiment of the present disclosure. As shown inFIG. 2 , thepolysilicon channel layer 14 has a first thickness t1, one of theconductive pads 16 has a second thickness t2, wherein the second thickness t2 is larger than the first thickness t1. It is noted that a length of thepolysilicon channel layer 14 parallel to a first direction D1 (ex: along X-direction) ofFIG. 2 is determined as the first thickness t1, and a length of theconductive pads 16 parallel to a second direction D2 (ex: along Z-direction) is determined as the second thickness t2 herein, wherein the second direction D2 is perpendicular to the first direction D1. Moreover, according an embodied configuration as shown inFIG. 2 , theconductive layers 112 of one of the patternedmulti-layered stacks 11M′ has a first width W1 along the first direction D1, one of theconductive pads 16 has a second width W2 along the first direction D1, wherein the second width W2 is larger than the first width W1. - Also, in one embodiment, a ratio of the second thickness t2 to the first thickness t1 is in a range of 2 to 10, such as in a range of 2 to 5. In one embodiment, the first thickness t1 is in a range of 50 Å to 150 Å. In one embodiment, the second thickness t2 is in a range of 200 Å to 600 Å. In one (but not limited) example, the second thickness t2 is about 400 Å when the adjacent
conductive pads 16 are spaced apart from about 100 nm. It is noted that those numerical values described herein are provided for illustration, not for limitation. - Noted that the configuration of the application could be slightly different, depending on the actual layers required in the practical application. For example, in one (but not limited) example, the charge trapping layer is formed on the
cap layer 118; thus, for the configuration of one stack, thecap layer 118, thetop oxide layer 117, thetop polysilicon layer 116, the patternedmulti-layered stack 11M′, thebottom oxide layer 113, thebottom gate layer 114 and the buriedoxide layer 115 are contained in thecharge trapping layer 13, as shown inFIG. 2 . However, those stacked layers would be modified or changed depending on the types of the semiconductor structures of the application. - According to the method and structures of the 3D stacked semiconductor structure as illustrated in the embodiment above, the conductive pads above the patterned multi-layered stacks are thickened such as by a selective epitaxial growth process, and the embodied structure provides reliable conductive pads with increased thickness for landing the conductive contacts (ex: BL contacts). In one embodiment, since the selective epitaxy only grows films on the polysilicon material rather than oxide material, the neighboring conductive pads can keep in excellent isolation. Hence the contact etching can stop on the thicker conductive pads (ex: BL pads) without increasing the thickness of the polysilicon channel layer. Therefore, the reliability of electrical performance of the 3D stacked semiconductor structure can be improved. Moreover, the method of the embodiment causes no damage to the related layers and components of the structure, and the method of the embodiment is also suitable for manufacturing the 3D stacked semiconductor structure with large number of the stacking layers without affecting the configuration of structure of the embodiment (i.e. structure possesses a solid construction, a complete profile of the related layers and components). Furthermore, the 3D stacked semiconductor structure of the embodiment is manufactured by adopting no time-consuming and expensive procedures, which is suitable for mass production.
- It is noted that the structures and methods as described above are provided for illustration. The disclosure is not limited to the configurations and procedures disclosed above. Other embodiments with different configurations of known elements can be applicable, and the exemplified structures could be adjusted and changed based on the actual needs of the practical applications. It is, of course, noted that the configurations of figures are depicted only for demonstration, not for limitation. Thus, it is known by people skilled in the art that the related elements and layers in the array area of a 3D stacked semiconductor structure, the shapes or positional relationship of the elements and the procedure details could be adjusted or changed according to the actual requirements and/or manufacturing steps of the practical applications.
- While the disclosure has been described by way of example and in terms of the exemplary embodiment(s), it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
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