US20190042090A1 - Technologies for separating control plane management from data plane management for distributed storage in a disaggregated architecture - Google Patents
Technologies for separating control plane management from data plane management for distributed storage in a disaggregated architecture Download PDFInfo
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- US20190042090A1 US20190042090A1 US15/922,493 US201815922493A US2019042090A1 US 20190042090 A1 US20190042090 A1 US 20190042090A1 US 201815922493 A US201815922493 A US 201815922493A US 2019042090 A1 US2019042090 A1 US 2019042090A1
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Abstract
Description
- The present application claims the benefit of Indian Provisional Patent Application No. 201741030632, filed Aug. 30, 2017 and U.S. Provisional Patent Application No. 62/584,401, filed Nov. 10, 2017.
- In some data centers, data sets may be stored in multiple data storage devices located in different areas of the data center (e.g., in different failure domains). Typically, in such systems, one compute device may receive a request to store a data set (e.g., a payload) and may store the data set in one or more data storage devices that are physically located on the compute device (e.g., connected through a local data bus such as a Peripheral Component Interconnect Express (PCIe) bus). Additionally, the compute device may send the data set to one or more other similarly equipped compute devices (e.g., in different failure domains), to store the same data set in data storage devices that are physically located on those compute devices. As such, typical distributed data storage systems are designed such that control plane management operations (e.g., selection of compute devices that are to store the data set) and data plane management operations (e.g., allocation of data blocks on a physical data storage device, fragmentation management, etc.) are performed on the same compute device.
- In data centers in which resources are disaggregated (e.g., some compute devices have comparatively more compute resources and less data storage resources, or comparatively more data storage resources and less compute resources), typical data storage systems may operate less efficiently, as the resources for performing both compute intensive operations (e.g., control plane operations) and storage device management operations (e.g., data plane management) are not equally present in the same physical compute device. For example, a data storage-focused compute device may have insufficient compute resources to efficiently perform control plane management operations.
- The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
-
FIG. 1 is a simplified diagram of at least one embodiment of a data center for executing workloads with disaggregated resources; -
FIG. 2 is a simplified diagram of at least one embodiment of a pod that may be included in the data center ofFIG. 1 ; -
FIG. 3 is a perspective view of at least one embodiment of a rack that may be included in the pod ofFIG. 2 ; -
FIG. 4 is a side elevation view of the rack ofFIG. 3 ; -
FIG. 5 is a perspective view of the rack ofFIG. 3 having a sled mounted therein; -
FIG. 6 is a is a simplified block diagram of at least one embodiment of a top side of the sled ofFIG. 5 ; -
FIG. 7 is a simplified block diagram of at least one embodiment of a bottom side of the sled ofFIG. 6 ; -
FIG. 8 is a simplified block diagram of at least one embodiment of a compute sled usable in the data center ofFIG. 1 ; -
FIG. 9 is a top perspective view of at least one embodiment of the compute sled ofFIG. 8 ; -
FIG. 10 is a simplified block diagram of at least one embodiment of an accelerator sled usable in the data center ofFIG. 1 ; -
FIG. 11 is a top perspective view of at least one embodiment of the accelerator sled ofFIG. 10 ; -
FIG. 12 is a simplified block diagram of at least one embodiment of a storage sled usable in the data center ofFIG. 1 ; -
FIG. 13 is a top perspective view of at least one embodiment of the storage sled ofFIG. 12 ; -
FIG. 14 is a simplified block diagram of at least one embodiment of a memory sled usable in the data center ofFIG. 1 ; and -
FIG. 15 is a simplified block diagram of a system that may be established within the data center ofFIG. 1 to execute workloads with managed nodes composed of disaggregated resources; -
FIG. 16 is a simplified block diagram of at least one embodiment of a system for providing distributed storage with physically separated control plane management and data plane management in a disaggregated architecture; -
FIGS. 17-19 are a simplified block diagram of at least one embodiment of a method for executing control plane management operations in response to a data access request that may be performed by a compute sled ofFIG. 16 ; and -
FIGS. 20-21 are a simplified block diagram of at least one embodiment of a method for executing data plane management operations that may be performed by a data storage sled ofFIG. 16 . - While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.
- References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).
- The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).
- In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features.
- Referring now to
FIG. 1 , adata center 100 in which disaggregated resources may cooperatively execute one or more workloads (e.g., applications on behalf of customers) includesmultiple pods data center 100 is shown with multiple pods, in some embodiments, thedata center 100 may be embodied as a single pod. As described in more detail herein, each rack houses multiple sleds, each of which may be primarily equipped with a particular type of resource (e.g., memory devices, data storage devices, accelerator devices, general purpose processors), i.e., resources that can be logically coupled to form a composed node, which can act as, for example, a server. In the illustrative embodiment, the sleds in eachpod spine switches 150 that switch communications among pods (e.g., thepods data center 100. In some embodiments, the sleds may be connected with a fabric using Intel Omni-Path technology. In other embodiments, the sleds may be connected with other fabrics, such as InfiniBand or Ethernet. As described in more detail herein, resources within sleds in thedata center 100 may be allocated to a group (referred to herein as a “managed node”) containing resources from one or more sleds to be collectively utilized in the execution of a workload. The workload can execute as if the resources belonging to the managed node were located on the same sled. The resources in a managed node may belong to sleds belonging to different racks, and even todifferent pods - A data center comprising disaggregated resources, such as
data center 100, can be used in a wide variety of contexts, such as enterprise, government, cloud service provider, and communications service provider (e.g., Telco's), as well in a wide variety of sizes, from cloud service provider mega-data centers that consume over 100,000 sq. ft. to single- or multi-rack installations for use in base stations. - The disaggregation of resources to sleds comprised predominantly of a single type of resource (e.g., compute sleds comprising primarily compute resources, memory sleds containing primarily memory resources), and the selective allocation and deallocation of the disaggregated resources to form a managed node assigned to execute a workload improves the operation and resource usage of the
data center 100 relative to typical data centers comprised of hyperconverged servers containing compute, memory, storage and perhaps additional resources in a single chassis. For example, because sleds predominantly contain resources of a particular type, resources of a given type can be upgraded independently of other resources. Additionally, because different resources types (processors, storage, accelerators, etc.) typically have different refresh rates, greater resource utilization and reduced total cost of ownership may be achieved. For example, a data center operator can upgrade the processors throughout their facility by only swapping out the compute sleds. In such a case, accelerator and storage resources may not be contemporaneously upgraded and, rather, may be allowed to continue operating until those resources are scheduled for their own refresh. Resource utilization may also increase. For example, if managed nodes are composed based on requirements of the workloads that will be running on them, resources within a node are more likely to be fully utilized. Such utilization may allow for more managed nodes to run in a data center with a given set of resources, or for a data center expected to run a given set of workloads, to be built using fewer resources. - Referring now to
FIG. 2 , thepod 110, in the illustrative embodiment, includes a set ofrows racks 240. Eachrack 240 may house multiple sleds (e.g., sixteen sleds) and provide power and data connections to the housed sleds, as described in more detail herein. In the illustrative embodiment, the racks in eachrow pod switch 250 includes a set ofports 252 to which the sleds of the racks of thepod 110 are connected and another set ofports 254 that connect thepod 110 to the spine switches 150 to provide connectivity to other pods in thedata center 100. Similarly, thepod switch 260 includes a set ofports 262 to which the sleds of the racks of thepod 110 are connected and a set ofports 264 that connect thepod 110 to the spine switches 150. As such, the use of the pair ofswitches pod 110. For example, if either of theswitches pod 110 may still maintain data communication with the remainder of the data center 100 (e.g., sleds of other pods) through theother switch switches - It should be appreciated that each of the
other pods pod 110 shown in and described in regard toFIG. 2 (e.g., each pod may have rows of racks housing multiple sleds as described above). Additionally, while twopod switches pod FIGS. 1-2 . For example, a pod may be embodied as multiple sets of racks in which each set of racks is arranged radially, i.e., the racks are equidistant from a center switch. - Referring now to
FIGS. 3-5 , eachillustrative rack 240 of thedata center 100 includes two elongated support posts 302, 304, which are arranged vertically. For example, the elongated support posts 302, 304 may extend upwardly from a floor of thedata center 100 when deployed. Therack 240 also includes one or morehorizontal pairs 310 of elongated support arms 312 (identified inFIG. 3 via a dashed ellipse) configured to support a sled of thedata center 100 as discussed below. Oneelongated support arm 312 of the pair ofelongated support arms 312 extends outwardly from theelongated support post 302 and the otherelongated support arm 312 extends outwardly from theelongated support post 304. - In the illustrative embodiments, each sled of the
data center 100 is embodied as a chassis-less sled. That is, each sled has a chassis-less circuit board substrate on which physical resources (e.g., processors, memory, accelerators, storage, etc.) are mounted as discussed in more detail below. As such, therack 240 is configured to receive the chassis-less sleds. For example, eachpair 310 ofelongated support arms 312 defines asled slot 320 of therack 240, which is configured to receive a corresponding chassis-less sled. To do so, each illustrativeelongated support arm 312 includes acircuit board guide 330 configured to receive the chassis-less circuit board substrate of the sled. Eachcircuit board guide 330 is secured to, or otherwise mounted to, atop side 332 of the correspondingelongated support arm 312. For example, in the illustrative embodiment, eachcircuit board guide 330 is mounted at a distal end of the correspondingelongated support arm 312 relative to the correspondingelongated support post circuit board guide 330 may be referenced in each Figure. - Each
circuit board guide 330 includes an inner wall that defines acircuit board slot 380 configured to receive the chassis-less circuit board substrate of asled 400 when thesled 400 is received in thecorresponding sled slot 320 of therack 240. To do so, as shown inFIG. 4 , a user (or robot) aligns the chassis-less circuit board substrate of anillustrative chassis-less sled 400 to asled slot 320. The user, or robot, may then slide the chassis-less circuit board substrate forward into thesled slot 320 such that eachside edge 414 of the chassis-less circuit board substrate is received in a correspondingcircuit board slot 380 of the circuit board guides 330 of thepair 310 ofelongated support arms 312 that define thecorresponding sled slot 320 as shown inFIG. 4 . By having robotically accessible and robotically manipulable sleds comprising disaggregated resources, each type of resource can be upgraded independently of each other and at their own optimized refresh rate. Furthermore, the sleds are configured to blindly mate with power and data communication cables in eachrack 240, enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. As such, in some embodiments, thedata center 100 may operate (e.g., execute workloads, undergo maintenance and/or upgrades, etc.) without human involvement on the data center floor. In other embodiments, a human may facilitate one or more maintenance or upgrade operations in thedata center 100. - It should be appreciated that each
circuit board guide 330 is dual sided. That is, eachcircuit board guide 330 includes an inner wall that defines acircuit board slot 380 on each side of thecircuit board guide 330. In this way, eachcircuit board guide 330 can support a chassis-less circuit board substrate on either side. As such, a single additional elongated support post may be added to therack 240 to turn therack 240 into a two-rack solution that can hold twice asmany sled slots 320 as shown inFIG. 3 . Theillustrative rack 240 includes sevenpairs 310 ofelongated support arms 312 that define a corresponding sevensled slots 320, each configured to receive and support acorresponding sled 400 as discussed above. Of course, in other embodiments, therack 240 may include additional orfewer pairs 310 of elongated support arms 312 (i.e., additional or fewer sled slots 320). It should be appreciated that because thesled 400 is chassis-less, thesled 400 may have an overall height that is different than typical servers. As such, in some embodiments, the height of eachsled slot 320 may be shorter than the height of a typical server (e.g., shorter than a single rank unit, “1 U”). That is, the vertical distance between eachpair 310 ofelongated support arms 312 may be less than a standard rack unit “1 U.” Additionally, due to the relative decrease in height of thesled slots 320, the overall height of therack 240 in some embodiments may be shorter than the height of traditional rack enclosures. For example, in some embodiments, each of the elongated support posts 302, 304 may have a length of six feet or less. Again, in other embodiments, therack 240 may have different dimensions. For example, in some embodiments, the vertical distance between eachpair 310 ofelongated support arms 312 may be greater than a standard rack until “1 U”. In such embodiments, the increased vertical distance between the sleds allows for larger heat sinks to be attached to the physical resources and for larger fans to be used (e.g., in thefan array 370 described below) for cooling each sled, which in turn can allow the physical resources to operate at increased power levels. Further, it should be appreciated that therack 240 does not include any walls, enclosures, or the like. Rather, therack 240 is an enclosure-less rack that is opened to the local environment. Of course, in some cases, an end plate may be attached to one of the elongated support posts 302, 304 in those situations in which therack 240 forms an end-of-row rack in thedata center 100. - In some embodiments, various interconnects may be routed upwardly or downwardly through the elongated support posts 302, 304. To facilitate such routing, each
elongated support post sled slot 320, power interconnects to provide power to eachsled slot 320, and/or other types of interconnects. - The
rack 240, in the illustrative embodiment, includes a support platform on which a corresponding optical data connector (not shown) is mounted. Each optical data connector is associated with acorresponding sled slot 320 and is configured to mate with an optical data connector of acorresponding sled 400 when thesled 400 is received in thecorresponding sled slot 320. In some embodiments, optical connections between components (e.g., sleds, racks, and switches) in thedata center 100 are made with a blind mate optical connection. For example, a door on each cable may prevent dust from contaminating the fiber inside the cable. In the process of connecting to a blind mate optical connector mechanism, the door is pushed open when the end of the cable approaches or enters the connector mechanism. Subsequently, the optical fiber inside the cable may enter a gel within the connector mechanism and the optical fiber of one cable comes into contact with the optical fiber of another cable within the gel inside the connector mechanism. - The
illustrative rack 240 also includes afan array 370 coupled to the cross-support arms of therack 240. Thefan array 370 includes one or more rows of coolingfans 372, which are aligned in a horizontal line between the elongated support posts 302, 304. In the illustrative embodiment, thefan array 370 includes a row of coolingfans 372 for eachsled slot 320 of therack 240. As discussed above, eachsled 400 does not include any on-board cooling system in the illustrative embodiment and, as such, thefan array 370 provides cooling for eachsled 400 received in therack 240. Eachrack 240, in the illustrative embodiment, also includes a power supply associated with eachsled slot 320. Each power supply is secured to one of theelongated support arms 312 of thepair 310 ofelongated support arms 312 that define thecorresponding sled slot 320. For example, therack 240 may include a power supply coupled or secured to eachelongated support arm 312 extending from theelongated support post 302. Each power supply includes a power connector configured to mate with a power connector of thesled 400 when thesled 400 is received in thecorresponding sled slot 320. In the illustrative embodiment, thesled 400 does not include any on-board power supply and, as such, the power supplies provided in therack 240 supply power to correspondingsleds 400 when mounted to therack 240. Each power supply is configured to satisfy the power requirements for its associated sled, which can vary from sled to sled. Additionally, the power supplies provided in therack 240 can operate independent of each other. That is, within a single rack, a first power supply providing power to a compute sled can provide power levels that are different than power levels supplied by a second power supply providing power to an accelerator sled. The power supplies may be controllable at the sled level or rack level, and may be controlled locally by components on the associated sled or remotely, such as by another sled or an orchestrator. - Referring now to
FIG. 6 , thesled 400, in the illustrative embodiment, is configured to be mounted in acorresponding rack 240 of thedata center 100 as discussed above. In some embodiments, eachsled 400 may be optimized or otherwise configured for performing particular tasks, such as compute tasks, acceleration tasks, data storage tasks, etc. For example, thesled 400 may be embodied as acompute sled 800 as discussed below in regard toFIGS. 8-9 , anaccelerator sled 1000 as discussed below in regard toFIGS. 10-11 , astorage sled 1200 as discussed below in regard toFIGS. 12-13 , or as a sled optimized or otherwise configured to perform other specialized tasks, such as amemory sled 1400, discussed below in regard toFIG. 14 . - As discussed above, the
illustrative sled 400 includes a chassis-lesscircuit board substrate 602, which supports various physical resources (e.g., electrical components) mounted thereon. It should be appreciated that thecircuit board substrate 602 is “chassis-less” in that thesled 400 does not include a housing or enclosure. Rather, the chassis-lesscircuit board substrate 602 is open to the local environment. The chassis-lesscircuit board substrate 602 may be formed from any material capable of supporting the various electrical components mounted thereon. For example, in an illustrative embodiment, the chassis-lesscircuit board substrate 602 is formed from an FR-4 glass-reinforced epoxy laminate material. Of course, other materials may be used to form the chassis-lesscircuit board substrate 602 in other embodiments. - As discussed in more detail below, the chassis-less
circuit board substrate 602 includes multiple features that improve the thermal cooling characteristics of the various electrical components mounted on the chassis-lesscircuit board substrate 602. As discussed, the chassis-lesscircuit board substrate 602 does not include a housing or enclosure, which may improve the airflow over the electrical components of thesled 400 by reducing those structures that may inhibit air flow. For example, because the chassis-lesscircuit board substrate 602 is not positioned in an individual housing or enclosure, there is no vertically-arranged backplane (e.g., a backplate of the chassis) attached to the chassis-lesscircuit board substrate 602, which could inhibit air flow across the electrical components. Additionally, the chassis-lesscircuit board substrate 602 has a geometric shape configured to reduce the length of the airflow path across the electrical components mounted to the chassis-lesscircuit board substrate 602. For example, the illustrative chassis-lesscircuit board substrate 602 has awidth 604 that is greater than adepth 606 of the chassis-lesscircuit board substrate 602. In one particular embodiment, for example, the chassis-lesscircuit board substrate 602 has a width of about 21 inches and a depth of about 9 inches, compared to a typical server that has a width of about 17 inches and a depth of about 39 inches. As such, anairflow path 608 that extends from afront edge 610 of the chassis-lesscircuit board substrate 602 toward arear edge 612 has a shorter distance relative to typical servers, which may improve the thermal cooling characteristics of thesled 400. Furthermore, although not illustrated inFIG. 6 , the various physical resources mounted to the chassis-lesscircuit board substrate 602 are mounted in corresponding locations such that no two substantively heat-producing electrical components shadow each other as discussed in more detail below. That is, no two electrical components, which produce appreciable heat during operation (i.e., greater than a nominal heat sufficient enough to adversely impact the cooling of another electrical component), are mounted to the chassis-lesscircuit board substrate 602 linearly in-line with each other along the direction of the airflow path 608 (i.e., along a direction extending from thefront edge 610 toward therear edge 612 of the chassis-less circuit board substrate 602). - As discussed above, the
illustrative sled 400 includes one or morephysical resources 620 mounted to atop side 650 of the chassis-lesscircuit board substrate 602. Although twophysical resources 620 are shown inFIG. 6 , it should be appreciated that thesled 400 may include one, two, or morephysical resources 620 in other embodiments. Thephysical resources 620 may be embodied as any type of processor, controller, or other compute circuit capable of performing various tasks such as compute functions and/or controlling the functions of thesled 400 depending on, for example, the type or intended functionality of thesled 400. For example, as discussed in more detail below, thephysical resources 620 may be embodied as high-performance processors in embodiments in which thesled 400 is embodied as a compute sled, as accelerator co-processors or circuits in embodiments in which thesled 400 is embodied as an accelerator sled, storage controllers in embodiments in which thesled 400 is embodied as a storage sled, or a set of memory devices in embodiments in which thesled 400 is embodied as a memory sled. - The
sled 400 also includes one or more additionalphysical resources 630 mounted to thetop side 650 of the chassis-lesscircuit board substrate 602. In the illustrative embodiment, the additional physical resources include a network interface controller (NIC) as discussed in more detail below. Of course, depending on the type and functionality of thesled 400, thephysical resources 630 may include additional or other electrical components, circuits, and/or devices in other embodiments. - The
physical resources 620 are communicatively coupled to thephysical resources 630 via an input/output (I/O)subsystem 622. The I/O subsystem 622 may be embodied as circuitry and/or components to facilitate input/output operations with thephysical resources 620, thephysical resources 630, and/or other components of thesled 400. For example, the I/O subsystem 622 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, waveguides, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In the illustrative embodiment, the I/O subsystem 622 is embodied as, or otherwise includes, a double data rate 4 (DDR4) data bus or a DDR5 data bus. - In some embodiments, the
sled 400 may also include a resource-to-resource interconnect 624. The resource-to-resource interconnect 624 may be embodied as any type of communication interconnect capable of facilitating resource-to-resource communications. In the illustrative embodiment, the resource-to-resource interconnect 624 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the resource-to-resource interconnect 624 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to resource-to-resource communications. - The
sled 400 also includes apower connector 640 configured to mate with a corresponding power connector of therack 240 when thesled 400 is mounted in thecorresponding rack 240. Thesled 400 receives power from a power supply of therack 240 via thepower connector 640 to supply power to the various electrical components of thesled 400. That is, thesled 400 does not include any local power supply (i.e., an on-board power supply) to provide power to the electrical components of thesled 400. The exclusion of a local or on-board power supply facilitates the reduction in the overall footprint of the chassis-lesscircuit board substrate 602, which may increase the thermal cooling characteristics of the various electrical components mounted on the chassis-lesscircuit board substrate 602 as discussed above. In some embodiments, voltage regulators are placed on a bottom side 750 (seeFIG. 7 ) of the chassis-lesscircuit board substrate 602 directly opposite of the processors 820 (seeFIG. 8 ), and power is routed from the voltage regulators to theprocessors 820 by vias extending through thecircuit board substrate 602. Such a configuration provides an increased thermal budget, additional current and/or voltage, and better voltage control relative to typical printed circuit boards in which processor power is delivered from a voltage regulator, in part, by printed circuit traces. - In some embodiments, the
sled 400 may also include mountingfeatures 642 configured to mate with a mounting arm, or other structure, of a robot to facilitate the placement of the sled 600 in arack 240 by the robot. The mounting features 642 may be embodied as any type of physical structures that allow the robot to grasp thesled 400 without damaging the chassis-lesscircuit board substrate 602 or the electrical components mounted thereto. For example, in some embodiments, the mounting features 642 may be embodied as non-conductive pads attached to the chassis-lesscircuit board substrate 602. In other embodiments, the mounting features may be embodied as brackets, braces, or other similar structures attached to the chassis-lesscircuit board substrate 602. The particular number, shape, size, and/or make-up of the mountingfeature 642 may depend on the design of the robot configured to manage thesled 400. - Referring now to
FIG. 7 , in addition to thephysical resources 630 mounted on thetop side 650 of the chassis-lesscircuit board substrate 602, thesled 400 also includes one ormore memory devices 720 mounted to abottom side 750 of the chassis-lesscircuit board substrate 602. That is, the chassis-lesscircuit board substrate 602 is embodied as a double-sided circuit board. Thephysical resources 620 are communicatively coupled to thememory devices 720 via the I/O subsystem 622. For example, thephysical resources 620 and thememory devices 720 may be communicatively coupled by one or more vias extending through the chassis-lesscircuit board substrate 602. Eachphysical resource 620 may be communicatively coupled to a different set of one ormore memory devices 720 in some embodiments. Alternatively, in other embodiments, eachphysical resource 620 may be communicatively coupled to eachmemory device 720. - The
memory devices 720 may be embodied as any type of memory device capable of storing data for thephysical resources 620 during operation of thesled 400, such as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4. Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces. - In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include next-generation nonvolatile devices, such as Intel 3D XPoint™ memory or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product. In some embodiments, the memory device may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance.
- Referring now to
FIG. 8 , in some embodiments, thesled 400 may be embodied as acompute sled 800. Thecompute sled 800 is optimized, or otherwise configured, to perform compute tasks. Of course, as discussed above, thecompute sled 800 may rely on other sleds, such as acceleration sleds and/or storage sleds, to perform such compute tasks. Thecompute sled 800 includes various physical resources (e.g., electrical components) similar to the physical resources of thesled 400, which have been identified inFIG. 8 using the same reference numbers. The description of such components provided above in regard toFIGS. 6 and 7 applies to the corresponding components of thecompute sled 800 and is not repeated herein for clarity of the description of thecompute sled 800. - In the
illustrative compute sled 800, thephysical resources 620 are embodied asprocessors 820. Although only twoprocessors 820 are shown inFIG. 8 , it should be appreciated that thecompute sled 800 may includeadditional processors 820 in other embodiments. Illustratively, theprocessors 820 are embodied as high-performance processors 820 and may be configured to operate at a relatively high power rating. Although theprocessors 820 generate additional heat operating at power ratings greater than typical processors (which operate at around 155-230 W), the enhanced thermal cooling characteristics of the chassis-lesscircuit board substrate 602 discussed above facilitate the higher power operation. For example, in the illustrative embodiment, theprocessors 820 are configured to operate at a power rating of at least 250 W. In some embodiments, theprocessors 820 may be configured to operate at a power rating of at least 350 W. - In some embodiments, the
compute sled 800 may also include a processor-to-processor interconnect 842. Similar to the resource-to-resource interconnect 624 of thesled 400 discussed above, the processor-to-processor interconnect 842 may be embodied as any type of communication interconnect capable of facilitating processor-to-processor interconnect 842 communications. In the illustrative embodiment, the processor-to-processor interconnect 842 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the processor-to-processor interconnect 842 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. - The
compute sled 800 also includes acommunication circuit 830. Theillustrative communication circuit 830 includes a network interface controller (NIC) 832, which may also be referred to as a host fabric interface (HFI). TheNIC 832 may be embodied as, or otherwise include, any type of integrated circuit, discrete circuits, controller chips, chipsets, add-in-boards, daughtercards, network interface cards, or other devices that may be used by thecompute sled 800 to connect with another compute device (e.g., with other sleds 400). In some embodiments, theNIC 832 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, theNIC 832 may include a local processor (not shown) and/or a local memory (not shown) that are both local to theNIC 832. In such embodiments, the local processor of theNIC 832 may be capable of performing one or more of the functions of theprocessors 820. Additionally or alternatively, in such embodiments, the local memory of theNIC 832 may be integrated into one or more components of the compute sled at the board level, socket level, chip level, and/or other levels. - The
communication circuit 830 is communicatively coupled to anoptical data connector 834. Theoptical data connector 834 is configured to mate with a corresponding optical data connector of therack 240 when thecompute sled 800 is mounted in therack 240. Illustratively, theoptical data connector 834 includes a plurality of optical fibers which lead from a mating surface of theoptical data connector 834 to anoptical transceiver 836. Theoptical transceiver 836 is configured to convert incoming optical signals from the rack-side optical data connector to electrical signals and to convert electrical signals to outgoing optical signals to the rack-side optical data connector. Although shown as forming part of theoptical data connector 834 in the illustrative embodiment, theoptical transceiver 836 may form a portion of thecommunication circuit 830 in other embodiments. - In some embodiments, the
compute sled 800 may also include anexpansion connector 840. In such embodiments, theexpansion connector 840 is configured to mate with a corresponding connector of an expansion chassis-less circuit board substrate to provide additional physical resources to thecompute sled 800. The additional physical resources may be used, for example, by theprocessors 820 during operation of thecompute sled 800. The expansion chassis-less circuit board substrate may be substantially similar to the chassis-lesscircuit board substrate 602 discussed above and may include various electrical components mounted thereto. The particular electrical components mounted to the expansion chassis-less circuit board substrate may depend on the intended functionality of the expansion chassis-less circuit board substrate. For example, the expansion chassis-less circuit board substrate may provide additional compute resources, memory resources, and/or storage resources. As such, the additional physical resources of the expansion chassis-less circuit board substrate may include, but is not limited to, processors, memory devices, storage devices, and/or accelerator circuits including, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits. - Referring now to
FIG. 9 , an illustrative embodiment of thecompute sled 800 is shown. As shown, theprocessors 820,communication circuit 830, andoptical data connector 834 are mounted to thetop side 650 of the chassis-lesscircuit board substrate 602. Any suitable attachment or mounting technology may be used to mount the physical resources of thecompute sled 800 to the chassis-lesscircuit board substrate 602. For example, the various physical resources may be mounted in corresponding sockets (e.g., a processor socket), holders, or brackets. In some cases, some of the electrical components may be directly mounted to the chassis-lesscircuit board substrate 602 via soldering or similar techniques. - As discussed above, the
individual processors 820 andcommunication circuit 830 are mounted to thetop side 650 of the chassis-lesscircuit board substrate 602 such that no two heat-producing, electrical components shadow each other. In the illustrative embodiment, theprocessors 820 andcommunication circuit 830 are mounted in corresponding locations on thetop side 650 of the chassis-lesscircuit board substrate 602 such that no two of those physical resources are linearly in-line with others along the direction of theairflow path 608. It should be appreciated that, although theoptical data connector 834 is in-line with thecommunication circuit 830, theoptical data connector 834 produces no or nominal heat during operation. - The
memory devices 720 of thecompute sled 800 are mounted to thebottom side 750 of the of the chassis-lesscircuit board substrate 602 as discussed above in regard to thesled 400. Although mounted to thebottom side 750, thememory devices 720 are communicatively coupled to theprocessors 820 located on thetop side 650 via the I/O subsystem 622. Because the chassis-lesscircuit board substrate 602 is embodied as a double-sided circuit board, thememory devices 720 and theprocessors 820 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-lesscircuit board substrate 602. Of course, eachprocessor 820 may be communicatively coupled to a different set of one ormore memory devices 720 in some embodiments. Alternatively, in other embodiments, eachprocessor 820 may be communicatively coupled to eachmemory device 720. In some embodiments, thememory devices 720 may be mounted to one or more memory mezzanines on the bottom side of the chassis-lesscircuit board substrate 602 and may interconnect with acorresponding processor 820 through a ball-grid array. - Each of the
processors 820 includes aheatsink 850 secured thereto. Due to the mounting of thememory devices 720 to thebottom side 750 of the chassis-less circuit board substrate 602 (as well as the vertical spacing of thesleds 400 in the corresponding rack 240), thetop side 650 of the chassis-lesscircuit board substrate 602 includes additional “free” area or space that facilitates the use ofheatsinks 850 having a larger size relative to traditional heatsinks used in typical servers. Additionally, due to the improved thermal cooling characteristics of the chassis-lesscircuit board substrate 602, none of theprocessor heatsinks 850 include cooling fans attached thereto. That is, each of theheatsinks 850 is embodied as a fan-less heatsink. In some embodiments, theheat sinks 850 mounted atop theprocessors 820 may overlap with the heat sink attached to thecommunication circuit 830 in the direction of theairflow path 608 due to their increased size, as illustratively suggested byFIG. 9 . - Referring now to
FIG. 10 , in some embodiments, thesled 400 may be embodied as anaccelerator sled 1000. Theaccelerator sled 1000 is configured, to perform specialized compute tasks, such as machine learning, encryption, hashing, or other computational-intensive task. In some embodiments, for example, acompute sled 800 may offload tasks to theaccelerator sled 1000 during operation. Theaccelerator sled 1000 includes various components similar to components of thesled 400 and/or computesled 800, which have been identified inFIG. 10 using the same reference numbers. The description of such components provided above in regard toFIGS. 6, 7, and 8 apply to the corresponding components of theaccelerator sled 1000 and is not repeated herein for clarity of the description of theaccelerator sled 1000. - In the
illustrative accelerator sled 1000, thephysical resources 620 are embodied asaccelerator circuits 1020. Although only twoaccelerator circuits 1020 are shown inFIG. 10 , it should be appreciated that theaccelerator sled 1000 may includeadditional accelerator circuits 1020 in other embodiments. For example, as shown inFIG. 11 , theaccelerator sled 1000 may include fouraccelerator circuits 1020 in some embodiments. Theaccelerator circuits 1020 may be embodied as any type of processor, co-processor, compute circuit, or other device capable of performing compute or processing operations. For example, theaccelerator circuits 1020 may be embodied as, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), neuromorphic processor units, quantum computers, machine learning circuits, or other specialized processors, controllers, devices, and/or circuits. - In some embodiments, the
accelerator sled 1000 may also include an accelerator-to-accelerator interconnect 1042. Similar to the resource-to-resource interconnect 624 of the sled 600 discussed above, the accelerator-to-accelerator interconnect 1042 may be embodied as any type of communication interconnect capable of facilitating accelerator-to-accelerator communications. In the illustrative embodiment, the accelerator-to-accelerator interconnect 1042 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the accelerator-to-accelerator interconnect 1042 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. In some embodiments, theaccelerator circuits 1020 may be daisy-chained with aprimary accelerator circuit 1020 connected to theNIC 832 andmemory 720 through the I/O subsystem 622 and asecondary accelerator circuit 1020 connected to theNIC 832 andmemory 720 through aprimary accelerator circuit 1020. - Referring now to
FIG. 11 , an illustrative embodiment of theaccelerator sled 1000 is shown. As discussed above, theaccelerator circuits 1020,communication circuit 830, andoptical data connector 834 are mounted to thetop side 650 of the chassis-lesscircuit board substrate 602. Again, theindividual accelerator circuits 1020 andcommunication circuit 830 are mounted to thetop side 650 of the chassis-lesscircuit board substrate 602 such that no two heat-producing, electrical components shadow each other as discussed above. Thememory devices 720 of theaccelerator sled 1000 are mounted to thebottom side 750 of the of the chassis-lesscircuit board substrate 602 as discussed above in regard to the sled 600. Although mounted to thebottom side 750, thememory devices 720 are communicatively coupled to theaccelerator circuits 1020 located on thetop side 650 via the I/O subsystem 622 (e.g., through vias). Further, each of theaccelerator circuits 1020 may include a heatsink 1070 that is larger than a traditional heatsink used in a server. As discussed above with reference to the heatsinks 870, the heatsinks 1070 may be larger than traditional heatsinks because of the “free” area provided by thememory resources 720 being located on thebottom side 750 of the chassis-lesscircuit board substrate 602 rather than on thetop side 650. - Referring now to
FIG. 12 , in some embodiments, thesled 400 may be embodied as astorage sled 1200. Thestorage sled 1200 is configured, to store data in adata storage 1250 local to thestorage sled 1200. For example, during operation, acompute sled 800 or anaccelerator sled 1000 may store and retrieve data from thedata storage 1250 of thestorage sled 1200. Thestorage sled 1200 includes various components similar to components of thesled 400 and/or thecompute sled 800, which have been identified inFIG. 12 using the same reference numbers. The description of such components provided above in regard toFIGS. 6, 7, and 8 apply to the corresponding components of thestorage sled 1200 and is not repeated herein for clarity of the description of thestorage sled 1200. - In the
illustrative storage sled 1200, thephysical resources 620 are embodied asstorage controllers 1220. Although only twostorage controllers 1220 are shown inFIG. 12 , it should be appreciated that thestorage sled 1200 may includeadditional storage controllers 1220 in other embodiments. Thestorage controllers 1220 may be embodied as any type of processor, controller, or control circuit capable of controlling the storage and retrieval of data into thedata storage 1250 based on requests received via thecommunication circuit 830. In the illustrative embodiment, thestorage controllers 1220 are embodied as relatively low-power processors or controllers. For example, in some embodiments, thestorage controllers 1220 may be configured to operate at a power rating of about 75 watts. - In some embodiments, the
storage sled 1200 may also include a controller-to-controller interconnect 1242. Similar to the resource-to-resource interconnect 624 of thesled 400 discussed above, the controller-to-controller interconnect 1242 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1242 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1242 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. - Referring now to
FIG. 13 , an illustrative embodiment of thestorage sled 1200 is shown. In the illustrative embodiment, thedata storage 1250 is embodied as, or otherwise includes, astorage cage 1252 configured to house one or more solid state drives (SSDs) 1254. To do so, thestorage cage 1252 includes a number of mountingslots 1256, each of which is configured to receive a correspondingsolid state drive 1254. Each of the mountingslots 1256 includes a number of drive guides 1258 that cooperate to define anaccess opening 1260 of thecorresponding mounting slot 1256. Thestorage cage 1252 is secured to the chassis-lesscircuit board substrate 602 such that the access openings face away from (i.e., toward the front of) the chassis-lesscircuit board substrate 602. As such, solid state drives 1254 are accessible while thestorage sled 1200 is mounted in a corresponding rack 204. For example, asolid state drive 1254 may be swapped out of a rack 240 (e.g., via a robot) while thestorage sled 1200 remains mounted in thecorresponding rack 240. - The
storage cage 1252 illustratively includes sixteen mountingslots 1256 and is capable of mounting and storing sixteen solid state drives 1254. Of course, thestorage cage 1252 may be configured to store additional or fewer solid state drives 1254 in other embodiments. Additionally, in the illustrative embodiment, the solid state drivers are mounted vertically in thestorage cage 1252, but may be mounted in thestorage cage 1252 in a different orientation in other embodiments. Eachsolid state drive 1254 may be embodied as any type of data storage device capable of storing long term data. To do so, the solid state drives 1254 may include volatile and non-volatile memory devices discussed above. - As shown in
FIG. 13 , thestorage controllers 1220, thecommunication circuit 830, and theoptical data connector 834 are illustratively mounted to thetop side 650 of the chassis-lesscircuit board substrate 602. Again, as discussed above, any suitable attachment or mounting technology may be used to mount the electrical components of thestorage sled 1200 to the chassis-lesscircuit board substrate 602 including, for example, sockets (e.g., a processor socket), holders, brackets, soldered connections, and/or other mounting or securing techniques. - As discussed above, the
individual storage controllers 1220 and thecommunication circuit 830 are mounted to thetop side 650 of the chassis-lesscircuit board substrate 602 such that no two heat-producing, electrical components shadow each other. For example, thestorage controllers 1220 and thecommunication circuit 830 are mounted in corresponding locations on thetop side 650 of the chassis-lesscircuit board substrate 602 such that no two of those electrical components are linearly in-line with each other along the direction of theairflow path 608. - The
memory devices 720 of thestorage sled 1200 are mounted to thebottom side 750 of the of the chassis-lesscircuit board substrate 602 as discussed above in regard to thesled 400. Although mounted to thebottom side 750, thememory devices 720 are communicatively coupled to thestorage controllers 1220 located on thetop side 650 via the I/O subsystem 622. Again, because the chassis-lesscircuit board substrate 602 is embodied as a double-sided circuit board, thememory devices 720 and thestorage controllers 1220 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-lesscircuit board substrate 602. Each of thestorage controllers 1220 includes a heatsink 1270 secured thereto. As discussed above, due to the improved thermal cooling characteristics of the chassis-lesscircuit board substrate 602 of thestorage sled 1200, none of the heatsinks 1270 include cooling fans attached thereto. That is, each of the heatsinks 1270 is embodied as a fan-less heatsink. - Referring now to
FIG. 14 , in some embodiments, thesled 400 may be embodied as amemory sled 1400. Thestorage sled 1400 is optimized, or otherwise configured, to provide other sleds 400 (e.g., compute sleds 800, accelerator sleds 1000, etc.) with access to a pool of memory (e.g., in two ormore sets memory sled 1200. For example, during operation, acompute sled 800 or anaccelerator sled 1000 may remotely write to and/or read from one or more of the memory sets 1430, 1432 of thememory sled 1200 using a logical address space that maps to physical addresses in the memory sets 1430, 1432. Thememory sled 1400 includes various components similar to components of thesled 400 and/or thecompute sled 800, which have been identified inFIG. 14 using the same reference numbers. The description of such components provided above in regard toFIGS. 6, 7, and 8 apply to the corresponding components of thememory sled 1400 and is not repeated herein for clarity of the description of thememory sled 1400. - In the
illustrative memory sled 1400, thephysical resources 620 are embodied asmemory controllers 1420. Although only twomemory controllers 1420 are shown inFIG. 14 , it should be appreciated that thememory sled 1400 may includeadditional memory controllers 1420 in other embodiments. Thememory controllers 1420 may be embodied as any type of processor, controller, or control circuit capable of controlling the writing and reading of data into the memory sets 1430, 1432 based on requests received via thecommunication circuit 830. In the illustrative embodiment, eachmemory controller 1420 is connected to acorresponding memory set memory devices 720 within the correspondingmemory set sled 400 that has sent a request to thememory sled 1400 to perform a memory access operation (e.g., read or write). - In some embodiments, the
memory sled 1400 may also include a controller-to-controller interconnect 1442. Similar to the resource-to-resource interconnect 624 of thesled 400 discussed above, the controller-to-controller interconnect 1442 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1442 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1442 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. As such, in some embodiments, amemory controller 1420 may access, through the controller-to-controller interconnect 1442, memory that is within the memory set 1432 associated with anothermemory controller 1420. In some embodiments, a scalable memory controller is made of multiple smaller memory controllers, referred to herein as “chiplets”, on a memory sled (e.g., the memory sled 1400). The chiplets may be interconnected (e.g., using EMIB (Embedded Multi-Die Interconnect Bridge)). The combined chiplet memory controller may scale up to a relatively large number of memory controllers and I/O ports, (e.g., up to 16 memory channels). In some embodiments, thememory controllers 1420 may implement a memory interleave (e.g., one memory address is mapped to thememory set 1430, the next memory address is mapped to thememory set 1432, and the third address is mapped to thememory set 1430, etc.). The interleaving may be managed within thememory controllers 1420, or from CPU sockets (e.g., of the compute sled 800) across network links to the memory sets 1430, 1432, and may improve the latency associated with performing memory access operations as compared to accessing contiguous memory addresses from the same memory device. - Further, in some embodiments, the
memory sled 1400 may be connected to one or more other sleds 400 (e.g., in thesame rack 240 or an adjacent rack 240) through a waveguide, using thewaveguide connector 1480. In the illustrative embodiment, the waveguides are 64 millimeter waveguides that provide 16 Rx (i.e., receive) lanes and 16 Tx (i.e., transmit) lanes. Each lane, in the illustrative embodiment, is either 16 GHz or 32 GHz. In other embodiments, the frequencies may be different. Using a waveguide may provide high throughput access to the memory pool (e.g., the memory sets 1430, 1432) to another sled (e.g., asled 400 in thesame rack 240 or anadjacent rack 240 as the memory sled 1400) without adding to the load on theoptical data connector 834. - Referring now to
FIG. 15 , a system for executing one or more workloads (e.g., applications) may be implemented in accordance with thedata center 100. In the illustrative embodiment, thesystem 1510 includes anorchestrator server 1520, which may be embodied as a managed node comprising a compute device (e.g., aprocessor 820 on a compute sled 800) executing management software (e.g., a cloud operating environment, such as OpenStack) that is communicatively coupled tomultiple sleds 400 including a large number of compute sleds 1530 (e.g., each similar to the compute sled 800), memory sleds 1540 (e.g., each similar to the memory sled 1400), accelerator sleds 1550 (e.g., each similar to the memory sled 1000), and storage sleds 1560 (e.g., each similar to the storage sled 1200). One or more of thesleds node 1570, such as by theorchestrator server 1520, to collectively perform a workload (e.g., anapplication 1532 executed in a virtual machine or in a container). The managednode 1570 may be embodied as an assembly ofphysical resources 620, such asprocessors 820,memory resources 720,accelerator circuits 1020, ordata storage 1250, from the same ordifferent sleds 400. Further, the managed node may be established, defined, or “spun up” by theorchestrator server 1520 at the time a workload is to be assigned to the managed node or at any other time, and may exist regardless of whether any workloads are presently assigned to the managed node. In the illustrative embodiment, theorchestrator server 1520 may selectively allocate and/or deallocatephysical resources 620 from thesleds 400 and/or add or remove one ormore sleds 400 from the managednode 1570 as a function of quality of service (QoS) targets (e.g., performance targets associated with a throughput, latency, instructions per second, etc.) associated with a service level agreement for the workload (e.g., the application 1532). In doing so, theorchestrator server 1520 may receive telemetry data indicative of performance conditions (e.g., throughput, latency, instructions per second, etc.) in eachsled 400 of the managednode 1570 and compare the telemetry data to the quality of service targets to determine whether the quality of service targets are being satisfied. Theorchestrator server 1520 may additionally determine whether one or more physical resources may be deallocated from the managednode 1570 while still satisfying the QoS targets, thereby freeing up those physical resources for use in another managed node (e.g., to execute a different workload). Alternatively, if the QoS targets are not presently satisfied, theorchestrator server 1520 may determine to dynamically allocate additional physical resources to assist in the execution of the workload (e.g., the application 1532) while the workload is executing. Similarly, theorchestrator server 1520 may determine to dynamically deallocate physical resources from a managed node if theorchestrator server 1520 determines that deallocating the physical resource would result in QoS targets still being met. - Additionally, in some embodiments, the
orchestrator server 1520 may identify trends in the resource utilization of the workload (e.g., the application 1532), such as by identifying phases of execution (e.g., time periods in which different operations, each having different resource utilizations characteristics, are performed) of the workload (e.g., the application 1532) and pre-emptively identifying available resources in thedata center 100 and allocating them to the managed node 1570 (e.g., within a predefined time period of the associated phase beginning). In some embodiments, theorchestrator server 1520 may model performance based on various latencies and a distribution scheme to place workloads among compute sleds and other resources (e.g., accelerator sleds, memory sleds, storage sleds) in thedata center 100. For example, theorchestrator server 1520 may utilize a model that accounts for the performance of resources on the sleds 400 (e.g., FPGA performance, memory access latency, etc.) and the performance (e.g., congestion, latency, bandwidth) of the path through the network to the resource (e.g., FPGA). As such, theorchestrator server 1520 may determine which resource(s) should be used with which workloads based on the total latency associated with each potential resource available in the data center 100 (e.g., the latency associated with the performance of the resource itself in addition to the latency associated with the path through the network between the compute sled executing the workload and thesled 400 on which the resource is located). - In some embodiments, the
orchestrator server 1520 may generate a map of heat generation in thedata center 100 using telemetry data (e.g., temperatures, fan speeds, etc.) reported from thesleds 400 and allocate resources to managed nodes as a function of the map of heat generation and predicted heat generation associated with different workloads, to maintain a target temperature and heat distribution in thedata center 100. Additionally or alternatively, in some embodiments, theorchestrator server 1520 may organize received telemetry data into a hierarchical model that is indicative of a relationship between the managed nodes (e.g., a spatial relationship such as the physical locations of the resources of the managed nodes within thedata center 100 and/or a functional relationship, such as groupings of the managed nodes by the customers the managed nodes provide services for, the types of functions typically performed by the managed nodes, managed nodes that typically share or exchange workloads among each other, etc.). Based on differences in the physical locations and resources in the managed nodes, a given workload may exhibit different resource utilizations (e.g., cause a different internal temperature, use a different percentage of processor or memory capacity) across the resources of different managed nodes. Theorchestrator server 1520 may determine the differences based on the telemetry data stored in the hierarchical model and factor the differences into a prediction of future resource utilization of a workload if the workload is reassigned from one managed node to another managed node, to accurately balance resource utilization in thedata center 100. - To reduce the computational load on the
orchestrator server 1520 and the data transfer load on the network, in some embodiments, theorchestrator server 1520 may send self-test information to thesleds 400 to enable eachsled 400 to locally (e.g., on the sled 400) determine whether telemetry data generated by thesled 400 satisfies one or more conditions (e.g., an available capacity that satisfies a predefined threshold, a temperature that satisfies a predefined threshold, etc.). Eachsled 400 may then report back a simplified result (e.g., yes or no) to theorchestrator server 1520, which theorchestrator server 1520 may utilize in determining the allocation of resources to managed nodes. - Referring now to
FIG. 16 , asystem 1610 for providing distributed storage with physically separated control plane management and data plane management in a disaggregated architecture includes anorchestrator server 1620 similar to theorchestrator server 1520, in communication withmultiple sleds 1616, including acompute sled 1630 that executes an application 1650 (e.g., a workload), similar to theapplication 1532, on behalf of aclient device 1614. Thesystem 1610 additionally includesmultiple compute sleds data storage sleds compute sled control plane manager 1660, which may be embodied as any circuitry or logic (e.g., a co-processor, an ASIC, software, etc.) capable of performing control plane management operations, such as placement grouping, logical storage pooling, and failure domain mapping functions, to determine whichdata storage sleds control plane manager 1660 may produce a hash of the data set and compare the hash to a database that relates hashes to partitions (e.g., compute sleds and their corresponding data storage sleds) of the distributed storage system. Further, in performing the control plane management operations, the control plane manager (e.g., the control plane manager 1660), in the illustrative embodiment, causes an object to be stored acrossmultiple failure domains 1690, 1692, 1694 (e.g., to guard against inaccessibility of the object if a power failure occurs in a failure domains). Eachfailure domain - In the illustrative embodiment, data plane management operations (e.g., block allocation, fragmentation management, wear leveling, etc.), which are typically performed by the same compute device that performs the control plane management operations, are decoupled from the compute sleds 1632, 1634, 1636 and, instead, are performed by
data plane managers data storage devices data storage 1250 ofFIG. 12 ). As such, the control plane management operations, which may be compute intensive, are confined to the compute sleds 1632, 1634, 1636, which are relatively better equipped to perform compute-intensive tasks, while the data plane management operations, which pertain to management of the physical storage media, are kept local to the correspondingdata storage sleds data storage devices - The
orchestrator server 1620, thesleds 1616, and theclient device 1614 are illustratively in communication via anetwork 1612, which may be embodied as any type of wired or wireless communication network, including global networks (e.g., the Internet), local area networks (LANs) or wide area networks (WANs), cellular networks (e.g., Global System for Mobile Communications (GSM), 3G, Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMAX), etc.), digital subscriber line (DSL) networks, cable networks (e.g., coaxial networks, fiber networks, etc.), or any combination thereof. - Referring now to
FIG. 17 , thecompute sled 1632, in operation, may execute amethod 1700 for executing control plane operations in response to a data access request (e.g., to store an object or to read an object from distributed storage). Themethod 1700 begins withblock 1702, in which thecompute sled 1632 receives a data access request. In the illustrative embodiment, thecompute sled 1632 receives the data access request (e.g., a PUT request or a GET request from a representational state transfer (REST) application programming interface (API)), from theapplication 1650 executed by thecompute sled 1630, as indicated inblock 1704. As indicated inblock 1706, thecompute sled 1632 may obtain a write request (e.g., a PUT request, as stated above). In receiving a write request, thecompute sled 1632 may receive, from the requesting compute device (e.g., the compute sled 1630) a data payload (e.g., a data set) indicative of the object to be stored, as indicated inblock 1708. Alternatively, thecompute sled 1632 may receive a read request (e.g., a GET request, as stated above), as indicated inblock 1710. The data access request may include an object identifier, which may be any sequence of characters, numbers, or other symbols that identify the object to be stored or read, as indicated inblock 1712. Subsequently, inblock 1714, thecompute sled 1632 determines the subsequent course of action as a function of whether the data access request is a write request. - If the
compute sled 1632 determines that the data access request is a write request, themethod 1700 advances to block 1716, in which thecompute sled 1632 verifies that the data payload represents an unstored object (e.g., an object that is not already stored in the distributed storage system). In doing so, thecompute sled 1632 may produce an object identifier from a uniform resource locator (URL) of the object (e.g., by performing a hashing function on the URL), as indicated inblock 1718. If the write request received inblock 1702 included an object identifier, thecompute sled 1632 may skip the production of an object identifier inblock 1716. Inblock 1720, thecompute sled 1632 determines whether the object identifier corresponds to a stored object. In doing so, thecompute sled 1632, in the illustrative embodiment, compares the object identifier to a database (e.g., in the memory 720) of object identifiers for objects stored in itsdata storage sled 1640, as indicated inblock 1722. Inblock 1724, thecompute sled 1632 determines the subsequent course of action as a function of whether the payload represents an unstored object (e.g., whether the payload identifier matches an object identifier of an object that is already stored in one or more of thedata storage sleds method 1700 advances to block 1726, in which thecompute sled 1632 sends a response message (e.g., to the compute sled 1630) that the object is already stored. In doing so, thecompute sled 1632 may add the object identifier to the response message, as indicated inblock 1728. Subsequently, themethod 1700 loops back to block 1702 in which thecompute sled 1632 awaits another data access request. Otherwise, if the object is not already stored, themethod 1700 advances to block 1730 ofFIG. 18 , in which thecompute sled 1632 maps the object to a set of data storage sleds (e.g., thedata storage sleds compute sled 1632 may skip the verification of whether the object identifier matches an already-stored object and proceed on the basis that any such object will be overwritten by the new object having the same object identifier. - Referring now to
FIG. 18 , in mapping the object to a set of data storage sleds, thecompute sled 1632 may map the object as a function of the object identifier, as indicated inblock 1732. For example, in cases in which the object identifier is a hash associated with the object (e.g., a hash of the URL of the object), thecompute sled 1632 may map the object to a set of data storage sleds as a function of the hash (e.g., using a table that associates hashes, or portions of hashes, with data storage sleds), as indicated inblock 1734. As indicated inblock 1736, thecompute sled 1632, in the illustrative embodiment, maps the object to data storage sleds in different failure domains (e.g., thedata storage sleds failure domains 1690, 1692, 1694). As indicated inblock 1738, thecompute sled 1632 maps the object to a set of data storage sleds that are to store corresponding replicas (e.g., copies) or erasure coded sections of the object. Additionally, as indicated inblock 1740, thecompute sled 1632 may associate, in a database, the object identifier with the data storage sleds that the object has been mapped to (e.g., by identifying the counterpart compute sleds 1634, 1636 that will own the object and identifying the correspondingdata storage sleds - In
block 1742, thecompute sled 1632 may send metadata associated with the object to other compute sleds with control plane managers (e.g., the compute sleds 1634, 1636 withcontrol plane managers 1662, 1664) associated with the mapped data storage sleds (e.g., thedata storage sleds 1642, 1644). In doing so, thecompute sled 1632 may send the object identifier to the compute sleds 1634, 1636, as indicated in block 1744. Further, thecompute sled 1632 may send metadata indicative of one or more attributes of the object (e.g., a data type of the object, such as an image, a video, or other data type, the size of the object, and/or other attributes), as indicated inblock 1748. - In
block 1750, thecompute sled 1632, in the illustrative embodiment, sends a write request to the mappeddata storage sleds block 1752, in sending the write request, thecompute sled 1632 sends the object (e.g., the data payload) and the object identifier to the mappeddata storage sleds compute sled 1632 tunnels the write request through a non-volatile memory express over fabric (NVMeOF) connection, as indicated inblock 1754. For example, thecompute sled 1632 may send the write request to one or more block devices that are exposed by an NVMeOF driver of thecompute sled 1632 and that are associated with (e.g., represent) the mappeddata storage sleds block 1756. As such, thecompute sled 1632, in the illustrative embodiment, operates as an NVMeOF initiator and eachdata storage sled compute sled 1632 may send the write request to one or more data storage sleds located in a different rack, pod, or data center than thecompute sled 1632, as indicated inblock 1758. - Referring back to block 1714 of
FIG. 17 , if thecompute sled 1632 instead determines that the data access request is not a write request (e.g., the data access request is a read request), themethod 1700 advances to block 1760 ofFIG. 19 , in which thecompute sled 1632 determines a set of data storage sleds that are mapped to the object identifier included in the data access request. In doing so, thecompute sled 1632 may compare the object identifier to a database of object identifiers for objects stored in one or more of thedata storage sleds block 1722 ofFIG. 17 ), as indicated inblock 1762. Subsequently, themethod 1700 advances to block 1764 in which thecompute sled 1632 sends a read request to one or more of the mappeddata storage sleds compute sled 1632 sends the object identifier to one or more of the mappeddata storage sleds block 1766. In the illustrative embodiment, in sending the read request, thecompute sled 1632 tunnels the read request through NVMeOF to one or more of the mappeddata storage sleds block 1768. For example, and as indicated inblock 1770, thecompute sled 1632 may send the read request to one or more block devices exposed by an NVMEOF driver of thecompute sled 1632 and that are associated with the mappeddata storage sleds block 1772, thecompute sled 1632 may send the read request to one or more data storage sleds located in a different rack, pod, or data center than thecompute sled 1632. Subsequently, inblock 1774, thecompute sled 1632 receives the read object from one or more of thedata storage sleds compute sled 1632 receives the object through an NVMEoF connection between the data storage sled (e.g., the data storage sled 1640) and thecompute sled 1632, as indicated inblock 1776. In some embodiments, thecompute sled 1632 may receive erasure coded sections of the object from thedata storage sleds block 1778. Subsequently, themethod 1700 advances to block 1780, in which thecompute sled 1632 sends the object to the requesting compute device. For example, and as indicated inblock 1782, thecompute sled 1632 sends the object to thecompute sled 1630 executing theapplication 1650. - Referring now to
FIG. 20 , a data storage sled (e.g., the data storage sled 1640) may execute amethod 2000 for executing data plane management operations in response to a data access request. Themethod 2000 begins withblock 2002, in which thedata storage sled 1640 determines whether a data access request (e.g., a write request or a read request from a compute sled, such as the compute sled 1632) has been received. If so, themethod 2000 advances to block 2004, in which thedata storage sled 1640 determines the subsequent course of action as a function of whether the data access request is a write request or not. In response to a determination that the data access request is a write request, themethod 2000 advances to block 2006, in which thedata storage sled 1632 determines one or more blocks of thedata storage devices 1680 to write the object to. Each block may be embodied as any fixed amount of data storage capacity (e.g., a gigabyte, a megabyte, a kilobyte, one byte, etc.). In doing so, thedata storage sled 1640 may determine the one or more blocks as a function of the object identifier (e.g., by using a portion of the object identifier as a logical block address), as indicated inblock 2008. Additionally or alternatively, thedata storage sled 1640 may determine the one or more blocks as a function of a fragmentation management scheme (e.g., to prioritize allocating physically contiguous blocks), as indicated inblock 2010. As indicated in block 2012, thedata storage sled 1260 may determine the blocks as a function of a wear leveling scheme (e.g., to prioritize evenly distributing writes among thedata storage devices 1682 rather than repeatedly writing to the same data storage devices 1682). Further, as indicated inblock 2014, thedata storage sled 1640 may determine the blocks to write the object to as a function of a target access latency to be obtained. For example, thedata storage sled 1640 may determine to write the different portions of the object across multipledata storage devices 1682, rather than writing the object to the blocks of a singledata storage device 1682, to lower the amount of time needed to read back the object in response to a subsequent read request. As indicated inblock 2016, thedata storage sled 1640 may write an identifier of each determined block to a block ownership database (e.g., in the memory 720) in association with the object identifier. Inblock 2018, thedata storage sled 1640 writes the object (e.g., a replica of the object or erasure coded sections of the object) to the determined block(s) of the corresponding data storage device(s) 1682. Afterwards, themethod 2000 loops back to block 2002, in which thedata storage sled 1640 awaits another data access request. Referring back toblock 2004, if thedata storage sled 1640 instead determines that the data access request is not a write request (e.g., the data access request is a read request), themethod 2000 advances to block 2020 ofFIG. 21 , in which thedata storage sled 1640 determines one or more blocks of the data storage device(s) 1682 to read the object from. - Referring now to block 2022 of
FIG. 21 , in determining the one or more blocks to read the object from, thedata storage sled 1640 may read an identifier for each block from a block ownership database that associates object identifiers with block identifiers (e.g., block addresses). For example, thedata storage sled 1640 may read from the block ownership database described above with reference to block 2016 ofFIG. 20 . Subsequently, inblock 2024, thedata storage sled 1640 reads the object from the determined one or more blocks of the data storage device(s) 1682 and, inblock 2026, sends the object to the requesting compute sled (e.g., the compute sled 1632). - Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.
- Example 1 includes a compute sled comprising a network interface controller; and circuitry to receive, through a network and with the network interface controller, a data access request from a compute device, wherein the data access request includes a data payload indicative of an object to be stored; map the object to a set of multiple data storage sleds for distributed storage of the object; and send, through the network and with a local data bus protocol mapped onto a network protocol, a write request to the mapped data storage sleds to store the object in one or more data storage devices located on each data storage sled.
- Example 2 includes the subject matter of Example 1, and wherein to send, through the network and with a local data bus protocol mapped onto a network protocol, a write request comprises to tunnel the write request through a non-volatile memory express over fabric (NVMeOF) connection to the data storage sleds.
- Example 3 includes the subject matter of any of Examples 1 and 2, and wherein to map the object to the data storage sleds comprises to map the object to data storage sleds in different failure domains.
- Example 4 includes the subject matter of any of Examples 1-3, and wherein the circuitry is further to send, through the network and to one or more other compute sleds, metadata associated with the object.
- Example 5 includes the subject matter of any of Examples 1-4, and wherein to send, through the network and to one or more other compute sleds, metadata associated with the object comprises to send the metadata to one or more compute sleds associated with the mapped data storage sleds.
- Example 6 includes the subject matter of any of Examples 1-5, and wherein to send the metadata comprises to send one or more of an object identifier associated with the object or metadata indicative of one or more attributes of the object.
- Example 7 includes the subject matter of any of Examples 1-6, and wherein to map the object to the data storage sleds comprises to map the object as a function of a hash of a uniform resource locator associated with the object.
- Example 8 includes the subject matter of any of Examples 1-7, and wherein the circuitry is further to verify, prior to sending the write request to the mapped data storage sled, that the data payload represents an object that is not already stored on one or more of the data storage sleds.
- Example 9 includes the subject matter of any of Examples 1-8, and wherein to verify that the data payload represents and object that is not already stored on one or more of the data storage sleds comprises to compare an object identifier associated with the object to object identifiers for objects stored in a data storage sled associated with the compute sled.
- Example 10 includes the subject matter of any of Examples 1-9, and wherein the circuitry is further to receive a request a read a second object, wherein the request includes an identifier of the second object; and determine, in response to the read request, one or more storage sleds mapped to the identifier of the second object; send, through the network and with the local data bus protocol mapped onto the network protocol, a read request to the mapped one or more data storage sleds; and receive the read object from the mapped one or more data storage sleds.
- Example 11 includes the subject matter of any of Examples 1-10, and wherein to send, through the network and with the local data bus protocol mapped onto the network protocol, a read request comprises to tunnel the read request through a non-volatile memory express over fabric (NVMeOF) connection to the one or more data storage sleds.
- Example 12 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a compute sled to receive, through a network and with a network interface controller, a data access request from a compute device, wherein the data access request includes a data payload indicative of an object to be stored; map the object to a set of multiple data storage sleds for distributed storage of the object; and send, through the network and with a local data bus protocol mapped onto a network protocol, a write request to the mapped data storage sleds to store the object in one or more data storage devices located on each data storage sled.
- Example 13 includes the subject matter of Example 12, and wherein to send, through the network and with a local data bus protocol mapped onto a network protocol, a write request comprises to tunnel the write request through a non-volatile memory express over fabric (NVMeOF) connection to the data storage sleds.
- Example 14 includes the subject matter of any of Examples 12 and 13, and wherein to map the object to the data storage sleds comprises to map the object to data storage sleds in different failure domains.
- Example 15 includes the subject matter of any of Examples 12-14, and wherein, when executed, the plurality of instructions further cause the compute sled to send, through the network and to one or more other compute sleds, metadata associated with the object.
- Example 16 includes the subject matter of any of Examples 12-15, and wherein to send, through the network and to one or more other compute sleds, metadata associated with the object comprises to send the metadata to one or more compute sleds associated with the mapped data storage sleds.
- Example 17 includes the subject matter of any of Examples 12-16, and wherein to send the metadata comprises to send one or more of an object identifier associated with the object or metadata indicative of one or more attributes of the object.
- Example 18 includes the subject matter of any of Examples 12-17, and wherein to map the object to the data storage sleds comprises to map the object as a function of a hash of a uniform resource locator associated with the object.
- Example 19 includes a method comprising receiving, by a compute sled with a network interface controller, a data access request from a compute device, wherein the data access request includes a data payload indicative of an object to be stored; mapping, by the compute sled, the object to a set of multiple data storage sleds for distributed storage of the object; and sending, by the compute sled, through a network and with a local data bus protocol mapped onto a network protocol, a write request to the mapped data storage sleds to store the object in one or more data storage devices located on each data storage sled.
- Example 20 includes the subject matter of Example 19, and wherein sending, through the network and with a local data bus protocol mapped onto a network protocol, a write request comprises tunneling the write request through a non-volatile memory express over fabric (NVMeOF) connection to the data storage sleds.
- Example 21 includes the subject matter of any of Examples 19 and 20, and wherein mapping the object to the data storage sleds comprises mapping the object to data storage sleds in different failure domains.
- Example 22 includes the subject matter of any of Examples 19-21, and further including sending, by the compute sled, through the network and to one or more other compute sleds, metadata associated with the object.
- Example 23 includes a data storage sled comprising a network interface controller; a set of data storage devices; and circuitry to receive, through the network interface controller and with a local data bus protocol mapped onto a network protocol, a write request from a compute sled of a distributed data storage system, wherein the write request includes an object to be written to one or more of the data storage devices; determine one or more blocks of the set of data storage devices to write the object to; write an identifier of each determined block to a block ownership database in association with an identifier of the object; and write the object to the determined one or more blocks.
- Example 24 includes the subject matter of Example 23, and wherein the data storage devices have different performance characteristics resulting from different physical storage media in each data storage device and wherein to determine the one or more blocks of the set of data storage devices to write the object to comprises to determine the one or more blocks as a function of a target access latency.
- Example 25 includes the subject matter of any of Examples 23 and 24, and wherein to determine the one or more blocks of the set of data storage devices to write the object to comprises to determine the one or more blocks as a function of a data storage device wear leveling scheme.
- Example 26 includes the subject matter of any of Examples 23-25, and wherein the circuitry is further to receive, through the network interface controller, a read request from the compute sled, wherein the read request includes the identifier of the object; determine, from the block ownership database, the one or more blocks of the set of data storage devices to read the object from; read the object from the determined one or more blocks of the set of data storage devices; and send the object to the compute sled.
- Example 27 includes a method comprising receiving, through a network interface controller of a data storage sled and with a local data bus protocol mapped onto a network protocol, a write request from a compute sled of a distributed data storage system, wherein the write request includes an object to be written to one or more data storage devices of the data storage sled; determining, by the data storage sled, one or more blocks of the data storage devices to write the object to; writing, by the data storage sled, an identifier of each determined block to a block ownership database in association with an identifier of the object; and writing, by the data storage sled, the object to the determined one or more blocks.
- Example 28 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a data storage sled to receive, through a network interface controller of the data storage sled and with a local data bus protocol mapped onto a network protocol, a write request from a compute sled of a distributed data storage system, wherein the write request includes an object to be written to one or more data storage devices of the data storage sled; determine, by the data storage sled, one or more blocks of the data storage devices to write the object to; write, by the data storage sled, an identifier of each determined block to a block ownership database in association with an identifier of the object; and write, by the data storage sled, the object to the determined one or more blocks.
Claims (28)
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