US20180358398A1 - Chip package and manufacturing method thereof - Google Patents
Chip package and manufacturing method thereof Download PDFInfo
- Publication number
- US20180358398A1 US20180358398A1 US15/996,841 US201815996841A US2018358398A1 US 20180358398 A1 US20180358398 A1 US 20180358398A1 US 201815996841 A US201815996841 A US 201815996841A US 2018358398 A1 US2018358398 A1 US 2018358398A1
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- Prior art keywords
- layer
- chip
- hole
- chip package
- wafer
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- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 238000002161 passivation Methods 0.000 claims abstract description 85
- 238000005538 encapsulation Methods 0.000 claims abstract description 75
- 238000002955 isolation Methods 0.000 claims abstract description 41
- 238000000465 moulding Methods 0.000 claims description 52
- 150000001875 compounds Chemical class 0.000 claims description 50
- 238000005520 cutting process Methods 0.000 claims description 8
- 238000000227 grinding Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 8
- 238000005553 drilling Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000005755 formation reaction Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 3
- 239000003921 oil Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000035807 sensation Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Definitions
- the present invention relates to a chip package and a manufacturing method of the chip package.
- a chip package can protect the chip therein to prevent the chip from environmental pollution, and it also provides electrical connection paths between inner electronic elements of the chip and external devices.
- moisture or oil stains easily remain on the electronic product, thereby causing the chip package in the electronic product to be polluted.
- a sensor is easily physically damaged, thereby reducing the lifespan of the electronic product.
- the capacitance of a typical electronic product is easily attenuated, thereby affecting the sensing capability of the typical electronic product, such as the capability of sensing fingerprints.
- An aspect of the present invention is to provide a chip package.
- a chip package includes a chip, a first isolation layer, a redistribution layer, a passivation layer, and an encapsulation layer.
- the chip has a sensor, a conductive pad, a through hole, a top surface, and a bottom surface that is opposite the top surface.
- the sensor and the conductive pad are located on the top surface, and the conductive pad is in the through hole.
- the first isolation layer is located on the bottom surface of the chip and a sidewall that surrounds the through hole.
- the redistribution layer is located on the first isolation layer and is in electrical contact with the conductive pad that is in the through hole.
- the passivation layer is located on the first isolation layer and the redistribution layer.
- the passivation layer on the bottom surface of the chip has an opening, and a portion of the redistribution layer is in the opening.
- the encapsulation layer is located on the top surface of the chip and covers the sensor and the conductive pad.
- the encapsulation layer has a flat surface facing away from the chip.
- An aspect of the present invention is to provide a manufacturing method of a chip package.
- a manufacturing method of a chip package includes forming a temporary bonding layer on a carrier, forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer, bonding the carrier to the wafer, in which the encapsulation layer and the temporary bonding layer are located between the wafer and the carrier, and the encapsulation layer covers a sensor and a conductive pad of the wafer, patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole, forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole, forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole, forming a passivation layer on the isolation layer and the redistribution layer, in which the passivation layer has an opening, and a portion of the redistribution layer is in the opening, and removing the temporary bonding layer and the carrier.
- An aspect of the present invention is to provide a chip package.
- a chip package includes a chip, a molding compound, a redistribution layer, a passivation layer, and an encapsulation layer.
- the chip has a sensor, a conductive pad, a top surface, a bottom surface that is opposite the top surface, and a lateral surface that adjoins the top surface and the bottom surface.
- the sensor and the conductive pad are located on the top surface, and the conductive pad protrudes from the lateral surface.
- the molding compound covers the bottom surface and the lateral surface of the chip, and has a through hole.
- the conductive pad is in the through hole.
- the redistribution layer is located on the molding compound and is in electrical contact with the conductive pad that is in the through hole.
- the passivation layer is located on the molding compound and the redistribution layer.
- the passivation layer on the bottom surface of the chip has an opening, and a portion of the redistribution layer is in the opening.
- the encapsulation layer is located on the top surface of the chip and covers the sensor and the conductive pad.
- the encapsulation layer has a flat surface facing away from the chip.
- An aspect of the present invention is to provide a manufacturing method of a chip package.
- a manufacturing method of a chip package includes forming a temporary bonding layer on a carrier, forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer, bonding the carrier to the wafer, in which the encapsulation layer and the temporary bonding layer are located between the wafer and the carrier, and the encapsulation layer covers a sensor and a conductive pad of the wafer, patterning a bottom surface of the wafer to form a dicing trench, in which the conductive pad is exposed through the dicing trench, molding a molding compound to cover the bottom surface of the wafer and the dicing trench, forming a through hole in the molding compound by laser drilling, in which the conductive pad is in the through hole, forming a redistribution layer on the molding compound and the conductive pad that is in the through hole, forming a passivation layer on the molding compound and the redistribution layer, in which the passivation layer has an opening, and a portion of
- the encapsulation layer is located on the top surface of the chip and covers the sensor and the conductive pad, thereby preventing the sensor and the conductive pad from being polluted by moisture, oil stain, or dust.
- the encapsulation layer has the flat surface facing away from the chip, and thus the top of the chip package is configured with full planarization. Such a design is a convenient factor for assembly, and can improve a tactile sensation for users.
- the encapsulation layer having a suitable thickness and a suitable dielectric constant can prevent capacitance attenuation, thereby improving the detect sensitivity of the chip package for fingerprints.
- FIG. 1A is a top view of a chip package according to one embodiment of the present invention.
- FIG. 1B is a cross-sectional view of the chip package taken along line 1 B- 1 B shown in FIG. 1A ;
- FIG. 2 is a cross-sectional view of a chip package according to one embodiment of the present invention.
- FIGS. 3 to 8 are cross-sectional views of a manufacturing method of a chip package according to one embodiment of the present invention.
- FIG. 9 is a cross-sectional view of a chip package according to one embodiment of the present invention.
- FIG. 10A is a cross-sectional view of a chip package according to one embodiment of the present invention.
- FIG. 10B is a cross-sectional view of a chip package according to one embodiment of the present invention.
- FIGS. 11 to 15B are cross-sectional views of a manufacturing method of a chip package according to some embodiments of the present invention.
- FIG. 16 is a cross-sectional view of a chip package according to one embodiment of the present invention.
- FIG. 17A is a cross-sectional view of a chip package according to one embodiment of the present invention.
- FIG. 17B is a cross-sectional view of a chip package according to one embodiment of the present invention.
- FIGS. 18 to 22 are cross-sectional views of a manufacturing method of a chip package according to some embodiments of the present invention.
- FIG. 1A is a top view of a chip package 100 according to one embodiment of the present invention.
- FIG. 1B is a cross-sectional view of the chip package 100 taken along line 1 B- 1 B shown in FIG. 1A .
- the chip package 100 includes a chip 110 , an isolation layer 120 , a redistribution layer 130 , a passivation layer 140 , and an encapsulation layer 150 .
- the chip 110 has a sensor 112 , a conductive pad 114 , a through hole 116 , a top surface 111 , and a bottom surface 113 that is opposite the top surface 111 .
- the sensor 112 and the conductive pad 114 are located on the top surface 111 of the chip 110 , and the conductive pad 114 is in the through hole 116 .
- the isolation layer 120 is located on the bottom surface 113 of the chip 110 and a sidewall 115 that surrounds the through hole 116 .
- the redistribution layer 130 is located on the isolation layer 120 , and is in electrical contact with the conductive pad 114 that is in the through hole 116 .
- the passivation layer 140 is located on the isolation layer 120 and the redistribution layer 130 .
- the passivation layer 140 on the bottom surface 113 of the chip 110 has an opening 142 , and a portion of the redistribution layer 130 is in the opening 142 .
- the encapsulation layer 150 is located on the top surface 111 of the chip 110 and covers the sensor 112 and the conductive pad 114 . Moreover, the encapsulation layer 150 has a flat surface 152 that faces away from the chip 110 .
- the chip 110 may be made of silicon.
- the sensor 112 is a fingerprint sensor.
- the sensor 112 may be an image sensor, and the present invention is not limited in this regard.
- the redistribution layer 130 of the chip package 100 is exposed through the opening 142 of the passivation layer 140 , and may be used to electrically connect to a conductive structure of an external electronic element (e.g., a printed circuit board). Such a configuration is described as a land grid array (LGA).
- LGA land grid array
- the encapsulation layer 150 is located on the top surface 111 of the chip 110 and covers the sensor 112 and the conductive pad 114 , the sensor 112 and the conductive pad 114 may be prevented from being polluted by moisture, oil stain, or dust. As a result, the yield and reliability of the chip package 100 can be improved, and the lifespan of the chip package 100 can be extended. Moreover, because the chip package 100 has the encapsulation layer 150 , designers may select the chip 110 having a small thickness to reduce the total thickness of the chip package 100 but not to lead the chip 110 to be broken. In addition, the encapsulation layer 150 has the flat surface 152 that faces away from the chip 110 , and thus the top of the chip package 100 is configured with full planarization.
- the encapsulation layer 150 having a suitable thickness and a suitable dielectric constant can prevent capacitance attenuation, thereby improving the detect sensitivity of the chip package 100 for fingerprints.
- the thickness of the encapsulation layer 150 may be in a range from 5 ⁇ m to 40 ⁇ m, and the dielectric constant of the encapsulation layer 150 may be greater than 5.
- the chip package 100 may further include an isolation layer 160 .
- the isolation layer 160 is located on the top surface 111 of the chip 110 , and is covered by the encapsulation layer 150 .
- FIG. 2 is a cross-sectional view of a chip package 100 a according to one embodiment of the present invention.
- the chip package 100 a includes the chip 110 , the isolation layer 120 , the redistribution layer 130 , the passivation layer 140 , and the encapsulation layer 150 .
- the difference between this embodiment and the embodiment shown in FIG. 1B is that the chip package 100 a further includes a conductive structure 170 .
- the conductive structure 170 is located on the redistribution layer 130 that is in the opening 142 of the passivation layer 140 , and protrudes from the passivation layer 140 .
- the conductive structure 170 may be used to electrically connect conductive contacts of an external electronic element (e.g., a printed circuit board).
- Such a configuration is a ball grid array (BGA).
- FIGS. 3 to 8 are cross-sectional views of a manufacturing method of a chip package according to one embodiment of the present invention.
- a temporary bonding layer 210 is formed on a carrier 220
- the encapsulation layer 150 is formed on the top surface 111 of a wafer 110 a or on the temporary bonding layer 210 .
- the wafer 110 a is referred to as a semiconductor structure which is not yet divided into plural chips 110 (see FIG. 1B and FIG. 2 ), such as a silicon wafer.
- the carrier 220 may be bonded to the wafer 110 a through the temporary bonding layer 210 and the encapsulation layer 150 , such that the encapsulation layer 150 and the temporary bonding layer 210 are located between the wafer 110 a and the carrier 220 , and the encapsulation layer 150 covers the sensor 112 and the conductive pad 114 of the wafer 110 a .
- a grinding treatment may be performed on a bottom surface 113 of the wafer 110 a to reduce the thickness of the wafer 110 a as deemed necessary.
- the bottom surface 113 of the wafer 110 a is patterned to form the through hole 116 , such that the conductive pad 114 is exposed through the through hole 116 .
- the wafer 110 a may be patterned by photolithography.
- photolithography may include exposure, development, and etch processes.
- the bottom surface of the wafer 113 may be patterned to form a dicing trench 105 , such that a portion of the wafer 110 a is located between the dicing trench 105 and the through hole 116 .
- the dicing trench 105 may be used as a cutting path for a cutting tool, as shown in FIG. 8 .
- the isolation layer 120 may be formed on the bottom surface 113 of the wafer 110 a , the sidewall 115 of the through hole 116 , and the conductive pad 114 that is in the through hole 116 through chemical vapor deposition (CVD). Thereafter, an etch process is performed on the isolation layer 120 to remove the isolation layer 120 that is on the conductive pad 114 . As shown in FIG. 6 , after the formation of the isolation layer 120 , the redistribution layer 130 may be formed on the isolation layer 120 and the conductive pad 114 that is in the through hole 116 .
- CVD chemical vapor deposition
- the passivation layer 140 may be formed on the isolation layer 120 and the redistribution layer 130 , and a portion of the passivation layer 140 may be located in the dicing trench 105 . Moreover, the passivation layer 140 may be patterned to have the opening 142 , such that a portion of the redistribution layer 130 is in the opening 142 . As shown in FIG. 8 , after the formation of the passivation layer 140 , the temporary bonding layer 210 and the carrier 220 may be optionally removed. For example, ultraviolet light may be utilized to irradiate the temporary bonding layer 210 , thereby eliminating the adhesion of the temporary bonding layer 210 .
- the encapsulation layer 150 and the passivation layer 140 may be cut along the dicing trench 105 .
- the encapsulation layer 150 and the passivation layer 140 may be cut along line L-L.
- the conductive structure 170 may be formed on the redistribution layer 130 that is in the opening 142 of the passivation layer 140 , such that the conductive structure 170 may be electrically connected to the conductive pad 114 through the redistribution layer 130 .
- the temporary bonding layer 210 and the carrier 220 may be optionally removed, and the encapsulation layer 150 and the passivation layer 140 are cut along line L-L. After the dicing step, the chip package 100 a of FIG. 2 can be obtained.
- FIG. 9 is a cross-sectional view of a chip package 100 b according to one embodiment of the present invention.
- the chip package 100 b includes the chip 110 , the isolation layer 120 , the redistribution layer 130 , the passivation layer 140 , and the encapsulation layer 150 .
- the difference between this embodiment and the embodiment shown in FIG. 1B is that the chip 110 of the chip package 100 b further has a concave portion 118 .
- the through hole 116 is higher than the concave portion 118 in position.
- the concave portion 118 has two adjacent surfaces 117 and 119 , and the surface 117 of the concave portion 118 adjoins the sidewall 115 of the through hole 116 , and the surface 119 of the concave portion 118 adjoins the bottom surface 113 of the chip 110 .
- An obtuse angle ⁇ is formed between the two surfaces 117 and 119 of the concave portion 118 .
- the sidewall 115 of the through hole 116 , the two surfaces 117 and 119 of the concave portion 118 , and the bottom surface 113 of the chip 110 present a step profile.
- the redistribution layer 130 extends from the conductive pad 114 to the bottom surface 113 of the chip 110 along the sidewall 115 of the through hole 116 and the two surfaces 117 and 119 of the concave portion 118 , such that the redistribution layer 130 presents a step profile to prevent from being easily broken.
- the redistribution layer 130 is exposed through the opening 142 of the passivation layer 140 , and thus the chip package 100 b has a land grid array.
- FIG. 10A is a cross-sectional view of a chip package 100 c according to one embodiment of the present invention.
- the chip package 100 c includes the chip 110 , the isolation layer 120 , the redistribution layer 130 , the passivation layer 140 , and the encapsulation layer 150 .
- the difference between this embodiment and the embodiment shown in FIG. 9 is that the chip package 100 c further includes the conductive structure 170 .
- the conductive structure 170 is located on the redistribution layer 130 that is in the opening 142 of the passivation layer 140 . In this embodiment, the conductive structure 170 protrudes from the passivation layer 140 , and the chip package 100 c has a ball grid array.
- FIG. 10B is a cross-sectional view of a chip package 100 c ′ according to one embodiment of the present invention.
- the chip package 100 c ′ includes the chip 110 , the isolation layer 120 , the redistribution layer 130 , the passivation layer 140 , and the encapsulation layer 150 .
- the chip package 100 c ′ further includes a conductive structure 170 a and a molding compound 190 .
- the conductive structure 170 a is located on the redistribution layer 130 that is in the opening 142 of the passivation layer 140 .
- the conductive structure 170 a has a bottom surface 172 facing away from the redistribution layer 130 .
- the molding compound 190 covers the passivation layer 140 and surrounds the conductive structure 170 a .
- the molding compound 190 has a bottom surface 192 facing away from the passivation layer 140 , and the bottom surface 192 of the molding compound 190 and the bottom surface 172 of the conductive structure 170 a are at the same horizontal level.
- FIGS. 11 to 15B are cross-sectional views of a manufacturing method of a chip package according to some embodiments of the present invention.
- the temporary bonding layer 210 is formed on the carrier 220
- the encapsulation layer 150 is formed on the top surface 111 of the wafer 110 a or on the temporary bonding layer 210 .
- the carrier 220 may be bonded to the wafer 110 a through the temporary bonding layer 210 and the encapsulation layer 150 , and a grinding treatment may be performed on the bottom surface 113 of the wafer 110 a to reduce the thickness of the wafer 110 a as deemed necessary.
- the bottom surface 113 of the wafer 110 a may be patterned to form the through hole 116 , such that the conductive pad 114 is exposed through the through hole 116 .
- the bottom surface 113 of the wafer 110 a is patterned to form the concave portion 118 , and the concave portion 118 has two adjacent surfaces 117 and 119 .
- the surface 117 of the concave portion 118 is patterned to form the through hole 116 , such that the two surfaces 117 and 119 of the concave portion 118 are respectively adjoin the sidewall 115 of the through hole 116 and the bottom surface 113 of the wafer 110 a .
- a two-step etch treatment is used to form the concave portion 118 and the through hole 116 in sequence.
- the wafer 110 a may be patterned to form the dicing trench 105 , such that a portion of the wafer 110 a is located between the dicing trench 105 and the through hole 116 .
- the dicing trench 105 may be used as a cutting path for a cutting tool, as shown in FIG. 15A .
- the isolation layer 120 may be formed on the bottom surface 113 of the wafer 110 a , the surfaces 117 and 119 of the concave portion 118 , the sidewall 115 of the through hole 116 , and the conductive pad 114 that is in the through hole 116 . Thereafter, an etch treatment is performed on the isolation layer 120 to remove the isolation layer 120 that is on the conductive pad 114 . As shown in FIG. 13 , after the isolation layer 120 is formed, the redistribution layer 130 may be formed on the isolation layer 120 and the conductive pad 114 that is in the through hole 116 .
- the passivation layer 140 may be formed on the isolation layer 120 and the redistribution layer 130 , and a portion of the passivation layer 140 may be located in the dicing trench 105 . Moreover, the passivation layer 140 may be patterned to have the opening 142 , such that a portion of the redistribution layer 130 is in the opening 142 . As shown in FIG. 15A , after the formation of the passivation layer 140 , the temporary bonding layer 210 and the carrier 220 may be optionally removed. For example, ultraviolet light may be utilized to irradiate the temporary bonding layer 210 , thereby eliminating the adhesion of the temporary bonding layer 210 .
- the encapsulation layer 150 and the passivation layer 140 may be cut along the dicing trench 105 .
- the encapsulation layer 150 and the passivation layer 140 may be cut along line L-L.
- the conductive structure 170 may be formed on the redistribution layer 130 that is in the opening 142 of the passivation layer 140 , such that the conductive structure 170 may be electrically connected to the conductive pad 114 through the redistribution layer 130 .
- the temporary bonding layer 210 and the carrier 220 may be optionally removed, and the encapsulation layer 150 and the passivation layer 140 are cut along line L-L. After the dicing step, the chip package 100 c of FIG. 10A can be obtained.
- the conductive structure 170 may be formed on the redistribution layer 130 that is in the opening 142 of the passivation layer 140 and then the molding compound 190 is formed to cover the passivation layer 140 and the conductive structure 170 before the dicing step of FIG. 15A . Thereafter, a grinding treatment may be performed on the molding compound 190 and the conductive structure 170 from the bottom surface 192 of the molding compound 190 . As a result, the chip package 100 c ′ having the conductive structure 170 a of FIG. 10B can be obtained after a dicing step.
- FIG. 16 is a cross-sectional view of a chip package 100 d according to one embodiment of the present invention.
- the chip package 100 d includes the chip 110 , a molding compound 180 , the redistribution layer 130 , the passivation layer 140 , and the encapsulation layer 150 .
- the chip 110 has the sensor 112 , the conductive pad 114 , the top surface 111 , the bottom surface 113 that is opposite the top surface 111 , and a lateral surface 109 that adjoins the top surface 111 and the bottom surface 113 .
- the sensor 112 and the conductive pad 114 are located on the top surface 111 of the chip 110 , and the conductive pad 114 protrudes from the lateral surface 109 .
- the molding compound 180 covers the bottom surface 113 and the lateral surface 109 of the chip 110 , and has a through hole 182 .
- the conductive pad 114 is in the through hole 182 .
- the redistribution layer 130 is located on the molding compound 180 and is in electrical contact with the conductive pad 114 that is in the through hole 182 .
- the passivation layer 140 is located on the molding compound 180 and the redistribution layer 130 . In this embodiment, the passivation layer 140 and the molding compound 180 may be made of the same material, such as epoxy, but the present invention is not limited in this regard.
- the passivation layer 140 on the bottom surface 113 of the chip 110 has an opening 142 , and a portion of the redistribution layer 130 is in the opening 142 .
- the redistribution layer 130 is exposed through the opening 142 of the passivation layer 140 , and thus the chip package 100 d has a land grid array.
- the encapsulation layer 150 is located on the top surface 111 of the chip 110 and covers the sensor 112 and the conductive pad 114 .
- the encapsulation layer 150 has the flat surface 152 that faces away from the chip 110 .
- the thickness of the encapsulation layer 150 may be in a range from 5 ⁇ m to 40 ⁇ m, and the dielectric constant of the encapsulation layer 150 may be greater than 5.
- the molding compound 180 has a surface 184 that surrounds the through hole 182 and a surface 186 that faces away from the bottom surface 113 of the chip 110 , and the surface 184 is perpendicular to the surface 186 .
- the redistribution layer 130 extends from the conductive pad 114 to the surface 186 of the molding compound 180 along the surface 184 of the molding compound 180 .
- the chip package 100 d may further include the isolation layer 160 .
- the isolation layer 160 is located on the top surface 111 of the chip 110 , and is covered by the encapsulation layer 150 .
- FIG. 17A is a cross-sectional view of a chip package 100 e according to one embodiment of the present invention.
- the chip package 100 e includes the chip 110 , the molding compound 180 , the redistribution layer 130 , the passivation layer 140 , and the encapsulation layer 150 .
- the difference between this embodiment and the embodiment shown in FIG. 16 is that the chip package 100 e further includes the conductive structure 170 .
- the conductive structure 170 is located on the redistribution layer 130 that is in the opening 142 of the passivation layer 140 . In this embodiment, the conductive structure 170 protrudes from the passivation layer 140 , and thus the chip package 100 e has a ball grid array.
- FIG. 17B is a cross-sectional view of a chip package 100 e ′ according to one embodiment of the present invention.
- the chip package 100 e ′ includes the chip 110 , the isolation layer 120 , a redistribution layer 130 a , the passivation layer 140 , and the encapsulation layer 150 .
- the difference between this embodiment and the embodiment shown in FIG. 17A is that a conductive structure 170 b of the chip package 100 e ′ has a bottom surface 172 facing away from the redistribution layer 130 a , and the bottom surface 172 of the conductive structure 170 b is level with the passivation layer 140 .
- a through hole 182 a and the redistribution layer 130 a of the chip package 100 e ′ extend to the encapsulation layer 150 , in which the redistribution layer 130 a may fill the through hole 182 a that is in the conductive pad 114 and the encapsulation layer 150 .
- FIGS. 18 to 22 are cross-sectional views of a manufacturing method of a chip package according to some embodiments of the present invention.
- the temporary bonding layer 210 is formed on the carrier 220
- the encapsulation layer 150 is formed on the top surface 111 of the wafer 110 a or on the temporary bonding layer 210 .
- the carrier 220 may be bonded to the wafer 110 a through the temporary bonding layer 210 and the encapsulation layer 150 , and a grinding treatment may be performed on the bottom surface 113 of the wafer 110 a to reduce the thickness of the wafer 110 a as deemed necessary.
- the bottom surface 113 of the wafer 110 a may be patterned to form the dicing trench 105 , such that the conductive pad 114 is exposed through the dicing trench 105 .
- the dicing trench 105 may be used as a cutting path for a cutting tool, as shown in FIG. 22 .
- the molding compound 180 is molded to cover the bottom surface 113 of the wafer 110 a and the dicing trench 105 . Thereafter, the through hole 182 is formed in the molding compound 180 by laser drilling, such that the conductive pad 114 is in the through hole 182 . As shown in FIG. 20A , after the formation of the through hole 182 of the molding compound 180 , the redistribution layer 130 may be formed on the surfaces 184 and 186 of the molding compound 180 and the conductive pad 114 that is in the through hole 182 .
- the passivation layer 140 may be formed on the molding compound 180 and the redistribution layer 130 . Moreover, the passivation layer 140 may be patterned to have the opening 142 , such that a portion of the redistribution layer 130 is in the opening 142 . As shown in FIG. 22 , after the formation of the passivation layer 140 , the temporary bonding layer 210 and the carrier 220 may be optionally removed. For example, ultraviolet light may be utilized to irradiate the temporary bonding layer 210 , thereby eliminating the adhesion of the temporary bonding layer 210 .
- the encapsulation layer 150 , the molding compound 180 , and the passivation layer 140 may be cut along the dicing trench 105 .
- the encapsulation layer 150 , the molding compound 180 , and the passivation layer 140 may be cut along line L-L.
- the chip package 100 d of FIG. 16 can be obtained.
- the conductive structure 170 may be formed on the redistribution layer 130 that is in the opening 142 of the passivation layer 140 , such that the conductive structure 170 may be electrically connected to the conductive pad 114 through the redistribution layer 130 .
- the temporary bonding layer 210 and the carrier 220 may be optionally removed, and the encapsulation layer 150 , the molding compound 180 , and the passivation layer 140 are cut along line L-L. After the dicing step, the chip package 100 e of FIG. 17A can be obtained.
- the through hole 182 a may be formed in the molding compound 180 by laser drilling, and the through hole 182 a passes through the conductive pad 114 and extends to the encapsulation layer 150 .
- the redistribution layer 130 a is formed not only on the surfaces 184 and 186 of the molding compound 180 and the conductive pad 114 that is in the through hole 182 a , but also on the encapsulation layer 150 that is in the through hole 182 a .
- the chip package 100 e ′ having the through hole 182 a , the redistribution layer 130 a , and the conductive structure 170 b of FIG. 17B can be obtained.
Abstract
Description
- This application claims priority to U.S. provisional Application Ser. No. 62/519,022, filed Jun. 13, 2017, which is herein incorporated by reference.
- The present invention relates to a chip package and a manufacturing method of the chip package.
- The process of packaging a chip is an important step for forming electronic products. A chip package can protect the chip therein to prevent the chip from environmental pollution, and it also provides electrical connection paths between inner electronic elements of the chip and external devices.
- During an electronic product capable of sensing fingerprints being used by a user, moisture or oil stains easily remain on the electronic product, thereby causing the chip package in the electronic product to be polluted. In addition, when the electronic product is operated, a sensor is easily physically damaged, thereby reducing the lifespan of the electronic product. Moreover, the capacitance of a typical electronic product is easily attenuated, thereby affecting the sensing capability of the typical electronic product, such as the capability of sensing fingerprints.
- An aspect of the present invention is to provide a chip package.
- According to an embodiment of the present invention, a chip package includes a chip, a first isolation layer, a redistribution layer, a passivation layer, and an encapsulation layer. The chip has a sensor, a conductive pad, a through hole, a top surface, and a bottom surface that is opposite the top surface. The sensor and the conductive pad are located on the top surface, and the conductive pad is in the through hole. The first isolation layer is located on the bottom surface of the chip and a sidewall that surrounds the through hole. The redistribution layer is located on the first isolation layer and is in electrical contact with the conductive pad that is in the through hole. The passivation layer is located on the first isolation layer and the redistribution layer. The passivation layer on the bottom surface of the chip has an opening, and a portion of the redistribution layer is in the opening. The encapsulation layer is located on the top surface of the chip and covers the sensor and the conductive pad. The encapsulation layer has a flat surface facing away from the chip.
- An aspect of the present invention is to provide a manufacturing method of a chip package.
- According to an embodiment of the present invention, a manufacturing method of a chip package includes forming a temporary bonding layer on a carrier, forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer, bonding the carrier to the wafer, in which the encapsulation layer and the temporary bonding layer are located between the wafer and the carrier, and the encapsulation layer covers a sensor and a conductive pad of the wafer, patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole, forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole, forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole, forming a passivation layer on the isolation layer and the redistribution layer, in which the passivation layer has an opening, and a portion of the redistribution layer is in the opening, and removing the temporary bonding layer and the carrier.
- An aspect of the present invention is to provide a chip package.
- According to an embodiment of the present invention, a chip package includes a chip, a molding compound, a redistribution layer, a passivation layer, and an encapsulation layer. The chip has a sensor, a conductive pad, a top surface, a bottom surface that is opposite the top surface, and a lateral surface that adjoins the top surface and the bottom surface. The sensor and the conductive pad are located on the top surface, and the conductive pad protrudes from the lateral surface. The molding compound covers the bottom surface and the lateral surface of the chip, and has a through hole. The conductive pad is in the through hole. The redistribution layer is located on the molding compound and is in electrical contact with the conductive pad that is in the through hole. The passivation layer is located on the molding compound and the redistribution layer. The passivation layer on the bottom surface of the chip has an opening, and a portion of the redistribution layer is in the opening. The encapsulation layer is located on the top surface of the chip and covers the sensor and the conductive pad. The encapsulation layer has a flat surface facing away from the chip.
- An aspect of the present invention is to provide a manufacturing method of a chip package.
- According to an embodiment of the present invention, a manufacturing method of a chip package includes forming a temporary bonding layer on a carrier, forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer, bonding the carrier to the wafer, in which the encapsulation layer and the temporary bonding layer are located between the wafer and the carrier, and the encapsulation layer covers a sensor and a conductive pad of the wafer, patterning a bottom surface of the wafer to form a dicing trench, in which the conductive pad is exposed through the dicing trench, molding a molding compound to cover the bottom surface of the wafer and the dicing trench, forming a through hole in the molding compound by laser drilling, in which the conductive pad is in the through hole, forming a redistribution layer on the molding compound and the conductive pad that is in the through hole, forming a passivation layer on the molding compound and the redistribution layer, in which the passivation layer has an opening, and a portion of the redistribution layer is in the opening, and removing the temporary bonding layer and the carrier.
- In the aforementioned embodiments of the present invention, the encapsulation layer is located on the top surface of the chip and covers the sensor and the conductive pad, thereby preventing the sensor and the conductive pad from being polluted by moisture, oil stain, or dust. Moreover, the encapsulation layer has the flat surface facing away from the chip, and thus the top of the chip package is configured with full planarization. Such a design is a convenient factor for assembly, and can improve a tactile sensation for users. In addition, when the chip package is a fingerprint sensing device, the encapsulation layer having a suitable thickness and a suitable dielectric constant can prevent capacitance attenuation, thereby improving the detect sensitivity of the chip package for fingerprints.
- It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed.
- The invention can be more fully understood by reading the following detailed description of the embodiments, with reference made to the accompanying drawings as follows:
-
FIG. 1A is a top view of a chip package according to one embodiment of the present invention; -
FIG. 1B is a cross-sectional view of the chip package taken alongline 1B-1B shown inFIG. 1A ; -
FIG. 2 is a cross-sectional view of a chip package according to one embodiment of the present invention; -
FIGS. 3 to 8 are cross-sectional views of a manufacturing method of a chip package according to one embodiment of the present invention; -
FIG. 9 is a cross-sectional view of a chip package according to one embodiment of the present invention; -
FIG. 10A is a cross-sectional view of a chip package according to one embodiment of the present invention; -
FIG. 10B is a cross-sectional view of a chip package according to one embodiment of the present invention; -
FIGS. 11 to 15B are cross-sectional views of a manufacturing method of a chip package according to some embodiments of the present invention; -
FIG. 16 is a cross-sectional view of a chip package according to one embodiment of the present invention; -
FIG. 17A is a cross-sectional view of a chip package according to one embodiment of the present invention; -
FIG. 17B is a cross-sectional view of a chip package according to one embodiment of the present invention; and -
FIGS. 18 to 22 are cross-sectional views of a manufacturing method of a chip package according to some embodiments of the present invention. - Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
-
FIG. 1A is a top view of achip package 100 according to one embodiment of the present invention.FIG. 1B is a cross-sectional view of thechip package 100 taken alongline 1B-1B shown inFIG. 1A . As shown inFIG. 1A andFIG. 1B , thechip package 100 includes achip 110, anisolation layer 120, aredistribution layer 130, apassivation layer 140, and anencapsulation layer 150. Thechip 110 has asensor 112, aconductive pad 114, a throughhole 116, atop surface 111, and abottom surface 113 that is opposite thetop surface 111. Thesensor 112 and theconductive pad 114 are located on thetop surface 111 of thechip 110, and theconductive pad 114 is in the throughhole 116. Theisolation layer 120 is located on thebottom surface 113 of thechip 110 and asidewall 115 that surrounds the throughhole 116. Theredistribution layer 130 is located on theisolation layer 120, and is in electrical contact with theconductive pad 114 that is in the throughhole 116. Thepassivation layer 140 is located on theisolation layer 120 and theredistribution layer 130. Thepassivation layer 140 on thebottom surface 113 of thechip 110 has anopening 142, and a portion of theredistribution layer 130 is in theopening 142. Theencapsulation layer 150 is located on thetop surface 111 of thechip 110 and covers thesensor 112 and theconductive pad 114. Moreover, theencapsulation layer 150 has aflat surface 152 that faces away from thechip 110. - In this embodiment, the
chip 110 may be made of silicon. Thesensor 112 is a fingerprint sensor. However, in another embodiment, thesensor 112 may be an image sensor, and the present invention is not limited in this regard. Theredistribution layer 130 of thechip package 100 is exposed through theopening 142 of thepassivation layer 140, and may be used to electrically connect to a conductive structure of an external electronic element (e.g., a printed circuit board). Such a configuration is described as a land grid array (LGA). - Since the
encapsulation layer 150 is located on thetop surface 111 of thechip 110 and covers thesensor 112 and theconductive pad 114, thesensor 112 and theconductive pad 114 may be prevented from being polluted by moisture, oil stain, or dust. As a result, the yield and reliability of thechip package 100 can be improved, and the lifespan of thechip package 100 can be extended. Moreover, because thechip package 100 has theencapsulation layer 150, designers may select thechip 110 having a small thickness to reduce the total thickness of thechip package 100 but not to lead thechip 110 to be broken. In addition, theencapsulation layer 150 has theflat surface 152 that faces away from thechip 110, and thus the top of thechip package 100 is configured with full planarization. Such a design is a convenient factor for assembly, and can improve a tactile sensation for users. When thechip package 100 is a fingerprint sensing device, theencapsulation layer 150 having a suitable thickness and a suitable dielectric constant can prevent capacitance attenuation, thereby improving the detect sensitivity of thechip package 100 for fingerprints. For example, the thickness of theencapsulation layer 150 may be in a range from 5 μm to 40 μm, and the dielectric constant of theencapsulation layer 150 may be greater than 5. - Furthermore, the
chip package 100 may further include anisolation layer 160. Theisolation layer 160 is located on thetop surface 111 of thechip 110, and is covered by theencapsulation layer 150. -
FIG. 2 is a cross-sectional view of achip package 100 a according to one embodiment of the present invention. Thechip package 100 a includes thechip 110, theisolation layer 120, theredistribution layer 130, thepassivation layer 140, and theencapsulation layer 150. The difference between this embodiment and the embodiment shown inFIG. 1B is that thechip package 100 a further includes aconductive structure 170. Theconductive structure 170 is located on theredistribution layer 130 that is in theopening 142 of thepassivation layer 140, and protrudes from thepassivation layer 140. Theconductive structure 170 may be used to electrically connect conductive contacts of an external electronic element (e.g., a printed circuit board). Such a configuration is a ball grid array (BGA). - In the following description, manufacturing methods of the
chip package 100 ofFIG. 1B and thechip package 100 a ofFIG. 2 will be described. -
FIGS. 3 to 8 are cross-sectional views of a manufacturing method of a chip package according to one embodiment of the present invention. As shown inFIG. 3 , first of all, atemporary bonding layer 210 is formed on acarrier 220, and theencapsulation layer 150 is formed on thetop surface 111 of awafer 110 a or on thetemporary bonding layer 210. Thewafer 110 a is referred to as a semiconductor structure which is not yet divided into plural chips 110 (seeFIG. 1B andFIG. 2 ), such as a silicon wafer. Thereafter, thecarrier 220 may be bonded to thewafer 110 a through thetemporary bonding layer 210 and theencapsulation layer 150, such that theencapsulation layer 150 and thetemporary bonding layer 210 are located between thewafer 110 a and thecarrier 220, and theencapsulation layer 150 covers thesensor 112 and theconductive pad 114 of thewafer 110 a. Afterwards, a grinding treatment may be performed on abottom surface 113 of thewafer 110 a to reduce the thickness of thewafer 110 a as deemed necessary. - As shown in
FIG. 4 , after bonding thecarrier 220 to thewafer 110 a and the grinding treatment, thebottom surface 113 of thewafer 110 a is patterned to form the throughhole 116, such that theconductive pad 114 is exposed through the throughhole 116. In this step, thewafer 110 a may be patterned by photolithography. For example, photolithography may include exposure, development, and etch processes. In this embodiment, the bottom surface of thewafer 113 may be patterned to form adicing trench 105, such that a portion of thewafer 110 a is located between the dicingtrench 105 and the throughhole 116. In the subsequent manufacturing process, the dicingtrench 105 may be used as a cutting path for a cutting tool, as shown inFIG. 8 . - As shown in
FIG. 5 , after the throughhole 116 is formed, theisolation layer 120 may be formed on thebottom surface 113 of thewafer 110 a, thesidewall 115 of the throughhole 116, and theconductive pad 114 that is in the throughhole 116 through chemical vapor deposition (CVD). Thereafter, an etch process is performed on theisolation layer 120 to remove theisolation layer 120 that is on theconductive pad 114. As shown inFIG. 6 , after the formation of theisolation layer 120, theredistribution layer 130 may be formed on theisolation layer 120 and theconductive pad 114 that is in the throughhole 116. - As shown in
FIG. 7 , next, thepassivation layer 140 may be formed on theisolation layer 120 and theredistribution layer 130, and a portion of thepassivation layer 140 may be located in the dicingtrench 105. Moreover, thepassivation layer 140 may be patterned to have theopening 142, such that a portion of theredistribution layer 130 is in theopening 142. As shown inFIG. 8 , after the formation of thepassivation layer 140, thetemporary bonding layer 210 and thecarrier 220 may be optionally removed. For example, ultraviolet light may be utilized to irradiate thetemporary bonding layer 210, thereby eliminating the adhesion of thetemporary bonding layer 210. Afterwards, theencapsulation layer 150 and thepassivation layer 140 may be cut along the dicingtrench 105. In other words, theencapsulation layer 150 and thepassivation layer 140 may be cut along line L-L. After the dicing step, thechip package 100 ofFIG. 1B can be obtained. - In addition, before the removal of the
temporary bonding layer 210 and thecarrier 220, the conductive structure 170 (seeFIG. 2 ) may be formed on theredistribution layer 130 that is in theopening 142 of thepassivation layer 140, such that theconductive structure 170 may be electrically connected to theconductive pad 114 through theredistribution layer 130. After the formation of theconductive structure 170, thetemporary bonding layer 210 and thecarrier 220 may be optionally removed, and theencapsulation layer 150 and thepassivation layer 140 are cut along line L-L. After the dicing step, thechip package 100 a ofFIG. 2 can be obtained. - It is to be noted that the connection relationship of the aforementioned elements will not be repeated. In the following description, other types of the chip packages will be described.
-
FIG. 9 is a cross-sectional view of achip package 100 b according to one embodiment of the present invention. Thechip package 100 b includes thechip 110, theisolation layer 120, theredistribution layer 130, thepassivation layer 140, and theencapsulation layer 150. The difference between this embodiment and the embodiment shown inFIG. 1B is that thechip 110 of thechip package 100 b further has aconcave portion 118. The throughhole 116 is higher than theconcave portion 118 in position. Theconcave portion 118 has twoadjacent surfaces surface 117 of theconcave portion 118 adjoins thesidewall 115 of the throughhole 116, and thesurface 119 of theconcave portion 118 adjoins thebottom surface 113 of thechip 110. An obtuse angle θ is formed between the twosurfaces concave portion 118. Thesidewall 115 of the throughhole 116, the twosurfaces concave portion 118, and thebottom surface 113 of thechip 110 present a step profile. Therefore, theredistribution layer 130 extends from theconductive pad 114 to thebottom surface 113 of thechip 110 along thesidewall 115 of the throughhole 116 and the twosurfaces concave portion 118, such that theredistribution layer 130 presents a step profile to prevent from being easily broken. In this embodiment, theredistribution layer 130 is exposed through theopening 142 of thepassivation layer 140, and thus thechip package 100 b has a land grid array. -
FIG. 10A is a cross-sectional view of achip package 100 c according to one embodiment of the present invention. Thechip package 100 c includes thechip 110, theisolation layer 120, theredistribution layer 130, thepassivation layer 140, and theencapsulation layer 150. The difference between this embodiment and the embodiment shown inFIG. 9 is that thechip package 100 c further includes theconductive structure 170. Theconductive structure 170 is located on theredistribution layer 130 that is in theopening 142 of thepassivation layer 140. In this embodiment, theconductive structure 170 protrudes from thepassivation layer 140, and thechip package 100 c has a ball grid array. -
FIG. 10B is a cross-sectional view of achip package 100 c′ according to one embodiment of the present invention. Thechip package 100 c′ includes thechip 110, theisolation layer 120, theredistribution layer 130, thepassivation layer 140, and theencapsulation layer 150. The difference between this embodiment and the embodiment shown inFIG. 9 is that thechip package 100 c′ further includes aconductive structure 170 a and amolding compound 190. Theconductive structure 170 a is located on theredistribution layer 130 that is in theopening 142 of thepassivation layer 140. In this embodiment, theconductive structure 170 a has abottom surface 172 facing away from theredistribution layer 130. Themolding compound 190 covers thepassivation layer 140 and surrounds theconductive structure 170 a. Themolding compound 190 has abottom surface 192 facing away from thepassivation layer 140, and thebottom surface 192 of themolding compound 190 and thebottom surface 172 of theconductive structure 170 a are at the same horizontal level. - In the following description, manufacturing methods of the
chip package 100 b ofFIG. 9 and thechip package 100 c ofFIG. 10A will be described. -
FIGS. 11 to 15B are cross-sectional views of a manufacturing method of a chip package according to some embodiments of the present invention. As shown inFIG. 3 andFIG. 11 , first of all, thetemporary bonding layer 210 is formed on thecarrier 220, and theencapsulation layer 150 is formed on thetop surface 111 of thewafer 110 a or on thetemporary bonding layer 210. Thereafter, thecarrier 220 may be bonded to thewafer 110 a through thetemporary bonding layer 210 and theencapsulation layer 150, and a grinding treatment may be performed on thebottom surface 113 of thewafer 110 a to reduce the thickness of thewafer 110 a as deemed necessary. After bonding thecarrier 220 to thewafer 110 a and the grinding treatment, thebottom surface 113 of thewafer 110 a may be patterned to form the throughhole 116, such that theconductive pad 114 is exposed through the throughhole 116. In this step, thebottom surface 113 of thewafer 110 a is patterned to form theconcave portion 118, and theconcave portion 118 has twoadjacent surfaces surface 117 of theconcave portion 118 is patterned to form the throughhole 116, such that the twosurfaces concave portion 118 are respectively adjoin thesidewall 115 of the throughhole 116 and thebottom surface 113 of thewafer 110 a. For example, a two-step etch treatment is used to form theconcave portion 118 and the throughhole 116 in sequence. Moreover, in the step of forming the throughhole 116, thewafer 110 a may be patterned to form the dicingtrench 105, such that a portion of thewafer 110 a is located between the dicingtrench 105 and the throughhole 116. In the subsequent manufacturing process, the dicingtrench 105 may be used as a cutting path for a cutting tool, as shown inFIG. 15A . - As shown in
FIG. 12 , after the formations of theconcave portion 118 and the throughhole 116, theisolation layer 120 may be formed on thebottom surface 113 of thewafer 110 a, thesurfaces concave portion 118, thesidewall 115 of the throughhole 116, and theconductive pad 114 that is in the throughhole 116. Thereafter, an etch treatment is performed on theisolation layer 120 to remove theisolation layer 120 that is on theconductive pad 114. As shown inFIG. 13 , after theisolation layer 120 is formed, theredistribution layer 130 may be formed on theisolation layer 120 and theconductive pad 114 that is in the throughhole 116. - As shown in
FIG. 14 , next, thepassivation layer 140 may be formed on theisolation layer 120 and theredistribution layer 130, and a portion of thepassivation layer 140 may be located in the dicingtrench 105. Moreover, thepassivation layer 140 may be patterned to have theopening 142, such that a portion of theredistribution layer 130 is in theopening 142. As shown inFIG. 15A , after the formation of thepassivation layer 140, thetemporary bonding layer 210 and thecarrier 220 may be optionally removed. For example, ultraviolet light may be utilized to irradiate thetemporary bonding layer 210, thereby eliminating the adhesion of thetemporary bonding layer 210. Afterwards, theencapsulation layer 150 and thepassivation layer 140 may be cut along the dicingtrench 105. In other words, theencapsulation layer 150 and thepassivation layer 140 may be cut along line L-L. After the dicing step, thechip package 100 b ofFIG. 9 can be obtained. - In addition, before the removal of the
temporary bonding layer 210 and thecarrier 220, the conductive structure 170 (seeFIG. 10A ) may be formed on theredistribution layer 130 that is in theopening 142 of thepassivation layer 140, such that theconductive structure 170 may be electrically connected to theconductive pad 114 through theredistribution layer 130. After the formation of theconductive structure 170, thetemporary bonding layer 210 and thecarrier 220 may be optionally removed, and theencapsulation layer 150 and thepassivation layer 140 are cut along line L-L. After the dicing step, thechip package 100 c ofFIG. 10A can be obtained. - In another embodiment, as shown in
FIG. 15B , theconductive structure 170 may be formed on theredistribution layer 130 that is in theopening 142 of thepassivation layer 140 and then themolding compound 190 is formed to cover thepassivation layer 140 and theconductive structure 170 before the dicing step ofFIG. 15A . Thereafter, a grinding treatment may be performed on themolding compound 190 and theconductive structure 170 from thebottom surface 192 of themolding compound 190. As a result, thechip package 100 c′ having theconductive structure 170 a ofFIG. 10B can be obtained after a dicing step. -
FIG. 16 is a cross-sectional view of achip package 100 d according to one embodiment of the present invention. Thechip package 100 d includes thechip 110, amolding compound 180, theredistribution layer 130, thepassivation layer 140, and theencapsulation layer 150. Thechip 110 has thesensor 112, theconductive pad 114, thetop surface 111, thebottom surface 113 that is opposite thetop surface 111, and alateral surface 109 that adjoins thetop surface 111 and thebottom surface 113. Thesensor 112 and theconductive pad 114 are located on thetop surface 111 of thechip 110, and theconductive pad 114 protrudes from thelateral surface 109. Themolding compound 180 covers thebottom surface 113 and thelateral surface 109 of thechip 110, and has a throughhole 182. Theconductive pad 114 is in the throughhole 182. Theredistribution layer 130 is located on themolding compound 180 and is in electrical contact with theconductive pad 114 that is in the throughhole 182. Thepassivation layer 140 is located on themolding compound 180 and theredistribution layer 130. In this embodiment, thepassivation layer 140 and themolding compound 180 may be made of the same material, such as epoxy, but the present invention is not limited in this regard. Thepassivation layer 140 on thebottom surface 113 of thechip 110 has anopening 142, and a portion of theredistribution layer 130 is in theopening 142. In this embodiment, theredistribution layer 130 is exposed through theopening 142 of thepassivation layer 140, and thus thechip package 100 d has a land grid array. Theencapsulation layer 150 is located on thetop surface 111 of thechip 110 and covers thesensor 112 and theconductive pad 114. Theencapsulation layer 150 has theflat surface 152 that faces away from thechip 110. The thickness of theencapsulation layer 150 may be in a range from 5 μm to 40 μm, and the dielectric constant of theencapsulation layer 150 may be greater than 5. - In this embodiment, the
molding compound 180 has asurface 184 that surrounds the throughhole 182 and asurface 186 that faces away from thebottom surface 113 of thechip 110, and thesurface 184 is perpendicular to thesurface 186. Moreover, theredistribution layer 130 extends from theconductive pad 114 to thesurface 186 of themolding compound 180 along thesurface 184 of themolding compound 180. In this embodiment, thechip package 100 d may further include theisolation layer 160. Theisolation layer 160 is located on thetop surface 111 of thechip 110, and is covered by theencapsulation layer 150. -
FIG. 17A is a cross-sectional view of achip package 100 e according to one embodiment of the present invention. Thechip package 100 e includes thechip 110, themolding compound 180, theredistribution layer 130, thepassivation layer 140, and theencapsulation layer 150. The difference between this embodiment and the embodiment shown inFIG. 16 is that thechip package 100 e further includes theconductive structure 170. Theconductive structure 170 is located on theredistribution layer 130 that is in theopening 142 of thepassivation layer 140. In this embodiment, theconductive structure 170 protrudes from thepassivation layer 140, and thus thechip package 100 e has a ball grid array. -
FIG. 17B is a cross-sectional view of achip package 100 e′ according to one embodiment of the present invention. Thechip package 100 e′ includes thechip 110, theisolation layer 120, aredistribution layer 130 a, thepassivation layer 140, and theencapsulation layer 150. The difference between this embodiment and the embodiment shown inFIG. 17A is that aconductive structure 170 b of thechip package 100 e′ has abottom surface 172 facing away from theredistribution layer 130 a, and thebottom surface 172 of theconductive structure 170 b is level with thepassivation layer 140. Moreover, a throughhole 182 a and theredistribution layer 130 a of thechip package 100 e′ extend to theencapsulation layer 150, in which theredistribution layer 130 a may fill the throughhole 182 a that is in theconductive pad 114 and theencapsulation layer 150. - In the following description, manufacturing methods of the
chip package 100 d ofFIG. 16 and thechip package 100 e ofFIG. 17A will be described. -
FIGS. 18 to 22 are cross-sectional views of a manufacturing method of a chip package according to some embodiments of the present invention. As shown inFIG. 3 andFIG. 18 , first of all, thetemporary bonding layer 210 is formed on thecarrier 220, and theencapsulation layer 150 is formed on thetop surface 111 of thewafer 110 a or on thetemporary bonding layer 210. Thereafter, thecarrier 220 may be bonded to thewafer 110 a through thetemporary bonding layer 210 and theencapsulation layer 150, and a grinding treatment may be performed on thebottom surface 113 of thewafer 110 a to reduce the thickness of thewafer 110 a as deemed necessary. After bonding thecarrier 220 to thewafer 110 a and the grinding treatment, thebottom surface 113 of thewafer 110 a may be patterned to form the dicingtrench 105, such that theconductive pad 114 is exposed through the dicingtrench 105. In the subsequent manufacturing process, the dicingtrench 105 may be used as a cutting path for a cutting tool, as shown inFIG. 22 . - As shown in
FIG. 19A , after the formation of the dicingtrench 105, themolding compound 180 is molded to cover thebottom surface 113 of thewafer 110 a and the dicingtrench 105. Thereafter, the throughhole 182 is formed in themolding compound 180 by laser drilling, such that theconductive pad 114 is in the throughhole 182. As shown inFIG. 20A , after the formation of the throughhole 182 of themolding compound 180, theredistribution layer 130 may be formed on thesurfaces molding compound 180 and theconductive pad 114 that is in the throughhole 182. - As shown in
FIG. 21 , next, thepassivation layer 140 may be formed on themolding compound 180 and theredistribution layer 130. Moreover, thepassivation layer 140 may be patterned to have theopening 142, such that a portion of theredistribution layer 130 is in theopening 142. As shown inFIG. 22 , after the formation of thepassivation layer 140, thetemporary bonding layer 210 and thecarrier 220 may be optionally removed. For example, ultraviolet light may be utilized to irradiate thetemporary bonding layer 210, thereby eliminating the adhesion of thetemporary bonding layer 210. Afterwards, theencapsulation layer 150, themolding compound 180, and thepassivation layer 140 may be cut along the dicingtrench 105. In other words, theencapsulation layer 150, themolding compound 180, and thepassivation layer 140 may be cut along line L-L. After the dicing step, thechip package 100 d ofFIG. 16 can be obtained. - In addition, before the removal of the
temporary bonding layer 210 and thecarrier 220, the conductive structure 170 (seeFIG. 17A ) may be formed on theredistribution layer 130 that is in theopening 142 of thepassivation layer 140, such that theconductive structure 170 may be electrically connected to theconductive pad 114 through theredistribution layer 130. After the formation of theconductive structure 170, thetemporary bonding layer 210 and thecarrier 220 may be optionally removed, and theencapsulation layer 150, themolding compound 180, and thepassivation layer 140 are cut along line L-L. After the dicing step, thechip package 100 e ofFIG. 17A can be obtained. - In another embodiment, as shown in
FIG. 19B , after the formation of themolding compound 180, the throughhole 182 a may be formed in themolding compound 180 by laser drilling, and the throughhole 182 a passes through theconductive pad 114 and extends to theencapsulation layer 150. Thereafter, as shown inFIG. 20B , theredistribution layer 130 a is formed not only on thesurfaces molding compound 180 and theconductive pad 114 that is in the throughhole 182 a, but also on theencapsulation layer 150 that is in the throughhole 182 a. Next, after the aforementioned steps of forming thepassivation layer 140 and theconductive structure 170, removing thetemporary bonding layer 210 and thecarrier 220, and dicing, thechip package 100 e′ having the throughhole 182 a, theredistribution layer 130 a, and theconductive structure 170 b ofFIG. 17B can be obtained. - Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims.
Claims (20)
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US15/996,841 US20180358398A1 (en) | 2017-06-13 | 2018-06-04 | Chip package and manufacturing method thereof |
US16/950,810 US11476293B2 (en) | 2017-06-13 | 2020-11-17 | Manufacturing method of chip package |
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US201762519022P | 2017-06-13 | 2017-06-13 | |
US15/996,841 US20180358398A1 (en) | 2017-06-13 | 2018-06-04 | Chip package and manufacturing method thereof |
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US11749618B2 (en) * | 2020-01-06 | 2023-09-05 | Xintec Inc. | Chip package including substrate having through hole and redistribution line |
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US20210066379A1 (en) | 2021-03-04 |
US11476293B2 (en) | 2022-10-18 |
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