US20180269136A1 - Electronic device - Google Patents
Electronic device Download PDFInfo
- Publication number
- US20180269136A1 US20180269136A1 US15/856,181 US201715856181A US2018269136A1 US 20180269136 A1 US20180269136 A1 US 20180269136A1 US 201715856181 A US201715856181 A US 201715856181A US 2018269136 A1 US2018269136 A1 US 2018269136A1
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- United States
- Prior art keywords
- electronic device
- edge
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- wiring pattern
- conductive
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- 239000010410 layer Substances 0.000 claims description 81
- 229920005989 resin Polymers 0.000 claims description 35
- 239000011347 resin Substances 0.000 claims description 35
- 239000011241 protective layer Substances 0.000 claims description 21
- 230000003287 optical effect Effects 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 7
- 230000008901 benefit Effects 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 102220474007 Gamma-secretase subunit PEN-2_W36A_mutation Human genes 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 102220632636 Immunoglobulin heavy variable 1-69_W35A_mutation Human genes 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920000915 polyvinyl chloride Polymers 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
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- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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Definitions
- the present disclosure relates to an electronic device.
- a conventional semiconductor light emitting device includes a base, a semiconductor light emitting element, a wiring pattern, a bonding layer, and a sealing resin.
- the wiring pattern is formed on the base.
- the semiconductor light emitting element is disposed on the wiring pattern via the bonding layer.
- the sealing resin is disposed on the base so as to cover the semiconductor light emitting element and the wiring pattern.
- Some embodiments of the present disclosure provide an electronic device capable of preventing a bonding layer from peeling from a wiring pattern or a base.
- FIG. 1 is a perspective view of an electronic device according to a first embodiment.
- FIG. 2 is a front view of the electronic device according to the first embodiment.
- FIG. 4 is a right side view of the electronic device according to the first embodiment.
- FIG. 5 is a plan view of the electronic device according to the first embodiment.
- FIG. 7 is a view in which a bonding layer is excluded from the electronic device shown in FIG. 6 .
- FIG. 10 is a cross-sectional view taken along line X-X in FIG. 5 .
- FIG. 11 is a plan view of an electronic device at a certain point of time in a method of manufacturing the electronic device according to the first embodiment.
- FIG. 12 is a plan view of an electronic device at a certain point of time in the method of manufacturing the electronic device according to the first embodiment.
- FIG. 13 is a plan view of an electronic device at a certain point of time in the method of manufacturing the electronic device according to the first embodiment.
- FIG. 14 is a plan view of an electronic device according to a second embodiment.
- FIG. 15 is a plan view of an electronic device according to a third embodiment.
- FIG. 1 is a perspective view of an electronic device according to a first embodiment.
- FIG. 2 is a front view of the electronic device according to the first embodiment.
- FIG. 3 is a left side view of the electronic device according to the first embodiment.
- FIG. 4 is a right side view of the electronic device according to the first embodiment.
- FIG. 5 is a plan view of the electronic device according to the first embodiment.
- the base 1 has a main surface 11 , a back surface 13 , a first side surface 15 A, a second side surface 15 B, a third side surface 15 C, and a fourth side surface 15 D.
- the opening 39 has an annular shape (more specifically, an annular shape with a portion missed).
- the bonding layer 5 is disposed in the opening 39 . As shown in FIG. 10 , the bonding layer 5 is in contact with a portion 119 of the base 1 exposed by the opening 39 in the wiring pattern 3 .
- the first conductive portion 32 includes a second inner side surface 321 facing the first inner side surface 311 .
- the second inner side surface 321 has an arc shape when viewed in the thickness direction Z 1 .
- the bonding layer 5 is in contact with the second inner side surface 321 .
- the second inner side surface 321 may not be in contact with the bonding layer 5 but may be separated from the bonding layer 5 .
- the first conductive portion 32 has a front surface 322 facing the thickness direction Z 1 of the base 1 .
- the front surface 322 of the first conductive portion 32 has a contact part 322 A and an exposed part 322 B.
- the contact part 322 A is in contact with the bonding layer 5 .
- the electronic element 41 need not be an optical element.
- the electronic element 41 may be an element (for example, a Zener diode or an IC chip) that does not perform an optical function.
- the electronic element 41 need not be a semiconductor element.
- the electronic element 41 may be a resistor or a capacitor.
- the width W 32 of the narrowest part of the first conductive portion 32 is smaller than any one of the width W 35 A of the first edge portion 35 A, the width W 36 A of the first connecting portion 36 A, and the width W 61 of the portion 61 of the protective layer 6 .
- the width W 35 A of the first edge portion 35 A and the width W 61 of the portion 61 of the protective layer 6 are smaller than the width W 36 A of the first connecting portion 36 A.
- a rectangular base 100 (see FIG. 11 ) in which a plurality of through-holes 16 are formed in a matrix is prepared.
- the base 100 has such a size that a plurality of bases 1 shown in FIG. 2 and so on can be formed.
- a plurality of circular through-holes 16 are formed in the base 100 .
- the base 100 is made of the same material (that is to say, glass epoxy resin) as the base 1 .
- the wiring pattern 3 is formed on the base 100 .
- the wiring pattern 3 is formed by plating Au on a Cu foil.
- the opening 39 is formed in the wiring pattern 3 .
- the bonding layer 5 is formed on the wiring pattern 3 .
- a portion of the bonding layer 5 is filled in the opening 39 of the wiring pattern 3 .
- the protective layer 6 is formed on the base 100 with the wiring pattern 3 formed thereon.
- a film-shaped resist is pressed and adhered to the base 100 .
- the electronic element 41 is disposed on the wiring pattern 3 via the bonding layer 5 .
- the wire 42 is wire-bonded to the electronic element 41 and the wiring pattern 3 .
- the electronic elements 41 and the wiring pattern 3 are electrically interconnected.
- a plurality of electronic devices A 1 shown in FIG. 1 and so on are produced by dicing an intermediate product on which the resin portion 7 is formed.
- the method of manufacturing the electronic device A 1 a case of manufacturing a plurality of electronic devices A 1 all at once has been illustrated above, but they may be manufactured one by one.
- the opening 39 is formed in the wiring pattern 3 .
- the bonding layer 5 is in contact with the portion 119 of the base 1 exposed by the opening 39 in the wiring pattern 3 .
- the bonding strength between the bonding layer 5 and the base 1 is greater than the bonding force between the bonding layer 5 derived from silver paste and the Au plating in the wiring pattern 3 . Therefore, in the embodiment in which the bonding layer 5 is derived from silver paste and the wiring pattern 3 includes the Au plating, it is possible to more effectively prevent the bonding layer 5 from being peeled from the base 1 and the wiring pattern 3 .
- the front surface 322 of the first conductive portion 32 includes the exposed part 322 B exposed from the bonding layer 5 .
- the contact part 322 A is located between the exposed part 322 B and the opening 39 when viewed in the thickness direction Z 1 of the base 1 .
- the second conductive portion 33 is disposed on a side opposite the first edge portion 35 A with respect to the die pad portion 31 . This makes it possible to minimize the transfer of heat from the first conductive portion 32 to the die pad portion 31 via the second conductive portion 33 .
- a second embodiment will be described with reference to FIG. 14 .
- FIG. 14 is a plan view of an electronic device A 2 according to a second embodiment in which a resin portion is excluded from the electronic device.
- the outer shape of the first conductive portion 32 and the specific shape of the protective layer 6 are different from those of the electronic device A 1 .
- the outer shape of the first conductive portion 32 is a circular shape.
- the protective layer 6 includes a portion 63 formed on the first connecting portion 36 A. The portion 63 extends along the same direction (the first direction X 1 ) as the extending direction of the first connecting portion 36 A. The position of a wire bonding pad portion 34 A deviates from the position of the wire bonding pad portion 34 of the first embodiment in the second direction Y 1 .
- the wire bonding pad portion 34 A is connected to a portion 34 B. The description of the wire bonding pad portion 34 of the first embodiment may be applied for the portion 34 B.
- the wire bonding pad portion 34 A includes edges 341 to 344 .
- the edge 341 is connected to the portion 34 B and extends substantially along the first direction X 1 (strictly speaking, a direction inclined to the first direction X 1 ).
- the edge 342 is connected to the edge 341 and extends substantially along the second direction Y 1 (strictly speaking, a direction inclined to the second direction Y 1 ).
- the edge 343 is connected to the edge 342 and extends along the first direction X 1 .
- the edge 344 is connected to the edge 343 and extends substantially along the second direction Y 1 (strictly speaking, a direction inclined to the second direction Y 1 ).
- the edge 344 is connected to the portion 34 B.
- the second embodiment has the following advantages in addition to the advantages described in the first embodiment.
- heat is transferred from the first edge portion 35 A side to the first conductive portion 32 via the first connecting portion 36 A.
- the resin portion 7 is bonded to the portion 61 on the first connecting portion 36 A. This makes it possible to prevent the resin portion 7 from being peeled from the wiring pattern 3 on the first connecting portion 36 A.
- the wire bonding pad portion 34 A is disposed at a position deviating from the electronic element 41 in the second direction Y 1 . Therefore, it is possible to secure a larger distance between two bonding positions of the wire 42 while suppressing an increase in the area of the main surface 11 . As a result, it is possible to improve the reliability of the connection of the wire 42 while reducing the area of the main surface 11 .
- a portion of the wire 42 overlaps with the opening 39 when viewed from a top view. This makes it possible to reduce parasitic capacitance that may occur between the wire 42 and the wiring pattern 3 . As a result, it is possible to control the electronic element 41 with higher accuracy.
- FIG. 15 is a plan view of an electronic device A 3 according to a third embodiment in which a resin portion is excluded from the electronic device.
- the third embodiment is different from the first embodiment in that the wiring pattern 3 includes a plurality of second conductive portions 33 . Each of the plurality of second conductive portions 33 radially extends from the die pad portion 31 . The opening 39 in the wiring pattern 3 has a plurality of portions 391 separated from each other.
- the configuration of the third embodiment may be combined with the configuration of the second embodiment.
- An electronic device including: a base; a wiring pattern formed on the base; an electronic element disposed on the wiring pattern; and a bonding layer interposed between the electronic element and the wiring pattern, wherein an opening is formed in the wiring pattern and the bonding layer is in contact with a portion of the base exposed by the opening in the wiring pattern.
- the electronic device of Supplementary Note 6 wherein the surface of the first conductive portion includes an exposed part exposed from the bonding layer and the contact part is located between the exposed part and the opening when viewed in the thickness direction of the base.
- the wiring pattern includes one or more second conductive portions connected to both the die pad portion and the first conductive portion, each of the one or more second conductive portions is located between the die pad portion and the first conductive portion, a part of one of the one or more second conductive portions defining the opening, and the bonding layer is in contact with the one or more second conductive portions.
- each of the one or more second conductive portions extends from the die pad portion toward the first conductive portion when viewed in the thickness direction of the base and has a front surface facing the thickness direction of the base, and the front surface of each of the one or more second conductive portions is in contact with the bonding layer.
- the electronic device of Supplementary Note 4 further including a wire bonded to the electronic element, wherein the wiring pattern includes a wire bonding pad portion to which the wire is bonded.
- the electronic device of Supplementary Note 13 wherein the base has a main surface and a back surface opposing each other, the electronic element is disposed on the main surface, and the wiring pattern is formed on the main surface and the back surface.
- the base has a first side surface and a second side surface facing a direction perpendicular to the thickness direction of the base, the first side surface and the second side surface opposing each other, wherein a first concave portion recessed from the first side surface and a second concave portion recessed from the second side surface are formed in the base
- the wiring pattern includes a first connecting portion, a second connecting portion, a first edge portion, a second edge portion, a first side surface portion, and a second side surface portion, wherein the first edge portion is formed on the main surface and extends along an edge of the first concave portion, wherein the second edge portion is formed on the main surface and extends along an edge of the second concave portion, wherein the first side surface portion is formed on an inner side surface of the first concave portion and is connected to the first edge portion, wherein the second side surface portion is formed on an inner side surface of the second concave portion and is connected to the second edge portion, wherein the first connecting portion is
- the electronic device of Supplementary Note 15 further including a protective layer covering the wiring pattern, wherein the protective layer includes a portion covering the first connecting portion.
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Abstract
Description
- This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2017-49556, filed on Mar. 15, 2017, the entire contents of which are incorporated herein by reference.
- The present disclosure relates to an electronic device.
- A conventional semiconductor light emitting device includes a base, a semiconductor light emitting element, a wiring pattern, a bonding layer, and a sealing resin. The wiring pattern is formed on the base. The semiconductor light emitting element is disposed on the wiring pattern via the bonding layer. The sealing resin is disposed on the base so as to cover the semiconductor light emitting element and the wiring pattern.
- Some embodiments of the present disclosure provide an electronic device capable of preventing a bonding layer from peeling from a wiring pattern or a base.
- According to one embodiment of the present disclosure, there is provided an electronic device including: a base; a wiring pattern formed on the base; an electronic element disposed on the wiring pattern; and a bonding layer interposed between the electronic element and the wiring pattern, wherein an opening is formed in the wiring pattern and the bonding layer is in contact with a portion of the base exposed by the opening in the wiring pattern.
- Other features and advantages of the present disclosure will become more apparent from the following detailed description in conjunction with the accompanying drawings.
-
FIG. 1 is a perspective view of an electronic device according to a first embodiment. -
FIG. 2 is a front view of the electronic device according to the first embodiment. -
FIG. 3 is a left side view of the electronic device according to the first embodiment. -
FIG. 4 is a right side view of the electronic device according to the first embodiment. -
FIG. 5 is a plan view of the electronic device according to the first embodiment. -
FIG. 6 is a view in which an electronic element, a wire, and a protective layer are excluded from the electronic device shown inFIG. 5 . -
FIG. 7 is a view in which a bonding layer is excluded from the electronic device shown inFIG. 6 . -
FIG. 8 is a bottom view of the electronic device according to the first embodiment. -
FIG. 9 is a cross-sectional view taken along line IX-IX inFIG. 5 . -
FIG. 10 is a cross-sectional view taken along line X-X inFIG. 5 . -
FIG. 11 is a plan view of an electronic device at a certain point of time in a method of manufacturing the electronic device according to the first embodiment. -
FIG. 12 is a plan view of an electronic device at a certain point of time in the method of manufacturing the electronic device according to the first embodiment. -
FIG. 13 is a plan view of an electronic device at a certain point of time in the method of manufacturing the electronic device according to the first embodiment. -
FIG. 14 is a plan view of an electronic device according to a second embodiment. -
FIG. 15 is a plan view of an electronic device according to a third embodiment. - Embodiments of the present disclosure will be now described in detail with reference to the drawings.
- A first embodiment will be described below with reference to
FIGS. 1 to 13 . -
FIG. 1 is a perspective view of an electronic device according to a first embodiment.FIG. 2 is a front view of the electronic device according to the first embodiment.FIG. 3 is a left side view of the electronic device according to the first embodiment.FIG. 4 is a right side view of the electronic device according to the first embodiment.FIG. 5 is a plan view of the electronic device according to the first embodiment. - An electronic device A1 shown in these figures includes a
base 1, awiring pattern 3, anelectronic element 41, awire 42, abonding layer 5, aprotective layer 6, and aresin portion 7. Theresin portion 7 is not shown inFIG. 5 . - The
base 1 is made of, e.g., insulating material such as insulating resin or ceramic. An example of the insulating resin may include glass epoxy resin or the like. An example of the ceramic may include Al2O3, SiC, AlN, or the like. Thebase 1 may be a substrate on which an insulating film made of metal such as aluminum is formed. Thebase 1 has a rectangular shape when viewed in a thickness direction Z1 of thebase 1. - The
base 1 has amain surface 11, aback surface 13, afirst side surface 15A, asecond side surface 15B, athird side surface 15C, and afourth side surface 15D. - The
main surface 11 and theback surface 13 are separated from each other in the thickness direction Z1 of thebase 1 and face opposite directions. Both themain surface 11 and theback surface 13 are flat. - The
first side surface 15A and thesecond side surface 15B are separated from each other in a first direction X1 and face opposite directions. Both thefirst side surface 15A and thesecond side surface 15B are connected to themain surface 11 and theback surface 13. Both thefirst side surface 15A and thesecond side surface 15B are flat. - A first
concave portion 16A and a secondconcave portion 16B are formed in thebase 1. The firstconcave portion 16A and the secondconcave portion 16B are recessed inwardly from thefirst side surface 15A and thesecond side surface 15B of thebase 1, respectively. Both the firstconcave portion 16A and the secondconcave portion 16B are formed to span from themain surface 11 to theback surface 13. In the first embodiment, the firstconcave portion 16A and the secondconcave portion 16B have a semicircular shape when viewed in the thickness direction Z1 of thebase 1. - The
third side surface 15C and thefourth side surface 15D are separated from each other in a second direction Y1 and face opposite directions. Both thethird side surface 15C and thefourth side surface 15D are connected to themain surface 11 and theback surface 13. Both thethird side surface 15C and thefourth side surface 15D are flat. -
FIG. 6 is a view in which an electronic element, a wire, and a protective layer are excluded from the electronic device shown inFIG. 5 .FIG. 7 is a view in which a bonding layer is excluded from the electronic device shown inFIG. 6 .FIG. 8 is a bottom view of the electronic device according to the first embodiment. - The
wiring pattern 3 shown inFIG. 5 toFIG. 7 defines a current path through which electric power is supplied to theelectronic element 41. Thewiring pattern 3 is electrically connected to theelectronic element 41. Thewiring pattern 3 is made of, e.g., metal such as Cu, Ni, Ti, Au, or the like alone or in combination. Thewiring pattern 3 is formed on thebase 1. In the first embodiment, thewiring pattern 3 is formed by plating Au on Cu. The material of thewiring pattern 3 is not particularly limited to those mentioned here. Thewiring pattern 3 is formed on themain surface 11 and theback surface 13. In the first embodiment, thewiring pattern 3 is formed in the firstconcave portion 16A and the secondconcave portion 16B. - The
wiring pattern 3 includes adie pad portion 31, a firstconductive portion 32, a secondconductive portion 33, afirst edge portion 35A, asecond edge portion 35B, a first connectingportion 36A, a second connectingportion 36B, a firstside surface portion 37A, a secondside surface portion 37B, a firstback surface portion 38A, and a secondback surface portion 38B. Anopening 39 is formed in thewiring pattern 3. -
FIG. 9 is a cross-sectional view taken along line IX-IX inFIG. 5 .FIG. 10 is a cross-sectional view taken along line X-X inFIG. 5 . - In the first embodiment, the
opening 39 has an annular shape (more specifically, an annular shape with a portion missed). Thebonding layer 5 is disposed in theopening 39. As shown inFIG. 10 , thebonding layer 5 is in contact with aportion 119 of thebase 1 exposed by theopening 39 in thewiring pattern 3. - As shown in
FIGS. 5 to 7 andFIGS. 9 and 10 , thedie pad portion 31, the firstconductive portion 32, the secondconductive portion 33, thefirst edge portion 35A, thesecond edge portion 35B, the first connectingportion 36A, and the second connectingportion 36B are formed on themain surface 11 of thebase 1. - The
electronic element 41 is disposed on thedie pad portion 31. A part of thedie pad portion 31 defines theopening 39. Thebonding layer 5 is in contact with thedie pad portion 31. Thedie pad portion 31 includes a firstinner side surface 311 facing a direction intersecting the thickness direction Z1 of the base 1 (a direction perpendicular to the thickness direction Z1 in the first embodiment). The firstinner side surface 311 defines a part of theopening 39. In the first embodiment, thebonding layer 5 is in contact with the firstinner side surface 311. As shown inFIG. 7 , thedie pad portion 31 includes afirst edge 31A and asecond edge 31B located opposite to each other in thedie pad portion 31 when viewed in the thickness direction Z1 of thebase 1. - The first
conductive portion 32 is separated from thedie pad portion 31. In the first embodiment, the firstconductive portion 32 is annular and surrounds thedie pad portion 31. More specifically, the firstconductive portion 32 is in an annular form having a rectangular outer shape. The outer shape of the firstconductive portion 32 is not limited to the rectangular shape but may be other shapes such as a circular shape and a triangular shape. A part of the firstconductive portion 32 defines theopening 39. When viewed in the thickness direction Z1 of thebase 1, theopening 39 is interposed between the firstconductive portion 32 and thedie pad portion 31. Thebonding layer 5 is in contact with the firstconductive portion 32. - As shown in
FIG. 10 , the firstconductive portion 32 includes a secondinner side surface 321 facing the firstinner side surface 311. The secondinner side surface 321 has an arc shape when viewed in the thickness direction Z1. Thebonding layer 5 is in contact with the secondinner side surface 321. Unlike the first embodiment, the secondinner side surface 321 may not be in contact with thebonding layer 5 but may be separated from thebonding layer 5. The firstconductive portion 32 has afront surface 322 facing the thickness direction Z1 of thebase 1. Thefront surface 322 of the firstconductive portion 32 has acontact part 322A and anexposed part 322B. Thecontact part 322A is in contact with thebonding layer 5. The exposedpart 322B is exposed from thebonding layer 5. Thecontact part 322A is located between theexposed part 322B and theopening 39 when viewed in the thickness direction Z1 of thebase 1. As shown inFIG. 7 , in the first embodiment, a distance L2 between the secondinner side surface 321 and the firstinner side surface 311 is substantially equal to a distance L1. However, the distance L2 may be smaller or larger than the distance L1. In the first embodiment, the distance L2 is larger than a width W1 of the secondconductive portion 33. For example, the distance L1 may be larger than the distance L2 and the distance L2 may be larger than the width W1. When the distances L1 and L2 are larger than the width W1, this means that the width of a portion (the second conductive portion 33) connecting thedie pad portion 31 is small, thereby limiting the possibility of thedie pad portion 31 from peeling. Since the distance L2 is smaller than the distance L1, a force of lifting theelectronic element 41 at the time of application of a thermal stress or the like becomes small, reducing the likelihood of theelectronic element 41 from slipping out. - As shown in
FIG. 7 , the secondconductive portion 33 is connected to both thedie pad portion 31 and the firstconductive portion 32. The secondconductive portion 33 is located between thedie pad portion 31 and the firstconductive portion 32. A part of the secondconductive portion 33 defines theopening 39. Thebonding layer 5 is in contact with the secondconductive portion 33. The secondconductive portion 33 extends from thedie pad portion 31 toward the firstconductive portion 32 when viewed in the thickness direction Z1 of thebase 1. Specifically, the secondconductive portion 33 is disposed on a side opposite thefirst edge portion 35A with respect to thedie pad portion 31. The secondconductive portion 33 has afront surface 332 facing the thickness direction Z1 of thebase 1. Thefront surface 332 of the secondconductive portion 33 is in contact with thebonding layer 5. In the first embodiment, the entirefront surface 332 is in contact with thebonding layer 5. In the first embodiment, the width W1 of the secondconductive portion 33 is smaller than the separation distance L1 between thefirst edge 31A and thesecond edge 31B. Unlike the first embodiment, the width W1 of the secondconductive portion 33 may be equal to or greater than the separation distance L1 between thefirst edge 31A and thesecond edge 31B. - Unlike the first embodiment, the second
conductive portion 33 may not be formed. Thedie pad portion 31 may be insulated from any other portion of thewiring pattern 3. In this case, theopening 39 may have a completely annular shape rather than the partial annular shape. - As shown in
FIG. 7 , thefirst edge portion 35A extends along anedge 161A of the firstconcave portion 16A. In the first embodiment, thefirst edge portion 35A is semi-annular. The first connectingportion 36A is located between the firstconductive portion 32 and thefirst edge portion 35A and is electrically connected to the firstconductive portion 32 and thefirst edge portion 35A. More specifically, the first connectingportion 36A is connected to the firstconductive portion 32 and thefirst edge portion 35A. - The
wire 42 is bonded to a wirebonding pad portion 34. The wirebonding pad portion 34 is separated from thedie pad portion 31 in the first direction X1. - The
second edge portion 35B extends along anedge 161B of the secondconcave portion 16B. In the first embodiment, thesecond edge portion 35B is semi-annular. The second connectingportion 36B is located between the wirebonding pad portion 34 and thesecond edge portion 35B and is electrically connected to the wirebonding pad portion 34 and thesecond edge portion 35B. More specifically, the second connectingportion 36B is connected to the wirebonding pad portion 34 and thesecond edge portion 35B. - In the first embodiment, the
wiring pattern 3 includes aconductive portion 36C. Theconductive portion 36C extends along the second direction Y1 and reaches thethird side surface 15C and thefourth side surface 15D. Theconductive portion 36C is connected to the wirebonding pad portion 34 and the second connectingportion 36B. - The first
side surface portion 37A is formed on the inner surface of the firstconcave portion 16A and is connected to thefirst edge portion 35A. The secondside surface portion 37B is formed on the inner surface of the secondconcave portion 16B and is connected to thesecond edge portion 35B. - As shown in
FIG. 8 , the firstback surface portion 38A and the secondback surface portion 38B are formed on theback surface 13 of thebase 1. - The first
back surface portion 38A is connected to the firstside surface portion 37A. The firstback surface portion 38A includesedges 381A to 387A. Theedge 381A extends along the first direction X1. Theedge 382A extends along the second direction Y1 and is connected to theedge 381A. Theedge 383A extends along the first direction X1 and is connected to theedge 382A. Theedge 384A extends along the second direction Y1 and is connected to theedge 381A. Theedge 384A is shorter than theedge 382A. Theedge 385A is a circular-arc shape and is connected to theedge 384A. Theedge 385A reaches an end of theback surface 13 of thebase 1 in the first direction X1. Theedge 386A extends along the second direction Y1 and is connected to theedge 383A. Theedge 386A is shorter than theedge 382A. Theedge 387A is a circular-arc shape and is connected to theedge 386A. Theedge 387A reaches the end of theback surface 13 of thebase 1 in the first direction X1. - The second
back surface portion 38B is connected to the secondside surface portion 37B. The secondback surface portion 38B includesedges 381B to 387B. Theedge 381B extends along the first direction X1. Theedge 382B extends along the second direction Y1 and is connected to theedge 381B. Theedge 383B extends along the first direction X1 and is connected to theedge 382B. Theedge 384B extends along the second direction Y1 and is connected to theedge 381B. Theedge 384B is shorter than theedge 382B. Theedge 385B is a circular-arc shape and is connected to theedge 384B. Theedge 385B reaches an end of theback surface 13 of thebase 1 in the first direction X1. Theedge 386B extends along the second direction Y1 and is connected to theedge 383B. Theedge 386B is shorter than theedge 382B. Theedge 387B is a circular-arc shape and is connected to theedge 386B. Theedge 387B reaches the end of theback surface 13 of thebase 1 in the first direction X1. - The
electronic element 41 is disposed on thedie pad portion 31 of thewiring pattern 3. In the first embodiment, theelectronic element 41 is a semiconductor element, more specifically an optical element including a light emitting element and a light receiving element. In the first embodiment, theelectronic element 41 is a light emitting element and serves as a light source of the electronic device A1. In the first embodiment, theelectronic element 41 is an LED chip. In the first embodiment, theelectronic element 41 includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The n-type semiconductor layer is laminated on the active layer. The active layer is laminated on the p-type semiconductor layer. Therefore, the active layer is located between the n-type semiconductor layer and the p-type semiconductor layer. The n-type semiconductor layer, the active layer, and the p-type semiconductor layer are made of, e.g., GaN. Theelectronic element 41 includes a main surface electrode pad (not shown) and a back surface electrode pad (not shown) facing opposite directions. Theelectronic element 41 is mounted on thebase 1. The emission color of theelectronic element 41 is not particularly limited. - Unlike the first embodiment, the
electronic element 41 need not be an optical element. For example, theelectronic element 41 may be an element (for example, a Zener diode or an IC chip) that does not perform an optical function. Theelectronic element 41 need not be a semiconductor element. For example, theelectronic element 41 may be a resistor or a capacitor. - The
wire 42 is bonded to theelectronic element 41 and the wirebonding pad portion 34. Thewire 42 is made of a conductive material. Thewire 42 makes electrical conduction with theelectronic element 41 and the wirebonding pad portion 34. In the first embodiment, thewire 42 extends along the first direction X1 when viewed in the thickness direction Z1. - As shown in
FIG. 10 , thebonding layer 5 is interposed between theelectronic element 41 and thewiring pattern 3. A part of thebonding layer 5 is filled in theopening 39. In the first embodiment, thebonding layer 5 is made of a conductive material. Thebonding layer 5 is derived from, e.g., silver paste. Unlike the first embodiment, thebonding layer 5 may be made of an insulating material. In the first embodiment, thebonding layer 5 is in contact with (or in close contact with) aside surface 411 of theelectronic element 41, the firstinner side surface 311 of thedie pad portion 31, and afront surface 312 of thedie pad portion 31. This allows thebonding layer 5 to hold theelectronic element 41 more firmly. The height of thebonding layer 5 from themain surface 11 is greater than the height of thedie pad portion 31 from themain surface 11. Afront surface 51 of thebonding layer 5 is located farther from themain surface 11 than thefront surface 312 of thedie pad portion 31. - The
protective layer 6 is made of an insulating material. Theprotective layer 6 may be sometimes referred to as a resist layer. Theprotective layer 6 is formed on themain surface 11 and thewiring pattern 3. As shown inFIGS. 3 and 4 , theprotective layer 6 is interposed between thebase 1 and theresin portion 7 and is in contact with thebase 1 and theresin portion 7. - The
protective layer 6 includesportions portions portions main surface 11 to the other end thereof in the second direction Y1. A part of theportion 61 is formed on the first connectingportion 36A. A part of theportion 62 is formed on the second connectingportion 36B. - As shown in
FIG. 5 , in the first embodiment, the width W32 of the narrowest part of the firstconductive portion 32 is smaller than any one of the width W35A of thefirst edge portion 35A, the width W36A of the first connectingportion 36A, and the width W61 of theportion 61 of theprotective layer 6. In the first embodiment, the width W35A of thefirst edge portion 35A and the width W61 of theportion 61 of theprotective layer 6 are smaller than the width W36A of the first connectingportion 36A. In the first embodiment, the width W34 of the wirebonding pad portion 34 is larger than any one of the width W35B of thesecond edge portion 35B, the width W36C of theconductive portion 36C, and the width W62 of theportion 62 of theprotective layer 6. In the first embodiment, the width W36C of theconductive portion 36C is smaller than any one of the width W35B of thesecond edge portion 35B, the width W36B of the second connectingportion 36B, and the width W62 of theportion 62 of theprotective layer 6. In the first embodiment, the width W34 of the wirebonding pad portion 34 is smaller than the width W36A of the first connectingportion 36A. - The
resin portion 7 covers thebase 1, theelectronic element 41, thewiring pattern 3, theprotective layer 6, and thewire 42. In the first embodiment, theresin portion 7 is made of resin that transmits light, such as transparent or translucent epoxy resin, silicone resin, acrylic resin, polyvinyl resin, or the like. Theresin portion 7 may include a fluorescent material which emits light of different wavelengths when excited by light from theelectronic element 41. In the first embodiment, unlike a case where the resin portion is a so-called black resin, no filler is mixed in theresin portion 7. As shown inFIGS. 1 to 4 and so on, theresin portion 7 includes anedge 71. Theedge 71 of theresin portion 7 extends along the second direction Y1. Theedge 71 extends from one end of the electronic device A1 to the other end thereof in the second direction Y1. - The
resin portion 7 is formed by molding. Theresin portion 7 is smaller than thebase 1 in the first direction X1. In the first embodiment, theresin portion 7 has a truncated quadrangular pyramid shape. Theresin portion 7 is not limited to the truncated quadrangular pyramid shape but may have a hemispherical shape protruding in the thickness direction Z1 of thebase 1 or may have a concave surface on the front side in the thickness direction Z1 of thebase 1. Unlike the first embodiment, a reflector surrounding theresin portion 7 and theelectronic element 41 may be disposed on thebase 1. - Next, a method of manufacturing the electronic device A1 according to the first embodiment will be described with reference to
FIGS. 11 to 13 . In the first embodiment, a case of manufacturing a plurality of electronic devices A1 will be described as an example. In the following description, the same or similar elements, portions and parts as above are denoted by the same reference numerals. - First, a rectangular base 100 (see
FIG. 11 ) in which a plurality of through-holes 16 are formed in a matrix is prepared. Thebase 100 has such a size that a plurality ofbases 1 shown inFIG. 2 and so on can be formed. A plurality of circular through-holes 16 are formed in thebase 100. Thebase 100 is made of the same material (that is to say, glass epoxy resin) as thebase 1. Next, thewiring pattern 3 is formed on thebase 100. Thewiring pattern 3 is formed by plating Au on a Cu foil. Theopening 39 is formed in thewiring pattern 3. - Next, as shown in
FIG. 12 , thebonding layer 5 is formed on thewiring pattern 3. A portion of thebonding layer 5 is filled in theopening 39 of thewiring pattern 3. - Next, as shown in
FIG. 13 , theprotective layer 6 is formed on the base 100 with thewiring pattern 3 formed thereon. In the first embodiment, a film-shaped resist is pressed and adhered to thebase 100. - Next, as shown in
FIG. 13 , theelectronic element 41 is disposed on thewiring pattern 3 via thebonding layer 5. Next, thewire 42 is wire-bonded to theelectronic element 41 and thewiring pattern 3. Thus, theelectronic elements 41 and thewiring pattern 3 are electrically interconnected. - Next, although not shown, after the
resin portion 7 is formed by molding, a plurality of electronic devices A1 shown inFIG. 1 and so on are produced by dicing an intermediate product on which theresin portion 7 is formed. In the method of manufacturing the electronic device A1, a case of manufacturing a plurality of electronic devices A1 all at once has been illustrated above, but they may be manufactured one by one. - Next, operations and effects of the first embodiment will be described.
- In the first embodiment, the
opening 39 is formed in thewiring pattern 3. Thebonding layer 5 is in contact with theportion 119 of thebase 1 exposed by theopening 39 in thewiring pattern 3. With such a configuration, since the bonding strength between thebonding layer 5 and thebase 1 is strong, it is possible to prevent thebonding layer 5 from being peeled from thebase 1 and thewiring pattern 3. - The bonding strength between the
bonding layer 5 and thebase 1 is greater than the bonding force between thebonding layer 5 derived from silver paste and the Au plating in thewiring pattern 3. Therefore, in the embodiment in which thebonding layer 5 is derived from silver paste and thewiring pattern 3 includes the Au plating, it is possible to more effectively prevent thebonding layer 5 from being peeled from thebase 1 and thewiring pattern 3. - In the case where no filler is mixed in the
resin portion 7 as in the first embodiment, theresin portion 7 is likely to absorb water. In this case, water vapor may be accumulated at the interface between theresin portion 7 and thebase 1 and at the interface between theresin portion 7 and thewiring pattern 3, possibly causing a water vapor explosion. Even in such a case, in this embodiment, since thebonding layer 5 in contact with theresin portion 7 is firmly bonded to thebase 1, it is possible to prevent thebonding layer 5 from being peeled from thewiring pattern 3. - In the first embodiment, the
wiring pattern 3 includes the firstconductive portion 32. Theopening 39 is located between the firstconductive portion 32 and thedie pad portion 31 when viewed in the thickness direction Z1 of thebase 1. With such a configuration, in manufacturing the electronic device A1, a material making up thebonding layer 5 can be stored in theopening 39. Therefore, when theelectronic element 41 is disposed on thewiring pattern 3, it is possible to make it easy for the material making thebonding layer 5 to seep up to theelectronic element 41. This is suitable to secure electrical conduction between theelectronic element 41 and thewiring pattern 3 more favorably when thebonding layer 5 has conductivity. Further, by storing the material making up thebonding layer 5 in theopening 39, it is possible to prevent the material making up thebonding layer 5 from flowing into the wirebonding pad portion 34. As a result, it is possible to prevent defective bonding of thewire 42 to the wirebonding pad portion 34. - In the first embodiment, the
front surface 322 of the firstconductive portion 32 includes the exposedpart 322B exposed from thebonding layer 5. Thecontact part 322A is located between theexposed part 322B and theopening 39 when viewed in the thickness direction Z1 of thebase 1. With such a configuration, when theelectronic element 41 is a light emitting element, light from the light emitting element can be reflected by the exposedpart 322B. Therefore, when theelectronic element 41 is a light emitting element, light from the light emitting element can be emitted outside of the electronic device A1 with higher efficiency. - During a flow of manufacture of the electronic device A1, heat is transferred from the
first edge portion 35A side to the firstconductive portion 32 via the first connectingportion 36A. In the first embodiment, the secondconductive portion 33 is disposed on a side opposite thefirst edge portion 35A with respect to thedie pad portion 31. This makes it possible to minimize the transfer of heat from the firstconductive portion 32 to thedie pad portion 31 via the secondconductive portion 33. - In the electronic device A1, element adhesion strength of a chip mounting portion is strong, but since the outermost surface of a ring-shaped or horn-shaped portion (the first conductive portion 32) located outside a circumference thereof is gold-plated, it is likely to peel from the
bonding layer 5. This may make it difficult only for theelectronic element 41 to be pulled upward. - A second embodiment will be described with reference to
FIG. 14 . -
FIG. 14 is a plan view of an electronic device A2 according to a second embodiment in which a resin portion is excluded from the electronic device. - In the following description, the same or similar elements, portions and parts as above are denoted by the same reference numerals and explanation thereof will not be repeated as appropriate.
- In the second embodiment, the outer shape of the first
conductive portion 32 and the specific shape of theprotective layer 6 are different from those of the electronic device A1. In the second embodiment, the outer shape of the firstconductive portion 32 is a circular shape. In addition, theprotective layer 6 includes aportion 63 formed on the first connectingportion 36A. Theportion 63 extends along the same direction (the first direction X1) as the extending direction of the first connectingportion 36A. The position of a wirebonding pad portion 34A deviates from the position of the wirebonding pad portion 34 of the first embodiment in the second direction Y1. The wirebonding pad portion 34A is connected to aportion 34B. The description of the wirebonding pad portion 34 of the first embodiment may be applied for theportion 34B. - In the second embodiment, the wire
bonding pad portion 34A includesedges 341 to 344. Theedge 341 is connected to theportion 34B and extends substantially along the first direction X1 (strictly speaking, a direction inclined to the first direction X1). Theedge 342 is connected to theedge 341 and extends substantially along the second direction Y1 (strictly speaking, a direction inclined to the second direction Y1). Theedge 343 is connected to theedge 342 and extends along the first direction X1. Theedge 344 is connected to theedge 343 and extends substantially along the second direction Y1 (strictly speaking, a direction inclined to the second direction Y1). Theedge 344 is connected to theportion 34B. - The second embodiment has the following advantages in addition to the advantages described in the first embodiment. During a flow of manufacture of the electronic device A2, heat is transferred from the
first edge portion 35A side to the firstconductive portion 32 via the first connectingportion 36A. However, since theportion 61 of theprotective layer 6 is formed on the first connectingportion 36A, theresin portion 7 is bonded to theportion 61 on the first connectingportion 36A. This makes it possible to prevent theresin portion 7 from being peeled from thewiring pattern 3 on the first connectingportion 36A. - According to the second embodiment, the wire
bonding pad portion 34A is disposed at a position deviating from theelectronic element 41 in the second direction Y1. Therefore, it is possible to secure a larger distance between two bonding positions of thewire 42 while suppressing an increase in the area of themain surface 11. As a result, it is possible to improve the reliability of the connection of thewire 42 while reducing the area of themain surface 11. As one of the reasons, for example, compared to a case where the wirebonding pad portion 34A is not disposed at a position deviating from theelectronic element 41 in the second direction Y1, it is possible to suppress increase in distance in the first direction X1 (this can cause an increase in area of the main surface 11) as much as possible while increasing the distance between theelectronic element 41 and the wirebonding pad portion 34A for wire bonding. - According to the second embodiment, a portion of the
wire 42 overlaps with theopening 39 when viewed from a top view. This makes it possible to reduce parasitic capacitance that may occur between thewire 42 and thewiring pattern 3. As a result, it is possible to control theelectronic element 41 with higher accuracy. - Next, a third embodiment will be described with reference to
FIG. 15 . -
FIG. 15 is a plan view of an electronic device A3 according to a third embodiment in which a resin portion is excluded from the electronic device. - In the following description, the same or similar elements, portions and parts as above are denoted by the same reference numerals and explanation thereof will not be repeated as appropriate.
- The third embodiment is different from the first embodiment in that the
wiring pattern 3 includes a plurality of secondconductive portions 33. Each of the plurality of secondconductive portions 33 radially extends from thedie pad portion 31. Theopening 39 in thewiring pattern 3 has a plurality ofportions 391 separated from each other. The configuration of the third embodiment may be combined with the configuration of the second embodiment. - The third embodiment is particularly suitable, for example, when the size of the
electronic element 41 is larger than the size in the first embodiment. - According to the third embodiment, a portion of the
wire 42 overlaps with theopening 39 when viewed from a top view. This makes it possible to reduce parasitic capacitance that may occur between thewire 42 and thewiring pattern 3. As a result, it is possible to control theelectronic element 41 with higher accuracy. - The present disclosure is not limited to the above-described embodiments. The specific configurations of various portions and parts of the present disclosure can be changed in design in different ways.
- Variations of the above-described embodiments will be supplemented as follows.
- An electronic device including: a base; a wiring pattern formed on the base; an electronic element disposed on the wiring pattern; and a bonding layer interposed between the electronic element and the wiring pattern, wherein an opening is formed in the wiring pattern and the bonding layer is in contact with a portion of the base exposed by the opening in the wiring pattern.
- The electronic device of
Supplementary Note 1, wherein the wiring pattern includes a die pad portion on which the electronic element is disposed, a part of the die pad portion defines the opening, and the bonding layer is in contact with the die pad portion. - The electronic device of Supplementary Note 2, wherein the die pad portion includes a first inner side surface facing a direction intersecting a thickness direction of the base, the first inner side surface defines a portion of the opening, and the bonding layer is in contact with the first inner side surface.
- The electronic device of
Supplementary Note 3, wherein the wiring pattern includes a first conductive portion and the opening is located between the first conductive portion and the die pad portion when viewed in the thickness direction of the base. - The electronic device of Supplementary Note 4, wherein the first conductive portion includes a second inner side surface facing the first inner side surface and the bonding layer is in contact with the second inner side surface.
- The electronic device of
Supplementary Note 4 or 5, wherein the first conductive portion includes a front surface facing the thickness direction of the base and the front surface of the first conductive portion includes a contact part in contact with the bonding layer. - The electronic device of
Supplementary Note 6, wherein the surface of the first conductive portion includes an exposed part exposed from the bonding layer and the contact part is located between the exposed part and the opening when viewed in the thickness direction of the base. - The electronic device of any one of Supplementary Notes 4 to 7, wherein the first conductive portion has an annular shape surrounding the die pad portion.
- The electronic device of Supplementary Note 4, wherein the wiring pattern includes one or more second conductive portions connected to both the die pad portion and the first conductive portion, each of the one or more second conductive portions is located between the die pad portion and the first conductive portion, a part of one of the one or more second conductive portions defining the opening, and the bonding layer is in contact with the one or more second conductive portions.
- The electronic device of Supplementary Note 9, wherein each of the one or more second conductive portions extends from the die pad portion toward the first conductive portion when viewed in the thickness direction of the base and has a front surface facing the thickness direction of the base, and the front surface of each of the one or more second conductive portions is in contact with the bonding layer.
- The electronic device of Supplementary Note 10, wherein the die pad portion includes a first edge and a second edge located on opposite sides in the die pad portion when viewed in the thickness direction of the base, and a width of each of the one or more second conductive portions is smaller than a separation distance between the first edge and the second edge.
- The electronic device of any one of
Supplementary Notes 1 to 11, wherein the electronic element is an optical element or a zener diode. - The electronic device of Supplementary Note 4, further including a wire bonded to the electronic element, wherein the wiring pattern includes a wire bonding pad portion to which the wire is bonded.
- The electronic device of
Supplementary Note 13, wherein the base has a main surface and a back surface opposing each other, the electronic element is disposed on the main surface, and the wiring pattern is formed on the main surface and the back surface. - The electronic device of Supplementary Note 14, wherein the base has a first side surface and a second side surface facing a direction perpendicular to the thickness direction of the base, the first side surface and the second side surface opposing each other, wherein a first concave portion recessed from the first side surface and a second concave portion recessed from the second side surface are formed in the base, wherein the wiring pattern includes a first connecting portion, a second connecting portion, a first edge portion, a second edge portion, a first side surface portion, and a second side surface portion, wherein the first edge portion is formed on the main surface and extends along an edge of the first concave portion, wherein the second edge portion is formed on the main surface and extends along an edge of the second concave portion, wherein the first side surface portion is formed on an inner side surface of the first concave portion and is connected to the first edge portion, wherein the second side surface portion is formed on an inner side surface of the second concave portion and is connected to the second edge portion, wherein the first connecting portion is formed on the main surface, is located between the first conductive portion and the first edge portion, and is electrically connected to the first conductive portion and the first edge portion, and wherein the second connecting portion is formed on the main surface, is located between the wire bonding pad portion and the second edge portion, and is electrically connected to the wire bonding pad portion and the second edge portion.
- The electronic device of any one of
Supplementary Notes 1 to 15, further including a resin portion covering the electronic element, the wiring pattern, and the base. - The electronic device of Supplementary Note 15, further including a protective layer covering the wiring pattern, wherein the protective layer includes a portion covering the first connecting portion.
- While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.
Claims (17)
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US20130043504A1 (en) * | 2010-04-30 | 2013-02-21 | Rohm Co., Ltd. | Led module |
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JP3400958B2 (en) * | 1999-07-07 | 2003-04-28 | 株式会社シチズン電子 | Multicolor light emitting diode |
JP2003174201A (en) * | 2001-12-04 | 2003-06-20 | Rohm Co Ltd | Mounting method of led chip and mounting structure of led chip |
JP3924481B2 (en) * | 2002-03-08 | 2007-06-06 | ローム株式会社 | Semiconductor device using semiconductor chip |
US7049639B2 (en) * | 2004-05-28 | 2006-05-23 | Harvatek Corporation | LED packaging structure |
US8507940B2 (en) * | 2010-04-05 | 2013-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Heat dissipation by through silicon plugs |
JP2014216329A (en) * | 2013-04-22 | 2014-11-17 | E&E Japan株式会社 | Method of manufacturing chip led |
JP2015115432A (en) * | 2013-12-11 | 2015-06-22 | ローム株式会社 | Semiconductor device |
JP6128267B2 (en) * | 2016-06-10 | 2017-05-17 | 日亜化学工業株式会社 | Semiconductor element mounting member and semiconductor device |
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