US20180227045A9

US20180227045A9 - Modular, Expandable System for Data Reception and Distribution

Info

Publication number: US20180227045A9
Application number: US15/623,486
Authority: US
Inventors: Curtis Ling; Timothy Gallagher; Glenn Chang
Original assignee: Radioxio LLC
Current assignee: Radioxio LLC
Priority date: 2011-05-19
Filing date: 2017-06-15
Publication date: 2018-08-09
Also published as: US20170317743A1; US9391689B2; US9634754B2; US9425887B2; US9813146B2; US20180013485A1; WO2013119519A1; US10027403B2; US20150208136A1; WO2013119624A1; US20130203337A1; US20130203338A1; WO2013119699A1; US20130205350A1; US20160036516A1; US9326101B2; US20150381262A1; US8615780B2; US9654204B2; US20180323864A1

Abstract

A satellite reception assembly may comprise a first module operable to demodulate a first one or more channels of a signal output by a direct broadcast satellite (DBS) low noise block downconverter (LNB). The first module may output a signal to a second module which may demodulate a second one or more channels of the signal output by the DBS LNB. The second module may be installed after the satellite reception assembly has been deployed upon a number of clients served by the satellite reception assembly reaching a threshold.

Description

CLAIM OF PRIORITY

This patent application is a continuation of U.S. patent application Ser. No. 13/758,366 (now U.S. Pat. No. 9,078,100) which in turn makes reference to, claims priority to and claims benefit from U.S. Provisional Patent Application Ser. No. 61/595,654 entitled “Method and System for an Internet Protocol LNB (IP LNB)” and filed on Feb. 6, 2012.
Each of the above-referenced documents are hereby incorporated herein by reference in its entirety.

INCORPORATION BY REFERENCE

This patent application also makes reference to:
U.S. Pat. No. 9,055,329 entitled “System and Method in a Broadband Receiver for Efficiently Receiving and Processing Signals” filed on Dec. 14, 2011; and
United States Patent Application Publication Serial No. 2012/0163518 entitled “Method and Apparatus for Broadband Data Conversion” filed on Dec. 23, 2011; and
U.S. Pat. No. 8,611,483 entitled “Multi-Layer Time-Interleaved Analog-To-Digital Convertor (ADC)” filed on May 31, 2012.
Each of the above-referenced documents is hereby incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

Certain implementations of this disclosure relate to data reception and distribution. More specifically, certain implementations of this disclosure relate to a modular, expandable system for data reception and distribution.

BACKGROUND OF THE INVENTION

Conventional methods and systems for data reception and distribution are too expensive, inefficient, and/or inflexible. Further limitations and disadvantages of conventional methods and systems will become apparent to one of skill in the art, through comparison of such systems with some aspects of this disclosure.

BRIEF SUMMARY OF THE INVENTION

A system and/or method is provided for a modular, expandable system for data reception and distribution as illustrated by and/or described in connection with at least one of the figures, as set forth more completely in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts an example network comprising satellite television components, local area networking components, and wide area networking components.

FIG. 2A depicts example circuitry of a satellite reception assembly.

FIG. 2B depicts example circuitry of a satellite reception assembly comprising a direct conversion LNB.

FIG. 3A depicts a first example implementation of a modular, expandable satellite reception assembly.

FIG. 3B depicts a second example implementation of a modular, expandable satellite reception assembly.

FIG. 3C depicts a third example implementation of a modular, expandable satellite reception assembly.

FIG. 4 depicts a flowchart of an example process for reception and distribution signals in a modular, expandable satellite reception assembly.

FIG. 5 depicts a flowchart for configuration of a modular, expandable satellite reception assembly.

DETAILED DESCRIPTION OF THE INVENTION

As utilized herein the terms “circuits” and “circuitry” refer to physical electronic components (i.e. hardware) and any software and/or firmware (“code”) which may configure the hardware, be executed by the hardware, and or otherwise be associated with the hardware. As used herein, for example, a particular processor and memory may comprise a first “circuit” when executing a first one or more lines of code and may comprise a second “circuit” when executing a second one or more lines of code. As utilized herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. As utilized herein, the term “example” means serving as a non-limiting example, instance, or illustration. As utilized herein, the terms “e.g.,” and “for example” set off lists of one or more non-limiting examples, instances, or illustrations. As utilized herein, circuitry is “operable” to perform a function whenever the circuitry comprises the necessary hardware and code (if any is necessary) to perform the function, regardless of whether performance of the function is disabled, or not enabled, by some user-configurable setting.
FIG. 1 depicts an example network comprising satellite television components, local area networking components, and wide area networking components. As shown in FIG. 1, the system 100 comprises an example in-premises network 100, a satellite reception assembly 106 comprising a housing 122, a wide area network (WAN) 112 comprising one or more servers 124, a network link 108 connecting the dish 106 and the in-premises network 100, and a link 110 connecting the in-home network 100 and the WAN 112. The example in-home network 100 comprises a gateway 102, television 114, and a local area network (LAN) 104.
The satellite reception assembly 106 may comprise circuitry operable to receive satellite signals (e.g., K, Ka, and/or Ku band Direct Broadcast Satellite (DBS) signals), process the satellite signals to recover channels and/or information carried in the satellite signals (e.g., television channels, media content, etc.), and output the channels and/or information to the gateway 102 via the communication link 108. Example details of the satellite dish 106 reception assembly are described below with reference to FIGS. 2-5.
Each of the communication links 108 and 110 may comprise one or more wired, wireless, and/or optical links. The communication link 108 may comprise, for example, a wired (e.g., coaxial and/or twisted-pair) and/or wireless communication medium which carries physical layer symbols in accordance with, for example, Multimedia over Coax Alliance (MoCA), Ethernet, and/or DBS standards. The communication link 110 may comprise, for example, a coaxial or twisted-pair cable and/or an optical fiber which carries physical layer symbols in accordance with, for example, DSL, DOCSIS, or Ethernet standards.
The WAN 112 may comprise, for example, a DSL (or Cable Television/DOCSIS, or Fiber to the Home, or the like) headend and associated circuitry and/or devices. Such devices may include one or more servers 124 which are operable to communicate with the gateway 102.
The LAN 104 may comprise any number and/or type of client devices that communicate with the gateway 102 via link 128 using a networking protocol (e.g., Ethernet or MoCA). Examples of such devices shown include a computer 116, network attached storage 120, and a wireless access point (WAP) 118.
The client device 114 may comprise a device that communicates with the gateway 102 via one or more point-to-point media links (e.g., HDMI, Display Port, analog video links, analog video links, or the like). An example of such a device is a television.
The gateway 102 may comprise circuitry operable to receive the signals communicated over the links 108 and 110, process the signals as necessary for outputting information contained therein via one or more links 130 (e.g., an HDMI or Display Port link) and/or one or more links 128 (e.g., a MocA or Ethernet link). The gateway 102 may also comprise circuitry operable to transmit signals via the link 108 and/or via the link 110. Thus, unless otherwise indicated, the term “gateway” in this disclosure refers to a client device that performs satellite set-top box functions and WAN modem functions, where “satellite set-top box” functions are for delivering data from the satellite reception assembly 106 to devices within the premises and “WAN modem” functionality refers to communicating data between the premises 101 and the wide area network 112.
FIG. 2A depicts example circuitry of a satellite reception assembly. The circuitry comprises a low-noise block-downconverter (LNB) 250, an IF processing circuit 252, a digital processing circuit 254, and a client interface circuit 258.
The LNB 250 may comprise circuitry operable to receive RF satellite signals (e.g., K, Ka, and/or Ku Band DBS signals) via a reflector of the satellite reception assembly, filter, downconvert, and/or amplify such signals to generate corresponding IF signals (e.g., in the L-band). The LNB 250 is illustrated outputting M (an integer number) of IF signals, labeled s₁to s_M. Each of the IF signals may, for example, comprise an IF signal in the L-band (950 MHz to 2150 MHz), and may correspond to a respective satellite signal (e.g., s₁may correspond to a first polarization of a first satellite, s₂may correspond to second polarization of the first satellite, s₃may correspond to a first polarization of a second satellite, and so on).
The IF processing circuit 252 may be operable to amplify, downconvert, filter, and/or digitize at least a portion of the IF signals s₁-s_Mto generate digital signals d₁-d_N, where N is an integer. In an example implementation of this disclosure, the IF processing circuit 242 may support full-spectrum capture where an entire spectrum of each of one or more protocols of interest may be concurrently digitized. For example, the IF processing circuit 252 may comprise M analog-to-digital converters each of which can digitize the entire bandwidth of one of the signals DBS signals s₁. . . s_Mto generate a corresponding one of signals d₁. . . d_M. In such an example implementation, each of the analog-to-digital converters may be as described in U.S. patent application Ser. No. 13/485,003 and/or U.S. patent application Ser. No. 13/336,451, each of which is incorporated by reference above. In another example implementation, only a portion of one or more of the signals s₁to s_Mmay be digitized and which portions are digitized may depend on which channels in the signals s₁to s_Mare selected by client devices (e.g., which television channels are being consumed by the client(s)). The IF processing circuit 252 may be configured via one or more control signals (not shown) from the digital processing circuit 254 and/or the client interface circuit 258 which may, in turn, be based on upstream communications from one or more clients.
The digital processing circuit 254 may be operable to process the signals d₁-d_Nto recover information carried in one or more channels contained in the signals d₁-d_Nand output that information to the client interface 258 (as signal 255) and/or via the expansion interface circuit 256. An example implementation of the digital processing circuit 254 is described below with reference to FIGS. 3A-3C.
The client interface circuit 258 may be operable to process data received as signal 255 and output that information onto link 108 in a format support by one or more client devices coupled to the link 108. For example, the client interface circuit 258 may be operable to packetize and transmit data received via signal 255 in accordance with one or more networking standards (e.g., Ethernet, Multimedia over Coax Alliance (MoCA), DOCSIS, and the like) to client devices that receive satellite data using such standards. Additionally, or alternatively, the client interface circuit 258 may be operable to perform operations (e.g., digital to analog conversion, modulation, frequency conversion, etc.) for outputting the data received via signal 255 according to one or more multimedia standards (e.g., ATSC, DVB-S, ISDB-S, and the like) to client devices that receives satellite data using such standards.
FIG. 2B depicts example circuitry of a satellite reception assembly comprising a direct conversion LNB. IN FIG. 2B, a LNB 270 directly outputs the signals d₁-d_N. Accordingly, the need for the IF processing block is eliminated.
FIG. 3A depicts a first example implementation of a modular, expandable satellite reception assembly. The satellite reception assembly 106 a comprises a housing 122 in which reside the LNB 250, a first module 302, a second module 312, and an aggregation circuit 314. The housing 122 may be, for example, part of a satellite reception assembly (e.g., a DBS satellite “dish”) and may be mounted on a boom at or near the focal point of a parabolic reflector.
The two modules 302 and 312 may reside on separate substrates. For example, the module 302 may be on a first semiconductor die on a first semiconductor package and the module 312 may be on a second semiconductor die in a second semiconductor package. Additionally or alternatively, the module 302 may reside on a first printed circuit board and the module 312 may reside on a second printed circuit board. In an example implementation, the module 302 may be hard-wired (e.g., soldered) to a motherboard in the housing 302 whereas the module 310 may be mounted to the motherboard via a socket. In an example implementation, the satellite reception assembly 106 a may have been deployed (e.g., mounted to the home or office of a DBS subscriber) without the module 312, and the module 312 may have been later installed while the assembly 122 was in the field.
The module 302 comprises an instance of the IF processing circuit 252, an instance of the client interface circuit 258, and an instance of the digital processing circuit 254. The module 312 comprises an instance of the client interface circuit 258 and an instance of the digital processing circuit 254.
The IF processing circuit 252 may be as described above with reference to FIG. 2, for example.
Each instance of the client interface circuit 258 in FIG. 3A may be as described above with reference to FIG. 2, for example. As an example, each instance of the client interface circuit 258 in FIG. 3A may output packets in accordance with a suitable networking standard. Accordingly, the aggregation circuit 314 may perform packet/frame routing/switching and/or act as a host/scheduler to manage delivery of the transport stream data from the two instances of the client interface circuit 258 onto the link 108.
Each instance of the digital processing circuit 254 may comprise one or more instances of expansion interface circuit 256 (labeled 256 a, 256 b, and so on), a channelizer circuit 304, and a demodulation circuit 306.
The expansion interface circuit 256 may be operable to communicate information across a signal bus 308 in accordance with one or more standards such as reduced gigabit media independent interface (RGMII), a communication standard or protocol operating at 60 GHz, Thunderbolt, or other suitable standard or protocol. In the example implementation depicted in FIG. 3A, one or more of the signals d₁. . . d_Nare output by module 302 via the expansion interface circuit 256 a. In module 312, signals received via expansion interface circuit 256 b are output via expansion interface circuit 256 c. In this manner, multiple modules 312 may be installed in the housing 122 in a daisy-chain-connected fashion. In another implementation, additional and/or alternative signals (e.g., selected channels output by the channelizer 304) may be communicated between modules 302 and 312 via the expansion interface circuits 256.
The channelizer circuit 304 may be operable to process the digitized signals d₁-d_N(e.g., decimate and filter such signals) such that it outputs the one or more channels of the digitized signals d₁-d_Mthat have been selected for consumption by a client device. In this regard, the channelizer 304 may, for example, serve as a crossbar for selecting a set of desired channels from among a plurality of channels available from one or more broadband sources. In an example full-spectrum capture implementation, N may be equal to 4, with signals d₁corresponding polarization one of satellite one, d₂corresponding to polarization two of satellite one, d₃corresponding to polarization one of satellite two, and d₄corresponding to polarization two of satellite two. In such an example, the channelizer 304 may select any arbitrary N (an integer) channels from among all channels carried by the two satellites. The number of channels the channelizer 304 is operable to select may be limited by size, power, and/or cost constraints. In an example implementation, channelizer 304 of module 302 may be operable to select N channels and channelizer 304 of module 312 may be operable to select M channels where N and M are integers which may or may not be equal.
The demodulation circuit 306 may comprise be operable to demodulate one or more of the selected channels output by the channelizer circuit 304 to recover one or more transport streams (e.g., MPEG transport streams) from the selected one or more channels. The demodulation circuit 306 may support any suitable modulation standards such as, for example, DVB-S and/or ISDB-S.
In another example implementation, the digital processing circuit 254 may comprise additional components such as, for example, a forward error correction circuit and/or packet id (PID) filter. By performing forward error correction and/or PID filtering in the satellite reception assembly 106 a, the amount of bandwidth needed on the link 108 for transmitting a received channel, for example, may be reduced by elimination of redundant data, parity bits, etc.
In another example implementation, the module 302 may interface to the direct conversion LNB 270. In such an implementation, the IF processing module 252 may not be populated in the module 302 and/or may be populated but bypassed.
FIG. 3B depicts a second example implementation of a modular, expandable satellite reception assembly. The satellite reception assembly 106 b comprises a housing 122 in which reside the LNB 250, a first module 322, a second module 324, and an aggregation circuit 356. The housing 122 may be, for example, part of a satellite reception assembly (e.g., a DBS satellite “dish”) and may be mounted on a boom at or near the focal point of a parabolic reflector.
The two modules 322 and 324 may be similar to the modules 302 and 312 of FIG. 3A, but may comprise instances of digital processing circuit 326 that, unlike digital processing circuit 254, does not comprise a demodulator. Consequently, the modules 322 and 324 may output selected channels without demodulating them. Accordingly, the aggregation circuit 356 may perform time and/or frequency division multiplexing in order combine the channels output from the various instances of client interface 256 onto the link 108. In an implementation using frequency division multiplexing on the link 108, the frequencies at which the client interface circuits 256 in FIG. 3B output the selected channels may be different (e.g., hard-coded differently, configured differently during installation of the module 324, and/or configurable during run-time) such that the aggregation circuit 356 may not be unnecessary.
In another example implementation, the module 302 may interface to the direct conversion LNB 270. In such an implementation, the IF processing module 252 may not be populated in the module 302 and/or may be populated but bypassed.
FIG. 3C depicts a third example implementation of a modular, expandable satellite reception assembly. The satellite reception assembly 106 c comprises a housing 122 in which reside the LNB 250, an instance of the module 322, an instance of the module 324, and an aggregation circuit 356. The housing 122 may be, for example, part of a satellite reception assembly (e.g., a DBS satellite “dish”) and may be mounted on a boom at or near the focal point of a parabolic reflector.
The module 322 may be as described with reference to FIG. 3B, and the module 312 may be as described with reference to FIG. 3A. As a result, the module 322 may output selected modulated channels while the module 312 may output packetized transport streams and the aggregation circuit 346 may be operable to combine the different types of outputs onto the link 108. For example, where the module 312 outputs Ethernet physical layer signals, the aggregation circuit may upconvert signals from the module 322 to frequencies above the band used for the Ethernet physical layer signals (e.g., 125 MHz). As another example, where the module 312 uses MoCA, the channels output by the module 322 may be output on the link 108 at frequencies below the MoCA band.
In another example implementation, the module 322 may interface to the direct conversion LNB 270. In such an implementation, the IF processing module 252 may not be populated in the module 302 and/or may be populated but bypassed.
FIG. 4 depicts a flowchart of an example process for reception and distribution signals in a modular, expandable satellite reception assembly. The flowchart of FIG. 4 may correspond to the example implementation in FIG. 3A, for example. In block 402, a satellite signal (e.g., Ka or Ku band DBS signal) is received at the LNB 250 via a reflector and a feedhorn of the satellite reception assembly 106. In block 404, the LNB downconverts the received signal to an IF signal (e.g., L-band signal). In block 406, the IF processing circuit 252 digitizes the IF signal from the LNB. In block 408, the digitized IF signal is conveyed to a plurality of instances of the channelizer 304, where one or more of the instances may be reached via an expansion interface circuit 256 and corresponding signal bus 308. In block 410, each instance of the channelizer 304 selects one or more channel from among the plurality of channels carried in the digitized IF signal. Which one or more channels are selected may be determined based on which channels/programs are being consumed by client devices served by the corresponding instance of channelizer 304. In block 412, the selected channels from each instance of the channelizer 304 are demodulated by a corresponding instance of demodulation circuit 306 to recover one or more transport streams. In block 414, the transport streams are packetized and transmitted by the instances of the client interface circuits 258. In block 416, the packet streams are aggregated onto the link 108 by the aggregation circuit 314. In block 418, the packet streams arrive at client devices which decapsulate the packets to recover the transport stream data.
FIG. 5 depicts a flowchart for configuration of a modular, expandable satellite reception assembly. In block 502, a DBS satellite reception assembly 106 is installed at a customer premises (e.g., a DBS subscriber's home or office). At the time of installation, the satellite reception assembly 106 supports up to N clients (e.g., it has circuitry for demodulating N channels). In block 504, additional client devices are installed at the premises such that the total number of clients to be served by the satellite reception assembly exceeds N. In block 506 an aggregation circuit is installed (if necessary). In block 508 a module (e.g., module 312 or 324) in installed in the satellite reception assembly 106 while the satellite reception assembly remained in the field (i.e., remains installed at the subscriber's premises). In one embodiment, the module may be hot-swappable. The satellite reception assembly 106 may then begin distributing satellite data to up to N+M clients. In step 510, when the number of clients being served by the satellite reception assembly 106 approaches or exceeds N+i*M, where i is the number of additional modules 312 or 324 installed, the process may return to block 508 and an additional module 312 or 324 may be installed.
Other embodiments of the invention may provide a non-transitory computer readable medium and/or storage medium, and/or a non-transitory machine readable medium and/or storage medium, having stored thereon, a machine code and/or a computer program having at least one code section executable by a machine and/or a computer, thereby causing the machine and/or computer to perform the steps as described herein.
Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention may be realized in a centralized fashion in at least one computing system, or in a distributed fashion where different elements are spread across several interconnected computing systems. Any kind of computing system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computing system with a program or other code that, when being loaded and executed, controls the computing system such that it carries out the methods described herein. Another typical implementation may comprise an application specific integrated circuit or chip.
The present invention may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form.
While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.

Claims

What is claimed is:

1-20. (canceled)

21. A system comprising:

an analog-to-digital converter circuit configured to digitize each of a plurality of down-converted satellite signals to generate a plurality of digitized satellite signals, each of the plurality of down-converted satellite signals comprising a plurality of channels;

a channelization circuit configured to select one or more of the channels for output via a first interface; and

an expansion interface configured to output one or more of the digitized satellite signals via a second interface.

22. The system of claim 21, comprising a device configured to receive the one or more of the digitized satellite signals from the second interface.

23. The system of claim 22, wherein the device comprises a channelization circuit configured to select one or more of the channels for output.

24. The system of claim 23, wherein the device comprises an expansion interface configured to output one or more of the digitized satellite signals.

25. The system of claim 22, wherein the analog-to-digital converter circuit resides on a first semiconductor die and the device resides on a second semiconductor die.

26. The system of claim 22, wherein the device resides in a socket on a printed circuit board such that the device is field replaceable.

27. The system of claim 22, wherein the analog-to-digital converter circuit and the device reside in a shared housing along with a low noise block down-converter that outputs the down-converted satellite signals.

28. The system of claim 21, wherein each of the down-converted satellite signals corresponds to a respective one of a plurality of polarizations of a respective one of a plurality of satellites.

29. The system of claim 21, comprising aggregation circuitry configured to receive the one or more of the channels output via the first interface and the one or more of the channels output via the device.

30. The system of claim 29, wherein the aggregation circuitry is configured to perform time division multiplexing and/or frequency division multiplexing of the one or more of the channels output via the first interface and the one or more of the channels output via the device onto a link to a client device.

31. A method comprising:

in first circuitry:

digitizing, via analog-to-digital conversion circuitry, each of a plurality of down-converted satellite signals to generate a plurality of digitized satellite signals, each of the plurality of down-converted satellite signals comprising a plurality of channels;

selecting, by channelization and client interface circuitry, one or more of the channels for output via a first interface of the first circuitry;

outputting, via expansion interface circuitry, one or more of the digitized satellite signals via a second interface of the first circuitry.

32. The method of claim 31, comprising receiving, in second circuitry, the one or more of the digitized satellite signals from the second interface of the first circuitry via a second interface of the second circuitry.

33. The method of claim 31, comprising selecting, by channelization and client interface circuitry of the second circuitry, one or more of the channels for output via a first interface of the second circuitry.

34. The method of claim 33, comprising outputting, by expansion interface circuitry of the second circuitry, one or more of the digitized satellite signals via a third interface of the second circuitry.

35. The method of claim 32, wherein the first circuitry resides on a first semiconductor die and the second circuitry resides on a second semiconductor die.

36. The method of claim 32, wherein the second circuitry resides in a socket on a printed circuit board such that the second circuitry is field replaceable.

37. The method of claim 22, wherein the first circuitry and the second circuitry reside in a shared housing along with a low noise block down-converter that outputs the down-converted satellite signals.

38. The method of claim 21, wherein each of the down-converted satellite signals corresponds to a respective one of a plurality of polarizations of a respective one of a plurality of satellites.

39. The method of claim 21, comprising receiving, in aggregation circuitry, the one or more channels output via the first interface of the first circuitry and the one or more of the channels output via the first interface of the second circuitry.

40. The method of claim 29, comprising time division multiplexing and/or frequency division multiplexing, by the aggregation circuitry, the one or more of the channels output via the first interface of the first circuitry and the one or more of the channels output via the first interface of the second circuitry onto a link to a client device.