US20180219092A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- US20180219092A1 US20180219092A1 US15/879,753 US201815879753A US2018219092A1 US 20180219092 A1 US20180219092 A1 US 20180219092A1 US 201815879753 A US201815879753 A US 201815879753A US 2018219092 A1 US2018219092 A1 US 2018219092A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 159
- 230000002093 peripheral effect Effects 0.000 claims abstract description 108
- 210000000746 body region Anatomy 0.000 claims abstract description 76
- 239000012535 impurity Substances 0.000 claims description 44
- 239000000758 substrate Substances 0.000 claims description 26
- 239000000969 carrier Substances 0.000 claims description 22
- 239000002245 particle Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000009751 slip forming Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 228
- 239000011229 interlayer Substances 0.000 description 15
- 238000011084 recovery Methods 0.000 description 14
- 238000004088 simulation Methods 0.000 description 11
- 230000003071 parasitic effect Effects 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 230000006798 recombination Effects 0.000 description 5
- 238000005215 recombination Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000010894 electron beam technology Methods 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000005192 partition Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000009623 Bosch process Methods 0.000 description 2
- 229910018503 SF6 Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000005352 clarification Methods 0.000 description 2
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- 230000010355 oscillation Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 241000237509 Patinopecten sp. Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 150000002371 helium Chemical class 0.000 description 1
- 239000003097 hole (electron) Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- BCCOBQSFUDVTJQ-UHFFFAOYSA-N octafluorocyclobutane Chemical compound FC1(F)C(F)(F)C(F)(F)C1(F)F BCCOBQSFUDVTJQ-UHFFFAOYSA-N 0.000 description 1
- 235000019407 octafluorocyclobutane Nutrition 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 235000020637 scallop Nutrition 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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Abstract
Description
- The present application corresponds to Japanese Patent Application No. 2017-13381 filed with the Japan Patent Office on Jan. 27, 2017, and the entire disclosure of the application is incorporated herein by reference.
- The present invention relates to a semiconductor device that has a superjunction structure.
- Patent Document 1 (PCT International Application Publication No. 2010/024433) discloses a semiconductor device that includes a first base layer, a drain layer disposed at a rear surface of the first base layer, a second base layer formed at a front surface of the first base layer, a source layer formed at a front surface of the second base layer, a gate insulating film disposed on a front surface of the source layer and on the front surface of the second base layer, a gate electrode disposed on the gate insulating film, a column layer formed so as to face the drain layer in the first base layer under the second base layer and the source layer, a drain electrode disposed at the drain layer, and a source electrode disposed at the source layer and at the second base layer, in which the column layer is subjected to heavy-particle irradiation, so that a trap level is locally formed.
- According to the invention of
Patent Document 1, carriers are trapped by the trap level formed below the column layer. The reverse recovery time trr of the semiconductor device is intended to be shortened by the trapping, and yet there is still scope for improvement. For example, although a trap level is formed in a region directly under the column layer in the invention ofPatent Document 1, it is possible to recombine even more carriers together at a trap level if a region in which many carriers are distributed when the semiconductor device is turned off is ascertained and if the trap level is formed in this region. - An object of the present invention is to provide a semiconductor device that is capable of controlling electric characteristics so that an electric current preferentially flows to an outer peripheral portion when the semiconductor device is turned off.
- Another object of the present invention is to provide a semiconductor device that is capable of making a reverse recovery time trr shorter than in the past.
-
FIG. 1 is a schematic plan view of a semiconductor device according to a preferred embodiment of the present invention. -
FIG. 2 is a perspective cross-sectional view of a part surrounded by a broken line II of the semiconductor device ofFIG. 1 . -
FIG. 3 is a cross-sectional view that appears when the semiconductor device is cut along line ofFIG. 1 . -
FIG. 4A toFIG. 4D are views showing a manufacturing process of the semiconductor device ofFIG. 3 . -
FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a preferred embodiment of the present invention. -
FIG. 6A toFIG. 6E are views showing a manufacturing process of the semiconductor device ofFIG. 5 . -
FIG. 7 is a schematic cross-sectional view of a semiconductor device according to a preferred embodiment of the present invention. -
FIG. 8 is a schematic cross-sectional perspective view of a semiconductor device according to a preferred embodiment of the present invention. -
FIG. 9A andFIG. 9B are views that show current waveforms when the semiconductor device is turned off and that show current waveforms of an electric current flowing to a source region and current waveforms of an electric current flowing to a column layer, respectively. -
FIG. 10A andFIG. 10B are views that show current waveforms when the semiconductor device is turned off and that show current waveforms of an electric current flowing to a source region and current waveforms of an electric current flowing to a column layer, respectively. -
FIG. 11A andFIG. 11B are views that show current waveforms when the semiconductor device is turned off and that show current waveforms of an electric current flowing to a source region and current waveforms of an electric current flowing to a column layer, respectively. -
FIG. 12A andFIG. 12B are views that show current waveforms when the semiconductor device is turned off and that show current waveforms of an electric current flowing to a source region and current waveforms of an electric current flowing to a column layer, respectively. -
FIG. 13A toFIG. 13C are schematic views of a semiconductor device used in 3D simulations. -
FIG. 14 is a view showing waveforms of results of the 3D simulations. - A semiconductor device according to a preferred embodiment of the present invention includes a first conductivity type semiconductor layer including an active cell portion and an outer peripheral portion around the active cell portion, a second conductivity type body region selectively formed at a surface portion of the semiconductor layer in the active cell portion, a first conductivity type source region formed at an inner part of the body region, a gate electrode that faces a part of the body region through a gate insulating film, a second conductivity type column layer straddling a boundary between the active cell portion and the outer peripheral portion inside the semiconductor layer such that the column layer is disposed at a lower part of the body region in the active cell portion, a source electrode that is electrically connected to the source region, and an outer peripheral electrode that is electrically connected to the column layer in the outer peripheral portion.
- According to this arrangement, in the outer peripheral portion, the column layer is connected to the outer peripheral electrode that is independent of the source electrode. This makes it possible to allow an electric current to preferentially flow to the outer peripheral portion by applying an appropriate voltage to the outer peripheral electrode when the semiconductor device is turned off. Although, normally, a reverse current flows to the source-drain path of the active cell portion by turning off the semiconductor device, it is possible to control the current so that a part of or all of the current flows to the outer peripheral portion. Therefore, it is possible to distribute even more carriers moving through the semiconductor layer in the outer peripheral portion than in the active cell portion when the semiconductor device is turned off.
- Therefore, preferably, the semiconductor device according to the preferred embodiment of the present invention additionally includes a carrier obstructing portion being in contact with the column layer in the outer peripheral portion. The carrier obstructing portion may be capable of trapping and reducing carriers in the column layer.
- According to this arrangement, the carrier obstructing portion is formed in the outer peripheral portion in which many carriers are distributed, and therefore it is possible to facilitate a recombination of carriers. As a result, it is possible to make a reverse recovery time trr shorter than before.
- In the semiconductor device according to the preferred embodiment of the present invention, the carrier obstructing portion may include a trap level region disposed in the semiconductor layer. In this case, the trap level region may include heavy particles that include any one of protons, 3He++, and 4He++.
- If the semiconductor device according to the preferred embodiment of the present invention additionally includes a deep trench that is formed adjacently to the column layer and that has a side surface from which the column layer is exposed, the carrier obstructing portion may include a minute concavo-convex portion formed at an exposed part of the column layer in the side surface of the deep trench. In this case, the semiconductor device according to the preferred embodiment of the present invention may additionally include an embedded insulating film that is formed in the deep trench.
- In the semiconductor device according to the preferred embodiment of the present invention, the column layer may include a separated column separated from the body region in the active cell portion.
- In the semiconductor device according to the preferred embodiment of the present invention, the column layer may include a continuous column that is continuously formed downwardly from the body region in the active cell portion.
- In the semiconductor device according to the preferred embodiment of the present invention, the body region may include a plurality of body regions that extend in a stripe shape with intervals from each other.
- If the semiconductor device according to the preferred embodiment of the present invention additionally includes a gate finger that surrounds the source electrode, the outer peripheral electrode may surround the gate finger.
- If the semiconductor device according to the preferred embodiment of the present invention additionally includes a contact layer that extends from the column layer toward a front surface side of the semiconductor layer in the outer peripheral portion and that is formed of a semiconductor impurity region exposed to a front surface of the semiconductor layer, the outer peripheral electrode may be connected to the contact layer in the front surface of the semiconductor layer.
- If the semiconductor device according to the preferred embodiment of the present invention additionally includes an embedded contact member that is embedded from a front surface of the semiconductor layer to a depth position below the body region in the outer peripheral portion and that is connected to the column layer at the depth position, the outer peripheral electrode may be connected to the embedded contact member in the front surface of the semiconductor layer.
- In the semiconductor device according to the preferred embodiment of the present invention, the semiconductor layer may include a silicon substrate.
- Preferred embodiments of the present invention will be hereinafter described in detail with reference to the accompanying drawings.
-
FIG. 1 is a schematic plan view of asemiconductor device 1 according to a preferred embodiment of the present invention. For clarification,electrode films 5 to 8 are shown by hatching inFIG. 1 . - The
semiconductor device 1 includes asemiconductor substrate 2 formed in a quadrangular shape in a plan view. A length L1 in a first direction of the semiconductor substrate 2 (i.e., length alongside surfaces 2A and 2C of thesemiconductor substrate 2 inFIG. 1 ) may be, for example, 1.0 mm to 9.0 mm, and a length L2 in a second direction perpendicular to the first direction (i.e., length alongside surfaces semiconductor substrate 2 inFIG. 1 ) may be, for example, 1.0 mm to 9.0 mm. - The
semiconductor substrate 2 includes anactive cell portion 3 in its central area in a plan view. Theactive cell portion 3 is a region in which aunit cell 29 described later is chiefly formed, and is a region in which an electric current flows in the thickness direction of thesemiconductor substrate 2 when a source-drain path of thesemiconductor device 1 is in an electrically conductive state (when turned on). Thesemiconductor substrate 2 additionally includes an outerperipheral portion 4 around theactive cell portion 3. - The
semiconductor device 1 includes asource electrode film 5 formed on theactive cell portion 3 and agate electrode film 6, an outerperipheral electrode film 7, and anequipotential ring film 8 that are formed on the outerperipheral portion 4. These electrode films are separated from each other by the patterning of a shared electrode film. - The
source electrode film 5 is formed in a substantially quadrangular shape in a plan view such that a greater part of theactive cell portion 3 is covered therewith. For-padconcave portions source electrode film 5 are respectively formed at a pair of side portions facing each other of the source electrode film 5 (inFIG. 1 , aside portion closer to aside surface 2A of thesemiconductor substrate 2 and a side portion closer to a side surface 2C thereof). The for-padconcave portions peripheral pad 17 and agate pad 12 described later. In comparison between the for-padconcave portions concave portion 9 for the outerperipheral pad 17 is formed more widely than theconcave portion 10 for thegate pad 12. - The
source electrode film 5 is selectively covered with a surface protection film 48 (seeFIG. 3 ), and its part is exposed to serve as asource pad 11. A joint member, such as a bonding wire, is connected to thesource pad 11. - The
gate electrode film 6 includes thegate pad 12 and agate finger 13. - The
gate pad 12 is a part of thegate electrode film 6 covered with the surface protection film 48 (seeFIG. 3 ), and this part is selectively exposed from thesurface protection film 48. A joint member, such as a bonding wire, is connected to thegate pad 12. Thegate pad 12 is selectively disposed on the side of one of a pair of side surfaces (theside surface 2A and the side surface 2C inFIG. 1 ) that face each other of thesemiconductor substrate 2. In the present preferred embodiment, thegate pad 12 is disposed such that thegate pad 12 overlaps with an inner region of the for-padconcave portion 10 in a plan view, and is interposed with intervals between a pair of projectingportions source electrode film 5 that partition side portions of the for-padconcave portion 10 from both sides. - The
gate finger 13 is formed linearly along the side surfaces 2A to 2D of thesemiconductor substrate 2 from thegate pad 12. In the present preferred embodiment, thegate finger 13 is formed in a closed ring shape that surrounds thesource electrode film 5. A part (part closer to theside surface 2A of the semiconductor substrate 2) of thegate finger 13 that faces thegate pad 12 is formed such that one side and the other side in its width direction extend along the for-padconcave portion 9 in a plan view. Consequently, a fingerconcave portion 15 partitioned by a part of thegate finger 13 is formed at the for-padconcave portion 9. In the present preferred embodiment, the fingerconcave portion 15 is interposed with intervals between a pair of projectingportions source electrode film 5 that partition side portions of the for-padconcave portion 9 from both sides in a plan view. Thegate finger 13 is not necessarily required to be formed in a closed ring shape, and it may be formed in a shape whose part is opened. For example, thegate finger 13 may be formed in a shape, in which a side opposite to thegate pad 12 is opened, following an outerperipheral finger 18 described later. Additionally, thegate finger 13 is covered with the surface protection film 48 (seeFIG. 3 ). - The outer
peripheral electrode film 7 includes the outerperipheral pad 17 and the outerperipheral finger 18. - The outer
peripheral pad 17 is a part of the outerperipheral electrode film 7 covered with the surface protection film 48 (seeFIG. 3 ), and this part is selectively exposed from thesurface protection film 48. A joint member, such as a bonding wire, is connected to the outerperipheral pad 17. The outerperipheral pad 17 is selectively disposed on the side of one of the pair of side surfaces (theside surface 2A and the side surface 2C inFIG. 1 ) that face each other of thesemiconductor substrate 2. In the present preferred embodiment, the outerperipheral pad 17 is disposed on the side opposite to thegate pad 12 in a plan view, and is provided such that the outerperipheral pad 17 overlaps with an inner region of the fingerconcave portion 15. Consequently, the outerperipheral pad 17 is interposed with intervals between a pair of projectingportions gate finger 13 that partition side portions of the fingerconcave portion 15 from both sides. Unlike the relationship between thegate pad 12 and the for-padconcave portion 10, the outerperipheral pad 17 is not disposed such that the outerperipheral pad 17 overlaps with an inner region of the for-padconcave portion 9 inFIG. 1 . However, for example, in a mode in which the for-pad concave-portion-9 side of thegate finger 13 is opened, the for-padconcave portion 9 may be substantially equal in width to the for-padconcave portion 10, and the outerperipheral pad 17 may be overlapped with the inner region of the for-padconcave portion 9. - The outer
peripheral finger 18 is formed linearly along side surfaces of the semiconductor substrate 2 (inFIG. 1 , side surfaces 2A, 2B, and 2D) from the outerperipheral pad 17. In the present preferred embodiment, the outerperipheral finger 18 is formed in a shape that surrounds thesource electrode film 5 and thegate electrode film 6 and in which a side opposite to the outerperipheral pad 17 is opened. The outerperipheral finger 18 may be formed in a closed ring shape that completely surrounds thesource electrode film 5 and thegate electrode film 6. Additionally, the outerperipheral finger 18 may be equal in width to thegate finger 13 and may be disposed in parallel to thegate finger 13 with an interval therebetween. The outerperipheral finger 18 is covered with the surface protection film 48 (seeFIG. 3 ). - The
equipotential ring film 8 is formed in a closed ring shape that surrounds thesource electrode film 5, thegate electrode film 6, and the outerperipheral electrode film 7. Theequipotential ring film 8 may be formed such that theequipotential ring film 8 is smaller in width than thegate finger 13 and than the outerperipheral finger 18. Theequipotential ring film 8 is covered with the surface protection film 48 (seeFIG. 3 ). -
FIG. 2 is a perspective cross-sectional view of a part surrounded by a broken line II of thesemiconductor device 1 ofFIG. 1 .FIG. 3 is a cross-sectional view that appears when thesemiconductor device 1 is cut along line ofFIG. 1 . InFIG. 2 , an arrangement on aninterlayer insulating film 43 is excluded. - The
semiconductor device 1 is an n channel type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that has a superjunction structure. - The
semiconductor device 1 includes an n+type drain layer 20, an ntype base layer 21, a ptype body region 22, a p−type column layer 23, an n+type source region 24, a p+ typebody contact region 25, agate insulating film 26, agate electrode 27, and adrain electrode 28. Thesemiconductor substrate 2 ofFIG. 1 may have a concept in which the n+type drain layer 20 and the n−type base layer 21 are combined together. - The n+
type drain layer 20 may be formed of an n+ type semiconductor substrate (for example, silicon substrate). Besides, it may be a substrate, such as a SiC substrate or a GaN substrate, that is generally employed in a transistor. The n+ type semiconductor substrate may be a semiconductor substrate that is subjected to crystal growth while being doped with an n type impurity. P (phosphorus), As (arsenic), and SB (antimony), etc., are applicable as the n type impurity. The impurity concentration of the n+type drain layer 20 is, for example, about 1.0×1018cm−3 to 5.0×1020cm−3. - The n−
type base layer 21 is a semiconductor layer into which an n type impurity is implanted. More specifically, it may be an n type epitaxial layer that is epitaxially grown while implanting an n type impurity on the n+type drain layer 20. The aforementioned one is applicable as the n type impurity. The impurity concentration of the n−type base layer 21 is lower than that of the n+type drain layer 20, and is, for example, about 1.0×1010 cm−3 to 1.0×1016cm−3. - The p
type body region 22 is a semiconductor layer into which a p type impurity is implanted. More specifically, it may be a semiconductor layer formed by performing the ion implantation (or, simply, implantation) of a p type impurity into the ntype base layer 21. B (boron), Al (aluminum), Ga (gallium), etc., are applicable as the p type impurity. The impurity concentration of the ptype body region 22 is, for example, about 1.0×1015cm−3 to 1.0×1019cm−3. - The p
type body region 22 is selectively formed at a surface portion of the n−type base layer 21. In the present preferred embodiment, as shown inFIG. 2 , the plurality of ptype body regions 22 are parallel to each other in a stripe shape, and extend in a direction, for example, along the side surfaces 2B and 2D of the semiconductor substrate 2 (seeFIG. 1 ). The plurality of ptype body regions 22 may be arranged in a matrix manner in the surface portion of the n−type base layer 21. The width of each of the ptype body regions 22 is, for example, 3 μm to 10 μm. A region including each of the ptype body regions 22 and the n−type base layer 21 therearound forms aunit cell 29. In other words, thesemiconductor device 1 has many (a plurality of)unit cells 29 arranged in a striped manner in a plan view in the layout ofFIG. 2 . - Additionally, each of the p
type body regions 22 straddles a boundary between theactive cell portion 3 and the outerperipheral portion 4 as shown inFIG. 3 . Anend portion 36 in the outerperipheral portion 4 of each of the ptype body regions 22 is disposed at a position with an interval inwardly with respect to theside surface 2A of thesemiconductor substrate 2, and a region between theend portion 36 and theside surface 2A is a region of the n−type base layer 21. Additionally, each of the ptype body regions 22 forms a parasitic diode (body diode) 34 at an interface (pn junction surface) with the n−type base layer 21 as shown inFIG. 2 . - The p−
type column layer 23 may be a semiconductor layer formed by performing the ion implantation (or, simply, implantation) of a p type impurity into the n−type base layer 21. The aforementioned one is applicable as the p type impurity. The impurity concentration of the p−type column layer 23 is lower than that of thetype body region 22, and is, for example, about 1.0×1015cm−3 to 1.0×1019cm−3. - As shown in
FIG. 2 , the p−type column layer 23 is formed in an inner region of the ptype body region 22 of each of theunit cells 29. More specifically, the ptype column layer 23 is formed in a stripe shape in a region of the center in the width direction of the ptype body region 22. - In the present preferred embodiment, the p−
type column layer 23 includes a separatedcolumn 30 formed with an interval below the ptype body region 22 in theactive cell portion 3. Consequently, an n−type interrupting region 31 formed of a part of the n−type base layer 21 is formed between the ptype body region 22 and the separatedcolumn 30. The interval of the interrupting region 31 (i.e., distance between a lower end of the ptype body region 22 and an upper end of the separated column 30) may be, for example, 0.5 μm to 5.0 μm. - As shown in
FIG. 3 , the p−type column layer 23 straddles a boundary between theactive cell portion 3 and the outerperipheral portion 4 in a lower part of the ptype body region 22. Consequently, the p−type column layer 23 additionally includes, in the outerperipheral portion 4, a drawnportion 32 that is formed of an extension portion of the separatedcolumn 30 and that is drawn outwardly from theend portion 36 in the outerperipheral portion 4 of the p type body region 22 (i.e., toward the side-surface-2A side). - A p−
type contact layer 33 that extends toward the front-surface side of the n−type base layer 21 from the drawnportion 32 and that is exposed to the front surface of the n−type base layer 21 is formed. The p−type contact layer 33 may be a semiconductor layer formed by performing the ion implantation (or, simply, implantation) of a p type impurity into the n−type base layer 21. The aforementioned one is applicable as the p type impurity. The impurity concentration of the p−type contact layer 33 is, for example, about 1.0×1015cm−3 to 1.0×1019cm−3 as in the p−type column layer 23. - The p−
type contact layer 33 extends in the thickness direction of the ntype base layer 21 at a position with an interval from theend portion 36 of the ptype body region 22. In other words, plainly speaking, a p type impurity region, in which the p−type column layer 23 and the p−type contact layer 33 are formed integrally with each other, is formed such that the p type impurity region comes around from a lateral part of the ptype body region 22 from the lower part thereof in the outerperipheral portion 4. The p type impurity region is separated from the ptype body region 22 by means of the n−type base layer 21 in both of the lower part and the lateral part of the ptype body region 22. Consequently, the ptype body region 22, the n−type base layer 21, and the p−type contact layer 33 are aligned in this order in a direction along the front surface of the ntype base layer 21, and, as a result, a pnp structure is formed. - Additionally, side surfaces extending in the depth direction of the n−
type base layer 21 of the p−type column layer 23 and of the p−type contact layer 33 are each formed as a concavo-convex surface that periodically undulates in the depth direction. Normally, the number of concaves and convexes of the concavo-convex surface is substantially equal to the number of steps of an n type semiconductor layer 51 (FIG. 4A ) described later. For clarification, the p−type column layer 23 from which the concavo-convex surface has been excluded is shown inFIG. 2 . - As shown in
FIG. 3 , atrap level region 38 is formed in the outerperipheral portion 4 of the n−type base layer 21. Thetrap level region 38 is a region formed by radiating heavy particles or electron beams from the rear-surface side of the ntype base layer 21. Many recombination centers that allow carriers to disappear by being trapped and recombined together exist in thetrap level region 38. - The
trap level region 38 is locally formed such that thetrap level region 38 spreads in a thin manner (for example, with a thickness of about 1 μm to 3 μm) at a predetermined depth position from a rear surface of the n+type drain layer 20 in the n−type base layer 21. For example, thetrap level region 38 may be formed in an upper region of the p−type column layer 23. Besides, thetrap level region 38 may be replaced by atrap level region 381 formed in a central region of the p−type column layer 23, by atrap level region 382 formed in a lower region of the ptype column layer 23, and by atrap level region 383 formed in a part of the n−type base layer 21 below the p−type column layer 23. Preferably, thetrap level region 38 is formed in the upper region of the p−type column layer 23 from the viewpoint of efficiently trapping carriers (positive holes) flowing toward the outerperipheral electrode film 7 that is placed above the p−type column layer 23, and, more preferably, thetrap level region 38 is overlapped with aconnection portion 39 between the p type column layer 23 (drawn portion 32) and the ptype contact layer 33 as shown inFIG. 3 . Carriers that flow toward the outerperipheral electrode film 7 necessarily pass through theconnection portion 39, and therefore it is possible to improve the trap efficiency of carriers by forming thetrap level region 38 at that position. - In order to form the
trap level region 38, it is possible to apply heavy-particle irradiation that uses heavy particles, such as protons, 3He++, or 4He++, and electron-beam irradiation. Particularly, it is preferable to use a helium nucleus (3He++ or 4He++) having large mass because it is capable of narrowing a distribution region in the thickness direction of recombination centers and is capable of locally distributing recombination centers in a narrow range with respect to the thickness direction. - The n+
type source region 24 is formed in an inner region of the ptype body region 22 of each of theunit cells 29. In this region, the n+type source region 24 is selectively formed at a surface portion of the ptype body region 22. The n+type source region 24 may be formed by selectively applying the ion implantation of an n type impurity into the ptype body region 22. Examples of the n type impurity are as mentioned above. The impurity concentration of the n+type source region 24 is higher than that of the n− type base layers 21, and is, for example, about 1.0×1018cm−3 to 5.0×1020cm−3. - The n+
type source region 24 is formed in the ptype body region 22 such that the n+type source region 24 is positioned at a predetermined distance inwardly from a peripheral edge of the p type body region 22 (an interface between the ptype body region 22 and the n− type base layer 21). Consequently, in a surface layer region of the semiconductor layer including the n−type base layer 21, the ptype body region 22, etc., a surface portion of the ptype body region 22 is interposed between the n+type source region 24 and the n−type base layer 21, and the surface portion interposed therebetween provides achannel region 35. - In the present preferred embodiment, the n+
type source region 24 is formed in a stripe shape, and is formed in a region outside a side surface of the p−type column layer 23. Thechannel region 35 has a stripe shape in accordance with the shape of the n+type source region 24. - The p− type
body contact region 25 is formed in a region directly on the p−type column layer 23. In this region, the p+ typebody contact region 25 is selectively formed at the surface portion of the ptype body region 22. The p− typebody contact region 25 may be formed by selectively applying the ion implantation of a p type impurity into the ptype body region 22. Examples of the p type impurity are as mentioned above. The impurity concentration of the p+ typebody contact region 25 is higher than that of the ptype body region 22, and is, for example, about 5.0×1017cm−3 to 1.0×1019cm−3. - The p| type
body contact region 25 passes through the n+type source region 24, and extends to a halfway position of the ptype body region 22 toward the n+type drain layer 20. - In the present preferred embodiment, the p+ type
body contact region 25 is formed in a stripe shape. As shown inFIG. 3 , anend portion 37 of each p+ typebody contact region 25 is disposed in theactive cell portion 3, and is disposed at a position with an interval inwardly with respect to theend portion 36 of the ptype body region 22. Consequently, a region between theend portion 37 and theend portion 36 of the ptype body region 22 becomes a region of the ptype body region 22. - Additionally, as shown in
FIG. 3 , an end-surface-sidep type region 42 that is exposed to an end surface (side surface of the semiconductor substrate 2) of the n−type base layer 21 and to the front surface of the n−type base layer 21 is formed at the surface portion of the n−type base layer 21. The end-surface-sidep type region 42 is formed through the same process as that of the ptype body region 22, and is the same in depth as the ptype body region 22. Therefore, the impurity concentration of the end-surface-sidep type region 42 is the same as that of the ptype body region 22, and is, for example, about 1.0×1015cm−3 to 1.0×1019cm−3. - The
gate insulating film 26 may be made of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, an alumina film, a tantalum oxide film, etc. As shown inFIG. 2 , thegate insulating film 26 is formed such that thegate insulating film 26 covers, at least, a front surface of the p type body region in thechannel region 35. In the present preferred embodiment, thegate insulating film 26 covers a part of the n+type source region 24, thechannel region 35, and the front surface of the n−type base layer 21. More plainly speaking, thegate insulating film 26 is formed with a pattern that has an opening in the p− typebody contact region 25 of each of theunit cells 29 and in an inner-edge region of the n+type source region 24 continuous with the p+ typebody contact region 25. Additionally, as shown inFIG. 3 , the gate insulating film extends from theactive cell portion 3 to the outerperipheral portion 4, and is selectively formed at the outerperipheral portion 4. - The
gate electrode 27 is facing thechannel region 35 through thegate insulating film 26. Thegate electrode 27 may be made of, for example, polysilicon that is lowered in resistance by implanting an impurity. - As shown in
FIG. 2 , in theactive cell portion 3, thegate electrode 27 is formed such that thegate electrode 27 has substantially the same pattern as thegate insulating film 26, and covers a front surface of thegate insulating film 26. In other words, thegate electrode 27 is disposed above a part of the n+type source region 24, thechannel region 35, and the front surface of the n−type base layer 21. More plainly speaking, thegate electrode 27 is formed with a pattern that has an opening in the p+typebody contact region 25 of each of theunit cells 29 and in the inner-edge region of the n+type source region 24 continuous with the p+ typebody contact region 25. In other words, thegate electrode 27 is capable of controlling the plurality ofunit cells 29 in common. Consequently, a planar gate structure is configured. - On the other hand, in the outer
peripheral portion 4, thegate electrode 27 has acontact portion 40 disposed at a position facing the region between theend portion 37 of the p| typebody contact region 25 and theend portion 36 of the ptype body region 22 as shown inFIG. 3 . The gate electrode film 6 (gate finger 13) that is an external electrode is connected to thecontact portion 40. Additionally, in the outerperipheral portion 4, anequipotential ring electrode 41 made of the same material as that of thegate electrode 27 is disposed on thegate insulating film 26. Theequipotential ring electrode 41 is disposed on a region between the p−type contact layer 33 and the end-surface-sidep type region 42, and is formed so as not to overlap with the p−type contact layer 33 and the end-surface-sidep type region 42. - An interlayer insulating
film 43 is formed on the ntype base layer 21 and covers thegate electrode 27 and theequipotential ring electrode 41. Theinterlayer insulating film 43 is made of an insulating material, such as a silicon oxide film, a silicon nitride film, or TEOS (tetraethoxysilane). - A
contact hole 44 by which the p+ typebody contact region 25 and the n+type source region 24 of each of theunit cells 29 are exposed, acontact hole 45 by which thecontact portion 40 of thegate electrode 27 is exposed, acontact hole 46 by which the p−type contact layer 33 is exposed, and acontact hole 47 by which theequipotential ring electrode 41 is exposed are formed in theinterlayer insulating film 43. These contact holes 44 to 47 are formed such that contact holes 44 to 47 pass through theinterlayer insulating film 43 and through thegate insulating film 26. - The
source electrode film 5 is made of aluminum or other metals. As shown inFIG. 3 , thesource electrode film 5 selectively covers a front surface of theinterlayer insulating film 43 and is embedded in thecontact hole 44. Consequently, thesource electrode film 5 is ohmically connected to the n+type source region 24. Therefore, thesource electrode film 5 is connected to the plurality ofunit cells 29 in parallel, and is arranged so that all electric currents flowing to the plurality ofunit cells 29 flow thereto. Additionally, thesource electrode film 5 is ohmically connected to the p| typebody contact region 25 of each of theunit cells 29 through thecontact hole 44, so that the electric potential of the ptype body region 22 is stabilized. - The
gate electrode film 6 is made of aluminum or other metals. As shown inFIG. 3 , thegate electrode film 6 is formed selectively covers the front surface of theinterlayer insulating film 43 and is embedded in thecontact hole 45. Consequently, thegate electrode film 6 is ohmically connected to thecontact portion 40 of thegate electrode 27. - The outer
peripheral electrode film 7 is made of aluminum or other metals. As shown inFIG. 3 , the outerperipheral electrode film 7 selectively covers the front surface of theinterlayer insulating film 43 and is embedded in thecontact hole 46. Consequently, the outerperipheral electrode film 7 is ohmically connected to the p−type contact layer 33. - The
equipotential ring film 8 is made of aluminum or other metals. As shown inFIG. 3 , theequipotential ring film 8 selectively covers the front surface of theinterlayer insulating film 43 and is embedded in thecontact hole 47. Consequently, theequipotential ring film 8 is ohmically connected to theequipotential ring electrode 41. - The
surface protection film 48 is formed on a topmost surface of thesemiconductor substrate 2 and covers theelectrode films 5 to 8. Thesurface protection film 48 is made of an insulating material, such as a silicon nitride film or a polyimide film. As shown inFIG. 3 , apad opening 49 by which a part of thesource electrode film 5 is exposed as thesource pad 11 is formed in thesurface protection film 48. A pad opening (not shown) by which a part of thegate electrode film 6 and a part of the outerperipheral electrode film 7 are exposed as thegate pad 12 and as the outerperipheral pad 17, respectively, is formed in thesurface protection film 48. On the other hand, a finger part of thegate electrode film 6 and a finger part of the outer peripheral electrode film 7 (thegate finger 13 and the outer peripheral finger 18) are covered with thesurface protection film 48. With respect to theequipotential ring film 8, its entirety is covered with thesurface protection film 48. - The
drain electrode 28 is made of aluminum or other metals. Thedrain electrode 28 is formed such that thedrain electrode 28 is in contact with the rear surface of the n+type drain layer 20. Consequently, thedrain electrode 28 is connected to the plurality ofunit cells 29 in parallel, and is arranged so that all electric currents flowing to the plurality ofunit cells 29 flow thereto. - When a DC power source is connected between the
source electrode film 5 and thedrain electrode 28 in a state in which thedrain electrode 28 is set as a high-potential side and in which thesource electrode film 5 is set as a low-potential side, a reverse bias is applied to theparasitic diode 34. If a control voltage lower than a predetermined threshold voltage is applied to thegate electrode 27 at this time, no current path is formed between the drain and source sides. In other words, thesemiconductor device 1 reaches an OFF state. On the other hand, if a control voltage greater than the threshold voltage is applied to thegate electrode 27, electrons are drawn to a front surface of thechannel region 35, so that an inversion layer (channel) is formed. Consequently, the path between the n+type source region 24 and the n−type base layer 21 is brought into an electrically conductive state. In other words, a current path is formed from thesource electrode film 5 to thedrain electrode 28 through the n|type source region 24, the inversion layer of thechannel region 35, and the n−type base layer 21 in this order. In other words, thesemiconductor device 1 reaches an ON state. - When the
semiconductor device 1 is applied to an inverter circuit that drives an inductive load, such as an electric motor, there is a case in which thesource electrode film 5 becomes higher in potential than thedrain electrode 28, and then theparasitic diode 34 is turned on, and an electric current flows through theparasitic diode 34. Thereafter, when thesource electrode film 5 becomes lower in potential than thedrain electrode 28, theparasitic diode 34 reaches a reverse bias state, and is turned off. When it is turned off, a depletion layer spreads from a pn junction portion of theparasitic diode 34, and carriers (positive holes) in the ptype body region 22 and in the p−type column layer 23 move to the source-electrode-film-5 side, and carriers (electrons) in the n−type base layer 21 move to the drain-electrode-28 side. - Because of the movement of the carriers, an electric current flows in a direction opposite to a direction in which it flows when the
parasitic diode 34 is in an ON state. This electric current is called a reverse recovery current. Generally, the reverse recovery current is temporarily increased and is then decreased. Time from when the forward current of the diode becomes zero until when the magnitude of the reverse recovery current decreases to 10% of its maximum value is called a reverse recovery time. When a change (dir/dt) in the reverse recovery current is large, there is a case in which oscillation (ringing) occurs until the electric current is settled to zero. This reverse recovery characteristic is called hard recovery, and causes noise or malfunctions. - In the present preferred embodiment, in the outer
peripheral portion 4, the p−type column layer 23 is connected to the outerperipheral electrode film 7 that is independent of thesource electrode film 5. This makes it possible to allow an electric current to preferentially flow to the outerperipheral portion 4 by applying an appropriate voltage to the outerperipheral electrode film 7 when thesemiconductor device 1 is turned off. It is possible to forcibly draw carriers (positive holes) existing in the ptype column layer 23 to the outerperipheral portion 4, for example, by applying a negative bias to the outerperipheral electrode film 7. In other words, although a reverse current flows to the source-drain path of theactive cell portion 3 by turning off thesemiconductor device 1 if normal, it is possible to control a part of or all of the reverse current so as to flow to the outerperipheral portion 4. Furthermore, it is possible to forcibly draw the carriers to the outerperipheral portion 4, and therefore it is possible to satisfactorily control electric characteristics during the turn-off time even if the p−type column layer 23 that is a moving path of the carriers is somewhat high in resistance. Therefore, in theactive cell portion 3, it is possible to easily expand a depletion layer from the pn junction portion between the p−type column layer 23 and the n−type base layer 21 by making the impurity concentration of the p−type column layer 23 lower than that of the ptype body region 22 as mentioned above, and therefore it is also possible to improve withstand voltage. - As described above, in the present preferred embodiment, it is possible to distribute even more carriers moving through the n
type base layer 21 in the outerperipheral portion 4 than in theactive cell portion 3 when thesemiconductor device 1 is turned off. Therefore, in the present preferred embodiment, thetrap level region 38 is disposed in the outerperipheral portion 4. It is possible to facilitate a recombination of carriers in the outerperipheral portion 4 by means of thetrap level region 38. As a result, it is possible to make the reverse recovery time trr shorter than before. -
FIG. 4A toFIG. 4D are views showing a process of manufacturing thesemiconductor device 1 in order of process steps.FIG. 4A toFIG. 4D correspond to the cross-sectional view ofFIG. 3 . - In order to manufacture the
semiconductor device 53, aninitial base layer 50 is first formed on the n+type drain layer 20 as shown inFIG. 4A . Thereafter, a plurality of n type semiconductor layers 51 are stacked together on theinitial base layer 50 by means of multi epitaxial growth to repeatedly perform a step of forming the ntype semiconductor layer 51 while selectively implanting a p type impurity in positions in which the p−type column layer 23 and the p−type contact layer 33 are to be formed. Consequently, the plurality of n type semiconductor layers 51 and theinitial base layer 50 are integrated with each other, so that the n−type base layer 21 is formed. - Thereafter, the p type impurity of the plurality of n type semiconductor layers 51 is subjected to a drive diffusion by annealing (1000° C. to 1200° C.). Consequently, the p−
type column layer 23 and the p−type contact layer 33 are simultaneously formed in the ntype base layer 21 as shown inFIG. 4B . - Thereafter, the p
type body region 22 and the end-surface-sidep type region 42 are formed by selectively implanting a p type impurity into the surface portion of the n−type base layer 21 as shown inFIG. 4C . Thereafter, the n+type source region 24 is formed by selectively implanting an n type impurity into the surface portion of the ptype body region 22. Thereafter, the p+ typebody contact region 25 is formed by selectively implanting a p type impurity into the surface portion of the ptype body region 22. - Thereafter, the
gate insulating film 26 is formed on the n−type base layer 21 as shown inFIG. 4C . Thegate insulating film 26 may be formed by the thermal oxidation of a semiconductor crystal surface. Furthermore, thegate electrode 27 and theequipotential ring electrode 41 are formed on thegate insulating film 26. Thegate electrode 27 and theequipotential ring electrode 41 may be formed, for example, by forming a polysilicon film, resistance of which has been lowered by the addition of impurities, on the entire surface and then selectively etching the polysilicon film according to photolithography. - Furthermore, the
interlayer insulating film 43 is formed so as to cover thegate electrode 27 and theequipotential ring electrode 41, and the contact holes 44 to 47 are formed in theinterlayer insulating film 43 according to photolithography as shown inFIG. 4C . Thereafter, thesource electrode film 5, thegate electrode film 6, the outerperipheral electrode film 7, and theequipotential ring film 8 are formed on theinterlayer insulating film 43. - Thereafter, the
surface protection film 48 is formed so as to cover thesource electrode film 5, thegate electrode film 6, the outerperipheral electrode film 7, and theequipotential ring film 8, and thepad opening 49 is formed in thesurface protection film 48 according to photolithography as shown inFIG. 4C . Thus, a MIS structure of thesemiconductor device 1 is formed as shown inFIG. 4C . - Thereafter, heavy-particle irradiation or electron-beam irradiation is performed from the rear surface of the n+
type drain layer 20 through amask plate 52 as shown inFIG. 4D . It is recommended to appropriately determine the irradiation energy of the heavy particles or of the electron beams in consideration of the depth position of thetrap level region 38. Consequently, thetrap level region 38 is formed in the p−type column layer 23. - Thereafter, the
drain electrode 28 is formed on the rear surface of the n|type drain layer 20, thus making it possible to obtain thesemiconductor device 1 ofFIG. 1 toFIG. 3 . -
FIG. 5 is a schematic cross-sectional view of asemiconductor device 53 according to a preferred embodiment of the present invention. InFIG. 5 , a description of each component that has already been described in thesemiconductor device 1 ofFIG. 1 toFIG. 3 is omitted by giving the same reference sign to the component. - The
semiconductor device 53 ofFIG. 5 has minute concavo-convex portions 55 formed onside surfaces deep trench 54, respectively, instead of thetrap level region 38 of thesemiconductor device 1 mentioned above. - More specifically, the
deep trench 54 is formed from the front surface of the n−type base layer 21 toward the n+type drain layer 20, and has, for example, a bottom portion at the same depth position as the bottom portion of the ptype column layer 23. The p−type contact layer 33 and the p−type column layer 23 are exposed to theside surface 56 closer to the p−type column layer 23 of thedeep trench 54 over the whole area in the depth direction. The minute concavo-convex portion 55 is formed both on exposed parts of the p−type contact layer 33 and of the ptype column layer 23 and on theside surface 57 facing the exposed parts. The minute concavo-convex portion 55 is formed in a manner in which the side surfaces 56 and 57 of thedeep trench 54 are roughened, and is formed extremely smaller than the concavo-convex surfaces (rugged surfaces) of the p−type column layer 23 and of the p−type contact layer 33. - The
deep trench 54 has its inside the whole of which is filled with an embedded insulatingfilm 58. The embedded insulatingfilm 58 is made of an insulating material, such as a silicon oxide film. - According to the
semiconductor device 53, in the carrier-moving path from the bottom portion of the p−type column layer 23 to the outerperipheral electrode film 7 through the p−type contact layer 33, the minute concavo-convex portion 55 is formed on the p−type column layer 23 and the p−type contact layer 33. Therefore, it is possible to allow the minute concavo-convex portion 55 to assume a role as a hole (electron) pocket, and it is possible to facilitate the disappearance of carriers that pass through the carrier-moving path. As a result, it is possible to make the reverse recovery time trr shorter than before. -
FIG. 6A toFIG. 6E are views showing a manufacturing process of thesemiconductor device 53 in order of process steps. - In order to manufacture the
semiconductor device 1, aninitial base layer 50 is first formed on the n+type drain layer 20 as shown inFIG. 6A . Thereafter, a plurality of n type semiconductor layers 51 are stacked together on theinitial base layer 50 by means of multi epitaxial growth to repeatedly perform a step of forming the ntype semiconductor layer 51 while selectively implanting a p type impurity in positions in which the ptype column layer 23 and the ptype contact layer 33 are to be formed. Consequently, the plurality of n type semiconductor layers 51 and theinitial base layer 50 are integrated with each other, so that the n−type base layer 21 is formed. - Thereafter, the p type impurity of the plurality of n type semiconductor layers 51 is subjected to a drive diffusion by annealing (1000° C. to 1200° C.). Consequently, the p−
type column layer 23 and the p−type contact layer 33 are simultaneously formed in the ntype base layer 21 as shown inFIG. 6B . - Thereafter, a mask (not shown) that selectively has an opening in a region in which the
deep trench 54 is to be formed is formed on the n−type base layer 21, and thedeep trench 54 is selectively formed in the n−type base layer 21 by anisotropic deep RIE (Reactive Ion Etching) that uses the mask as a hard mask, i.e., by a Bosch process. In the Bosch process, for example, a step of etching the n−type base layer 21 by use of SF6 (sulfur hexafluoride) and a step of forming a protective film on an etched surface by use of C4F8 (perfluorocyclobutane) are alternately repeated. This makes it possible to etch the ntype base layer 21 at a high aspect ratio, and makes it possible to form a wave-shaped concavo-convex portion (minute concavo-convex portion 55), which is called a scallop, on the etched surface (the side surfaces 56 and 57 of the deep trench 54) as shown inFIG. 6C . - Thereafter, an insulating material is embedded in the
deep trench 54 according to, for example, a CVD method as shown inFIG. 6D . Consequently, the embedded insulatingfilm 58 is formed. - Thereafter, the p
type body region 22 and the end-surface-sidep type region 42 are formed by selectively implanting a p type impurity into the surface portion of the n−type base layer 21 as shown inFIG. 6E . Thereafter, the n+type source region 24 is formed by selectively implanting an n type impurity into the surface portion of the ptype body region 22. Thereafter, the p+ typebody contact region 25 is formed by selectively implanting a p type impurity into the surface portion of the ptype body region 22. - Thereafter, the
gate insulating film 26 is formed on the ntype base layer 21 as shown inFIG. 6E . Thegate insulating film 26 may be formed by the thermal oxidation of a semiconductor crystal surface. Furthermore, thegate electrode 27 and theequipotential ring electrode 41 are formed on thegate insulating film 26. Thegate electrode 27 and theequipotential ring electrode 41 may be formed, for example, by forming a polysilicon film, resistance of which has been lowered by the addition of impurities, on the entire surface and then selectively etching the polysilicon film according to photolithography. - Furthermore, the
interlayer insulating film 43 is formed so as to cover thegate electrode 27 and theequipotential ring electrode 41, and the contact holes 44 to 47 are formed in theinterlayer insulating film 43 according to photolithography as shown inFIG. 6E . Thereafter, thesource electrode film 5, thegate electrode film 6, the outerperipheral electrode film 7, and theequipotential ring film 8 are formed on theinterlayer insulating film 43. - Thereafter, the
surface protection film 48 is formed so as to cover thesource electrode film 5, thegate electrode film 6, the outerperipheral electrode film 7, and theequipotential ring film 8, and thepad opening 49 is formed in thesurface protection film 48 according to photolithography as shown inFIG. 6E . Thus, a MIS structure of thesemiconductor device 53 is formed. - Thereafter, the
drain electrode 28 is formed on the rear surface of the n+type drain layer 20, thus making it possible to obtain thesemiconductor device 53 ofFIG. 5 . -
FIG. 7 is a schematic cross-sectional view of asemiconductor device 59 according to a preferred embodiment of the present invention. - The
semiconductor device 59 ofFIG. 7 includes an embeddedcontact member 60 that is embedded from the front surface of the n−type base layer 21 to the p−type column layer 23 and that is connected to the p−type column layer 23, instead of the ptype contact layer 33. - An insulating
film 61 is interposed between the embeddedcontact member 60 and the n−type base layer 21, and insulation between the embeddedcontact member 60 and the n−type base layer 21 is made by the insulatingfilm 61. - The outer
peripheral electrode film 7 is connected to the embeddedcontact member 60 exposed to the front surface of the n−type base layer 21. - The embedded
contact member 60 is made of a metallic material excellent in embeddability, such as tungsten or copper. It is possible to excellently draw carriers (positive holes) existing in the p−type column layer 23 to the outerperipheral portion 4 by using a metallic material that is low in resistance as a contact portion between the outerperipheral electrode film 7 and the p−type column layer 23, unlike an impurity region such as the p−type contact layer 33. - Although the preferred embodiments of the present invention have been described as above, the present invention can be embodied in other modes.
- For example, as in a
semiconductor device 62 ofFIG. 8 , the p−type column layer 23 may include acontinuous column 63 that is continuously formed downwardly from the ptype body region 22 in theactive cell portion 3. Although only one separatedcolumn 30 and only onecontinuous column 63 are shown inFIG. 8 , the separatedcolumn 30 and thecontinuous column 63 may be alternately arranged, for example, in a direction perpendicular to the stripe direction. - Additionally, although the p−
type column layer 23 is formed by multi epitaxial growth as described in the above preferred embodiments, it is also possible to form the p−type column layer 23, for example, by forming a deep trench in the n−type base layer 21 and embedding a p− type semiconductor layer in the deep trench. - Additionally, the structure of the
unit cell 29 may be a planar gate structure or a trench gate structure as described in the above preferred embodiments. - Additionally, an arrangement may be employed in which the conductivity type of each semiconductor part of the
semiconductor devices semiconductor device 1, the p type part may be an n type part, and the n type part may be a p type part. - Besides, various design changes can be made within the scope of the subject matter described in the claims.
- Simulation results of
FIG. 9A ,FIG. 9B ,FIG. 10A ,FIG. 10B ,FIG. 11A ,FIG. 11B ,FIG. 12A , andFIG. 12B show effects achieved by the application of a voltage to the outerperipheral electrode film 7 when thesemiconductor devices - Of the figures mentioned above, figures for which “A” is given to the end of the figure number each show a current value of an electric current that flows to the source region of the semiconductor device when the semiconductor device is turned off. On the other hand, of the figures mentioned above, figures for which “B” is given to the end of the figure number each show a current value of an electric current that flows to the column layer of the semiconductor device when the semiconductor device is turned off. Additionally,
FIG. 9A ,FIG. 9B ,FIG. 11A , andFIG. 11B show examples in which thecontinuous column 63 is used as the ptype column layer 23, whereasFIG. 10A ,FIG. 10B ,FIG. 12A , andFIG. 12B show examples in which the separatedcolumn 30 is used as the p−type column layer 23. In each simulation, an electrode embedded in the p−type column layer 23 was set instead of the outerperipheral electrode film 7, and a voltage was applied to this electrode independently of the source electrode. - As a result of the simulations, in comparison between
FIGS. 9A, 10A, 11A, 12A andFIGS. 9B, 10B, 11B, 12B , substantially the same amount of electric current flowed to the source region and to the column layer in “ref” for which a voltage was not applied to the embedded electrode (corresponding to the outer peripheral electrode film 7) of the p−type column layer 23 when the semiconductor device is turned off. On the other hand, referring to examples in which the applied voltage is −1 V, −2 V, −3 V, −5 V, 1 V, 2 V, 3 V, and 5 V, an electric current flowing to the source region was reduced, and an electric current preferentially flowed to the column layer in any example. - From these results, it is clear that an electric current preferentially flows to the outer
peripheral portion 4 of the n−type base layer 21 in the above preferred embodiments. Therefore, it is understood that it is possible to settle an electric current flowing to the outerperipheral portion 4 and shorten the reverse recovery time trr by disposing a carrier obstructing portion, such as thetrap level region 38 or the minute concavo-convex portion 55, at the outerperipheral portion 4. -
FIG. 13A toFIG. 13C are schematic views of the semiconductor device used in 3D simulations, andFIG. 13A and -
FIG. 13B are views when the semiconductor device is viewed from mutually different angles, andFIG. 13C is an enlarged view of a main part ofFIG. 13A . InFIG. 13A toFIG. 13C , only reference signs necessary in the following description are shown among the reference signs ofFIG. 2 andFIG. 3 . - In 2D simulations whose results are shown in
FIG. 9A toFIG. 12B mentioned above, the electrode embedded in the ptype column layer 23 was set instead of the outerperipheral electrode film 7, and effects of the invention were verified. On the other hand, in the 3D simulations, a contact A (ContA) corresponding to thesource electrode film 5 and a contact B (ContB) corresponding to the outerperipheral electrode film 7 were set as shown inFIG. 13A toFIG. 13C , and effects were verified under conditions closer to the structure of each preferred embodiment mentioned above. ContA is set in an electrically floating state, and ContB is connected to +5 V. - In the simulations, a reverse voltage of 600 V was applied to the source-drain path in a state in which an electric current of 20 A flows to the source-drain path, and the semiconductor device was turned off. Thereafter, waveforms were verified until the electric current flowing to ContA and to ContB was settled. Results are shown in
FIG. 14 . - As a result of the simulations, in comparison between the electric current (“ContA (A)” of
FIG. 14 ) flowing to ContA and the electric current (“ContB (A)” ofFIG. 14 ) flowing to ContB, the electric current flowing to ContA on the source side was small in amount, whereas the electric current preferentially flowed to ContB on the column side. Additionally, it has been recognized that the reverse recovery currents flowing to ContA and ContB are both smaller than a - Ref current (A) in which the column layer is not separated. Additionally, with respect to the voltage (“ContA, B (V)” of
FIG. 14 ) between the source and the drain, a change in the electric current becomes gentle due to the divided flow effect to ContA and to ContB, and it is possible to suppress the oscillation to be smaller than the Ref voltage (V).
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