US20180145596A1 - Method for conrolling on time of power switch in power converter - Google Patents
Method for conrolling on time of power switch in power converter Download PDFInfo
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- US20180145596A1 US20180145596A1 US15/872,481 US201815872481A US2018145596A1 US 20180145596 A1 US20180145596 A1 US 20180145596A1 US 201815872481 A US201815872481 A US 201815872481A US 2018145596 A1 US2018145596 A1 US 2018145596A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/083—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the ignition at the zero crossing of the voltage or the current
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/12—Arrangements for reducing harmonics from ac input or output
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4258—Arrangements for improving power factor of AC input using a single converter stage both for correction of AC input power factor and generation of a regulated and galvanically isolated DC output voltage
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
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- H02M2001/0009—
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/10—Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier
Abstract
A method for controlling a power switch of a power converter includes: detecting whether a zero current event occurs; generating an error signal; generating an ramp signal having a slope proportional to a ratio of an on time during which of the power switch is turned on in a previous switching cycle to a time length of the previous switching cycle; comparing the ramp signal with the error signal; turning on the power switch when the zero current event occurs; and turning off the power switch and rapidly lowering the level of the ramp signal when the ramp signal is greater than or equal to the error signal.
Description
- This application is a Continuation of and claims the benefit of priority to U.S. patent application Ser. No. 15/586,976, filed on May 4, 2017, which is a Continuation of and claims the benefit of priority to U.S. patent application Ser. No. 14/547,870, filed on Nov. 19, 2014, which claims the benefit of priority to Patent Application No. 102144716, filed in Taiwan on Dec. 5, 2013; the entirety of which is incorporated herein by reference for all purposes.
- The disclosure generally relates to a power factor correction circuit and, more particularly, to a power factor correction circuit of a power converter.
- The power utilization efficiency of electronic devices has become more and more important as the energy shortage problem deteriorates. The traditional power converter is typically realized by using diode rectifiers. Although such structure is simple and low cost, serious non-linear distortion occurs at an input current to greatly increase the low frequency harmonics, thereby decreasing the power factor. The power factor is defined as a ratio of the working power to the apparent power, and is an indicator for measuring the power utilization efficiency. Electronic devices with low power factor not only waste energy, but also generate enormous harmonics to adversely affect the stability of the power system and thus cause problems to the power generator, thereby seriously affecting the quality of power supply.
- In general, the power factor of the power converter may be improved by adding a power factor correction (PFC) circuit to the power converter. However, the newly developed electronic devices are required to meet more severe total harmonic distortion (THD) requirement, and the structure of traditional PFC circuit is difficult to satisfy the specification requirements of the newly developed electronic devices.
- An example embodiment of a method for controlling a power switch of a flyback power converter is disclosed. The flyback power converter comprises a primary side coil, a secondary side coil, and an inductive coil, wherein the primary side coil is coupled between an input voltage signal and the power switch, the secondary side coil is configured to operably provide an output voltage signal and an output current signal, the inductive coil is configured to operably sense the primary side coil to generate an inductive signal, and the power switch is coupled between the primary side coil and a fixed-voltage terminal. The method comprises: detecting the inductive signal to determine whether a zero current event occurs; generating an error signal corresponding to the output voltage signal or the output current signal according to a reference signal; generating an ramp signal having a slope proportional to a ratio of an on time during which of the power switch is turned on in a previous switching cycle to a time length of the previous switching cycle; comparing the ramp signal with the error signal; turning on the power switch when the zero current event occurs; and when the ramp signal is greater than or equal to the error signal, turning off the power switch and rapidly lowering the level of the ramp signal.
- Another example embodiment of a method for controlling a power switch of an asynchronous-type buck-boost power converter is disclosed. The asynchronous-type buck-boost power converter comprises a first coil, an inductive coil, and a diode, wherein the first coil is coupled between an input voltage signal and the power switch, the inductive coil is configured to operably sense the first coil to provide an inductive signal, the power switch is coupled between the first coil and a fixed-voltage terminal, and the diode is coupled between the first coil and a load of the asynchronous-type buck-boost power converter. The method comprises: detecting the inductive signal to determine whether a zero current event occurs; generating an error signal corresponding to an output voltage signal or an output current signal of the asynchronous-type buck-boost power converter according to a reference signal; generating an ramp signal having a slope proportional to a ratio of an on time during which of the power switch is turned on in a previous switching cycle to a time length of the previous switching cycle; comparing the ramp signal with the error signal; turning on the power switch when the zero current event occurs; and when the ramp signal is greater than or equal to the error signal, turning off the power switch and rapidly lowering the level of the ramp signal.
- Another example embodiment of a power switch of a synchronous-type buck-boost power converter is disclosed. The synchronous-type buck-boost power converter comprises a first coil, an inductive coil, and a second power switch, wherein the first coil is coupled between an input voltage signal and the power switch, the inductive coil is configured to operably sense the first coil to provide an inductive signal, the first power switch is coupled between a second terminal of the first coil and a fixed-voltage terminal, and the second power switch is coupled between the second terminal of the first coil and a load of the synchronous-type buck-boost power converter. The method comprises: detecting the inductive signal to determine whether a zero current event occurs; generating an error signal corresponding to an output voltage signal or an output current signal of the synchronous-type buck-boost power converter according to a reference signal; generating an ramp signal having a slope proportional to a ratio of an on time during which of the power switch is turned on in a previous switching cycle to a time length of the previous switching cycle; comparing the ramp signal with the error signal; turning on the power switch when the zero current event occurs; and when the ramp signal is greater than or equal to the error signal, turning off the power switch and rapidly lowering the level of the ramp signal.
- Both the foregoing general description and the following detailed description are examples and explanatory only, and are not restrictive of the invention as claimed.
-
FIG. 1 shows a simplified functional block diagram of a flyback power converter according to one embodiment of the present disclosure. -
FIG. 2 shows a simplified schematic diagram of the relationship between an input voltage signal and an input current signal of the flyback power converter ofFIG. 1 according to one embodiment of the present disclosure. -
FIG. 3 shows a simplified functional block diagram of a power factor correction (PFC) circuit inFIG. 1 according to one embodiment of the present disclosure. -
FIG. 4 shows a simplified functional block diagram of an asynchronous-type buck-boost power converter according to one embodiment of the present disclosure. -
FIG. 5 shows a simplified functional block diagram of a synchronous-type buck-boost power converter according to one embodiment of the present disclosure. - Reference is made in detail to embodiments of the invention, which are illustrated in the accompanying drawings. The same reference numbers may be used throughout the drawings to refer to the same or like parts, components, or operations.
-
FIG. 1 shows a simplified functional block diagram of aflyback power converter 100 according to one embodiment of the present disclosure. Thepower converter 100 is utilized for converting an AC voltage signal Vac provided by anAC power source 101 into a DC output voltage signal Vout, so that the output voltage signal Vout can be utilized by aload 119 in the subsequent stage. In this embodiment, thepower converter 100 comprises arectifier 103, aninput capacitor 105, aprimary side coil 107, asecondary side coil 109, aninductive coil 111, apower switch 113, adiode 115, anoutput capacitor 117, a power factor correction (PFC)circuit 120, aresistance device 130, and afeedback circuit 140. - The
rectifier 103 is configured to operably rectify the AC voltage signal Vac provided from theAC power source 101 into an input voltage signal Vin having m-shape waveform. Theinput capacitor 105 is coupled with an output terminal of therectifier 103 and configured to operably reduce the noise in the input voltage signal Vin. A first terminal of theprimary side coil 107 is coupled with the input voltage signal Vin. A first terminal of thesecondary side coil 109 is utilized for providing the output voltage signal Vout. Theinductive coil 111 is configured to operably sense theprimary side coil 107 to provide an inductive signal SS. Thepower switch 113 is coupled between a second terminal of theprimary side coil 107 and a fixed-voltage terminal (such as a ground terminal). An input terminal of thediode 115 is coupled with the first terminal of thesecondary side coil 109, and an output terminal of thediode 115 is coupled with theload 119 of thepower converter 100. Theoutput capacitor 117 is coupled with the output terminal of thediode 115 and configured to operably reduce the noise in the output voltage signal Vout. ThePFC circuit 120 is configured to operably control the switching operations of thepower switch 113 to adjust a current IL flowing through theprimary side coil 107 to thereby change the magnitude of a current Ido flowing through thediode 115 so as to adjust the output voltage signal Vout. Theresistance device 130 may conduct a voltage-dividing operation on the inductive signal SS. Thefeedback circuit 140 is configured to operably generate a corresponding feedback signal FB according to the output voltage signal Vout or the output current signal Iout of thepower converter 100. - As shown in
FIG. 1 , thePFC circuit 120 comprises a zero current detection (ZCD)circuit 121, anerror detection circuit 123, a rampsignal generating circuit 125, acomparison circuit 127, and atrigger circuit 129. In the embodiment ofFIG. 1 , the zerocurrent detection circuit 121 is configured to operably detect the inductive signal SS when coupling with theinductive coil 111 to generate a detection signal DS. Theerror detection circuit 123 is configured to operably generate an error signal COMP corresponding to the output voltage signal Vout according to a reference signal Vref. The rampsignal generating circuit 125 is configured to operably generate a ramp signal RAMP. Thecomparison circuit 127 is coupled with theerror detection circuit 123 and the rampsignal generating circuit 125, and configured to operably compare the ramp signal RAMP with the error signal COMP to generate a comparison signal VC. Thetrigger circuit 129 is coupled with the zerocurrent detection circuit 121, the rampsignal generating circuit 125, and thecomparison circuit 127. Thetrigger circuit 129 is configured to operably generate a control signal CTL for controlling thepower switch 113 according to the detection signal DS and the comparison signal VC, and also configured to operably control the rampsignal generating circuit 125 to adjust a slope of the ramp signal RAMP. - In practice, the zero
current detection circuit 121 may detect a voltage-divided generated by theresistance device 130 to generate the aforementioned detection signal DS. Theerror detection circuit 123 may generate the error signal COMP corresponding to the output voltage signal Vout according to the feedback signal FB generated by thefeedback circuit 140 and the reference signal Vref. -
FIG. 2 shows a simplified schematic diagram of the relationship between the input voltage signal Vin and the input current signal Iin of theflyback power converter 100 ofFIG. 1 according to one embodiment of the present disclosure. For the purpose of explanatory convenience in the following description, it is assumed herein that the control signal CTL in the embodiment ofFIG. 2 is an active high signal. That is, thepower switch 113 would be turned on when thePFC circuit 120 configures the control signal CTL to an active level. - In
FIG. 2 , IL_pk denotes an envelope of peak values of the current flowing through theprimary side coil 107, Ton denotes the on time at which thepower switch 113 is turned on in each switching cycle, Toff denotes the off time at which thepower switch 113 is turned off in each switching cycle, Ts denotes a total time length of the on time Ton and the off time Toff of thepower switch 113. That is, Ts represents the time length of each switching cycle of thepower switch 113, and is also equivalent to the period length of the control signal CTL. - When the
power switch 113 is turned on, the current flows to thepower switch 113 through theprimary side coil 107, so that the energy of the input voltage signal Vin received by theprimary side coil 107 is passed to thesecondary side coil 109 through the inductive effect to generate the current Ido flowing through thediode 115 when thepower switch 113 is turned off. In this situation, the current Ido charges theoutput capacitor 117 to rise up the output voltage signal Vout. - The
PFC circuit 120 controls the magnitude of the current IL by switching thepower switch 113 at a high frequency, and the high frequency component in the current IL is filtered out by theinput capacitor 105, so that the magnitude of the input current signal Iin becomes the average of the current IL. Accordingly, thePFC circuit 120 makes the waveform of the input current signal Iin to follow the waveform of the input voltage signal Vin by controlling the magnitude of the current IL, so that the waveform of the input current signal Iin approaches to the sine waveform to thereby increase the power factor while effectively reducing the total harmonic distortion (THD). -
FIG. 3 shows a simplified functional block diagram of thePFC circuit 120 inFIG. 1 according to one embodiment of the present disclosure. As shown inFIG. 3 , the rampsignal generating circuit 125 of thePFC circuit 120 comprises afirst switch 310, asecond switch 320, acontrol circuit 330, a low-pass filter 340, atransconductance amplifier 350, acapacitor 360, and athird switch 370. Thefirst switch 310 is coupled between a settingsignal input terminal 302 and anode 304, wherein the settingsignal input terminal 302 is utilized for receiving a setting voltage Vset. Thesecond switch 320 is coupled between thenode 304 and a fixed-voltage terminal (such as a ground terminal). Thecontrol circuit 330 is coupled with a control terminal of thefirst switch 310 and a control terminal of thesecond switch 320. Thecontrol circuit 330 is configured to operably switch thefirst switch 310 and thesecond switch 320 alternatively under control of thetrigger circuit 129, so as to render thenode 304 to provide an adjusted voltage Vset2 less than the setting voltage Vset. The low-pass filter 340 comprises aresistor 342 and acapacitor 344, and is coupled with thenode 304. The low-pass filter 340 is configured to operably perform a low-pass filtering operation on the adjusted voltage Vset2 to generate a filtered signal VF. Thetransconductance amplifier 350 is coupled with the low-pass filter 340 and configured to operably convert the filtered signal VF into the ramp signal RAMP. Thecapacitor 360 is coupled with an output terminal of thetransconductance amplifier 350. Thethird switch 370 is coupled between the output terminal of thetransconductance amplifier 350 and a fixed-voltage terminal (such as a ground terminal), and a control terminal of thethird switch 370 is coupled with an output terminal of thetrigger circuit 129. - In practice, the
trigger circuit 129 may be realized with a variety of flip-flop structures. In the embodiment ofFIG. 3 , for example, thetrigger circuit 129 of thePFC circuit 120 is realized with a RS flip-flop. As shown inFIG. 3 , the RS flip-flop comprises a set terminal, a reset terminal, a non-inverted output terminal, and an inverted output terminal. The set terminal is coupled with the zerocurrent detection circuit 121. The reset terminal is coupled with thecomparison circuit 127. The non-inverted output terminal is utilized for providing the control signal CTL. The inverted output terminal is coupled with thethird switch 370 of the rampsignal generating circuit 125. In this embodiment, the non-inverted output terminal of the RS flip-flop is further coupled with thecontrol circuit 330 of the rampsignal generating circuit 125. - Each time the zero
current detection circuit 121 has detected that a zero current event occurs, e.g., when the inductive signal SS is less than a predetermined threshold, the zerocurrent detection circuit 121 switches the detection signal DS to an active level (e.g., the high level in this embodiment) to configure the set terminal of thetrigger circuit 129, so that thetrigger circuit 129 configures the control signal CTL to the active level (e.g., the high level in this embodiment) to turn on thepower switch 113. Meanwhile, thetrigger circuit 129 configures the inverted signal CTLB outputted at the inverted output terminal to an inactive level (e.g., the low level in this embodiment), so as to turn off thethird switch 370 of the rampsignal generating circuit 125. - Each time the
power switch 113 is turned on, the current IL gradually rises up from zero. Meanwhile, the level of the ramp signal RAMP generated by the rampsignal generating circuit 125 also gradually rises up with a predetermined slope. When thecomparison circuit 127 detects that the ramp signal RAMP is greater than or equal to the error signal COMP, thecomparison circuit 127 configures the reset terminal of thetrigger circuit 129 to the active level (e.g., the high level in this embodiment), so as to transit the control signal CTL to the inactive level (e.g., the low level in this embodiment) to thereby turn off thepower switch 113. Meanwhile, the inverted signal CTLB outputted at the inverted output terminal of thetrigger circuit 129 transits to the active level (e.g., the high level in this embodiment) to turn on thethird switch 370 of the rampsignal generating circuit 125, so that the level of the ramp signal RAMP drops down rapidly. When the zerocurrent detection circuit 121 afterwards detects that another zero current event occurs, thetrigger circuit 129 switches the control signal CTL to the active level to turn on thepower switch 113 again. - According to the foregoing descriptions, the on time Ton of the
power switch 113 is determined by the slope of the ramp signal RAMP, and could be represented as below: -
Ton=(Cramp*Vcomp)/[Vset2*Gm] Formula (1) - wherein Cramp denotes the capacitance value of the
capacitor 360 of the rampsignal generating circuit 125, Vcomp denotes the voltage value of the error signal COMP generated by theerror detection circuit 123, and Gm denotes the transconductance value of thetransconductance amplifier 350. - In the embodiment of
FIG. 3 , thecontrol circuit 330 alternatively switches thefirst switch 310 and thesecond switch 320 according to the control signal CTL, so that thefirst switch 310 and thesecond switch 320 are alternatively turned on to change the slope of the ramp signal RAMP outputted from the rampsignal generating circuit 125. Specifically, thecontrol circuit 330 may turn on thefirst switch 310 and turn off thesecond switch 320 when the control signal CTL is at the active level, thecontrol circuit 330 may turn off thefirst switch 310 and turn on thesecond switch 320 when the control signal CTL is at the inactive level. Accordingly, the magnitude of the adjusted voltage Vset2 on thenode 304 could be represented as below: -
Vset2=Vset*(Ton/Ts) Formula (2) - The following Formula (3) could be obtained by substituting the Formula (2) into the Formula (1):
-
Ton=(Cramp*Vcomp)/[Vset*(Ton/Ts)*Gm] Formula (3) - It is obvious that the Formula (3) is an iterative operation. Accordingly, it is apparent that Ts of the item (Ton/Ts) corresponds to the time length of the previous switching cycle of the
power switch 113 while Ton of the item (Ton/Ts) corresponds to the on time of thepower switch 113 in the previous switching cycle. In other words, the item (Ton/Ts) corresponds to the duty ratio of the control signal CTL of thepower switch 113 in the previous switching cycle. Since the values of Cramp, Vcomp, Vset, and Gm are substantially fixed, it can be appreciated from the Formula (3) that the on time Ton of the power switching 113 is proportional to the item (Ts/Ton). - In addition, assuming that the inductance value of the
primary side coil 107 is L, then the average value of the input current signal Iin in each switching cycle of thepower switch 113 could be represented as below: -
Iin=(½)*(Vin/L)*Ton*(Ton/Ts) Formula (4) - Since L is substantially a fixed value and Ton is proportional to the item (Ts/Ton), it can be appreciated from the Formula (4) that the waveform of the input current signal Iin would completely follow the change of the waveform of the input voltage signal Vin, and thus there is no phase difference between the input current signal Iin and the waveform of the input voltage signal Vin.
- In other words, the way that the
trigger circuit 129 controls the rampsignal generating circuit 125 to adjust the slope of the ramp signal RAMP renders the waveform of the input current signal Iin of thepower converter 100 to completely follow the waveform of the input voltage signal Vin. Accordingly, with the operations of the disclosedPFC circuit 120, the input current signal Iin and the input voltage signal Vin are enabled to have the same phase, and the input current signal Iin is enabled to have a waveform approaching to the sine waveform. As a result, the total harmonic distortion can be effectively reduced while improving the power factor of thepower converter 100. - In the previous embodiments, the
feedback circuit 140 generates the feedback signal FB directly based on the output voltage signal Vout or the output current signal Iout of thepower converter 100. But this is merely an exemplary embodiment, rather than a restriction to the practical implementations. In practice, thefeedback circuit 140 may be instead designed to generate the feedback signal FB corresponding to the output current signal lout of thepower converter 100 according to the detection signal DS outputted from the zerocurrent detection circuit 121 or the current flowing through thepower switch 113. - In previous embodiments, the
control circuit 330 of the rampsignal generating circuit 125 controls the switching operations of thefirst switch 310 and thesecond switch 320 according to the signal outputted from the non-inverted output terminal of thetrigger circuit 129. But this is merely an exemplary embodiment, rather than a restriction to the practical implementations. In practice, the inverted output terminal of thetrigger circuit 129 inFIG. 3 may be instead coupled with thecontrol circuit 330 and the logic combinations inside thecontrol circuit 330 may be adjusted, so as to render thecontrol circuit 330 to change the slope of the ramp signal RAMP outputted from the rampsignal generating circuit 125 by controlling the switching operations of thefirst switch 310 and thesecond switch 320 according to the inverted signal CTLB outputted from the inverted output terminal of thetrigger circuit 129. For example, thecontrol circuit 330 may be instead designed to turn on thefirst switch 310 and turn off thesecond switch 320 when the inverted signal CTLB is at the inactive level, and instead designed to turn off thefirst switch 310 and turn on thesecond switch 320 when the inverted signal CTLB is at the active level. - In addition, when the
first switch 310 and thesecond switch 320 of the rampsignal generating circuit 125 are instead realized with switch components of opposing control logics, the inverted output terminal of thetrigger circuit 129 inFIG. 3 may be instead coupled with thecontrol circuit 330, so that thecontrol circuit 330 controls the switching operations of thefirst switch 310 and thesecond switch 320 according to the inverted signal CTLB outputted from the inverted output terminal of thetrigger circuit 129. In this situation, thecontrol circuit 330 may be instead designed to turn on thefirst switch 310 and turn off thesecond switch 320 when the inverted signal CTLB is at the active level, and instead designed to turn off thefirst switch 310 and turn on thesecond switch 320 when the inverted signal CTLB is at the inactive level. - Similarly, when the
third switch 370 in the rampsignal generating circuit 125 is instead realized with a switch component of opposing control logic, the non-inverted output terminal of thetrigger circuit 129 inFIG. 3 may be instead coupled with the control terminal of thethird switch 370, so that thethird switch 370 switches according to the control signal CTL outputted from the non-inverted output terminal of thetrigger circuit 129. - Similarly, when the
power switch 113 is instead realized with a switch component of opposing control logic, the inverted output terminal of thetrigger circuit 129 inFIG. 3 may be instead coupled with the control terminal of thepower switch 113, and the inverted signal CTLB outputted from the inverted output terminal may be instead employed as the control signal for controlling thepower switch 113. - Different functional blocks in the
power converter 100 may be respectively realized with different circuits, or may be integrated into a single circuit chip. For example, all functional blocks in thePFC circuit 120 may be integrated in a single controller IC. Thepower switch 113 may be further integrated into thePFC circuit 120 to form a single controller IC. In addition, theresistance device 130 and/or thefeedback circuit 140 may be further integrated into thePFC circuit 120. - In practical applications, the structure of the disclosed
PFC circuit 120 is also applicable to other power converters having different structures. For example,FIG. 4 shows a simplified functional block diagram of an asynchronous-type buck-boost power converter 400 adopting theaforementioned PFC circuit 120 according to one embodiment of the present disclosure.FIG. 5 shows a simplified functional block diagram of a synchronous-type buck-boost power converter 500 adopting theaforementioned PFC circuit 120 according to one embodiment of the present disclosure. - As shown in
FIG. 4 , thepower converter 400 comprises therectifier 103, theinput capacitor 105, afirst coil 407, aninductive coil 411, thepower switch 113, adiode 415, anoutput capacitor 417, thePFC circuit 120, aresistance device 430, and afeedback circuit 140. A first terminal of thefirst coil 407 is coupled with the input voltage signal Vin. Thepower switch 113 is coupled between a second terminal of thefirst coil 407 and a fixed-voltage terminal (such as a ground terminal). Thediode 415 is coupled between the second terminal of thefirst coil 407 and theload 119 of the asynchronous-type buck-boost power converter 400. Theinductive coil 411 is configured to operably sense thefirst coil 407 to provide an inductive signal SS. Theoutput capacitor 117 is coupled between the output terminal of thediode 115 and the first terminal of thefirst coil 407, and configured to operably reduce the noise in the output voltage signal Vout. - In the embodiment of
FIG. 4 , the zerocurrent detection circuit 121 of thePFC circuit 120 is configured to operable detect the inductive signal SS when coupling with theinductive coil 411 to generate the detection signal DS. ThePFC circuit 120 may control the magnitude of the current IL flowing through thefirst coil 407 by controlling the switching operations of thepower switch 113 with the manner described previously to render the waveform of the input current signal Iin to follow the waveform of the input voltage signal Vin, so that the waveform of the input current signal Iin approaches to the sine waveform to thereby increase the power factor while effectively reducing the total harmonic distortion. - The descriptions regarding the operations, implementations, varieties, and related advantages of other corresponding functional blocks in the foregoing
FIG. 1 andFIG. 3 are also applicable to the embodiment ofFIG. 4 . For the sake of brevity, those descriptions will not be repeated here. - In the embodiment of
FIG. 4 , thefeedback circuit 140, thediode 415, and/or theresistance device 430 may be instead integrated into thePFC circuit 120. - As shown in
FIG. 5 , thepower converter 500 comprises therectifier 103, theinput capacitor 105, thefirst coil 407, thefirst power switch 113, asecond power switch 515, theoutput capacitor 417, thePFC circuit 120, theresistance device 430, and thefeedback circuit 140. A first terminal of thefirst coil 407 is coupled with the input voltage signal Vin. Thefirst power switch 113 is coupled between a second terminal of thefirst coil 407 and a fixed-voltage terminal (such as a ground terminal). Thesecond power switch 515 is coupled between the second terminal of thefirst coil 407 and theload 119 of the synchronous-type buck-boost power converter 500. - In the embodiment of
FIG. 5 , thePFC circuit 120 may also utilize the control signal CTL outputted from thetrigger circuit 129 as a first control signal for controlling one of thefirst power switch 113 and thesecond power switch 515, while utilize the inverted signal CTLB outputted from thetrigger circuit 129 as a second control signal for controlling another power switch. ThePFC circuit 120 may control the magnitude of the current IL flowing through thefirst coil 407 by controlling the switching operations of thefirst power switch 113 and thesecond power switch 515 with the manner described previously to render the waveform of the input current signal Iin to follow the waveform of the input voltage signal Vin, so that the waveform of the input current signal Iin approaches to the sine waveform to thereby increase the power factor while effectively reducing the total harmonic distortion. - The descriptions regarding the operations, implementations, varieties, and related advantages of other corresponding functional blocks in the foregoing
FIG. 1 ,FIG. 3 , andFIG. 4 are also applicable to the embodiment ofFIG. 5 . For the sake of brevity, those descriptions will not be repeated here. - In the embodiment of
FIG. 5 , thefirst power switch 113, thesecond power switch 515, thefeedback circuit 140, and/or theresistance device 430 may be integrated into thePFC circuit 120. - As can be appreciated from the foregoing elaborations that the disclosed
PFC circuit 120 effectively reduces the total harmonic distortion and increases the power factor. - Furthermore, the proposed
PFC circuit 120 has a very compact circuitry structure and could be applied in many power converters of different structures, so thePFC circuit 120 has high application flexibility and a very wide application scope. - Certain terms are used throughout the description and the claims to refer to particular components. One skilled in the art appreciates that a component may be referred to as different names. This disclosure does not intend to distinguish between components that differ in name but not in function. In the description and in the claims, the term “comprise” is used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to.” The phrases “be coupled with,” “couples with,” and “coupling with” are intended to compass any indirect or direct connection. Accordingly, if this disclosure mentioned that a first device is coupled with a second device, it means that the first device may be directly or indirectly connected to the second device through electrical connections, wireless communications, optical communications, or other signal connections with/without other intermediate devices or connection means.
- The term “and/or” may comprise any and all combinations of one or more of the associated listed items. In addition, the singular forms “a,” “an,” and “the” herein are intended to comprise the plural forms as well, unless the context clearly indicates otherwise.
- The term “voltage signal” used throughout the description and the claims may be expressed in the format of a current in implementations, and the term “current signal” used throughout the description and the claims may be expressed in the format of a voltage in implementations.
- Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention indicated by the following claims.
Claims (21)
1. A method for controlling a power switch (113) of a flyback power converter (100), the flyback power converter (100) comprising a primary side coil (107), a secondary side coil (109), and an inductive coil (111), wherein the primary side coil (107) is coupled between an input voltage signal (Vin) and the power switch (113), the secondary side coil (109) is configured to operably provide an output voltage signal (Vout) and an output current signal (Iout), the inductive coil (111) is configured to operably sense the primary side coil (107) to generate an inductive signal (SS), and the power switch (113) is coupled between the primary side coil (107) and a fixed-voltage terminal, the method comprising:
detecting the inductive signal (SS) to determine whether a zero current event occurs;
generating an error signal (COMP) corresponding to the output voltage signal (Vout) or the output current signal (Iout) according to a reference signal (Vref);
generating an ramp signal (RAMP) having a slope proportional to a ratio of an on time during which of the power switch (113) is turned on in a previous switching cycle to a time length of the previous switching cycle;
comparing the ramp signal (RAMP) with the error signal (COMP);
turning on the power switch (113) when the zero current event occurs; and
when the ramp signal (RAMP) is greater than or equal to the error signal (COMP), turning off the power switch (113) and rapidly lowering the level of the ramp signal (RAMP).
2. The method of claim 1 , wherein the operation of generating the ramp signal (RAMP) comprises:
generating an adjusted voltage (Vset2) less than a setting voltage (Vset) by multiplying the setting voltage (Vset) by the ratio of the on time during which of the power switch (113) is turned on in the previous switching cycle to the time length of the previous switching cycle;
performing a low-pass filtering operation on the adjusted voltage (Vset2) to generate a filtered signal (VF);
providing a transconductance amplifier (350) configured to operably convert the filtered signal (VF) into a ramp signal (RAMP); and
providing a capacitor (360) configured to be coupled with an output terminal of the transconductance amplifier (350).
3. The method of claim 2 , wherein an on time (Ton) during which the power switch (113) is turned on in each switching cycle is directly proportional to a capacitance value of the capacitor (360) and a voltage value of the error signal (COMP), but is inversely proportional to a voltage value of the adjusted voltage (Vset2) and a transconductance value of the transconductance amplifier (350).
4. The method of claim 3 , wherein the on time (Ton) during which the power switch (113) is turned on in each switching cycle is determined by the following formula:
Ton=(Cramp*Vcomp)/[Vset2*Gm]
Ton=(Cramp*Vcomp)/[Vset2*Gm]
wherein Ton denotes the on time at which the power switch (113) is turned on in each switching cycle, Cramp denotes a capacitance value of the capacitor (360), Vcomp denotes a voltage value of the error signal (COMP), Vset2 denotes a voltage value of the adjusted voltage (Vset2), and Gm denotes a transconductance value of the transconductance amplifier (350).
5. The method of claim 3 , wherein the ratio of the on time during which of the power switch (113) is turned on in the previous switching cycle to the time length of the previous switching cycle is directly proportional to a duty ratio of a control signal (CTL) utilized for controlling the power switch (113).
6. The method of claim 3 , wherein the operation of generating the adjusted voltage (Vset2) comprises:
providing a first switch (310) configured to be coupled between a setting signal input terminal (302) and a node (304), wherein the setting signal input terminal (302) is utilized for receiving the setting voltage (Vset);
providing a second switch (320) configured to be coupled between the node (304) and a fixed-voltage terminal; and
switching the first switch (310) and the second switch (320) alternatively to render the node (304) to provide the adjusted voltage (Vset2).
7. The method of claim 3 , wherein the operation of rapidly lowering the level of the ramp signal (RAMP) comprises:
providing a third switch (370) configured to be coupled between the output terminal of the transconductance amplifier (350) and a fixed-voltage terminal; and
turning on the third switch (370) when the ramp signal (RAMP) is greater than or equal to the error signal (COMP).
8. A method for controlling a power switch (113) of an asynchronous-type buck-boost power converter (400), the asynchronous-type buck-boost power converter (400) comprising a first coil (407), an inductive coil (411), and a diode (415), wherein the first coil (407) is coupled between an input voltage signal (Vin) and the power switch (113), the inductive coil (411) is configured to operably sense the first coil (407) to provide an inductive signal (SS), the power switch (113) is coupled between the first coil (407) and a fixed-voltage terminal, and the diode (415) is coupled between the first coil (407) and a load (119) of the asynchronous-type buck-boost power converter (400), the method comprising:
detecting the inductive signal (SS) to determine whether a zero current event occurs;
generating an error signal (COMP) corresponding to an output voltage signal (Vout) or an output current signal (Iout) of the asynchronous-type buck-boost power converter (400) according to a reference signal (Vref);
generating an ramp signal (RAMP) having a slope proportional to a ratio of an on time during which of the power switch (113) is turned on in a previous switching cycle to a time length of the previous switching cycle;
comparing the ramp signal (RAMP) with the error signal (COMP);
turning on the power switch (113) when the zero current event occurs; and
when the ramp signal (RAMP) is greater than or equal to the error signal (COMP), turning off the power switch (113) and rapidly lowering the level of the ramp signal (RAMP).
9. The method of claim 8 , wherein the operation of generating the ramp signal (RAMP) comprises:
generating an adjusted voltage (Vset2) less than a setting voltage (Vset) by multiplying the setting voltage (Vset) by the ratio of the on time during which of the power switch (113) is turned on in the previous switching cycle to the time length of the previous switching cycle;
performing a low-pass filtering operation on the adjusted voltage (Vset2) to generate a filtered signal (VF);
providing a transconductance amplifier (350) configured to operably convert the filtered signal (VF) into a ramp signal (RAMP); and
providing a capacitor (360) configured to be coupled with an output terminal of the transconductance amplifier (350).
10. The method of claim 9 , wherein an on time (Ton) during which the power switch (113) is turned on in each switching cycle is directly proportional to a capacitance value of the capacitor (360) and a voltage value of the error signal (COMP), but is inversely proportional to a voltage value of the adjusted voltage (Vset2) and a transconductance value of the transconductance amplifier (350).
11. The method of claim 10 , wherein the on time (Ton) during which the power switch (113) is turned on in each switching cycle is determined by the following formula:
Ton=(Cramp*Vcomp)/[Vset2*Gm]
Ton=(Cramp*Vcomp)/[Vset2*Gm]
wherein Ton denotes the on time at which the power switch (113) is turned on in each switching cycle, Cramp denotes a capacitance value of the capacitor (360), Vcomp denotes a voltage value of the error signal (COMP), Vset2 denotes a voltage value of the adjusted voltage (Vset2), and Gm denotes a transconductance value of the transconductance amplifier (350).
12. The method of claim 10 , wherein the ratio of the on time during which of the power switch (113) is turned on in the previous switching cycle to the time length of the previous switching cycle is directly proportional to a duty ratio of a control signal (CTL) utilized for controlling the power switch (113).
13. The method of claim 10 , wherein the operation of generating the adjusted voltage (Vset2) comprises:
providing a first switch (310) configured to be coupled between a setting signal input terminal (302) and a node (304), wherein the setting signal input terminal (302) is utilized for receiving the setting voltage (Vset);
providing a second switch (320) configured to be coupled between the node (304) and a fixed-voltage terminal; and
switching the first switch (310) and the second switch (320) alternatively to render the node (304) to provide the adjusted voltage (Vset2).
14. The method of claim 10 , wherein the operation of rapidly lowering the level of the ramp signal (RAMP) comprises:
providing a third switch (370) configured to be coupled between the output terminal of the transconductance amplifier (350) and a fixed-voltage terminal; and
turning on the third switch (370) when the ramp signal (RAMP) is greater than or equal to the error signal (COMP).
15. A method for controlling a power switch (113) of a synchronous-type buck-boost power converter (500), the synchronous-type buck-boost power converter (500) comprising a first coil (407), an inductive coil (411), and a second power switch (515), wherein the first coil (407) is coupled between an input voltage signal (Vin) and the power switch (113), the inductive coil (411) is configured to operably sense the first coil (407) to provide an inductive signal (SS), the first power switch (113) is coupled between a second terminal of the first coil (407) and a fixed-voltage terminal, and the second power switch (515) is coupled between the second terminal of the first coil (407) and a load (119) of the synchronous-type buck-boost power converter (500), the method comprising:
detecting the inductive signal (SS) to determine whether a zero current event occurs;
generating an error signal (COMP) corresponding to an output voltage signal (Vout) or an output current signal (Iout) of the synchronous-type buck-boost power converter (500) according to a reference signal (Vref);
generating an ramp signal (RAMP) having a slope proportional to a ratio of an on time during which of the power switch (113) is turned on in a previous switching cycle to a time length of the previous switching cycle;
comparing the ramp signal (RAMP) with the error signal (COMP);
turning on the power switch (113) when the zero current event occurs; and
when the ramp signal (RAMP) is greater than or equal to the error signal (COMP), turning off the power switch (113) and rapidly lowering the level of the ramp signal (RAMP).
16. The method of claim 15 , wherein the operation of generating the ramp signal (RAMP) comprises:
generating an adjusted voltage (Vset2) less than a setting voltage (Vset) by multiplying the setting voltage (Vset) by the ratio of the on time during which of the power switch (113) is turned on in the previous switching cycle to the time length of the previous switching cycle;
performing a low-pass filtering operation on the adjusted voltage (Vset2) to generate a filtered signal (VF);
providing a transconductance amplifier (350) configured to operably convert the filtered signal (VF) into a ramp signal (RAMP); and
providing a capacitor (360) configured to be coupled with an output terminal of the transconductance amplifier (350).
17. The method of claim 16 , wherein an on time (Ton) during which the power switch (113) is turned on in each switching cycle is directly proportional to a capacitance value of the capacitor (360) and a voltage value of the error signal (COMP), but is inversely proportional to a voltage value of the adjusted voltage (Vset2) and a transconductance value of the transconductance amplifier (350).
18. The method of claim 17 , wherein an on time (Ton) during which the power switch (113) is turned on in each switching cycle is determined by the following formula:
Ton=(Cramp*Vcomp)/[Vset2*Gm]
Ton=(Cramp*Vcomp)/[Vset2*Gm]
wherein Ton denotes the on time at which the power switch (113) is turned on in each switching cycle, Cramp denotes a capacitance value of the capacitor (360), Vcomp denotes a voltage value of the error signal (COMP), Vset2 denotes a voltage value of the adjusted voltage (Vset2), and Gm denotes a transconductance value of the transconductance amplifier (350).
19. The method of claim 17 , wherein the ratio of the on time during which of the power switch (113) is turned on in the previous switching cycle to the time length of the previous switching cycle is directly proportional to a duty ratio of a control signal (CTL) utilized for controlling the power switch (113).
20. The method of claim 17 , wherein the operation of generating the adjusted voltage (Vset2) comprises:
providing a first switch (310) configured to be coupled between a setting signal input terminal (302) and a node (304), wherein the setting signal input terminal (302) is utilized for receiving the setting voltage (Vset);
providing a second switch (320) configured to be coupled between the node (304) and a fixed-voltage terminal; and
switching the first switch (310) and the second switch (320) alternatively to render the node (304) to provide the adjusted voltage (Vset2).
21. The method of claim 17 , wherein the operation of rapidly lowering the level of the ramp signal (RAMP) comprises:
providing a third switch (370) configured to be coupled between the output terminal of the transconductance amplifier (350) and a fixed-voltage terminal; and
turning on the third switch (370) when the ramp signal (RAMP) is greater than or equal to the error signal (COMP).
Priority Applications (1)
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US15/872,481 US20180145596A1 (en) | 2013-12-05 | 2018-01-16 | Method for conrolling on time of power switch in power converter |
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TW102144716 | 2013-12-05 | ||
TW102144716A TWI499183B (en) | 2013-12-05 | 2013-12-05 | Power factor correction circuit of power converter |
US14/547,870 US9680369B2 (en) | 2013-12-05 | 2014-11-19 | Power factor correction circuit of power converter |
US15/586,976 US20170237353A1 (en) | 2013-12-05 | 2017-05-04 | Method for conrolling on time of power switch in power converter |
US15/872,481 US20180145596A1 (en) | 2013-12-05 | 2018-01-16 | Method for conrolling on time of power switch in power converter |
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US15/586,976 Continuation US20170237353A1 (en) | 2013-12-05 | 2017-05-04 | Method for conrolling on time of power switch in power converter |
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US20180145596A1 true US20180145596A1 (en) | 2018-05-24 |
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US14/547,870 Expired - Fee Related US9680369B2 (en) | 2013-12-05 | 2014-11-19 | Power factor correction circuit of power converter |
US15/586,976 Abandoned US20170237353A1 (en) | 2013-12-05 | 2017-05-04 | Method for conrolling on time of power switch in power converter |
US15/872,481 Abandoned US20180145596A1 (en) | 2013-12-05 | 2018-01-16 | Method for conrolling on time of power switch in power converter |
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US14/547,870 Expired - Fee Related US9680369B2 (en) | 2013-12-05 | 2014-11-19 | Power factor correction circuit of power converter |
US15/586,976 Abandoned US20170237353A1 (en) | 2013-12-05 | 2017-05-04 | Method for conrolling on time of power switch in power converter |
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WO2021179939A1 (en) * | 2020-03-12 | 2021-09-16 | Oppo广东移动通信有限公司 | Power supply circuit and charging device |
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CN105226931B (en) * | 2015-09-25 | 2017-12-12 | 南京理工大学 | Improve the control device of DCM Buck pfc converter PF values |
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US9997993B1 (en) * | 2016-12-12 | 2018-06-12 | National Chung Shan Institute Of Science And Technology | Single-phase bridgeless insulated power factor adjustment circuit |
CN109149931B (en) * | 2018-08-29 | 2019-10-11 | 北京机械设备研究所 | Slope-error compensation circuit for peak value comparison method BUCK converter |
US10763738B1 (en) * | 2019-07-03 | 2020-09-01 | Silanna Asia Pte Ltd | Light load mode entry or exit for power converter |
TWI704839B (en) * | 2019-08-16 | 2020-09-11 | 宏碁股份有限公司 | Driving device |
TWI704755B (en) | 2019-12-20 | 2020-09-11 | 群光電能科技股份有限公司 | Power supply apparatus and method of operating the same |
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Also Published As
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US20170237353A1 (en) | 2017-08-17 |
US20150162821A1 (en) | 2015-06-11 |
US9680369B2 (en) | 2017-06-13 |
TW201524095A (en) | 2015-06-16 |
TWI499183B (en) | 2015-09-01 |
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