US20180082941A1 - Substrate structure and manufacturing method thereof - Google Patents
Substrate structure and manufacturing method thereof Download PDFInfo
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- US20180082941A1 US20180082941A1 US15/390,892 US201615390892A US2018082941A1 US 20180082941 A1 US20180082941 A1 US 20180082941A1 US 201615390892 A US201615390892 A US 201615390892A US 2018082941 A1 US2018082941 A1 US 2018082941A1
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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Definitions
- This invention relates to a substrate structure and a manufacturing method thereof, in particular, to a semiconductor substrate structure and a manufacturing method thereof.
- a chip scale package is a type of integrated circuit package. Originally, the CSP was the acronym for chip-size packaging. Since only a few packages are chip size, the meaning of the acronym was adapted to chip-scale packaging. The CSP is applied with the smart phone, the tablet, the laptop or the miniature camera to operate under high frequency and high speed processing.
- the substrate in the CSP is made of fiberglass that is easy to wrap and deformation.
- the blind holes of the substrate are used for the different layers to electrically connect to each other that are usually made by laser drilling or mechanical drilling. It is difficult to narrow the aperture of the blind hole by laser drilling or mechanical drilling and cannot achieve the circuit with the fine pitch.
- FIG. 15A depicts a conventional package structure 4 using the wire bonding technology.
- the package structure 4 includes a substrate 41 , a chip 42 , an electrical conductive layer 43 , an electrical conductive wire 45 and a solder ball 46 .
- a first surface of the substrate 41 has at least an electrode pad 411 .
- the electrical conductive layer 43 through the substrate 41 via a through hole so that the both side of the substrate 41 could be electrically connected via the electrical conductive layer 43 .
- the chip 42 is disposed on the first surface of the substrate 41 .
- the electrical conductive wire 45 is electrically connected to the chip 42 and the electrode pad 411 .
- the solder ball 46 is electrically connected to the electrical conductive layer 43 that is disposed on a second surface, which is opposite to the first surface of the substrate 41 . It is easy to result drawbacks as mentioned above due to the material of the substrate 41 is most used the fiberglass, and the blind holes are usually made by laser drilling or mechanical drilling.
- FIG. 15B depicts another conventional package structure 5 .
- the package structure 5 includes a substrate 51 , a chip 52 , an electrical conductive adhesive layer 53 , a dielectric layer 54 , a conductive wiring layer 55 , a blind hole 56 and a through hole 57 .
- the chip 52 is disposed on a surface of the substrate 51 .
- the dielectric layer 54 has an opening to expose a plurality of electrode pads 521 of the chip 52 .
- the dielectric layer 54 covers a part of the chip 52 , the electrical conductive adhesive layer 53 and the exposed surface of the substrate 51 .
- the conductive wiring layer 55 is disposed on a surface of dielectric layer 54 , which is far away from the substrate 51 .
- a part of the conductive wiring layer 55 is electrically connected to the electrode pads 521 of the chip 52 via the blind hole 56 .
- the other part of the conductive wiring layer 55 is electrically connected to the electrode pads 521 of the chip 52 via the through hole 57 . It is easy to result drawbacks as mentioned above due to the blind hole 56 and the through hole 57 are usually made by laser drilling or mechanical drilling.
- the present invention is to provide a substrate structure and its manufacturing method having rigidity and heat dissipation and meeting the fine line spacing, high-density, thinning tendency, low-cost and high electric characteristics.
- the present invention is to provide a substrate structure.
- the substrate structure comprises a metal substrate, a first connection layer, a metal core layer, a second connection layer, an internal component and a dielectric material layer.
- the metal core layer having an opening is disposed on a first surface of the first connection layer.
- the second connection layer is disposed on the first surface of the metal substrate and located in the opening.
- the internal component having a plurality of electrode pads is disposed on the second connection layer and located in the opening.
- the dielectric material layer is disposed on the first surface of the metal substrate to partially cover the first and second connection layers, the metal core layer and the internal component.
- the metal core layer is electrically connected to one of the electrode pads via the metal substrate, the first and the second connection layers.
- the present invention is to provide a manufacturing method of substrate structure.
- the manufacturing method comprises the steps of: providing a metal substrate; providing an internal component having a plurality of electrode pads; forming a first connection layer and a second connection layer on a first surface of the metal substrate; forming a metal core layer having an opening on the first connection layer; disposing the internal component on the second connection layer and in the opening; forming a dielectric material layer on the first surface of the metal substrate to cover the first connection layer, the metal core layer, the second connection layer and the internal component; and exposing a surface of the metal core layer and a surface of parts of the electrode pads.
- FIG. 1 is a schematic diagram showing a substrate structure according to the first embodiment of the present invention.
- FIG. 2 is a schematic diagram showing a part of the substrate structure according to the first embodiment of the present invention.
- FIG. 3 is a sectional view of A-A′ line of the FIG. 1 .
- FIG. 4 is a schematic diagram showing view of a substrate structure according to the second embodiment of the present invention.
- FIG. 5 is a sectional view of B-B′ line of the FIG. 4 .
- FIG. 6 is a schematic diagram showing view of a substrate structure according to the third embodiment the present invention.
- FIG. 7 is a sectional view of C-C′ line of the FIG. 6 .
- FIG. 8 is a flow chart showing a manufacturing method of a substrate structure according to the fourth embodiment of the present invention.
- FIGS. 9A-9G are schematic diagrams showing the manufacturing method of the substrate structure according to FIG. 8 .
- FIG. 10 is a flow chart showing a manufacturing method of a substrate structure according to the fifth embodiment of the present invention.
- FIG. 11 is a flow chart showing a manufacturing method of a substrate structure according to the sixth embodiment of the present invention.
- FIG. 12 is a flow chart showing a manufacturing method of a substrate structure according to the seventh embodiment of the present invention.
- FIGS. 13A-13F are schematic diagrams showing the manufacturing method of the substrate structure according to FIG. 12 .
- FIG. 14 is a flow chart of forming a dielectric material layer.
- FIGS. 15A-15B are schematic diagrams showing the conventional package structure.
- FIG. 1 , FIG. 2 and FIG. 3 depict a first embodiment of the present invention.
- FIG. 1 is a schematic diagram of a substrate structure 1
- FIG. 2 is a schematic diagram of a part of substrate structure 1
- FIG. 3 is a sectional diagram of A-A′ line of FIG. 1 .
- the substrate structure 1 comprises a metal substrate 101 , a first connection layer 103 , a second connection layer 105 , a metal core layer 107 , an internal component 109 , a dielectric material layer 111 , a conductive pillar layer 113 and a conductive wiring layer 115 .
- the metal substrate 101 has a first surface 1011 and a second surface 1013 .
- the first connection layer 103 has a surface 1031 .
- the second connection layer 105 has a surface 1051 .
- the metal core layer 107 has an opening 1071 .
- the internal component 109 has a plurality of electrode pads 1091 , a first surface 1093 and a
- the metal core layer 107 is for electrical conductivity and provides characteristics of rigidity and heat dissipation.
- the materials are selected from cooper, nickel, stainless steel or a combination thereof, preferably selected from stainless steel or Ni—Cu alloy on the surface of stainless steel.
- the dielectric material layer 111 is an organic resin without glass fiber or a molding compound layer, which has novolac-based resin, epoxy-based resin, silicone-based resin or other suitable molding compound.
- the material of the dielectric material layer 111 is molding compound, which has characteristics of higher heat dissipation and lower expansion coefficient.
- the materials of metal substrate 101 are selected from aluminum, copper, nickel, stainless steel or a combination thereof.
- the internal component 109 has three electrode pads 1091 . More specifically, one of the electrode pads 1091 is disposed on the first surface 1093 of the internal component 109 , and two of the electrode pads 1091 are disposed on the second surface 1095 of the internal component 109 .
- the internal component could have any number of the electrode pads, and the electrode pads could be disposed on either the first surface 1011 or the second surface 1013 of the metal substrate 101 .
- the shape of the electrode pads may be circular, rectangle, L-shaped or polygon.
- the conductive pillar layer 113 has four conductive pillars.
- the conductive pillar layer 113 could have any number of the conductive pillars according to the function and the type of the substrate structure 1 .
- the shape of the conductive pillars may be circular, rectangle, L-shaped or polygon.
- the first connection layer 103 is disposed on the first surface 1011 of the metal substrate 101 .
- the second connection 105 is disposed on the first surface 1011 of the metal substrate 101 and located in the opening 1071 of the metal core layer 107 .
- the materials of the first connection layer 103 and the second connection layer 105 have characteristics of electrical conductivity and thermal conductivity, which may be copper, silver, nickel or a combination thereof.
- the metal core layer 107 is disposed on the surface 1031 of the first connection layer 103 .
- the internal component 109 is located in the opening 1071 of the metal core layer 107 and disposed on the surface 1051 of the second connection layer 105 .
- the conductive pillar layer 113 is disposed on the metal core layer 107 and on the electrode pad 1091 , which is disposed on the second surface 1095 of the internal component 109 .
- the dielectric material layer 111 is disposed on the first surface 1011 of the metal substrate 101 so as to partially cover the first connection layer 103 , the metal core layer 107 , the second connection layer 105 , the internal component 109 and the conductive pillar layer 113 .
- the conductive wiring layer 115 is disposed on the dielectric material layer 111 and on the conductive pillar layer 113 .
- the first connection layer 103 may be disposed on the first surface 1011 of the metal substrate 101 partly or entirely.
- the first connection layer 103 could be patterned by photo lithography process or laser etching process.
- the metal core layer 107 may be electrically connected to one of the electrode pads 1091 via the first connection layer 103 , metal substrate 101 and the second connection layer 105 . More detailed, the metal core layer 107 is electrically connected to one of the electrode pads 1091 , which is disposed on the first surface 1093 of the internal component 109 , via the first connection layer 103 , the metal substrate 101 and the second connection layer 105 . In addition, the conductive wiring layer 115 is electrically connected to the metal core layer 107 and the electrode pad 1091 , which is disposed on the second surface 1095 of the internal component 109 , via the conductive pillar layer 113 .
- the metal core layer 107 may be formed by a plurality of independent metal blocks.
- the independent metal block could be an electrode individually, a source, a drain, a gate, an emitter, a base or a collector of a semiconductor.
- the metal core layer 107 may be a plate, which has a flat surface without patterned.
- the layers e.g., dielectric material layer, conductive pillar layer or metal connection layer
- the electric components could be disposed on the conductive wiring layer 115 .
- FIG. 4 and FIG. 5 are showing a substrate structure 2 according to the second embodiment of the present invention.
- the substrate structure 2 is similar to the substrate structure 1 of the first embodiment, wherein the substrate structure 2 further comprises a thermal conductive insulation layer 201 , which is disposed on the second surface 1013 of the metal substrate 101 .
- FIG. 6 and FIG. 7 are showing a substrate structure 3 according to the third embodiment of the present invention.
- the substrate structure 3 is similar to the substrate structure 2 of the second embodiment in the present invention.
- the substrate structure 3 further comprises a thermal conductive insulation layer 201 , which is disposed on a thermal conductive plate 301 .
- FIG. 8 is a flow chart showing a manufacturing method of a substrate structure according to the fourth embodiment of the present invention.
- the manufacturing method may be utilized to make the substrate structure 1 of the first embodiment.
- step 801 is executed to provide a metal substrate 101 .
- the materials of the metal substrate 101 are selected from aluminum, copper, nickel, stainless steel or a combination thereof.
- Step 803 is executed to provide an internal component having a plurality of electrode pads. (Not shown in figured)
- step 805 is executed to form a first connection layer 103 and a second connection layer 105 on a first surface 1011 of the metal substrate 101 .
- step 807 is executed to form a metal core layer 107 having an opening 1071 on a surface 1031 of the first connection layer 103 .
- step 809 is executed to dispose the internal component 109 on a surface 1051 of the second connection layer 105 and in the opening 1071 of the metal core layer 107 .
- step 811 is executed to form a dielectric material layer 111 on the first surface 1011 of the metal substrate 101 .
- the dielectric material layer 111 is partially covering the first connection layer 103 , the metal core layer 107 , the second connection layer 105 and the internal component 109 .
- step 813 is executed to expose a surface of the metal core layer 107 and a surface of parts of the electrode pads 1091 .
- step 815 is executed to form a conductive pillar layer 113 on the surface of the metal core layer 107 and the surface of parts of the electrode pads 1091 .
- step 817 is executed to form a conductive wiring layer 115 on the dielectric material layer 111 and the conductive pillar layer 113 so as to form the substrate structure 1 as shown in FIG. 3 .
- FIG. 10 is a flow chart showing a manufacturing method of a substrate structure according to the fifth embodiment of the present invention.
- the manufacturing method may be utilized to make the substrate structure 2 of the second embodiment.
- step 1001 to step 1017 is similar to step 801 to step 817 .
- step 1019 is executed to form a thermal conductive insulation layer 201 on the second surface 1013 of the metal substrate 101 so as to form the substrate structure 2 as shown in FIG. 5 .
- FIG. 11 is a flow chart showing a manufacturing method of a substrate structure according to the sixth embodiment of the present invention.
- the manufacturing method may be utilized to make the substrate structure 3 of the third embodiment.
- step 1101 to step 1119 is similar to step 1001 to step 1019 .
- step 1121 is executed to form a thermal conductive plate 301 on the thermal conductive insulation layer 201 so as to form the substrate structure 3 as shown in FIG. 7 .
- FIG. 12 is a flow chart showing a manufacturing method of a substrate structure according to the seventh embodiment of the present invention.
- the manufacturing method may be utilized to make the substrate structure 1 of the first embodiment.
- step 1201 is executed to provide a metal substrate 101 .
- the materials of the metal substrate 101 are selected from aluminum, copper, nickel, stainless steel or a combination thereof.
- Step 1203 is executed to provide an internal component having a plurality of electrode pads and at least a conductive pillar. (Not shown in figure)
- step 1205 is executed to form a first connection layer 103 and a second connection layer 105 on a first surface 1011 of the metal substrate 101 .
- step 1207 is executed to form a metal core layer 107 , which has an opening 1071 , on a surface 1031 of the first connection layer 103 , and to form at least an second conductive pillar 113 b on the surface 1031 , which is far away from the first connection layer 103 of the metal core layer 107 .
- step 1209 is executed to dispose the internal component 109 with the electrode pads 1091 and the conductive pillars 113 a on a surface 1051 of the second connection layer 105 and in the opening 1071 of the metal core layer 107 .
- the conductive pillar 113 a and the conductive pillar 113 b consist of the conductive pillar layer 113 of the first embodiment, and the conductive pillar layer can be made by method of electroplating or non-electroplating.
- step 1211 is executed to form a dielectric material layer 111 on the first surface 1011 of the metal substrate 101 , and to partially cover the first connection layer 103 , the metal core layer 107 , the second connection layer 105 and the internal component 109 .
- the height of the conductive pillar 113 a and the height of the conductive pillar 113 b may not equal to each other.
- step 1213 is executed to expose the conductive pillar 113 a and the conductive pillar 113 b , which are formed on the surface of the metal core layer 107 and the electrode pads 1091 .
- the conductive pillar 113 a and the conductive pillar 113 b are exposed after milling the dielectric material layer 111 .
- step 1215 is executed to form a conductive wiring layer 115 on the dielectric material layer 111 , the conductive pillar 113 a and the conductive pillar 113 b of the conductive pillar layer so as to form the substrate structure 1 as shown in FIG. 3 .
- steps 811 , 1011 , 1111 and 1211 for forming the dielectric material layer further includes the following steps.
- step 1401 is providing a molding compound material.
- step 1403 is heating the molding compound material into a liquid molding compound material.
- Step 1405 is injecting the liquid molding compound material to cover at least one of the first connection layer 103 , the metal core layer 107 , the second connection layer 105 and the internal component 109 .
- Step 1407 is curing the liquid molding compounding to form a molding compound layer.
- the molding compound layer is the dielectric component layer 111 .
- the substrate structure and its manufacturing method of the present invention utilizes the metal substrate to replace the conventional fiberglass substrate to improve the structure rigidity.
- the metal substrate may provide the advantage of good conductivity, high thermal efficiency and EMI protection.
- the metal core layer and the conductive pillar layer also can improve the structure rigidity.
- the manufacturing method of the substrate structure abandons to use the method of laser drilling and the mechanical drilling so as to reduce the labor hour and the cost. Therefore, the substrate structure and its manufacturing method of the present invention that has the advantage of higher rigidity, higher heat dissipation and meeting the fine line spacing, high-density, thinning tendency, low cost and high electric characteristics.
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Abstract
Description
- This Non-provisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No. 105130268 filed in Taiwan on Sep. 20, 2016, the entire contents of which are hereby incorporated by reference.
- This invention relates to a substrate structure and a manufacturing method thereof, in particular, to a semiconductor substrate structure and a manufacturing method thereof.
- In recent years, users prefer electronic products with compact size, high performance and versatility. Thus, electronics manufacturers have to accommodate more components in a limited space of an integrated circuit (IC) to achieve high density and miniaturization. As a result, electronics manufacturers advance a new IC package for embedding components in a substrate to reduce the package size and the connection path between the components and the substrate.
- A chip scale package (CSP) is a type of integrated circuit package. Originally, the CSP was the acronym for chip-size packaging. Since only a few packages are chip size, the meaning of the acronym was adapted to chip-scale packaging. The CSP is applied with the smart phone, the tablet, the laptop or the miniature camera to operate under high frequency and high speed processing.
- In general, the substrate in the CSP is made of fiberglass that is easy to wrap and deformation. In addition, the blind holes of the substrate are used for the different layers to electrically connect to each other that are usually made by laser drilling or mechanical drilling. It is difficult to narrow the aperture of the blind hole by laser drilling or mechanical drilling and cannot achieve the circuit with the fine pitch.
-
FIG. 15A depicts aconventional package structure 4 using the wire bonding technology. Thepackage structure 4 includes asubstrate 41, achip 42, an electricalconductive layer 43, an electricalconductive wire 45 and asolder ball 46. A first surface of thesubstrate 41 has at least anelectrode pad 411. The electricalconductive layer 43 through thesubstrate 41 via a through hole so that the both side of thesubstrate 41 could be electrically connected via the electricalconductive layer 43. Thechip 42 is disposed on the first surface of thesubstrate 41. The electricalconductive wire 45 is electrically connected to thechip 42 and theelectrode pad 411. Thesolder ball 46 is electrically connected to the electricalconductive layer 43 that is disposed on a second surface, which is opposite to the first surface of thesubstrate 41. It is easy to result drawbacks as mentioned above due to the material of thesubstrate 41 is most used the fiberglass, and the blind holes are usually made by laser drilling or mechanical drilling. - Moreover,
FIG. 15B depicts anotherconventional package structure 5. Thepackage structure 5 includes asubstrate 51, achip 52, an electrical conductiveadhesive layer 53, adielectric layer 54, aconductive wiring layer 55, ablind hole 56 and a throughhole 57. Thechip 52 is disposed on a surface of thesubstrate 51. Thedielectric layer 54 has an opening to expose a plurality ofelectrode pads 521 of thechip 52. Thedielectric layer 54 covers a part of thechip 52, the electrical conductiveadhesive layer 53 and the exposed surface of thesubstrate 51. Theconductive wiring layer 55 is disposed on a surface ofdielectric layer 54, which is far away from thesubstrate 51. A part of theconductive wiring layer 55 is electrically connected to theelectrode pads 521 of thechip 52 via theblind hole 56. The other part of theconductive wiring layer 55 is electrically connected to theelectrode pads 521 of thechip 52 via the throughhole 57. It is easy to result drawbacks as mentioned above due to theblind hole 56 and the throughhole 57 are usually made by laser drilling or mechanical drilling. - Therefore, it is an important subject to provide a substrate structure and its manufacturing method that has the advantage of higher rigidity, higher heat dissipation and meeting the fine line spacing, high-density, thinning tendency, low cost and high electric characteristics.
- In view of the foregoing, the present invention is to provide a substrate structure and its manufacturing method having rigidity and heat dissipation and meeting the fine line spacing, high-density, thinning tendency, low-cost and high electric characteristics.
- To achieve the above, the present invention is to provide a substrate structure. The substrate structure comprises a metal substrate, a first connection layer, a metal core layer, a second connection layer, an internal component and a dielectric material layer. The metal core layer having an opening is disposed on a first surface of the first connection layer. The second connection layer is disposed on the first surface of the metal substrate and located in the opening. The internal component having a plurality of electrode pads is disposed on the second connection layer and located in the opening. The dielectric material layer is disposed on the first surface of the metal substrate to partially cover the first and second connection layers, the metal core layer and the internal component. The metal core layer is electrically connected to one of the electrode pads via the metal substrate, the first and the second connection layers.
- To achieve the above, the present invention is to provide a manufacturing method of substrate structure. The manufacturing method comprises the steps of: providing a metal substrate; providing an internal component having a plurality of electrode pads; forming a first connection layer and a second connection layer on a first surface of the metal substrate; forming a metal core layer having an opening on the first connection layer; disposing the internal component on the second connection layer and in the opening; forming a dielectric material layer on the first surface of the metal substrate to cover the first connection layer, the metal core layer, the second connection layer and the internal component; and exposing a surface of the metal core layer and a surface of parts of the electrode pads.
- The detailed technology and preferred embodiments implemented for the subject invention are described in the following paragraphs accompanying the appended drawings for people skilled in this field to well appreciate the features of the claimed invention.
- The parts in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of at least one embodiment. In the drawings, like reference numerals designate corresponding parts throughout the various diagrams, and all the diagrams are schematic.
-
FIG. 1 is a schematic diagram showing a substrate structure according to the first embodiment of the present invention. -
FIG. 2 is a schematic diagram showing a part of the substrate structure according to the first embodiment of the present invention. -
FIG. 3 is a sectional view of A-A′ line of theFIG. 1 . -
FIG. 4 is a schematic diagram showing view of a substrate structure according to the second embodiment of the present invention. -
FIG. 5 is a sectional view of B-B′ line of theFIG. 4 . -
FIG. 6 is a schematic diagram showing view of a substrate structure according to the third embodiment the present invention. -
FIG. 7 is a sectional view of C-C′ line of theFIG. 6 . -
FIG. 8 is a flow chart showing a manufacturing method of a substrate structure according to the fourth embodiment of the present invention. -
FIGS. 9A-9G are schematic diagrams showing the manufacturing method of the substrate structure according toFIG. 8 . -
FIG. 10 is a flow chart showing a manufacturing method of a substrate structure according to the fifth embodiment of the present invention. -
FIG. 11 is a flow chart showing a manufacturing method of a substrate structure according to the sixth embodiment of the present invention. -
FIG. 12 is a flow chart showing a manufacturing method of a substrate structure according to the seventh embodiment of the present invention -
FIGS. 13A-13F are schematic diagrams showing the manufacturing method of the substrate structure according toFIG. 12 . -
FIG. 14 is a flow chart of forming a dielectric material layer. -
FIGS. 15A-15B are schematic diagrams showing the conventional package structure. - Reference will now be made to the drawings to describe various inventive embodiments of the present disclosure in detail, wherein like numerals refer to like elements throughout.
-
FIG. 1 ,FIG. 2 andFIG. 3 depict a first embodiment of the present invention.FIG. 1 is a schematic diagram of asubstrate structure 1 andFIG. 2 is a schematic diagram of a part ofsubstrate structure 1.FIG. 3 is a sectional diagram of A-A′ line ofFIG. 1 . Thesubstrate structure 1 comprises ametal substrate 101, afirst connection layer 103, asecond connection layer 105, ametal core layer 107, aninternal component 109, adielectric material layer 111, aconductive pillar layer 113 and aconductive wiring layer 115. Themetal substrate 101 has afirst surface 1011 and asecond surface 1013. Thefirst connection layer 103 has asurface 1031. Thesecond connection layer 105 has asurface 1051. Themetal core layer 107 has anopening 1071. Theinternal component 109 has a plurality ofelectrode pads 1091, afirst surface 1093 and asecond surface 1095. - The
metal core layer 107 is for electrical conductivity and provides characteristics of rigidity and heat dissipation. The materials are selected from cooper, nickel, stainless steel or a combination thereof, preferably selected from stainless steel or Ni—Cu alloy on the surface of stainless steel. - The
dielectric material layer 111 is an organic resin without glass fiber or a molding compound layer, which has novolac-based resin, epoxy-based resin, silicone-based resin or other suitable molding compound. In the embodiment, the material of thedielectric material layer 111 is molding compound, which has characteristics of higher heat dissipation and lower expansion coefficient. The materials ofmetal substrate 101 are selected from aluminum, copper, nickel, stainless steel or a combination thereof. In the embodiment, theinternal component 109 has threeelectrode pads 1091. More specifically, one of theelectrode pads 1091 is disposed on thefirst surface 1093 of theinternal component 109, and two of theelectrode pads 1091 are disposed on thesecond surface 1095 of theinternal component 109. However, in the other embodiments, the internal component could have any number of the electrode pads, and the electrode pads could be disposed on either thefirst surface 1011 or thesecond surface 1013 of themetal substrate 101. The shape of the electrode pads may be circular, rectangle, L-shaped or polygon. Similarly, in the present embodiment, theconductive pillar layer 113 has four conductive pillars. In the other embodiments, theconductive pillar layer 113 could have any number of the conductive pillars according to the function and the type of thesubstrate structure 1. The shape of the conductive pillars may be circular, rectangle, L-shaped or polygon. - The
first connection layer 103 is disposed on thefirst surface 1011 of themetal substrate 101. Thesecond connection 105 is disposed on thefirst surface 1011 of themetal substrate 101 and located in theopening 1071 of themetal core layer 107. The materials of thefirst connection layer 103 and thesecond connection layer 105 have characteristics of electrical conductivity and thermal conductivity, which may be copper, silver, nickel or a combination thereof. Themetal core layer 107 is disposed on thesurface 1031 of thefirst connection layer 103. Theinternal component 109 is located in theopening 1071 of themetal core layer 107 and disposed on thesurface 1051 of thesecond connection layer 105. Theconductive pillar layer 113 is disposed on themetal core layer 107 and on theelectrode pad 1091, which is disposed on thesecond surface 1095 of theinternal component 109. Thedielectric material layer 111 is disposed on thefirst surface 1011 of themetal substrate 101 so as to partially cover thefirst connection layer 103, themetal core layer 107, thesecond connection layer 105, theinternal component 109 and theconductive pillar layer 113. Theconductive wiring layer 115 is disposed on thedielectric material layer 111 and on theconductive pillar layer 113. - To be noted, the
first connection layer 103 may be disposed on thefirst surface 1011 of themetal substrate 101 partly or entirely. In other words, thefirst connection layer 103 could be patterned by photo lithography process or laser etching process. - The
metal core layer 107 may be electrically connected to one of theelectrode pads 1091 via thefirst connection layer 103,metal substrate 101 and thesecond connection layer 105. More detailed, themetal core layer 107 is electrically connected to one of theelectrode pads 1091, which is disposed on thefirst surface 1093 of theinternal component 109, via thefirst connection layer 103, themetal substrate 101 and thesecond connection layer 105. In addition, theconductive wiring layer 115 is electrically connected to themetal core layer 107 and theelectrode pad 1091, which is disposed on thesecond surface 1095 of theinternal component 109, via theconductive pillar layer 113. - To be noted, the
metal core layer 107 may be formed by a plurality of independent metal blocks. The independent metal block could be an electrode individually, a source, a drain, a gate, an emitter, a base or a collector of a semiconductor. In addition, themetal core layer 107 may be a plate, which has a flat surface without patterned. - In other embodiment, the layers (e.g., dielectric material layer, conductive pillar layer or metal connection layer) or the electric components could be disposed on the
conductive wiring layer 115. -
FIG. 4 andFIG. 5 are showing asubstrate structure 2 according to the second embodiment of the present invention. Thesubstrate structure 2 is similar to thesubstrate structure 1 of the first embodiment, wherein thesubstrate structure 2 further comprises a thermalconductive insulation layer 201, which is disposed on thesecond surface 1013 of themetal substrate 101. -
FIG. 6 andFIG. 7 are showing asubstrate structure 3 according to the third embodiment of the present invention. Thesubstrate structure 3 is similar to thesubstrate structure 2 of the second embodiment in the present invention. In the third embodiment, thesubstrate structure 3 further comprises a thermalconductive insulation layer 201, which is disposed on a thermalconductive plate 301. -
FIG. 8 is a flow chart showing a manufacturing method of a substrate structure according to the fourth embodiment of the present invention. In this embodiment, the manufacturing method may be utilized to make thesubstrate structure 1 of the first embodiment. - Referring to
FIG. 8 andFIG. 9A ,step 801 is executed to provide ametal substrate 101. The materials of themetal substrate 101 are selected from aluminum, copper, nickel, stainless steel or a combination thereof. Step 803 is executed to provide an internal component having a plurality of electrode pads. (Not shown in figured) - Referring to
FIG. 8 andFIG. 9B ,step 805 is executed to form afirst connection layer 103 and asecond connection layer 105 on afirst surface 1011 of themetal substrate 101. - Referring to
FIG. 8 andFIG. 9C ,step 807 is executed to form ametal core layer 107 having anopening 1071 on asurface 1031 of thefirst connection layer 103. - Referring to
FIG. 8 andFIG. 9D ,step 809 is executed to dispose theinternal component 109 on asurface 1051 of thesecond connection layer 105 and in theopening 1071 of themetal core layer 107. - Referring to
FIG. 8 andFIG. 9E ,step 811 is executed to form adielectric material layer 111 on thefirst surface 1011 of themetal substrate 101. Thedielectric material layer 111 is partially covering thefirst connection layer 103, themetal core layer 107, thesecond connection layer 105 and theinternal component 109. - Referring to
FIG. 8 andFIG. 9F ,step 813 is executed to expose a surface of themetal core layer 107 and a surface of parts of theelectrode pads 1091. - Referring to
FIG. 8 andFIG. 9G ;step 815 is executed to form aconductive pillar layer 113 on the surface of themetal core layer 107 and the surface of parts of theelectrode pads 1091. - Referring to
FIG. 8 ,step 817 is executed to form aconductive wiring layer 115 on thedielectric material layer 111 and theconductive pillar layer 113 so as to form thesubstrate structure 1 as shown inFIG. 3 . -
FIG. 10 is a flow chart showing a manufacturing method of a substrate structure according to the fifth embodiment of the present invention. In this embodiment, the manufacturing method may be utilized to make thesubstrate structure 2 of the second embodiment. In the embodiment,step 1001 to step 1017 is similar to step 801 to step 817. - Referring to
FIG. 10 ,step 1019 is executed to form a thermalconductive insulation layer 201 on thesecond surface 1013 of themetal substrate 101 so as to form thesubstrate structure 2 as shown inFIG. 5 . -
FIG. 11 is a flow chart showing a manufacturing method of a substrate structure according to the sixth embodiment of the present invention. In this embodiment, the manufacturing method may be utilized to make thesubstrate structure 3 of the third embodiment. In the embodiment,step 1101 to step 1119 is similar to step 1001 to step 1019. - Referring to
FIG. 11 ,step 1121 is executed to form a thermalconductive plate 301 on the thermalconductive insulation layer 201 so as to form thesubstrate structure 3 as shown inFIG. 7 . -
FIG. 12 is a flow chart showing a manufacturing method of a substrate structure according to the seventh embodiment of the present invention. In this embodiment, the manufacturing method may be utilized to make thesubstrate structure 1 of the first embodiment. - Referring to
FIG. 12 andFIG. 13A ,step 1201 is executed to provide ametal substrate 101. Wherein, the materials of themetal substrate 101 are selected from aluminum, copper, nickel, stainless steel or a combination thereof.Step 1203 is executed to provide an internal component having a plurality of electrode pads and at least a conductive pillar. (Not shown in figure) - Referring to
FIG. 12 andFIG. 13B ,step 1205 is executed to form afirst connection layer 103 and asecond connection layer 105 on afirst surface 1011 of themetal substrate 101. - Referring to
FIG. 12 andFIG. 13C ,step 1207 is executed to form ametal core layer 107, which has anopening 1071, on asurface 1031 of thefirst connection layer 103, and to form at least an secondconductive pillar 113 b on thesurface 1031, which is far away from thefirst connection layer 103 of themetal core layer 107. - Referring to
FIG. 12 andFIG. 13D ,step 1209 is executed to dispose theinternal component 109 with theelectrode pads 1091 and theconductive pillars 113 a on asurface 1051 of thesecond connection layer 105 and in theopening 1071 of themetal core layer 107. In the present embodiment, theconductive pillar 113 a and theconductive pillar 113 b consist of theconductive pillar layer 113 of the first embodiment, and the conductive pillar layer can be made by method of electroplating or non-electroplating. - Referring to
FIG. 12 andFIG. 13E ,step 1211 is executed to form adielectric material layer 111 on thefirst surface 1011 of themetal substrate 101, and to partially cover thefirst connection layer 103, themetal core layer 107, thesecond connection layer 105 and theinternal component 109. In the embodiment, the height of theconductive pillar 113 a and the height of theconductive pillar 113 b may not equal to each other. - Referring to
FIG. 12 andFIG. 13F ,step 1213 is executed to expose theconductive pillar 113 a and theconductive pillar 113 b, which are formed on the surface of themetal core layer 107 and theelectrode pads 1091. In the embodiment, theconductive pillar 113 a and theconductive pillar 113 b are exposed after milling thedielectric material layer 111. - Referring to
FIG. 12 ,step 1215 is executed to form aconductive wiring layer 115 on thedielectric material layer 111, theconductive pillar 113 a and theconductive pillar 113 b of the conductive pillar layer so as to form thesubstrate structure 1 as shown inFIG. 3 . - Additionally, steps 811, 1011, 1111 and 1211 for forming the dielectric material layer further includes the following steps. As shown in
FIG. 14 ,step 1401 is providing a molding compound material.Step 1403 is heating the molding compound material into a liquid molding compound material.Step 1405 is injecting the liquid molding compound material to cover at least one of thefirst connection layer 103, themetal core layer 107, thesecond connection layer 105 and theinternal component 109.Step 1407 is curing the liquid molding compounding to form a molding compound layer. In other words, the molding compound layer is thedielectric component layer 111. - As mentioned above, the substrate structure and its manufacturing method of the present invention utilizes the metal substrate to replace the conventional fiberglass substrate to improve the structure rigidity. In addition, the metal substrate may provide the advantage of good conductivity, high thermal efficiency and EMI protection. Moreover, the metal core layer and the conductive pillar layer also can improve the structure rigidity. Furthermore, the manufacturing method of the substrate structure abandons to use the method of laser drilling and the mechanical drilling so as to reduce the labor hour and the cost. Therefore, the substrate structure and its manufacturing method of the present invention that has the advantage of higher rigidity, higher heat dissipation and meeting the fine line spacing, high-density, thinning tendency, low cost and high electric characteristics.
- Even though numerous characteristics and advantages of certain inventive embodiments have been set out in the foregoing description, together with details of the structures and functions of the embodiments, the disclosure is illustrative only. Changes may be made in detail, especially in matters of arrangement of parts, within the principles of the present disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
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