US20180068947A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- US20180068947A1 US20180068947A1 US15/449,493 US201715449493A US2018068947A1 US 20180068947 A1 US20180068947 A1 US 20180068947A1 US 201715449493 A US201715449493 A US 201715449493A US 2018068947 A1 US2018068947 A1 US 2018068947A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 239000004020 conductor Substances 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims 5
- KTUFNOKKBVMGRW-UHFFFAOYSA-N imatinib Chemical compound C1CN(C)CCN1CC1=CC=C(C(=O)NC=2C=C(NC=3N=C(C=CN=3)C=3C=NC=CC=3)C(C)=CC=2)C=C1 KTUFNOKKBVMGRW-UHFFFAOYSA-N 0.000 description 38
- 239000010410 layer Substances 0.000 description 34
- 239000000758 substrate Substances 0.000 description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 230000015556 catabolic process Effects 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
Definitions
- Embodiments hereof relate to a semiconductor device.
- An anti-fuse element utilizing a MOSFET structure is sometimes provided in a semiconductor device.
- a gate electrode and a semiconductor substrate are insulated from each other by a gate insulating film in an initial state, however, when breakdown occurs in the gate insulating film by applying a predetermined voltage thereacross, the gate electrode and the semiconductor substrate are electrically connected to each other. According to this, for example, a redundant circuit becomes available.
- FIG. 1A is a top view showing a semiconductor device according to a first embodiment
- FIG. 1B is a sectional view taken along a line A-A′ shown in FIG. 1A ;
- FIG. 2 is a sectional view showing a region B in FIG. 1B ;
- FIGS. 3A to 4C are sectional views showing a method for manufacturing a semiconductor device according to the first embodiment
- FIG. 5A is a top view showing a semiconductor device according to a second embodiment
- FIG. 5B is a sectional view taken along a line D-D′ shown in FIG. 5A ;
- FIG. 6A is a top view showing a semiconductor device according to a third embodiment, and FIG. 6B is a sectional view taken along a line E-E′ shown in FIG. 6A ;
- FIG. 7A is a top view showing a semiconductor device according to a fourth embodiment, and FIG. 7B is a sectional view taken along a line F-F′ shown in FIG. 7A ;
- FIG. 8A is a top view showing a semiconductor device according to a fifth embodiment
- FIG. 8B is a sectional view taken along a line G-G′ shown in FIG. 8A .
- a semiconductor device includes a semiconductor layer comprising an upper surface and a recess extending inwardly of the upper surface, the recess including a lower part, an upper part, and a side surface, the side surface terminating at the upper surface of the semiconductor layer at an upper edge, an insulating member in the lower part of the recess, an insulating film comprising a first portion on the upper edge of the recess, a second portion on the side surface of the recess in the upper part thereof, and a third portion on at least a portion of the semiconductor layer adjacent to the upper edge of the recess, and an electrode on the insulating member and on the portion of the insulating film covering the upper edge of the recess, wherein the first portion of the insulating film is thinner than the thicknesses of each of the second portion of the insulating film and of the third portion of the insulating film.
- FIG. 1A is a top view showing a semiconductor device according to the embodiment
- FIG. 1B is a sectional view of the semiconductor device taken along line A-A′ shown in FIG. 1A .
- FIG. 2 is a sectional view showing a region B in FIG. 1B .
- the semiconductor device is a semiconductor device including a gate insulating film breakdown-type anti-fuse element (eFuse), and is, for example, a semiconductor memory device including a redundant circuit.
- eFuse gate insulating film breakdown-type anti-fuse element
- a silicon substrate 10 is provided.
- the silicon substrate 10 is formed of, for example, a silicon (Si) single crystal.
- Si silicon
- an XYZ orthogonal coordinate system is adopted. Two directions parallel to an upper surface 10 a of the silicon substrate 10 and also orthogonal to each other are referred to as the “X-direction” and the “Y-direction”, and a direction perpendicular to the upper surface 10 a of the silicon substrate 10 is referred to as the “Z-direction”.
- one side of the substrate 10 is referred to as “upper”, and the other side is referred to as “lower”, however, these expressions are for reference only, and are irrelevant to the direction of gravity.
- an n-type well 12 is provided in a part of an upper layer portion of the silicon substrate 10 .
- a recessed portion 12 a is formed in an upper surface of the well 12 .
- an STI structure (Shallow Trench Isolation) 13 composed of, for example, silicon oxide (SiO), is provided in a lower part in the recessed portion 12 a .
- the shape of the STI 13 as viewed in the Z-direction is a rectangle.
- the height of the STI 13 with respect to a depth of the recessed portion 12 a is 3 ⁇ 4 or less.
- an STI 14 is provided in a part of an upper layer portion of the well 12 .
- the shape of the STI 14 as viewed in the Z-direction is a frame shape surrounding the STI 13 .
- the STI 14 is not in contact with the STI 13 .
- the rectangular region surrounded by the STI 14 in the well 12 becomes an active area 17 .
- the STI 13 is disposed in the active area 17 .
- an STI 15 is provided in a region surrounding the STI 14 in the well 12 .
- the STI 15 surrounds the STI 14 and is spaced from the STI 14 .
- a region between the STI 14 and the STI 15 in the silicon substrate 10 becomes a frame-shaped substrate contact region 18 .
- the substrate contact region 18 surrounds the active area 17 .
- the shape of the active area 17 as viewed in the Z-direction is a rectangle in which the X-direction is a longitudinal direction.
- a source region 21 and a drain region 22 are provided on opposed sides in the X-direction of the active area 17 .
- the source region 21 and the drain region 22 are spaced from the recessed portion 12 a and disposed such that the recessed portion 12 a is interposed therebetween.
- the recessed portion 12 a is located in the well 12 .
- the conductivity type of the source region 21 and the drain region 22 is p-type.
- a p + -type source contact layer 21 a is formed in an upper part of the source region 21 and on a side of the recessed portion 12 a .
- a p + -type drain contact layer 22 a is formed in an upper part of the drain region 22 and on a side of the recessed portion 12 a .
- the carrier concentration in the source contact layer 21 a and the drain contact layer 22 a is higher than the carrier concentration in the source region 21 and the drain region 22 .
- the conductivity type of the substrate contact region 18 is p-type.
- the carrier concentration in the substrate contact region 18 is higher than the carrier concentration in the well 12 .
- an n + -type substrate contact layer 18 a is formed in an upper part of the substrate contact region 18 .
- the carrier concentration in the substrate contact layer 18 a is higher than the carrier concentration in the substrate contact region 18 .
- a gate insulating film 24 composed of, for example, silicon oxide is provided on a side surface of an upper part of the recessed portion 12 a and on an upper surface of the active area 17 .
- the gate insulating film 24 covers an upper edge 12 b of the recessed portion 12 a .
- An end portion of the gate insulating film 24 is in contact with the STI 13 .
- a gate electrode 25 is provided on the gate insulating film 24 .
- the gate electrode 25 is formed of, for example, a conductive material such as polysilicon.
- the gate electrode 25 is provided continuously on the STI 13 and on a portion to either side in the X-direction of the STI 13 in the active area 17 , and a part of the gate electrode 25 penetrates into the upper part of the recessed portion 12 a . Therefore, the gate electrode 25 covers the upper edge 12 b of the recessed portion 12 a with the gate insulating film 24 therebetween.
- the sidewall 27 of the gate electrode 25 is spaced outwardly of the recessed portion 12 a , and the shortest distance L between the recessed portion 12 a and the sidewall 27 where the gate electrode 25 overlies the active area 17 is 0.2 ⁇ m or less, i.e., 0.2 ⁇ m ⁇ L>0.
- a cavity 25 a is formed in a region immediately above the recessed portion 12 a in an upper surface of the gate electrode 25 .
- a sidewall 26 composed of, for example, silicon oxide is provided on a side surface of the gate electrode 25 .
- an interlayer insulating film 30 is provided so as to cover the gate electrode 25 and the like.
- a plurality of contacts 31 to 34 extending in the Z-direction are provided.
- upper layer interconnects 36 and 37 are provided on the interlayer insulating film 30 .
- FIG. 1A in order to make the drawing easier to understand, the illustration of the sidewall 26 and the interlayer insulating film 30 is omitted, and the upper layer interconnects 36 and 37 are each shown by a two-dot chain line.
- the contact 31 is connected between the source contact layer 21 a and the upper layer interconnect 36 .
- the contact 32 is connected between the drain contact layer 22 a and the upper layer interconnect 36 .
- the contact 33 is connected between the substrate contact layer 18 a and the upper layer interconnect 36 .
- the source contact layer 21 a , the drain contact layer 22 a , and the substrate contact layer 18 a are short-circuited through the upper layer interconnect 36 , i.e., they are electrically connected to have the same electric potential.
- the contact 34 is connected between the gate electrode 25 and the upper layer interconnect 37 .
- the thickness to of a portion 24 a of the gate insulating film 24 in contact with the upper edge 12 b of the active area 17 of the well 12 is thinner than the thickness tb of a portion 24 b of the gate insulating film 24 disposed on a side surface of the recessed portion 12 a of the active area 17 of the well 12 and a thickness tc of a portion 24 c of the gate insulating film 24 disposed on an upper surface of the active area 17 . That is, the following relationships are satisfied: ta ⁇ tb and ta ⁇ tc.
- the thicknesses of the portion 24 b and the portion 24 c are each 3 nm, and the thickness of the portion 24 a is from 1 to 2 nm.
- the ridgeline is the upper edge 12 b of the recessed portion 12 a .
- a portion having a maximum curvature in a cross section including the Z-direction is defined as the upper edge 12 b.
- an anti-fuse element having an MOS capacitor structure is formed of the active area 17 , the gate insulating film 24 , and the gate electrode 25 .
- the gate electrode 25 is insulated from the active area 17 by the gate insulating film 24 .
- the write voltage is applied between the well 12 , the source region 21 , and the drain region 22 each connected to the upper layer interconnect 36 and the gate electrode 25 connected to the upper layer interconnect 37 , and an electric field is concentrated in the portion 24 a of the gate insulating film 24 which is thinnest in the portion thereof interposed between the active area 17 and the gate electrode 25 , and electrical breakdown occurs in the portion 24 a .
- the well 12 and the gate electrode 25 are electrically connected to each other, and for example, a redundant circuit connected to the anti-fuse element becomes effective, or a one-bit value is written to the anti-fuse element.
- FIGS. 3A to 4C are sectional views showing the method for manufacturing a semiconductor device according to the embodiment.
- FIGS. 3A to 3C, and 4B and 4C each show a cross section corresponding to FIG. 1B .
- FIG. 4A shows a region C in FIG. 3C .
- a silicon substrate 10 is prepared. Subsequently, an upper layer portion of the silicon substrate 10 is selectively removed, whereby a trench 41 is formed. Subsequently, for example, by a CVD (Chemical Vapor Deposition) method using TEOS (Tetra Ethyl Ortho Silicate: Si(OC 2 H 5 ) 4 ) as a raw material, a silicon oxide film is formed on the entire surface. Subsequently, by performing CMP (Chemical Mechanical Polishing), the silicon oxide film is left only in the trenches 41 . By doing this, STIs 13 to 15 are formed.
- CVD Chemical Vapor Deposition
- TEOS Tetra Ethyl Ortho Silicate: Si(OC 2 H 5 ) 4
- a sacrificial oxide film 42 is formed on an upper surface of the silicon substrate 10 , and an impurity which becomes an acceptor is ion-implanted into a part of the upper layer portion of the silicon substrate 10 , followed by a heat treatment, whereby a n-type well 12 is formed on the substrate 10 .
- a resist pattern 43 is formed on the sacrificial oxide film 42 , and a region immediately above the STI 13 is exposed, and the other surface region of the well 12 is covered.
- isotropic etching such as wet etching using the resist pattern 43 as a mask, an exposed portion of the sacrificial oxide film 42 and an upper part of the STI 13 are removed, whereby a recessed portion 12 a is formed as is shown in FIG. 3B .
- one-fourth or more of the STI 13 in the Z-direction is removed.
- the resist pattern 43 is removed.
- a remaining part of the sacrificial oxide film 42 is removed.
- a thermal oxidation treatment at a temperature of, for example, 650 to 750° C. the gate insulating film 24 is formed.
- a portion 24 a of the gate insulating film 24 covering an upper edge 12 b of the recessed portion 12 a is thinner than the other portions, for example, portions 24 b and 24 c.
- a silicon film 44 is formed.
- a cavity 25 a which reflects the shape of the underlying recessed portion 12 a is formed over the location of the STI 13 .
- a resist pattern (not shown) is formed on the silicon film 44 , and anisotropic etching such as RIE (Reactive Ion Etching) is performed using the resist pattern as a mask.
- RIE Reactive Ion Etching
- the silicon film 44 is processed, whereby a gate electrode 25 is formed therefrom.
- the edge 25 b of the gate electrode 25 is located to the outer side of the recessed portion 12 a , and the shortest distance L between the recessed portion 12 a and the edge 25 b of the gate electrode 25 is set to 0.2 ⁇ m or less by properly sizing the opening in the mask (not shown).
- a manufacturing method thereafter is the same as a conventional method. According to this, as shown in FIGS. 1A, 1B, and 2 , the semiconductor device 1 according to the embodiment is manufactured.
- the portion 24 a covering the upper edge 12 b in the gate insulating film 24 can be made thinner (is formed thinner) than the other portions of the gate insulating film 24 as shown in FIG. 4A .
- a predetermined write voltage is applied between the upper layer interconnect 36 and the upper layer interconnect 37 .
- breakdown can be reliably caused in the portion 24 a of the gate insulating film 24 . Due to this, the reliability of the anti-fuse element of the semiconductor device 1 is high. Further, it is not necessary to excessively increase the write voltage, and therefore, a peripheral circuit can be shrunk.
- the thickness of the gate insulating film 24 is uniform, in the case where the gate insulating film 24 becomes thicker than a design value due to a variation in deposition conditions or the like, breakdown does not occur in the gate insulating film even when a predetermined write voltage is applied, and the device may not function as the anti-fuse element. In order to avoid this phenomenon, it is necessary to sufficiently increase the write voltage, however, in that case, it is necessary to increase the breakdown voltage of all portions to which the write voltage is applied, and therefore, the shrinkage of the semiconductor device is inhibited.
- the edge 25 b of the gate electrode 25 is located spaced from the outer side of the recessed portion 12 a .
- the gate electrode 25 can be formed so as to cover the upper edge 12 b of the recessed portion 12 a with the gate insulating film 24 therebetween.
- the write voltage can be reliably applied to the portion 24 a of the gate insulating film 24 , and thus electrical breakdown can be caused at that location.
- the shortest distance L between the recessed portion 12 a and the sidewall 27 of the gate electrode 25 and the active area 17 overlap each other is set to 0.2 ⁇ m or less. According to this, in a process for patterning the gate electrode 25 shown in FIG. 4C , a margin for alignment is ensured, and the edge 25 b is reliably located to the outer side of the recessed portion 12 a , and thus, the size of the gate electrode 25 can be prevented from excessively increasing.
- FIG. 5A is a top view showing a semiconductor device according to the embodiment
- FIG. 5B is a sectional view taken along a line D-D′ shown in FIG. 5A .
- a recessed portion 12 a of a well 12 is disposed on a side of a drain region 22 . That is, a distance between a source region 21 and the recessed portion 12 a is longer than a distance between the drain region 22 and the recessed portion 12 a . Further, a distance L between the recessed portion 12 a and a sidewall 27 of the gate electrode 25 , as viewed from above, is 0.2 ⁇ m or less on a side of the drain region 22 and on both sides in the Y-direction (a channel width direction). On the other hand, on a side of the source region 21 , the distance is greater than 0.2 ⁇ m.
- the other elements, operation, manufacturing method, and effect of the embodiment are the same as those of the above-mentioned first embodiment.
- FIG. 6A is a top view showing a semiconductor device according to the embodiment
- FIG. 6B is a sectional view taken along a line E-E′ shown in FIG. 6A .
- a shortest distance L between the recessed portion 12 a and an edge 27 of a region where the locations of the gate electrode 25 and an active area 17 overlap with each other, i.e., the minimum span of the side of the electrode 25 from the edge 27 of the recessed portion 12 a as viewed from above is 0.2 ⁇ m or less.
- a distance L between the two recessed portions 12 a is, for example, 0.2 ⁇ m or less.
- a length of a thin portion 24 a of a gate insulating film 24 becomes longer and corner portions increase, and therefore, electrical breakdown can be more reliably caused in the gate insulating film 24 .
- the other elements, operation, manufacturing method, and effect of the embodiment are the same as those of the above-mentioned first embodiment.
- FIG. 7A is a top view showing a semiconductor device according to the embodiment
- FIG. 7B is a sectional view taken along a line F-F′ shown in FIG. 7A .
- the width of the gate electrode 25 in a central portion thereof in the Y-direction is smaller than the length of both end portions in the X-direction.
- the side surface 25 c on opposite sides of the gate electrode 25 in the X-direction a recess is formed.
- the Y-direction is a longitudinal direction of the gate electrode 25 , and is a channel width direction of an MOS structure.
- a shortest distance L between a recessed portion 12 a and an edge 27 of a region where the gate electrode 25 and an active area 17 overlap each other as viewed from an upper side is 0.2 ⁇ m or less.
- the embodiment when a write voltage is applied between the gate electrode 25 and the active area 17 , an electric field is likely to be concentrated in the portion of the recess in the side surface 25 c of the gate electrode 25 , and therefore, electrical breakdown is likely to occur in the gate insulating film 24 adjacent to this portion. According to this, when a write voltage is applied, breakdown can be more reliably caused in the gate insulating film 24 .
- the other elements, operation, manufacturing method, and effect of the embodiment are the same as those of the above-mentioned first embodiment.
- FIG. 8A is a top view showing a semiconductor device according to the embodiment
- FIG. 8B is a sectional view taken along a line G-G′ shown in FIG. 8A .
- a semiconductor device 5 according to the embodiment differs in the following points as compared with the semiconductor device 1 (see FIGS. 1A and 1B ) according to the above-mentioned first embodiment.
- a drain region 22 and a STI 13 are not provided.
- a recessed portion 14 a is formed in an upper surface of the STI 14 .
- a gate electrode 25 extends from over a source region 21 to the STI 14 , and a part of a gate electrode 25 extends into the recessed portion 14 a .
- a contact 31 is connected to an upper layer interconnect 51 extending in the Y-direction, and a contact 33 is connected to an upper layer interconnect 53 extending in the Y-direction.
- a gate insulating film 24 is provided over the upper surface of the source region 21 , the side surface of the recessed portion 14 a of the STI 14 and over an upper edge 14 b of the recessed portion 14 a . Then, a portion 24 a of the gate insulating film 24 in contact with the upper edge 14 b is thinner than a portion 24 b disposed on a side surface of the recessed portion 14 a and a portion 24 c disposed on the source region 21 .
- the shortest distance L between the recessed portion 14 a and an edge 27 of a region where the gate electrode 25 and the source region 21 overlap with each other as viewed from above is 0.2 ⁇ m or less.
- an anti-fuse element can be realized by utilizing a gate capacitor structure.
- the other configuration, operation, manufacturing method, and effect of the embodiment are the same as those of the above-mentioned first embodiment.
- a semiconductor device including an anti-fuse element with high reliability can be realized.
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Abstract
A semiconductor device includes a semiconductor layer comprising an upper surface and a recess through the upper surface and including a lower part, an upper part, and a side surface, the side surface terminating at the upper surface at an upper edge, an insulating member in the lower part of the recess, an insulating film comprising a first portion on the upper edge of the recess, a second portion on the side surface of the recess in the upper part thereof, and a third portion on a portion of the semiconductor layer adjacent to the upper edge of the recess, and an electrode on the insulating member and the portion of the insulating film covering the upper edge of the recess. The first portion of the insulating film is thinner than thicknesses of each of the second and third portions thereof.
Description
- This application claims benefit of U.S. provisional patent application Ser. No. 62/384,785, filed Sep. 8, 2016, which is herein incorporated by reference.
- Embodiments hereof relate to a semiconductor device.
- An anti-fuse element utilizing a MOSFET structure is sometimes provided in a semiconductor device. In such an anti-fuse element, a gate electrode and a semiconductor substrate are insulated from each other by a gate insulating film in an initial state, however, when breakdown occurs in the gate insulating film by applying a predetermined voltage thereacross, the gate electrode and the semiconductor substrate are electrically connected to each other. According to this, for example, a redundant circuit becomes available.
-
FIG. 1A is a top view showing a semiconductor device according to a first embodiment, andFIG. 1B is a sectional view taken along a line A-A′ shown inFIG. 1A ; -
FIG. 2 is a sectional view showing a region B inFIG. 1B ; -
FIGS. 3A to 4C are sectional views showing a method for manufacturing a semiconductor device according to the first embodiment; -
FIG. 5A is a top view showing a semiconductor device according to a second embodiment, andFIG. 5B is a sectional view taken along a line D-D′ shown inFIG. 5A ; -
FIG. 6A is a top view showing a semiconductor device according to a third embodiment, andFIG. 6B is a sectional view taken along a line E-E′ shown inFIG. 6A ; -
FIG. 7A is a top view showing a semiconductor device according to a fourth embodiment, andFIG. 7B is a sectional view taken along a line F-F′ shown inFIG. 7A ; and -
FIG. 8A is a top view showing a semiconductor device according to a fifth embodiment, andFIG. 8B is a sectional view taken along a line G-G′ shown inFIG. 8A . - A semiconductor device according to an embodiment includes a semiconductor layer comprising an upper surface and a recess extending inwardly of the upper surface, the recess including a lower part, an upper part, and a side surface, the side surface terminating at the upper surface of the semiconductor layer at an upper edge, an insulating member in the lower part of the recess, an insulating film comprising a first portion on the upper edge of the recess, a second portion on the side surface of the recess in the upper part thereof, and a third portion on at least a portion of the semiconductor layer adjacent to the upper edge of the recess, and an electrode on the insulating member and on the portion of the insulating film covering the upper edge of the recess, wherein the first portion of the insulating film is thinner than the thicknesses of each of the second portion of the insulating film and of the third portion of the insulating film.
- First, a first embodiment will be described.
-
FIG. 1A is a top view showing a semiconductor device according to the embodiment, andFIG. 1B is a sectional view of the semiconductor device taken along line A-A′ shown inFIG. 1A . -
FIG. 2 is a sectional view showing a region B inFIG. 1B . - The embodiments hereof are schematically illustrated, and for example, an aspect ratio of each constituent member does not necessarily coincide with those of an actual device.
- The semiconductor device according to the embodiment is a semiconductor device including a gate insulating film breakdown-type anti-fuse element (eFuse), and is, for example, a semiconductor memory device including a redundant circuit.
- As shown in
FIGS. 1A and 1B , in asemiconductor device 1 according to the embodiment, asilicon substrate 10 is provided. Thesilicon substrate 10 is formed of, for example, a silicon (Si) single crystal. Hereinafter, in the specification, for the sake of convenience of description, an XYZ orthogonal coordinate system is adopted. Two directions parallel to anupper surface 10 a of thesilicon substrate 10 and also orthogonal to each other are referred to as the “X-direction” and the “Y-direction”, and a direction perpendicular to theupper surface 10 a of thesilicon substrate 10 is referred to as the “Z-direction”. Further, in the Z-direction, one side of thesubstrate 10 is referred to as “upper”, and the other side is referred to as “lower”, however, these expressions are for reference only, and are irrelevant to the direction of gravity. - In a part of an upper layer portion of the
silicon substrate 10, for example, an n-type well 12 is provided. In an upper surface of the well 12, a recessedportion 12 a is formed. In a lower part in the recessedportion 12 a, an STI structure (Shallow Trench Isolation) 13 composed of, for example, silicon oxide (SiO), is provided. The shape of theSTI 13 as viewed in the Z-direction is a rectangle. The height of theSTI 13 with respect to a depth of the recessedportion 12 a is ¾ or less. - In a part of an upper layer portion of the well 12, an
STI 14 is provided. The shape of theSTI 14 as viewed in the Z-direction is a frame shape surrounding theSTI 13. TheSTI 14 is not in contact with theSTI 13. The rectangular region surrounded by theSTI 14 in the well 12 becomes anactive area 17. TheSTI 13 is disposed in theactive area 17. - In a region surrounding the
STI 14 in the well 12, anSTI 15 is provided. TheSTI 15 surrounds theSTI 14 and is spaced from the STI 14. A region between theSTI 14 and theSTI 15 in thesilicon substrate 10 becomes a frame-shapedsubstrate contact region 18. Thesubstrate contact region 18 surrounds theactive area 17. - The shape of the
active area 17 as viewed in the Z-direction is a rectangle in which the X-direction is a longitudinal direction. On opposed sides in the X-direction of theactive area 17, asource region 21 and adrain region 22 are provided. Thesource region 21 and thedrain region 22 are spaced from the recessedportion 12 a and disposed such that the recessedportion 12 a is interposed therebetween. Thus, the recessedportion 12 a is located in thewell 12. - The conductivity type of the
source region 21 and thedrain region 22 is p-type. In an upper part of thesource region 21 and on a side of the recessedportion 12 a, a p+-typesource contact layer 21 a is formed. Further, in an upper part of thedrain region 22 and on a side of the recessedportion 12 a, a p+-typedrain contact layer 22 a is formed. The carrier concentration in thesource contact layer 21 a and thedrain contact layer 22 a is higher than the carrier concentration in thesource region 21 and thedrain region 22. - The conductivity type of the
substrate contact region 18 is p-type. The carrier concentration in thesubstrate contact region 18 is higher than the carrier concentration in thewell 12. In an upper part of thesubstrate contact region 18, an n+-typesubstrate contact layer 18 a is formed. The carrier concentration in thesubstrate contact layer 18 a is higher than the carrier concentration in thesubstrate contact region 18. - On a side surface of an upper part of the recessed
portion 12 a and on an upper surface of theactive area 17, agate insulating film 24 composed of, for example, silicon oxide is provided. Thegate insulating film 24 covers anupper edge 12 b of the recessedportion 12 a. An end portion of thegate insulating film 24 is in contact with theSTI 13. - On the
gate insulating film 24, agate electrode 25 is provided. Thegate electrode 25 is formed of, for example, a conductive material such as polysilicon. Thegate electrode 25 is provided continuously on theSTI 13 and on a portion to either side in the X-direction of theSTI 13 in theactive area 17, and a part of thegate electrode 25 penetrates into the upper part of the recessedportion 12 a. Therefore, thegate electrode 25 covers theupper edge 12 b of the recessedportion 12 a with thegate insulating film 24 therebetween. - As viewed from above, the
sidewall 27 of thegate electrode 25 is spaced outwardly of the recessedportion 12 a, and the shortest distance L between the recessedportion 12 a and thesidewall 27 where thegate electrode 25 overlies theactive area 17 is 0.2 μm or less, i.e., 0.2 μm≧L>0. In a region immediately above the recessedportion 12 a in an upper surface of thegate electrode 25, acavity 25 a is formed. On a side surface of thegate electrode 25, asidewall 26 composed of, for example, silicon oxide is provided. - On the
silicon substrate 10, aninterlayer insulating film 30 is provided so as to cover thegate electrode 25 and the like. In theinterlayer insulating film 30, a plurality ofcontacts 31 to 34 extending in the Z-direction are provided. On theinterlayer insulating film 30, upper layer interconnects 36 and 37 are provided. Incidentally, inFIG. 1A , in order to make the drawing easier to understand, the illustration of thesidewall 26 and theinterlayer insulating film 30 is omitted, and the upper layer interconnects 36 and 37 are each shown by a two-dot chain line. - The
contact 31 is connected between thesource contact layer 21 a and theupper layer interconnect 36. Thecontact 32 is connected between thedrain contact layer 22 a and theupper layer interconnect 36. Thecontact 33 is connected between thesubstrate contact layer 18 a and theupper layer interconnect 36. In this manner, thesource contact layer 21 a, thedrain contact layer 22 a, and thesubstrate contact layer 18 a are short-circuited through theupper layer interconnect 36, i.e., they are electrically connected to have the same electric potential. On the other hand, thecontact 34 is connected between thegate electrode 25 and theupper layer interconnect 37. - Then, as shown in
FIG. 2 , the thickness to of aportion 24 a of thegate insulating film 24 in contact with theupper edge 12 b of theactive area 17 of the well 12 is thinner than the thickness tb of aportion 24 b of thegate insulating film 24 disposed on a side surface of the recessedportion 12 a of theactive area 17 of the well 12 and a thickness tc of aportion 24 c of thegate insulating film 24 disposed on an upper surface of theactive area 17. That is, the following relationships are satisfied: ta<tb and ta<tc. For example, the thicknesses of theportion 24 b and theportion 24 c are each 3 nm, and the thickness of theportion 24 a is from 1 to 2 nm. Incidentally, in the case where a ridgeline, i.e., a sharp corner, exits in a boundary between a side surface of the recessedportion 12 a and an upper surface of theactive area 17, the ridgeline is theupper edge 12 b of the recessedportion 12 a. In the case where a clear ridgeline does not exist between a side surface of the recessedportion 12 a and an upper surface of theactive area 17, a portion having a maximum curvature in a cross section including the Z-direction is defined as theupper edge 12 b. - In the
semiconductor device 1 according to the embodiment, an anti-fuse element having an MOS capacitor structure is formed of theactive area 17, thegate insulating film 24, and thegate electrode 25. In an initial state, thegate electrode 25 is insulated from theactive area 17 by thegate insulating film 24. Then, when a predetermined write voltage of, for example, 7 to 8 V is applied between theupper layer interconnect 36 and theupper layer interconnect 37, the write voltage is applied between the well 12, thesource region 21, and thedrain region 22 each connected to theupper layer interconnect 36 and thegate electrode 25 connected to theupper layer interconnect 37, and an electric field is concentrated in theportion 24 a of thegate insulating film 24 which is thinnest in the portion thereof interposed between theactive area 17 and thegate electrode 25, and electrical breakdown occurs in theportion 24 a. As a result, the well 12 and thegate electrode 25 are electrically connected to each other, and for example, a redundant circuit connected to the anti-fuse element becomes effective, or a one-bit value is written to the anti-fuse element. - Next, a method for manufacturing a semiconductor device according to the embodiment will be described.
-
FIGS. 3A to 4C are sectional views showing the method for manufacturing a semiconductor device according to the embodiment. -
FIGS. 3A to 3C, and 4B and 4C each show a cross section corresponding toFIG. 1B .FIG. 4A shows a region C inFIG. 3C . - First, as shown in
FIG. 3A , asilicon substrate 10 is prepared. Subsequently, an upper layer portion of thesilicon substrate 10 is selectively removed, whereby atrench 41 is formed. Subsequently, for example, by a CVD (Chemical Vapor Deposition) method using TEOS (Tetra Ethyl Ortho Silicate: Si(OC2H5)4) as a raw material, a silicon oxide film is formed on the entire surface. Subsequently, by performing CMP (Chemical Mechanical Polishing), the silicon oxide film is left only in thetrenches 41. By doing this,STIs 13 to 15 are formed. Subsequently, asacrificial oxide film 42 is formed on an upper surface of thesilicon substrate 10, and an impurity which becomes an acceptor is ion-implanted into a part of the upper layer portion of thesilicon substrate 10, followed by a heat treatment, whereby a n-type well 12 is formed on thesubstrate 10. - Subsequently, as shown in
FIG. 3B , a resistpattern 43 is formed on thesacrificial oxide film 42, and a region immediately above theSTI 13 is exposed, and the other surface region of the well 12 is covered. Subsequently, by performing isotropic etching such as wet etching using the resistpattern 43 as a mask, an exposed portion of thesacrificial oxide film 42 and an upper part of theSTI 13 are removed, whereby a recessedportion 12 a is formed as is shown inFIG. 3B . At this time, one-fourth or more of theSTI 13 in the Z-direction is removed. - Subsequently, as shown in
FIG. 3C , the resistpattern 43 is removed. Subsequently, by performing wet etching, a remaining part of thesacrificial oxide film 42 is removed. Subsequently, by performing a thermal oxidation treatment at a temperature of, for example, 650 to 750° C., thegate insulating film 24 is formed. At this time, as shown inFIG. 4A , aportion 24 a of thegate insulating film 24 covering anupper edge 12 b of the recessedportion 12 a is thinner than the other portions, for example,portions - Subsequently, as shown in
FIG. 4B , polysilicon is deposited on the entire surface, whereby asilicon film 44 is formed. At this time, in a region immediately above the recessedportion 12 a in thesilicon film 44, acavity 25 a which reflects the shape of the underlying recessedportion 12 a is formed over the location of theSTI 13. - Subsequently, as shown in
FIG. 4C , a resist pattern (not shown) is formed on thesilicon film 44, and anisotropic etching such as RIE (Reactive Ion Etching) is performed using the resist pattern as a mask. By doing this, thesilicon film 44 is processed, whereby agate electrode 25 is formed therefrom. At this time, as viewed from above (the Z direction), theedge 25 b of thegate electrode 25 is located to the outer side of the recessedportion 12 a, and the shortest distance L between the recessedportion 12 a and theedge 25 b of thegate electrode 25 is set to 0.2 μm or less by properly sizing the opening in the mask (not shown). A manufacturing method thereafter is the same as a conventional method. According to this, as shown inFIGS. 1A, 1B, and 2 , thesemiconductor device 1 according to the embodiment is manufactured. - Next, an effect of the embodiment will be described.
- In the embodiment, by forming the recessed
portion 12 a in the well 12 as shown inFIG. 3B and thereafter forming thegate insulating film 24 as shown inFIG. 3C , theportion 24 a covering theupper edge 12 b in thegate insulating film 24 can be made thinner (is formed thinner) than the other portions of thegate insulating film 24 as shown inFIG. 4A . According to this, when a predetermined write voltage is applied between theupper layer interconnect 36 and theupper layer interconnect 37, breakdown can be reliably caused in theportion 24 a of thegate insulating film 24. Due to this, the reliability of the anti-fuse element of thesemiconductor device 1 is high. Further, it is not necessary to excessively increase the write voltage, and therefore, a peripheral circuit can be shrunk. - On the other hand, if the thickness of the
gate insulating film 24 is uniform, in the case where thegate insulating film 24 becomes thicker than a design value due to a variation in deposition conditions or the like, breakdown does not occur in the gate insulating film even when a predetermined write voltage is applied, and the device may not function as the anti-fuse element. In order to avoid this phenomenon, it is necessary to sufficiently increase the write voltage, however, in that case, it is necessary to increase the breakdown voltage of all portions to which the write voltage is applied, and therefore, the shrinkage of the semiconductor device is inhibited. - Further, in the embodiment, as viewed from above, the
edge 25 b of thegate electrode 25 is located spaced from the outer side of the recessedportion 12 a. According to this, thegate electrode 25 can be formed so as to cover theupper edge 12 b of the recessedportion 12 a with thegate insulating film 24 therebetween. As a result, the write voltage can be reliably applied to theportion 24 a of thegate insulating film 24, and thus electrical breakdown can be caused at that location. - Further, in the embodiment, the shortest distance L between the recessed
portion 12 a and thesidewall 27 of thegate electrode 25 and theactive area 17 overlap each other is set to 0.2 μm or less. According to this, in a process for patterning thegate electrode 25 shown inFIG. 4C , a margin for alignment is ensured, and theedge 25 b is reliably located to the outer side of the recessedportion 12 a, and thus, the size of thegate electrode 25 can be prevented from excessively increasing. - In this manner, according to the embodiment, both reliability and shrinkage of the anti-fuse element can be achieved.
- Next, a second embodiment will be described.
-
FIG. 5A is a top view showing a semiconductor device according to the embodiment, andFIG. 5B is a sectional view taken along a line D-D′ shown inFIG. 5A . - As shown in
FIGS. 5A and 5B , in asemiconductor device 2 according to the embodiment, a recessedportion 12 a of a well 12 is disposed on a side of adrain region 22. That is, a distance between asource region 21 and the recessedportion 12 a is longer than a distance between thedrain region 22 and the recessedportion 12 a. Further, a distance L between the recessedportion 12 a and asidewall 27 of thegate electrode 25, as viewed from above, is 0.2 μm or less on a side of thedrain region 22 and on both sides in the Y-direction (a channel width direction). On the other hand, on a side of thesource region 21, the distance is greater than 0.2 μm. The other elements, operation, manufacturing method, and effect of the embodiment are the same as those of the above-mentioned first embodiment. - Next, a third embodiment will be described.
-
FIG. 6A is a top view showing a semiconductor device according to the embodiment, andFIG. 6B is a sectional view taken along a line E-E′ shown inFIG. 6A . - As shown in
FIGS. 6A and 6B , in asemiconductor device 3 according to the embodiment, in a region immediately below thegate electrode 25, two recessedportions 12 a are provided. The two recessedportions 12 a are arranged in the X-direction, and each recessedportion 12 a extends in the Y-direction. Also in this case, a shortest distance L between the recessedportion 12 a and anedge 27 of a region where the locations of thegate electrode 25 and anactive area 17 overlap with each other, i.e., the minimum span of the side of theelectrode 25 from theedge 27 of the recessedportion 12 a as viewed from above is 0.2 μm or less. Further, also a distance L between the two recessedportions 12 a is, for example, 0.2 μm or less. According to the embodiment, as compared with the above-mentioned first embodiment, a length of athin portion 24 a of agate insulating film 24 becomes longer and corner portions increase, and therefore, electrical breakdown can be more reliably caused in thegate insulating film 24. The other elements, operation, manufacturing method, and effect of the embodiment are the same as those of the above-mentioned first embodiment. - Next, a fourth embodiment will be described.
-
FIG. 7A is a top view showing a semiconductor device according to the embodiment, andFIG. 7B is a sectional view taken along a line F-F′ shown inFIG. 7A . - As shown in
FIGS. 7A and 7B , in asemiconductor device 4 according to the embodiment, the width of thegate electrode 25 in a central portion thereof in the Y-direction, that is, a length in the X-direction is smaller than the length of both end portions in the X-direction. Theside surface 25 c on opposite sides of thegate electrode 25 in the X-direction, a recess is formed. Incidentally, the Y-direction is a longitudinal direction of thegate electrode 25, and is a channel width direction of an MOS structure. Also in this case, a shortest distance L between a recessedportion 12 a and anedge 27 of a region where thegate electrode 25 and anactive area 17 overlap each other as viewed from an upper side is 0.2 μm or less. - According to the embodiment, when a write voltage is applied between the
gate electrode 25 and theactive area 17, an electric field is likely to be concentrated in the portion of the recess in theside surface 25 c of thegate electrode 25, and therefore, electrical breakdown is likely to occur in thegate insulating film 24 adjacent to this portion. According to this, when a write voltage is applied, breakdown can be more reliably caused in thegate insulating film 24. The other elements, operation, manufacturing method, and effect of the embodiment are the same as those of the above-mentioned first embodiment. - Next, a fifth embodiment will be described.
-
FIG. 8A is a top view showing a semiconductor device according to the embodiment, andFIG. 8B is a sectional view taken along a line G-G′ shown inFIG. 8A . - As shown in
FIGS. 8A and 8B , asemiconductor device 5 according to the embodiment differs in the following points as compared with the semiconductor device 1 (seeFIGS. 1A and 1B ) according to the above-mentioned first embodiment. Firstly, in thesemiconductor device 5, adrain region 22 and aSTI 13 are not provided. Secondly, in an upper surface of theSTI 14, a recessedportion 14 a is formed. Thirdly, agate electrode 25 extends from over asource region 21 to theSTI 14, and a part of agate electrode 25 extends into the recessedportion 14 a. Fourthly, acontact 31 is connected to anupper layer interconnect 51 extending in the Y-direction, and acontact 33 is connected to anupper layer interconnect 53 extending in the Y-direction. - A
gate insulating film 24 is provided over the upper surface of thesource region 21, the side surface of the recessedportion 14 a of theSTI 14 and over an upper edge 14 b of the recessedportion 14 a. Then, aportion 24 a of thegate insulating film 24 in contact with the upper edge 14 b is thinner than aportion 24 b disposed on a side surface of the recessedportion 14 a and aportion 24 c disposed on thesource region 21. Incidentally, the shortest distance L between the recessedportion 14 a and anedge 27 of a region where thegate electrode 25 and thesource region 21 overlap with each other as viewed from above is 0.2 μm or less. - Also, according to the embodiment, an anti-fuse element can be realized by utilizing a gate capacitor structure. The other configuration, operation, manufacturing method, and effect of the embodiment are the same as those of the above-mentioned first embodiment.
- According to the embodiments described above, a semiconductor device including an anti-fuse element with high reliability can be realized.
- While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention. Additionally, the embodiments described above can be combined mutually.
Claims (20)
1. A semiconductor device, comprising:
a semiconductor layer having an upper surface and a recess extending inwardly of the upper surface, the recess including a lower part, an upper part, and a side surface, the side surface terminating at the upper surface of the semiconductor layer at an upper edge;
an insulating member in the lower part of the recess;
an insulating film comprising a first portion on the upper edge of the recess, a second portion on the side surface of the recess in the upper part thereof, and a third portion on the upper surface of the semiconductor layer on at least a portion of the upper surface adjacent to the upper edge; and
an electrode on the insulating member and on the first portion of the insulating film, the first portion of insulating film separating the electrode from the upper edge of the recess, wherein
the first portion of the insulating film has a thickness between the semiconductor layer and the electrode that is thinner less than a thickness of the second portion of the insulating film between the semiconductor layer and the electrode and a thickness of the third portion of the insulating film between the semiconductor and the electrode.
2. The semiconductor device according to claim 1 , further comprising:
an interconnect; and
a first contact connected to the interconnect, wherein
the semiconductor layer further comprises: a first region of a first conductivity type in which the recess extend, the upper edge of the recess being a portion of the first region, and a second region of a second conductivity type, the second region being spaced from the recess in a direction parallel to the first surface and in electrical contact with the first contact.
3. The semiconductor device according to claim 2 , further comprising a second contact connected to the interconnect, wherein
the semiconductor layer further comprises a third region of the second conductivity type that is spaced from the recess and electrically connected to the second contact, and
the recess is between the second region and the third region.
4. The semiconductor device according to claim 3 , wherein a distance between the second region of and the recess along the direction parallel to the first surface is greater than a distance between the third region of and the recess along the direction parallel to the first surface.
5. The semiconductor device according to claim 2 , further comprising a second recess extending inwardly of the first region of the semiconductor layer.
6. The semiconductor device according to claim 1 , wherein
the electrode extends in a first direction between a first end and a second end and has opposed side surfaces spaced from each other in a second direction crossing the first direction, the opposed side surface extending along the first direction between the first and second ends of the electrode, and
the width of the electrode in the second direction at a position between the first and second ends in the first direction, is less than the width of the electrode in the second direction at either of the first and second ends of the electrode.
7. The semiconductor device according to claim 1 , further comprising:
an interconnect; and
a first contact connected to the interconnect, wherein
the semiconductor layer further comprises:
a first region of a first conductivity type; and
a second region of a second conductivity type adjacent to the first region and electrically connected to the first contact.
8. The semiconductor device according to claim 1 , wherein the thickness of the insulating member is not greater than 75% of the depth of the recess into the semiconductor layer from the first surface.
9. The semiconductor device according to claim 1 , wherein the semiconductor layer further comprises:
a first region of a first conductivity type; and
a second region of a second conductivity type adjacent to the first region, wherein
the shortest distance between the recess and the second region is less than or equal to 0.2 μm.
10. The semiconductor device according to claim 1 , further comprising:
an interconnect;
a first contact connected to the interconnect; and
a second contact connected to the interconnect, wherein
the semiconductor layer further comprises:
a well of a first conductivity type;
a first semiconductor region of a second conductivity type contacting the well and electrically connected to the first contact; and
a second semiconductor region of the first conductivity type and contacting the well in a location other than where the first semiconductor region contacts the well, and having a carrier concentration that is greater than a carrier concentration of the well, the second semiconductor region being electrically connected to the second contact.
11. The semiconductor device according to claim 10 , wherein the well is the upper edge of the recess.
12. The semiconductor device according to claim 10 , wherein the second semiconductor region surrounds the first semiconductor region in a plane parallel to the first surface.
13. The semiconductor device according to claim 1 , wherein a cavity is in an upper surface of the electrode in a region immediately above the recess.
14. A semiconductor device, comprising:
a first semiconductor region having a first surface;
a first recess extending inwardly of the first surface, the first recess comprising a base, a sidewall, and an upper edge at the intersection of the sidewall and the first surface;
an insulator in the first recess, an upper surface of the insulator recessed inwardly of the first surface;
a first insulating layer disposed on the sidewall of the first recess above the insulator, the upper edge of the first recess, and the first surface;
an electrode on the insulator in the recess and a portion of the first insulating layer that is on the first surface, the electrode having a sidewall portion over the first surface outside the upper edge of the first recess; and
a second semiconductor region adjacent to the first semiconductor region in a first direction parallel to the first surface, the second semiconductor region spaced in the first direction from the upper edge of the first recess, wherein the minimum distance between the upper edge of the first recess and the sidewall portion of the electrode is greater than zero, wherein
a thickness of a first portion the first insulating layer disposed on the upper edge of the first recess is less than a thickness of a second portion the first insulating layer disposed on the sidewall of the first recess above the insulator and a thickness of a third portion of the first insulating layer disposed on the first surface.
15. The semiconductor device according to claim 14 , wherein the minimum distance between the upper edge of the first recess and the sidewall portion of the electrode is less than or equal to 0.2 μm.
16. (canceled)
17. The semiconductor device according to claim 14 , wherein
the first semiconductor region is a first conductivity type, and
the second semiconductor region is a second conductivity type.
18. The semiconductor device according to claim 17 , further comprising:
a second insulating layer overlying the electrode and the second semiconductor layer;
a first conductor on the second insulating layer; and
a first contact extending through the second insulating layer and from the first conductor to the second semiconductor region.
19. The semiconductor device according to claim 17 , further comprising a second recess extending inwardly of the first surface and surrounding the first recess in a plane parallel to the first surface.
20. The semiconductor device according to claim 19 , wherein the second semiconductor region is between the first recess and the second recess.
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CN114975458A (en) * | 2018-12-11 | 2022-08-30 | 美光科技公司 | Microelectronic device including capacitor structure and method of forming a microelectronic device |
US11799038B2 (en) | 2018-12-11 | 2023-10-24 | Lodestar Licensing Group Llc | Apparatuses including capacitors including multiple dielectric materials, and related methods |
KR102642921B1 (en) | 2018-12-11 | 2024-03-05 | 마이크론 테크놀로지, 인크 | Electronic devices including capacitor structures and related systems |
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