US20180033657A1 - Pressure purge etch method for etching complex 3-d structures - Google Patents
Pressure purge etch method for etching complex 3-d structures Download PDFInfo
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- US20180033657A1 US20180033657A1 US15/220,785 US201615220785A US2018033657A1 US 20180033657 A1 US20180033657 A1 US 20180033657A1 US 201615220785 A US201615220785 A US 201615220785A US 2018033657 A1 US2018033657 A1 US 2018033657A1
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- 238000000034 method Methods 0.000 title claims abstract description 118
- 238000010926 purge Methods 0.000 title claims abstract description 45
- 238000005530 etching Methods 0.000 title claims abstract description 25
- 238000012545 processing Methods 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 239000006227 byproduct Substances 0.000 claims abstract description 25
- 230000001939 inductive effect Effects 0.000 claims description 12
- 229910052731 fluorine Inorganic materials 0.000 claims description 11
- 239000011737 fluorine Substances 0.000 claims description 11
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 10
- 239000006185 dispersion Substances 0.000 claims description 6
- 238000009616 inductively coupled plasma Methods 0.000 claims description 6
- 239000012530 fluid Substances 0.000 claims description 5
- 238000004891 communication Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 abstract description 12
- 239000007789 gas Substances 0.000 description 73
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 238000009826 distribution Methods 0.000 description 16
- 229910052581 Si3N4 Inorganic materials 0.000 description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 12
- 235000012431 wafers Nutrition 0.000 description 10
- 239000010410 layer Substances 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 9
- 239000000203 mixture Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- 230000001154 acute effect Effects 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002894 chemical waste Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005672 electromagnetic field Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 238000010943 off-gassing Methods 0.000 description 1
- -1 oxides Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
- H01J37/32816—Pressure
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
- H01J37/3211—Antennas, e.g. particular shapes of coils
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32174—Circuits specially adapted for controlling the RF discharge
- H01J37/32183—Matching circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32357—Generation remote from the workpiece, e.g. down-stream
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/3244—Gas supply means
- H01J37/32449—Gas control, e.g. control of the gas flow
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
- H01J37/32816—Pressure
- H01J37/32825—Working under atmospheric pressure or higher
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
- H01J37/32816—Pressure
- H01J37/32834—Exhausting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
- H01J37/32853—Hygiene
- H01J37/32871—Means for trapping or directing unwanted particles
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02046—Dry cleaning only
-
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- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
-
- H01L27/11551—
-
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Definitions
- the present disclosure relates to substrate processing systems and methods, and more particularly to substrate processing systems and methods for selective etching of one film material relative to other film materials and removal of etch byproducts.
- Substrate processing systems may be used to etch film on a substrate such as a semiconductor wafer.
- the substrate processing systems typically include a processing chamber, a gas distribution device and a substrate support. During processing, the substrate is arranged on the substrate support. Different gas mixtures may be introduced into the processing chamber and plasma may be used to activate chemical reactions.
- NAND flash memory uses dense 3D structures in order to increase memory capacity while maintaining low cost per bit and without degrading performance. Creating the 3D structures involves depositing and etching multiple layers of different films. Etching film from the 3D structures is particularly difficult because etch byproducts such as fluorine are often trapped in the 3D structures, which leads to defects and device failures.
- one type of film such as silicon nitride (SiN) film
- SiN silicon dioxide
- wet etching processes such as hot phosphoric acid are typically used for selectively etching the SiN film.
- Hot phosphoric acid has several limitations including meeting selectivity requirements with respect to low density oxide, particle and defect control (particularly in oxide fins), slow etch rate, pattern collapse from surface tension, high cost due to expensive wet chemicals and chemical waste management.
- a method for etching a substrate and removing byproducts includes a) setting process parameters of a processing chamber for a selective dry etch process; b) setting process pressure of the processing chamber to a first predetermined pressure in a range from 1 Torr to 10 Torr for the selective dry etch process; c) selectively etching a first film material of a substrate relative to a second film material of the substrate in the processing chamber during a first period; d) lowering pressure in the processing chamber to a second predetermined pressure that is less than the first predetermined pressure by a factor greater than or equal to 4; and e) purging the processing chamber at the second predetermined pressure for a second period.
- the method includes repeating a) through e) N times, where N is an integer greater than one.
- the method includes repeating b) through e) N times, where N is an integer greater than one.
- the method includes varying at least one of the first predetermined pressure and the first period during at least one of the N times.
- the method includes varying at least one of the second predetermined pressure and the second period during at least one of the N times.
- the selective dry etch process uses remote plasma.
- the remote plasma is maintained during b) through e).
- the remote plasma is ignited prior to c) and extinguished after c).
- the remote plasma is generated using process gas including fluorine gas.
- the processing chamber includes an upper chamber region; an inductive coil arranged outside of the upper chamber region; a lower chamber region including a substrate support; and a gas dispersion device arranged between the upper chamber region and the lower chamber region.
- the gas dispersion device includes a plurality of holes in fluid communication with the upper chamber region and the lower chamber region. Inductively coupled plasma is generated in the upper chamber region by supplying power to the inductive coil.
- FIGS. 1A and 1B are side cross-sectional views of an example of a substrate including stacks of alternating layers of a first film material that is selectively etched relative to a second film material according to the present disclosure
- FIG. 2 is a flowchart illustrating an example of a method for selective dry etching and removing byproducts according to the present disclosure
- FIGS. 3A to 3C are graphs illustrating examples of variation of process periods and pressures according to the present disclosure.
- FIGS. 4 and 5 are flowcharts illustrating other example of methods for selective dry etching and removing byproducts according to the present disclosure.
- FIG. 6 is a functional block diagram of an example of an inductively coupled plasma (ICP) substrate processing chamber for selectively etching silicon nitride film according to the present disclosure.
- ICP inductively coupled plasma
- the present disclosure relates to systems and methods for increasing etch efficiency during selective etching of one type of film material of a substrate relative to another type of film material of the substrate using a dry etch process.
- the substrate is a memory device that includes 3-D structures, although other types of devices can be used.
- the present disclosure describes systems and methods for selective etching and removing byproducts after the selective dry etch process without additional plasma treatment. The approach described herein also helps with outgassing in the substrate.
- the systems and methods according to the present disclosure create a pressure difference between an etch step and a purge step following the etch step.
- the etch and purge steps can be modified depending on the geometry of structures and the amount of byproducts that are produced. For example, the number of etch/purge steps, specific gas flows, pressures, and periods can be modified as needed.
- the method according to the present disclosure can be used to etch SiN film in 3D NAND devices selective to SiO 2 film.
- the method according to the present disclosure can be used to etch other 3D structures such as tungsten (W) (selective to SiO 2 ) recess after W deposition in 3D NAND devices.
- a substrate 6 includes one or more stacks 8 arranged on one or more underlying layers 16 .
- the stacks 8 include alternating layers 10 such as fins 12 and intervening layers 14 .
- the fins 12 are made of SiO 2 and the intervening layers 14 are made of SiN.
- the layers 14 need to be etched inwardly relative to ends of the fins 12 as can be seen in FIG. 1B .
- the stacks 8 are arranged in close proximity. In addition to selective etching, byproducts of the etch process need to be removed from the substrate 6 .
- a method 40 for selectively etching a first type of film relative to a second type of film of a substrate and removing etch byproducts is shown.
- selective dry etching process parameters of a processing chamber are set.
- chamber pressure is set to a first predetermined pressure value for the selective dry etch process.
- the selective dry etch process is performed to remove one type of film selectively relative to another type of film during a first predetermined period.
- the process parameters of the selective dry etch are optimized for selective removal of SiN.
- Examples of systems and methods for performing selective dry etch are described in “Ultrahigh Selective Nitride Etch to Form FinFET Devices”, U.S. Patent Provisional Application Ser. No. 62/294,603, filed on Feb. 12, 2016, which is hereby incorporated by reference in its entirety. Additional examples of systems and methods for performing selective dry etch are described in “Selective Nitride Etch”, U.S. patent application Ser. No. 14/576,020 filed Dec. 18, 2014, which is hereby incorporated by reference in its entirety.
- the chamber pressure is significantly reduced from the first predetermined pressure value for etching to a second predetermined pressure value for purging.
- the first predetermined pressure is in a range from 1 Torr 10 Torr and is reduced by a factor greater than or equal to 4.
- the purge parameters of the processing chamber are set.
- the purge step is performed to remove byproducts of the dry etch process during a second predetermined period at the second predetermined pressure.
- the selective dry etch step may be performed at 2 Torr (T).
- T 2 Torr
- the pressure is reduced from 2 T to less than or equal to 500 mT or lower, although other pressure values can be used.
- the pressure during the purge step is reduced to less than or equal to 200 mT, although other pressure values can be used. Due to the lower pressure during the purge step, etch byproducts are efficiently pumped out of complex 3D structures of the NAND device and the concentration of etch byproduct over the substrate surface falls. The reduction creates a steep gradient of chemical potential between outer locations of the substrate surface and locations inside of the 3D structures. The chemical potential gradient increases the diffusion of etch byproduct from inside of the 3D structures.
- etch byproduct that is pumped out during one etch/purge cycle helps to increase the efficiency of the etch process during the following cycle since the byproducts are removed mid-process.
- 3 to 10 etch/purge cycles are performed over a combined period from 3 to 20 minutes.
- 6 etch/purge cycles are performed during a combined period of 8 to 10 minutes.
- the lower pressure purge step extracts excess fluorine from the 3D structures and prevents subsequent damage to the 3D structures caused by the fluorine.
- the purge step can be performed at the end of two or more etch cycles or between each etch cycle.
- the etch/purge periods can be constant or variable periods.
- RF plasma power can be varied during etch and purge step or held constant.
- the etch and purge step pressures can be constant or varied.
- the purge step can be performed with inert gas and no other process gases in the processing chamber, with low pressure process gases without plasma, or with low pressure process gases with plasma.
- the process periods and process pressures during the dry selective etching and/or purge steps can remain the same, respectively, for each of the cycles as shown in FIG. 3A .
- the process periods and/or process pressures can be varied (increased or decreased), respectively, during the dry etching and/or purge steps for one or more of the cycles.
- the pressure is varied.
- the process periods are varied. As can be appreciated, other combinations are contemplated.
- the remote plasma may be left on during the purge step (as in FIG. 2 ) if the plasma is capable of remaining ignited at lower pressures used during the purge step. Alternately, the plasma can be extinguished during the purge step.
- the remote plasma is struck at 62 before performing step 46 . After performing step 46 , the remote plasma is extinguished at 64 .
- the selective dry etch process is used to selectively etch SiN relative to SiO 2 in a 3D NAND memory device, although types of film or devices can be used.
- the etch/purge process includes multiple etch/purge cycles. In some examples, the process employs between 4 and 10 process cycles. For example, the edge/purge process may employ 6 etch/purge cycles.
- the SiN film that is to be etched is located in recessed areas of the 3D NAND memory device.
- the chamber pressure during the selective dry etch is in a range between 1 Torr and 10 Torr, although higher or lower chamber pressures may be used. In some examples, the chamber pressure during the selective dry etch is in a range between 1 Torr and 3 Torr, although higher or lower chamber pressures may be used. In some examples, the chamber pressure during the purge step is in a range between 100 mTorr and 1 Torr, although higher or lower chamber pressures may be used. In some examples, the chamber pressure during the purge step is in a range between 100 mTorr and 500 mTorr, although higher or lower chamber pressures may be used.
- the chamber pressure during the purge step is reduced by a factor of 4 to 20 relative to the chamber pressure used during the selective dry etch process, although higher or lower factors may be used. In some examples, the chamber pressure during the purge step is reduced by a factor of 4 to 10 relative to the chamber pressure used during the selective dry etch process, although higher or lower factors may be used.
- the substrate processing chamber 100 is used to etch SiN film relative to SiO 2 film in a 3D NAND structure. While a specific substrate processing chamber is shown and described, the methods described herein may be implemented on other types of substrate processing systems.
- the substrate processing chamber 100 includes a downstream inductively coupled plasma (ICP) source.
- ICP inductively coupled plasma
- CCP capacitively coupled plasma
- the substrate processing chamber 100 includes a lower chamber region 102 and an upper chamber region 104 .
- the lower chamber region 102 is defined by chamber sidewall surfaces 108 , a chamber bottom surface 110 and a lower surface of a gas distribution device 114 .
- the gas distribution device 114 is omitted.
- the upper chamber region 104 is defined by an upper surface of the gas distribution device 114 and an inner surface of a dome 118 .
- the dome 118 rests on a first annular support 121 .
- the first annular support 121 includes one or more spaced holes 123 for delivering process gas to the upper chamber region 104 , as will be described further below.
- the process gas is delivered by the one or more spaced holes 123 in an upward direction at an acute angle relative to a plane including the gas distribution device 114 , although other angles/directions may be used.
- a gas flow channel 134 in the first annular support 121 supplies gas to the one or more spaced holes 123 .
- the first annular support 121 may rest on a second annular support 125 that defines one or more spaced holes 127 for delivering process gas from a gas flow channel 129 to the lower chamber region 102 .
- holes 131 in the gas distribution device 114 align with the holes 127 .
- the gas distribution device 114 has a smaller diameter and the holes 131 are not needed.
- the process gas is delivered by the one or more spaced holes 127 in a downward direction towards the substrate at an acute angle relative to the plane including the gas distribution device 114 , although other angles/directions may be used.
- the upper chamber region 104 is cylindrical with a flat top surface and one or more flat inductive coils may be used.
- a single chamber may be used with a spacer located between a showerhead and the substrate support.
- a substrate support 122 is arranged in the lower chamber region 104 .
- the substrate support 122 includes an electrostatic chuck (ESC), although other types of substrate supports can be used.
- a substrate 126 is arranged on an upper surface of the substrate support 122 during etching.
- a temperature of the substrate 126 may be controlled by a heater plate 125 , an optional cooling plate with fluid channels and one or more sensors (not shown); although any other suitable substrate support temperature control system may be used.
- the gas distribution device 114 includes a showerhead (for example, a plate 128 having a plurality of spaced holes 129 ).
- the plurality of spaced holes 129 extend from the upper surface of the plate 128 to the lower surface of the plate 128 .
- the spaced holes 129 have a diameter in a range from 0.4′′ to 0.75′′ and the showerhead is made of a conducting material such as aluminum or a non-conductive material such as ceramic with an embedded electrode made of a conducting material.
- One or more inductive coils 140 are arranged around an outer portion of the dome 118 . When energized, the one or more inductive coils 140 create an electromagnetic field inside of the dome 118 . In some examples, an upper coil and a lower coil are used.
- a gas injector 142 injects one or more gas mixtures from a gas delivery system 150 - 1 .
- a gas delivery system 150 - 1 includes one or more gas sources 152 , one or more valves 154 , one or more mass flow controllers (MFCs) 156 , and a mixing manifold 158 , although other types of gas delivery systems may be used.
- a gas splitter (not shown) may be used to vary flow rates of a gas mixture.
- Another gas delivery system 150 - 2 may be used to supply an etch gas or an etch gas mixture to the gas flow channels 129 and/or 134 (in addition to or instead of etch gas from the gas injector 142 ).
- Suitable gas delivery systems are shown and described in commonly assigned U.S. patent application Ser. No. 14/945,680, entitled “Gas Delivery System” and filed on Dec. 4, 2015, which is hereby incorporated by reference in its entirety.
- Suitable single or dual gas injectors and other gas injection locations are shown and described in commonly assigned U.S. Provisional Patent Application Ser. No. 62/275,837, entitled “Substrate Processing System with Multiple Injection Points and Dual Injector” and filed on Jan. 7, 2016, which is hereby incorporated by reference in its entirety.
- the gas injector 142 includes a center injection location that directs gas in a downward direction and one or more side injection locations that inject gas at an angle with respect to the downward direction.
- the gas delivery system 150 - 1 delivers a first portion of the gas mixture at a first flow rate to the center injection location and a second portion of the gas mixture at a second flow rate to the side injection location(s) of the gas injector 142 .
- different gas mixtures are delivered by the gas injector 142 .
- the gas delivery system 150 - 1 delivers tuning gas to the gas flow channels 129 and 134 and/or to other locations in the processing chamber as will be described below.
- a plasma generator 170 may be used to generate RF power that is output to the one or more inductive coils 140 .
- Plasma 190 is generated in the upper chamber region 104 .
- the plasma generator 170 includes an RF generator 172 and a matching network 174 .
- the matching network 174 matches an impedance of the RF generator 172 to the impedance of the one or more inductive coils 140 .
- the gas distribution device 114 is connected to a reference potential such as ground.
- a valve 178 and a pump 180 may be used to control pressure inside of the lower and upper chamber regions 102 , 104 and to evacuate reactants.
- a controller 176 communicates with the gas delivery systems 150 - 1 and 150 - 2 , the valve 178 , the pump 180 , and/or the plasma generator 170 to control flow of process gas, purge gas, RF plasma and chamber pressure.
- plasma is sustained inside the dome 118 by the one or more inductive coils 140 .
- One or more gas mixtures are introduced from a top portion of the chamber using the gas injector 142 (and/or holes 123 ) and plasma is confined within the dome 118 using the gas distribution device 114 .
- Confining the plasma in the dome 118 allows volume recombination of plasma species and effusing desired etchant species through the gas distribution device 114 .
- Some amount of ions will diffuse out of the plasma region through the gas distribution device 114 .
- the amount of plasma that diffuses is an order of magnitude lower than the plasma located inside the dome 118 .
- Most of ions in the plasma are lost by volume recombination at high pressures. Surface recombination loss at the upper surface of the gas distribution device 114 also lowers ion density below the gas distribution device 114 .
- an RF bias generator 184 is provided and includes an RF generator 186 and a matching network 188 .
- the RF bias can be used to create plasma between the gas distribution device 114 and the substrate support or to create a self-bias on the substrate 126 to attract ions.
- the controller 176 may be used to control the RF bias.
- the systems and methods according to the present disclosure provide a selective dry etch process with byproduct removal that improves throughput and decreases cost of ownership.
- the methods described herein make it more feasible to selectively remove film in complicated 3D structures without pattern collapse.
- the low pressure purge sequence after the selective dry etch increases etch efficiency and helps to reduce fluorine in the 3D structures thereby preventing damage to the 3D structures due to fluorine attack.
- the method according to the present disclosure creates a chemical potential gradient between the substrate surface and inside portions of the 3D structures thereby increasing diffusion of etch byproducts.
- the processing chamber described above can be configured with a relatively small volume (55 L) for a single station and high total gas flow. Due to high gas flow, residence time is very low, which helps to purge out the main etch gases very quickly.
- the processing chamber uses an inductively coupled plasma (ICP) source to generate high density plasma, which diffuses out through the showerhead and contacts the wafer. Due to the downstream nature of the reactive species, SiN film is etched with very high selectivity to SiO 2 . High density of radicals pass through the grounded showerhead and chemically modify the film's surface. Dangling bonds are formed on the SiN surface during desorption. Fluorine radicals start to remove nitride.
- ICP inductively coupled plasma
- oxide and poly form a thermodynamically stable monolayer, which is immune to fluorine attack. Since the 3D structures are complicated, there is a high probability that volatile byproducts will be trapped inside of the 3D structure.
- the pressure/purge treatment described herein effectively removes the byproducts.
- Spatial and functional relationships between elements are described using various terms, including “connected,” “engaged,” “coupled,” “adjacent,” “next to,” “on top of,” “above,” “below,” and “disposed.” Unless explicitly described as being “direct,” when a relationship between first and second elements is described in the above disclosure, that relationship can be a direct relationship where no other intervening elements are present between the first and second elements, but can also be an indirect relationship where one or more intervening elements are present (either spatially or functionally) between the first and second elements.
- the phrase at least one of A, B, and C should be construed to mean a logical (A OR B OR C), using a non-exclusive logical OR, and should not be construed to mean “at least one of A, at least one of B, and at least one of C.”
- a controller is part of a system, which may be part of the above-described examples.
- Such systems can comprise semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.).
- These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate.
- the electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems.
- the controller may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with a specific system.
- temperature settings e.g., heating and/or cooling
- RF radio frequency
- the controller may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like.
- the integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software).
- Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system.
- the operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer.
- the controller may be a part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof.
- the controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing.
- the computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process.
- a remote computer e.g. a server
- the remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer.
- the controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control.
- the controller may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein.
- An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.
- example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and/or manufacturing of semiconductor wafers.
- PVD physical vapor deposition
- CVD chemical vapor deposition
- ALD atomic layer deposition
- ALE atomic layer etch
- the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.
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Abstract
A method for etching a substrate and removing byproducts includes a) setting process parameters of a processing chamber for a selective dry etch process; b) setting process pressure of the processing chamber to a first predetermined pressure in a range from 1 Torr to 10 Torr for the selective dry etch process; c) selectively etching a first film material of a substrate relative to a second film material of the substrate in the processing chamber during a first period; d) lowering pressure in the processing chamber to a second predetermined pressure that is less than the first predetermined pressure by a factor greater than or equal to 4; and e) purging the processing chamber at the second predetermined pressure for a second period.
Description
- The present disclosure relates to substrate processing systems and methods, and more particularly to substrate processing systems and methods for selective etching of one film material relative to other film materials and removal of etch byproducts.
- The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
- Substrate processing systems may be used to etch film on a substrate such as a semiconductor wafer. The substrate processing systems typically include a processing chamber, a gas distribution device and a substrate support. During processing, the substrate is arranged on the substrate support. Different gas mixtures may be introduced into the processing chamber and plasma may be used to activate chemical reactions.
- NAND flash memory uses dense 3D structures in order to increase memory capacity while maintaining low cost per bit and without degrading performance. Creating the 3D structures involves depositing and etching multiple layers of different films. Etching film from the 3D structures is particularly difficult because etch byproducts such as fluorine are often trapped in the 3D structures, which leads to defects and device failures.
- When integrating some semiconductor substrates such as the 3-D NAND flash memory devices, one type of film (such as silicon nitride (SiN) film) needs to be etched with very high selectivity to another type of film (such as silicon dioxide (SiO2), polysilicon, etc.). Wet etching processes such as hot phosphoric acid are typically used for selectively etching the SiN film. Hot phosphoric acid has several limitations including meeting selectivity requirements with respect to low density oxide, particle and defect control (particularly in oxide fins), slow etch rate, pattern collapse from surface tension, high cost due to expensive wet chemicals and chemical waste management.
- A method for etching a substrate and removing byproducts includes a) setting process parameters of a processing chamber for a selective dry etch process; b) setting process pressure of the processing chamber to a first predetermined pressure in a range from 1 Torr to 10 Torr for the selective dry etch process; c) selectively etching a first film material of a substrate relative to a second film material of the substrate in the processing chamber during a first period; d) lowering pressure in the processing chamber to a second predetermined pressure that is less than the first predetermined pressure by a factor greater than or equal to 4; and e) purging the processing chamber at the second predetermined pressure for a second period.
- In other features, the method includes repeating a) through e) N times, where N is an integer greater than one.
- In other features, the method includes repeating b) through e) N times, where N is an integer greater than one.
- In other features, the method includes varying at least one of the first predetermined pressure and the first period during at least one of the N times.
- In other features, the method includes varying at least one of the second predetermined pressure and the second period during at least one of the N times.
- In other features, the selective dry etch process uses remote plasma. The remote plasma is maintained during b) through e). The remote plasma is ignited prior to c) and extinguished after c). The remote plasma is generated using process gas including fluorine gas.
- In other features, the processing chamber includes an upper chamber region; an inductive coil arranged outside of the upper chamber region; a lower chamber region including a substrate support; and a gas dispersion device arranged between the upper chamber region and the lower chamber region. The gas dispersion device includes a plurality of holes in fluid communication with the upper chamber region and the lower chamber region. Inductively coupled plasma is generated in the upper chamber region by supplying power to the inductive coil.
- Further areas of applicability of the present disclosure will become apparent from the detailed description, the claims and the drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure.
- The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:
-
FIGS. 1A and 1B are side cross-sectional views of an example of a substrate including stacks of alternating layers of a first film material that is selectively etched relative to a second film material according to the present disclosure; -
FIG. 2 is a flowchart illustrating an example of a method for selective dry etching and removing byproducts according to the present disclosure; -
FIGS. 3A to 3C are graphs illustrating examples of variation of process periods and pressures according to the present disclosure; -
FIGS. 4 and 5 are flowcharts illustrating other example of methods for selective dry etching and removing byproducts according to the present disclosure; and -
FIG. 6 is a functional block diagram of an example of an inductively coupled plasma (ICP) substrate processing chamber for selectively etching silicon nitride film according to the present disclosure. - In the drawings, reference numbers may be reused to identify similar and/or identical elements.
- The present disclosure relates to systems and methods for increasing etch efficiency during selective etching of one type of film material of a substrate relative to another type of film material of the substrate using a dry etch process. In some examples, the substrate is a memory device that includes 3-D structures, although other types of devices can be used. The present disclosure describes systems and methods for selective etching and removing byproducts after the selective dry etch process without additional plasma treatment. The approach described herein also helps with outgassing in the substrate.
- In some examples, the systems and methods according to the present disclosure create a pressure difference between an etch step and a purge step following the etch step. In some examples, the etch and purge steps can be modified depending on the geometry of structures and the amount of byproducts that are produced. For example, the number of etch/purge steps, specific gas flows, pressures, and periods can be modified as needed.
- For example only, the method according to the present disclosure can be used to etch SiN film in 3D NAND devices selective to SiO2 film. In other examples, the method according to the present disclosure can be used to etch other 3D structures such as tungsten (W) (selective to SiO2) recess after W deposition in 3D NAND devices.
- In
FIGS. 1A-1B , asubstrate 6 includes one ormore stacks 8 arranged on one or moreunderlying layers 16. Thestacks 8 includealternating layers 10 such asfins 12 and interveninglayers 14. In some examples, thefins 12 are made of SiO2 and the interveninglayers 14 are made of SiN. During processing, thelayers 14 need to be etched inwardly relative to ends of thefins 12 as can be seen inFIG. 1B . As can be appreciated, thestacks 8 are arranged in close proximity. In addition to selective etching, byproducts of the etch process need to be removed from thesubstrate 6. - Referring now to
FIG. 2 , amethod 40 for selectively etching a first type of film relative to a second type of film of a substrate and removing etch byproducts is shown. At 42, selective dry etching process parameters of a processing chamber are set. At 44, chamber pressure is set to a first predetermined pressure value for the selective dry etch process. At 46, the selective dry etch process is performed to remove one type of film selectively relative to another type of film during a first predetermined period. - In some examples, the process parameters of the selective dry etch are optimized for selective removal of SiN. Examples of systems and methods for performing selective dry etch are described in “Ultrahigh Selective Nitride Etch to Form FinFET Devices”, U.S. Patent Provisional Application Ser. No. 62/294,603, filed on Feb. 12, 2016, which is hereby incorporated by reference in its entirety. Additional examples of systems and methods for performing selective dry etch are described in “Selective Nitride Etch”, U.S. patent application Ser. No. 14/576,020 filed Dec. 18, 2014, which is hereby incorporated by reference in its entirety.
- At 48, the chamber pressure is significantly reduced from the first predetermined pressure value for etching to a second predetermined pressure value for purging. In some examples, the first predetermined pressure is in a range from 1
Torr 10 Torr and is reduced by a factor greater than or equal to 4. At 50, the purge parameters of the processing chamber are set. At 52, the purge step is performed to remove byproducts of the dry etch process during a second predetermined period at the second predetermined pressure. - For example only, the selective dry etch step may be performed at 2 Torr (T). During the purge step, the pressure is reduced from 2 T to less than or equal to 500 mT or lower, although other pressure values can be used. In some examples, the pressure during the purge step is reduced to less than or equal to 200 mT, although other pressure values can be used. Due to the lower pressure during the purge step, etch byproducts are efficiently pumped out of complex 3D structures of the NAND device and the concentration of etch byproduct over the substrate surface falls. The reduction creates a steep gradient of chemical potential between outer locations of the substrate surface and locations inside of the 3D structures. The chemical potential gradient increases the diffusion of etch byproduct from inside of the 3D structures. The increase in etch byproduct that is pumped out during one etch/purge cycle helps to increase the efficiency of the etch process during the following cycle since the byproducts are removed mid-process. In some examples, 3 to 10 etch/purge cycles are performed over a combined period from 3 to 20 minutes. In some examples, 6 etch/purge cycles are performed during a combined period of 8 to 10 minutes.
- In examples using fluorine process gas during etching, the lower pressure purge step extracts excess fluorine from the 3D structures and prevents subsequent damage to the 3D structures caused by the fluorine. In some examples, the purge step can be performed at the end of two or more etch cycles or between each etch cycle. The etch/purge periods can be constant or variable periods. In addition, RF plasma power can be varied during etch and purge step or held constant. In addition, the etch and purge step pressures can be constant or varied. The purge step can be performed with inert gas and no other process gases in the processing chamber, with low pressure process gases without plasma, or with low pressure process gases with plasma.
- If additional etch/purge cycles are to be performed as determined at 54, the method returns to 42. Otherwise the method ends.
- Referring now to
FIGS. 3A to 3C , the process periods and process pressures during the dry selective etching and/or purge steps can remain the same, respectively, for each of the cycles as shown inFIG. 3A . Alternately, the process periods and/or process pressures can be varied (increased or decreased), respectively, during the dry etching and/or purge steps for one or more of the cycles. InFIG. 3B , the pressure is varied. InFIG. 3C , the process periods are varied. As can be appreciated, other combinations are contemplated. - Referring now to
FIG. 4 , another example of amethod 60 for selectively etching a first film relative to a second film of a substrate and removing etch byproducts is shown. As can be appreciated, the remote plasma may be left on during the purge step (as inFIG. 2 ) if the plasma is capable of remaining ignited at lower pressures used during the purge step. Alternately, the plasma can be extinguished during the purge step. At 62, the remote plasma is struck at 62 before performingstep 46. After performingstep 46, the remote plasma is extinguished at 64. - In some examples, the selective dry etch process is used to selectively etch SiN relative to SiO2 in a 3D NAND memory device, although types of film or devices can be used. In some examples, the etch/purge process includes multiple etch/purge cycles. In some examples, the process employs between 4 and 10 process cycles. For example, the edge/purge process may employ 6 etch/purge cycles. In some examples, the SiN film that is to be etched is located in recessed areas of the 3D NAND memory device.
- In some examples, the chamber pressure during the selective dry etch is in a range between 1 Torr and 10 Torr, although higher or lower chamber pressures may be used. In some examples, the chamber pressure during the selective dry etch is in a range between 1 Torr and 3 Torr, although higher or lower chamber pressures may be used. In some examples, the chamber pressure during the purge step is in a range between 100 mTorr and 1 Torr, although higher or lower chamber pressures may be used. In some examples, the chamber pressure during the purge step is in a range between 100 mTorr and 500 mTorr, although higher or lower chamber pressures may be used. In some examples, the chamber pressure during the purge step is reduced by a factor of 4 to 20 relative to the chamber pressure used during the selective dry etch process, although higher or lower factors may be used. In some examples, the chamber pressure during the purge step is reduced by a factor of 4 to 10 relative to the chamber pressure used during the selective dry etch process, although higher or lower factors may be used.
- Referring now to
FIG. 5 , an example of asubstrate processing chamber 100 for selective dry etching and byproduct removal according to the present disclosure is shown. In some examples, thesubstrate processing chamber 100 is used to etch SiN film relative to SiO2 film in a 3D NAND structure. While a specific substrate processing chamber is shown and described, the methods described herein may be implemented on other types of substrate processing systems. In some examples, thesubstrate processing chamber 100 includes a downstream inductively coupled plasma (ICP) source. An optional capacitively coupled plasma (CCP) source may be provided. - The
substrate processing chamber 100 includes alower chamber region 102 and anupper chamber region 104. Thelower chamber region 102 is defined by chamber sidewall surfaces 108, achamber bottom surface 110 and a lower surface of agas distribution device 114. In some examples, thegas distribution device 114 is omitted. - The
upper chamber region 104 is defined by an upper surface of thegas distribution device 114 and an inner surface of adome 118. In some examples, thedome 118 rests on a firstannular support 121. In some examples, the firstannular support 121 includes one or more spacedholes 123 for delivering process gas to theupper chamber region 104, as will be described further below. In some examples, the process gas is delivered by the one or more spacedholes 123 in an upward direction at an acute angle relative to a plane including thegas distribution device 114, although other angles/directions may be used. In some examples, agas flow channel 134 in the firstannular support 121 supplies gas to the one or more spacedholes 123. - The first
annular support 121 may rest on a secondannular support 125 that defines one or more spacedholes 127 for delivering process gas from agas flow channel 129 to thelower chamber region 102. In some examples, holes 131 in thegas distribution device 114 align with theholes 127. In other examples, thegas distribution device 114 has a smaller diameter and theholes 131 are not needed. In some examples, the process gas is delivered by the one or more spacedholes 127 in a downward direction towards the substrate at an acute angle relative to the plane including thegas distribution device 114, although other angles/directions may be used. - In other examples, the
upper chamber region 104 is cylindrical with a flat top surface and one or more flat inductive coils may be used. In still other examples, a single chamber may be used with a spacer located between a showerhead and the substrate support. - A
substrate support 122 is arranged in thelower chamber region 104. In some examples, thesubstrate support 122 includes an electrostatic chuck (ESC), although other types of substrate supports can be used. Asubstrate 126 is arranged on an upper surface of thesubstrate support 122 during etching. In some examples, a temperature of thesubstrate 126 may be controlled by aheater plate 125, an optional cooling plate with fluid channels and one or more sensors (not shown); although any other suitable substrate support temperature control system may be used. - In some examples, the
gas distribution device 114 includes a showerhead (for example, aplate 128 having a plurality of spaced holes 129). The plurality of spacedholes 129 extend from the upper surface of theplate 128 to the lower surface of theplate 128. In some examples, the spacedholes 129 have a diameter in a range from 0.4″ to 0.75″ and the showerhead is made of a conducting material such as aluminum or a non-conductive material such as ceramic with an embedded electrode made of a conducting material. - One or more
inductive coils 140 are arranged around an outer portion of thedome 118. When energized, the one or moreinductive coils 140 create an electromagnetic field inside of thedome 118. In some examples, an upper coil and a lower coil are used. Agas injector 142 injects one or more gas mixtures from a gas delivery system 150-1. - In some examples, a gas delivery system 150-1 includes one or
more gas sources 152, one ormore valves 154, one or more mass flow controllers (MFCs) 156, and a mixingmanifold 158, although other types of gas delivery systems may be used. A gas splitter (not shown) may be used to vary flow rates of a gas mixture. Another gas delivery system 150-2 may be used to supply an etch gas or an etch gas mixture to thegas flow channels 129 and/or 134 (in addition to or instead of etch gas from the gas injector 142). - Suitable gas delivery systems are shown and described in commonly assigned U.S. patent application Ser. No. 14/945,680, entitled “Gas Delivery System” and filed on Dec. 4, 2015, which is hereby incorporated by reference in its entirety. Suitable single or dual gas injectors and other gas injection locations are shown and described in commonly assigned U.S. Provisional Patent Application Ser. No. 62/275,837, entitled “Substrate Processing System with Multiple Injection Points and Dual Injector” and filed on Jan. 7, 2016, which is hereby incorporated by reference in its entirety.
- In some examples, the
gas injector 142 includes a center injection location that directs gas in a downward direction and one or more side injection locations that inject gas at an angle with respect to the downward direction. In some examples, the gas delivery system 150-1 delivers a first portion of the gas mixture at a first flow rate to the center injection location and a second portion of the gas mixture at a second flow rate to the side injection location(s) of thegas injector 142. In other examples, different gas mixtures are delivered by thegas injector 142. In some examples, the gas delivery system 150-1 delivers tuning gas to thegas flow channels - A
plasma generator 170 may be used to generate RF power that is output to the one or moreinductive coils 140.Plasma 190 is generated in theupper chamber region 104. In some examples, theplasma generator 170 includes anRF generator 172 and amatching network 174. Thematching network 174 matches an impedance of theRF generator 172 to the impedance of the one or moreinductive coils 140. In some examples, thegas distribution device 114 is connected to a reference potential such as ground. Avalve 178 and apump 180 may be used to control pressure inside of the lower andupper chamber regions - A
controller 176 communicates with the gas delivery systems 150-1 and 150-2, thevalve 178, thepump 180, and/or theplasma generator 170 to control flow of process gas, purge gas, RF plasma and chamber pressure. In some examples, plasma is sustained inside thedome 118 by the one or moreinductive coils 140. One or more gas mixtures are introduced from a top portion of the chamber using the gas injector 142 (and/or holes 123) and plasma is confined within thedome 118 using thegas distribution device 114. - Confining the plasma in the
dome 118 allows volume recombination of plasma species and effusing desired etchant species through thegas distribution device 114. In some examples, there is no RF bias applied to thesubstrate 126. As a result, there is no active sheath on thesubstrate 126 and ions are not hitting the substrate with any finite energy. Some amount of ions will diffuse out of the plasma region through thegas distribution device 114. However, the amount of plasma that diffuses is an order of magnitude lower than the plasma located inside thedome 118. Most of ions in the plasma are lost by volume recombination at high pressures. Surface recombination loss at the upper surface of thegas distribution device 114 also lowers ion density below thegas distribution device 114. - In other examples, an
RF bias generator 184 is provided and includes anRF generator 186 and amatching network 188. The RF bias can be used to create plasma between thegas distribution device 114 and the substrate support or to create a self-bias on thesubstrate 126 to attract ions. Thecontroller 176 may be used to control the RF bias. - The systems and methods according to the present disclosure provide a selective dry etch process with byproduct removal that improves throughput and decreases cost of ownership. The methods described herein make it more feasible to selectively remove film in complicated 3D structures without pattern collapse. The low pressure purge sequence after the selective dry etch increases etch efficiency and helps to reduce fluorine in the 3D structures thereby preventing damage to the 3D structures due to fluorine attack.
- The method according to the present disclosure creates a chemical potential gradient between the substrate surface and inside portions of the 3D structures thereby increasing diffusion of etch byproducts.
- In some examples, the processing chamber described above can be configured with a relatively small volume (55 L) for a single station and high total gas flow. Due to high gas flow, residence time is very low, which helps to purge out the main etch gases very quickly. In some examples, the processing chamber uses an inductively coupled plasma (ICP) source to generate high density plasma, which diffuses out through the showerhead and contacts the wafer. Due to the downstream nature of the reactive species, SiN film is etched with very high selectivity to SiO2. High density of radicals pass through the grounded showerhead and chemically modify the film's surface. Dangling bonds are formed on the SiN surface during desorption. Fluorine radicals start to remove nitride. On other surfaces, oxide and poly form a thermodynamically stable monolayer, which is immune to fluorine attack. Since the 3D structures are complicated, there is a high probability that volatile byproducts will be trapped inside of the 3D structure. The pressure/purge treatment described herein effectively removes the byproducts.
- The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. It should be understood that one or more steps within a method may be executed in different order (or concurrently) without altering the principles of the present disclosure. Further, although each of the embodiments is described above as having certain features, any one or more of those features described with respect to any embodiment of the disclosure can be implemented in and/or combined with features of any of the other embodiments, even if that combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and permutations of one or more embodiments with one another remain within the scope of this disclosure.
- Spatial and functional relationships between elements (for example, between modules, circuit elements, semiconductor layers, etc.) are described using various terms, including “connected,” “engaged,” “coupled,” “adjacent,” “next to,” “on top of,” “above,” “below,” and “disposed.” Unless explicitly described as being “direct,” when a relationship between first and second elements is described in the above disclosure, that relationship can be a direct relationship where no other intervening elements are present between the first and second elements, but can also be an indirect relationship where one or more intervening elements are present (either spatially or functionally) between the first and second elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A OR B OR C), using a non-exclusive logical OR, and should not be construed to mean “at least one of A, at least one of B, and at least one of C.”
- In some implementations, a controller is part of a system, which may be part of the above-described examples. Such systems can comprise semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems. The controller, depending on the processing requirements and/or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with a specific system.
- Broadly speaking, the controller may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer.
- The controller, in some implementations, may be a part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus as described above, the controller may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.
- Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and/or manufacturing of semiconductor wafers.
- As noted above, depending on the process step or steps to be performed by the tool, the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.
Claims (21)
1. A method for etching a substrate and removing byproducts, the substrate comprising a stack including a plurality of first layers and a plurality of second layers, the first layers alternating with the second layers, the method comprising:
a) setting process parameters of a processing chamber for a selective dry etch process;
b) setting process pressure of the processing chamber to a first predetermined pressure in a range from 1 Torr to 10 Torr for the selective dry etch process;
c) selectively etching portion of one of the first layers relative to one of the second layers in the processing chamber during a first period;
d) lowering pressure in the processing chamber to a second predetermined pressure that is less than the first predetermined pressure by a factor greater than or equal to 4 in order to purge the processing chamber at the second predetermined pressure for a second period;
e) purging the processing chamber at the second predetermined pressure for the second period: and
f) repeating a) through e) or b) through e) N times, where N is an integer greater than one.
2-3. (canceled)
4. The method of claim 1 , further comprising varying at least one of the first predetermined pressure and the first period during at least one of the N times.
5. The method of claim 1 , further comprising varying at least one of the second predetermined pressure and the second period during at least one of the N times.
6. The method of claim 1 , wherein the selective dry etch process uses remote plasma.
7. The method of claim 6 , wherein the remote plasma is maintained during b) through e).
8. The method of claim 6 , wherein the remote plasma is ignited prior to c) and extinguished after c).
9. The method of claim 6 , wherein the remote plasma is generated using process gas including fluorine gas.
10. The method of claim 1 , wherein the processing chamber includes:
an upper chamber region;
an inductive coil arranged outside of the upper chamber region;
a lower chamber region including a substrate support; and
a gas dispersion device arranged between the upper chamber region and the lower chamber region.
11. The method of claim 10 , wherein:
the gas dispersion device includes a plurality of holes in fluid communication with the upper chamber region and the lower chamber region; and
inductively coupled plasma is generated in the upper chamber region by supplying power to the inductive coil.
12. A method for etching a substrate and removing byproducts, the substrate comprising a stack including a plurality of first layers and a plurality of second layers, the first layers alternating with the second layers, comprising:
a) setting process parameters of a processing chamber for an etch process;
b) setting process pressure of the processing chamber to a first predetermined pressure in a range from 1 Torr to 3 Torr for the etch process;
c) selectively etching a portion of one of the first layers relative to a one of the second layers in the processing chamber during a first period;
d) lowering pressure in the processing chamber to a second predetermined pressure that is less than the first predetermined pressure by a factor greater than or equal to 4 in order to purge the processing chamber at the second predetermined pressure for a second period; and
e) purging the processing chamber at the second predetermined pressure for the second period; and
f) repeating b) through e) N times, where N is an integer greater than one.
13. The method of claim 12 , further comprising varying at least one of the first predetermined pressure and the first period during at least one of the N times.
14. The method of claim 12 , further comprising varying at least one of the second predetermined pressure and the second period during at least one of the N times.
15. The method of claim 12 , wherein the etch process uses remote plasma.
16. The method of claim 15 , wherein the remote plasma is maintained during b) through e).
17. The method of claim 15 , wherein the remote plasma is ignited prior to c) and extinguished after c).
18. The method of claim 15 , wherein the remote plasma is generated using process gas including fluorine gas.
19. The method of claim 12 , wherein the processing chamber includes:
an upper chamber region;
an inductive coil arranged outside of the upper chamber region;
a lower chamber region including a substrate support; and
a gas dispersion device arranged between the upper chamber region and the lower chamber region.
20. The method of claim 19 , wherein:
the gas dispersion device includes a plurality of holes in fluid communication with the upper chamber region and the lower chamber region; and
inductively coupled plasma is generated in the upper chamber region by supplying power to the inductive coil.
21. A method for etching a substrate and removing byproducts, the substrate comprising a stack including a plurality of first layers and a plurality of second layers, the first layers alternating with the second layers, the method comprising:
a) setting process parameters of a processing chamber for a selective dry etch process;
b) setting process pressure of the processing chamber to a first predetermined pressure for the selective dry etch process;
c) selectively etching a portion of one of the first layers relative to one of the second layers in the processing chamber during a first period;
d) lowering pressure in the processing chamber to a second predetermined pressure that is less than the first predetermined pressure in order to purge the processing chamber at the second predetermined pressure for a second period
e) purging the processing chamber at the second predetermined pressure for the second period: and
f) repeating a) through e) or b) through e) N times, where N is an integer greater than one.
22. (canceled)
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US15/220,785 US9870932B1 (en) | 2016-07-27 | 2016-07-27 | Pressure purge etch method for etching complex 3-D structures |
KR1020170089742A KR102549146B1 (en) | 2016-07-27 | 2017-07-14 | Pressure purge etch method for etching complex 3-d structures |
CN201710589164.6A CN107665803B (en) | 2016-07-27 | 2017-07-19 | Pressure purge etching method for etching composite three-dimensional structures |
TW106124687A TWI721196B (en) | 2016-07-27 | 2017-07-24 | Pressure purge etch method for etching complex 3-d structures |
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WO2019200311A1 (en) * | 2018-04-12 | 2019-10-17 | Seaboard International, Inc. | Frac sand separator system |
JP2020077862A (en) * | 2018-11-05 | 2020-05-21 | 東京エレクトロン株式会社 | Etching method and plasma processing apparatus |
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US10741495B2 (en) * | 2018-01-18 | 2020-08-11 | Globalfoundries Inc. | Structure and method to reduce shorts and contact resistance in semiconductor devices |
CN111146086B (en) * | 2018-11-05 | 2024-05-03 | 东京毅力科创株式会社 | Etching method and plasma processing apparatus |
KR102328573B1 (en) * | 2020-01-17 | 2021-11-17 | 성균관대학교산학협력단 | Highly Selective Dry Etching of Silicon Nitride over Silicon Dioxide using C-free halogen based gas |
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US4960488A (en) * | 1986-12-19 | 1990-10-02 | Applied Materials, Inc. | Reactor chamber self-cleaning process |
JPH02128421A (en) * | 1988-11-08 | 1990-05-16 | Tokyo Electron Ltd | Etching device |
DE69128050D1 (en) | 1990-06-29 | 1997-12-04 | Applied Materials Inc | Two-stage self-cleaning process of a reaction chamber |
US6362110B1 (en) * | 2000-03-30 | 2002-03-26 | Lam Research Corporation | Enhanced resist strip in a dielectric etcher using downstream plasma |
KR101025323B1 (en) * | 2004-01-13 | 2011-03-29 | 가부시키가이샤 아루박 | Etching apparatus and etching method |
US7939450B2 (en) * | 2007-09-21 | 2011-05-10 | Tokyo Electron Limited | Method and apparatus for spacer-optimization (S-O) |
CN101728230A (en) * | 2008-10-17 | 2010-06-09 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Method for processing semiconductor substrate |
US20110065276A1 (en) * | 2009-09-11 | 2011-03-17 | Applied Materials, Inc. | Apparatus and Methods for Cyclical Oxidation and Etching |
US8985152B2 (en) | 2012-06-15 | 2015-03-24 | Novellus Systems, Inc. | Point of use valve manifold for semiconductor fabrication equipment |
US9595466B2 (en) * | 2015-03-20 | 2017-03-14 | Applied Materials, Inc. | Methods for etching via atomic layer deposition (ALD) cycles |
-
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WO2019200311A1 (en) * | 2018-04-12 | 2019-10-17 | Seaboard International, Inc. | Frac sand separator system |
JP2020077862A (en) * | 2018-11-05 | 2020-05-21 | 東京エレクトロン株式会社 | Etching method and plasma processing apparatus |
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CN107665803B (en) | 2021-10-26 |
TW201810395A (en) | 2018-03-16 |
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