US20180025972A1 - Power line layout structure for semiconductor device - Google Patents
Power line layout structure for semiconductor device Download PDFInfo
- Publication number
- US20180025972A1 US20180025972A1 US15/483,608 US201715483608A US2018025972A1 US 20180025972 A1 US20180025972 A1 US 20180025972A1 US 201715483608 A US201715483608 A US 201715483608A US 2018025972 A1 US2018025972 A1 US 2018025972A1
- Authority
- US
- United States
- Prior art keywords
- power line
- power
- line
- layout structure
- structure according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000002184 metal Substances 0.000 description 51
- 238000005086 pumping Methods 0.000 description 10
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000007792 addition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H01L27/108—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
- H01L2027/11868—Macro-architecture
- H01L2027/11874—Layout specification, i.e. inner core region
- H01L2027/11881—Power supply lines
Definitions
- Embodiments of the present disclosure generally relate to a semiconductor device, and more particularly to a power line layout structure for more efficiently arranging power lines located at a plurality of metal layers in a semiconductor device.
- Interconnects distribute a variety of signals and provide a variety of levels of power to the semiconductor devices, which means that a semiconductor device has various types of interconnects.
- a power line layout structure of a semiconductor device may include first through fifth power lines.
- the first and second power lines may be located at a first layer, and may provide different types of power-supply voltages.
- the third power line may be located at a second layer disposed at a level different from that of the first layer.
- the third power line may be coupled to the first power line through a first contact, and may extend in the same direction as the first power line.
- the fourth power line may be located at the second layer, and may be coupled to the second power line through a second contact.
- the fourth power line may extend in the same direction as the second power line.
- the fifth power line may be disposed between the first power line and the second power line in the first layer.
- a power line layout structure in accordance with an embodiment may include two or more power lines providing the same type of power-supply voltages.
- the two or more power lines may be disposed at different levels and extend in the same direction. At least one of the two or more power lines is narrower in width than another power line disposed at an adjacent level.
- the power line layout structure in accordance with an embodiment may include another power line providing a power supply voltage different from those the two or more power lines provide.
- the another power line may be disposed next to the at least one of the power lines at the same level as the at least one of the two or more first power lines.
- FIG. 1 is a plan view illustrating an example of a power line layout structure of a semiconductor device according to an embodiment of the present disclosure.
- FIG. 2 is a cross-sectional view illustrating the semiconductor device taken along the line A-A′ of FIG. 1 .
- FIG. 3 is a diagram illustrating an example method of forming parasitic capacitance in the semiconductor device illustrated in FIG. 2 .
- FIG. 1 is a plan view illustrating an example of a power line layout structure of a semiconductor device according to an embodiment of the present disclosure.
- FIG. 2 is a cross-sectional view illustrating the semiconductor device taken along the line A-A′ of FIG. 1 .
- FIGS. 1 and 2 illustrates an example in which power lines are formed in each of a second metal layer M 2 and a third metal layer M 3 .
- the second metal layer M 2 may include a plurality of power lines, for example, a first ground voltage line VSS (M 2 ), a first power-supply voltage line VDD (M 2 ), a second power-supply voltage line VDDQ (M 2 ), a second ground voltage power VSSQ (M 2 ), and a pumping voltage line VPPE (M 2 ).
- a third metal layer M 3 may include a plurality of power lines, for example, a first ground voltage line VSS (M 3 ), a first power-supply line VDD (M 3 ), and a pumping voltage line VPPE (M 3 ).
- the first ground voltage line VSS (M 3 ), the first power-supply voltage line VDD (M 3 ), and the pumping voltage line VPPE (M 3 ) located at the third metal layer M 3 may have the same line width W as one another, and a spacing S between adjacent lines may be the same as one another.
- the same type of power lines formed in the second metal layer M 2 and the third metal layer M 3 may be coupled to each other through contacts C 1 , C 2 , and C 3 .
- the first ground voltage line VSS (M 2 ) formed in the second metal layer M 2 and the first ground voltage line VSS (M 3 ) formed in the third metal layer M 3 may be coupled to each other through the contact C 1 .
- the first power-supply voltage line VDD (M 2 ) formed in the second metal layer M 2 and the first power-supply voltage line VDD (M 3 ) formed in the third metal layer M 3 may be coupled to each other through the contact C 2 .
- the pumping voltage line VPPE (M 2 ) formed in the second metal layer M 2 and the pumping voltage line VPPE (M 3 ) formed in the third metal layer M 3 may be coupled to each other through the contact C 3 .
- power lines in the second metal layer M 2 and the third metal layer M 3 may be arranged in the same direction.
- the first ground voltage line VSS (M 2 ) of the second metal layer M 2 and the first ground voltage line VSS (M 3 ) of the third metal layer M 3 may be arranged in the same direction.
- the first power-supply voltage line VDD (M 2 ) of the second metal layer M 2 and the first power-supply voltage line VDD (M 3 ) of the third metal layer M 3 may be arranged in the same direction.
- the pumping voltage line VPPE (M 2 ) of the second metal layer M 2 and the pumping voltage line VPPE (M 3 ) of the third metal layer M 3 may be arranged in the same direction.
- line widths (W) of power lines formed in the second metal layer M 2 may be different from line widths (W) of power lines formed in the third metal layer M 3 .
- the first ground voltage line VSS (M 2 ), the first power-supply voltage line VDD (M 2 ), and the pumping voltage line VPPE (M 2 ) formed in the second metal layer M 2 may be smaller in line width than the first ground voltage line VSS (M 3 ), the first power-supply voltage line VDD (M 3 ), and the pumping voltage line VPPE (M 3 ) formed in the third metal layer M 3 , respectively.
- power lines formed in the third metal layer M 3 may be smaller in line width than power lines formed in the second metal layer M 3 .
- the same type of power lines interconnected through the contact C 1 , C 2 or C 3 and formed in the second metal layer M 2 and the third metal layer M 3 may be arranged in the same direction as each other, and the same type of power lines in the second metal layer M 2 and the third metal layer M 3 may have different line widths from each other.
- power lines VSS (M 3 ), VDD (M 3 ), and VPPE (M 3 ) formed in the third metal layer M 3 may have the same line width W as each other, and a spacing S between adjacent power lines (e.g., VSS, VDD, and VPPE) may be the same or substantially the same as one another.
- each power line (e.g., VSS, VDD, VPPE) formed in the second metal layer M 2 may be smaller in line width than the above power lines formed in the third metal layer M 3 .
- the line widths of the power lines (e.g., VSS, VDD, and VPPE) formed in the second metal layer M 2 may have a minimum line width needed for connection to the contacts C 1 , C 2 , and C 3 .
- each power lines (e.g., VSS, VDD, VPPE) formed in the second metal layer M 2 may have a line width that is equal to or larger than a diameter of the corresponding contact C 1 , C 2 , or C 3 .
- each power line VSS (M 2 ), VDD (M 2 ), or VPPE (M 2 ) of the second metal layer M 2 is smaller than the line width of each power line VSS (M 3 ), VDD (M 3 ), or VPPE (M 3 ) of the third metal layer M 3 , more space between adjacent power lines may become available in the second metal layer M 2 compared to that in the third metal layer M 3 .
- different types of power lines that are not coupled to the power lines VSS (M 3 ), VDD (M 3 ), and VPPE (M 3 ) of the third metal layer M 3 may be formed in the spaces between adjacent power lines VSS (M 2 ), VDD (M 2 ), and VPPE (M 2 ) of the second metal layer M 2 .
- the second power-supply voltage line VDDQ (M 2 ) and the second ground voltage line VSSQ (M 2 ) formed in the second metal layer M 2 may partially overlap power lines VSS (M 3 ), VDD (M 3 ), and VPPE (M 3 ) of the third metal layer M 3 .
- the second power-supply voltage line VDDQ of the second metal layer M 2 may partially overlap the first ground voltage line VSS (M 3 ) and the first power-supply voltage line VDD (M 3 ) of the third metal layer M 3 .
- the second ground voltage line VSSQ of the second metal layer M 2 may partially overlap the first power-supply voltage line VDD (M 3 ) and the pumping voltage line VPPE (M 3 ) of the third metal layer M 3 , when seen from above.
- the second power-supply line VDDQ and the second ground voltage line VSSQ of the second metal layer M 2 may overlap the power lines VSS (M 3 ), VDD (M 3 ), VPPE (M 3 ) of the third metal layer M 3 , such that parasitic capacitance is formed therebetween as illustrated in FIG. 3 to achieve power stabilization.
- operation characteristics of the semiconductor device can be improved.
- a power line layout structure in accordance with an embodiment may include two or more power lines providing the same type of power-supply voltages.
- the two or more power lines may be disposed at different levels and extend in the same direction. At least one of the two or more power lines is narrower in width than another power line disposed at an adjacent level.
- the power line layout structure in accordance with an embodiment may include another power line providing a power supply voltage different from those the two or more power lines provide.
- the another power line may be disposed next to the at least one of the power lines at the same level as the at least one of the two or more first power lines.
- the second power line when seen from above, partially overlaps the another first power line disposed at the adjacent level.
- the power line layout structure according to an embodiment may allow a larger number of power lines to be arranged in the semiconductor device without increasing the size thereof.
- the power line layout structure of the semiconductor device in accordance with an embodiment can increase parasitic capacitance between power sources by allowing different power lines to overlap each other. As a result, a power supply for the semiconductor device may be stabilized, and operation characteristics of the semiconductor device may be improved.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A power line layout structure of the semiconductor device may include first through fifth power lines. The first and second power lines may be located at a first layer, and may provide different types of power-supply voltages. The third power line may be located at a second layer disposed at a level different from that of the first layer. The third power line may be coupled to the first power line through a first contact, and may extend in the same direction as the first power line. The fourth power line may be located at the second layer, and may be coupled to the second power line through a second contact. The fourth power line may extend in the same direction as the second power line. The fifth power line may be disposed between the first power line and the second power line in the first layer.
Description
- The present application claims priority under 35 U.S.C 119(a) to Korean patent application number 10-2016-0091253 filed on 19 Jul. 2016, the disclosure of which is hereby incorporated by reference in its entirety.
- Embodiments of the present disclosure generally relate to a semiconductor device, and more particularly to a power line layout structure for more efficiently arranging power lines located at a plurality of metal layers in a semiconductor device.
- In manufacturing highly integrated, low-power semiconductor devices, an interconnect size and a spacing between adjacent interconnects in the semiconductor devices are becoming very important factors.
- Interconnects distribute a variety of signals and provide a variety of levels of power to the semiconductor devices, which means that a semiconductor device has various types of interconnects.
- However, it is difficult to effectively arrange such various types of interconnects in a limited area.
- In accordance with an aspect of the present disclosure, a power line layout structure of a semiconductor device may include first through fifth power lines. The first and second power lines may be located at a first layer, and may provide different types of power-supply voltages. The third power line may be located at a second layer disposed at a level different from that of the first layer. The third power line may be coupled to the first power line through a first contact, and may extend in the same direction as the first power line. The fourth power line may be located at the second layer, and may be coupled to the second power line through a second contact. The fourth power line may extend in the same direction as the second power line. The fifth power line may be disposed between the first power line and the second power line in the first layer.
- A power line layout structure in accordance with an embodiment may include two or more power lines providing the same type of power-supply voltages. The two or more power lines may be disposed at different levels and extend in the same direction. At least one of the two or more power lines is narrower in width than another power line disposed at an adjacent level. The power line layout structure in accordance with an embodiment may include another power line providing a power supply voltage different from those the two or more power lines provide. The another power line may be disposed next to the at least one of the power lines at the same level as the at least one of the two or more first power lines.
- It is to be understood that both the foregoing general description and the following detailed description are provided as example embodiments.
-
FIG. 1 is a plan view illustrating an example of a power line layout structure of a semiconductor device according to an embodiment of the present disclosure. -
FIG. 2 is a cross-sectional view illustrating the semiconductor device taken along the line A-A′ ofFIG. 1 . -
FIG. 3 is a diagram illustrating an example method of forming parasitic capacitance in the semiconductor device illustrated inFIG. 2 . - Reference will now be made in detail to certain embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. In the following description, a detailed description of related known configurations or functions incorporated herein will be omitted when it may make the subject matter less clear.
-
FIG. 1 is a plan view illustrating an example of a power line layout structure of a semiconductor device according to an embodiment of the present disclosure.FIG. 2 is a cross-sectional view illustrating the semiconductor device taken along the line A-A′ ofFIG. 1 . -
FIGS. 1 and 2 illustrates an example in which power lines are formed in each of a second metal layer M2 and a third metal layer M3. - The second metal layer M2 may include a plurality of power lines, for example, a first ground voltage line VSS (M2), a first power-supply voltage line VDD (M2), a second power-supply voltage line VDDQ (M2), a second ground voltage power VSSQ (M2), and a pumping voltage line VPPE (M2).
- A third metal layer M3 may include a plurality of power lines, for example, a first ground voltage line VSS (M3), a first power-supply line VDD (M3), and a pumping voltage line VPPE (M3). In this case, the first ground voltage line VSS (M3), the first power-supply voltage line VDD (M3), and the pumping voltage line VPPE (M3) located at the third metal layer M3 may have the same line width W as one another, and a spacing S between adjacent lines may be the same as one another.
- The same type of power lines formed in the second metal layer M2 and the third metal layer M3 may be coupled to each other through contacts C1, C2, and C3. In other words, the first ground voltage line VSS (M2) formed in the second metal layer M2 and the first ground voltage line VSS (M3) formed in the third metal layer M3 may be coupled to each other through the contact C1. The first power-supply voltage line VDD (M2) formed in the second metal layer M2 and the first power-supply voltage line VDD (M3) formed in the third metal layer M3 may be coupled to each other through the contact C2. The pumping voltage line VPPE (M2) formed in the second metal layer M2 and the pumping voltage line VPPE (M3) formed in the third metal layer M3 may be coupled to each other through the contact C3.
- In this case, power lines in the second metal layer M2 and the third metal layer M3 may be arranged in the same direction. In more detail, the first ground voltage line VSS (M2) of the second metal layer M2 and the first ground voltage line VSS (M3) of the third metal layer M3 may be arranged in the same direction. The first power-supply voltage line VDD (M2) of the second metal layer M2 and the first power-supply voltage line VDD (M3) of the third metal layer M3 may be arranged in the same direction. The pumping voltage line VPPE (M2) of the second metal layer M2 and the pumping voltage line VPPE (M3) of the third metal layer M3 may be arranged in the same direction.
- However, among power lines interconnected through the contact C1, C2, and C3, line widths (W) of power lines formed in the second metal layer M2 may be different from line widths (W) of power lines formed in the third metal layer M3. For example, as illustrated in
FIGS. 1 and 2 , the first ground voltage line VSS (M2), the first power-supply voltage line VDD (M2), and the pumping voltage line VPPE (M2) formed in the second metal layer M2 may be smaller in line width than the first ground voltage line VSS (M3), the first power-supply voltage line VDD (M3), and the pumping voltage line VPPE (M3) formed in the third metal layer M3, respectively. Alternatively, power lines formed in the third metal layer M3 may be smaller in line width than power lines formed in the second metal layer M3. - In an embodiment, the same type of power lines interconnected through the contact C1, C2 or C3 and formed in the second metal layer M2 and the third metal layer M3 may be arranged in the same direction as each other, and the same type of power lines in the second metal layer M2 and the third metal layer M3 may have different line widths from each other.
- Referring to
FIGS. 1 and 2 , power lines VSS (M3), VDD (M3), and VPPE (M3) formed in the third metal layer M3 may have the same line width W as each other, and a spacing S between adjacent power lines (e.g., VSS, VDD, and VPPE) may be the same or substantially the same as one another. In addition, each power line (e.g., VSS, VDD, VPPE) formed in the second metal layer M2 may be smaller in line width than the above power lines formed in the third metal layer M3. For example, the line widths of the power lines (e.g., VSS, VDD, and VPPE) formed in the second metal layer M2 may have a minimum line width needed for connection to the contacts C1, C2, and C3. For example, each power lines (e.g., VSS, VDD, VPPE) formed in the second metal layer M2 may have a line width that is equal to or larger than a diameter of the corresponding contact C1, C2, or C3. - As described above, assuming that the line width of each power line VSS (M2), VDD (M2), or VPPE (M2) of the second metal layer M2 is smaller than the line width of each power line VSS (M3), VDD (M3), or VPPE (M3) of the third metal layer M3, more space between adjacent power lines may become available in the second metal layer M2 compared to that in the third metal layer M3. In an embodiment, different types of power lines that are not coupled to the power lines VSS (M3), VDD (M3), and VPPE (M3) of the third metal layer M3 may be formed in the spaces between adjacent power lines VSS (M2), VDD (M2), and VPPE (M2) of the second metal layer M2.
- In this case, when seen from above, the second power-supply voltage line VDDQ (M2) and the second ground voltage line VSSQ (M2) formed in the second metal layer M2 may partially overlap power lines VSS (M3), VDD (M3), and VPPE (M3) of the third metal layer M3. For example, as illustrated in
FIG. 2 , when seen from above, the second power-supply voltage line VDDQ of the second metal layer M2 may partially overlap the first ground voltage line VSS (M3) and the first power-supply voltage line VDD (M3) of the third metal layer M3. The second ground voltage line VSSQ of the second metal layer M2 may partially overlap the first power-supply voltage line VDD (M3) and the pumping voltage line VPPE (M3) of the third metal layer M3, when seen from above. - As described above, when seen from above, the second power-supply line VDDQ and the second ground voltage line VSSQ of the second metal layer M2 may overlap the power lines VSS (M3), VDD (M3), VPPE (M3) of the third metal layer M3, such that parasitic capacitance is formed therebetween as illustrated in
FIG. 3 to achieve power stabilization. As a result, operation characteristics of the semiconductor device can be improved. - A power line layout structure in accordance with an embodiment may include two or more power lines providing the same type of power-supply voltages. The two or more power lines may be disposed at different levels and extend in the same direction. At least one of the two or more power lines is narrower in width than another power line disposed at an adjacent level. The power line layout structure in accordance with an embodiment may include another power line providing a power supply voltage different from those the two or more power lines provide. The another power line may be disposed next to the at least one of the power lines at the same level as the at least one of the two or more first power lines. Here, the second power line, when seen from above, partially overlaps the another first power line disposed at the adjacent level.
- The power line layout structure according to an embodiment may allow a larger number of power lines to be arranged in the semiconductor device without increasing the size thereof.
- In addition, the power line layout structure of the semiconductor device in accordance with an embodiment can increase parasitic capacitance between power sources by allowing different power lines to overlap each other. As a result, a power supply for the semiconductor device may be stabilized, and operation characteristics of the semiconductor device may be improved.
- Those skilled in the art will appreciate that embodiments of the present disclosure may be carried out in other ways than those set forth herein without departing from the spirit and essential characteristics of these embodiments. The above embodiments are therefore to be construed in all aspects as illustrative and not restrictive.
- The above embodiments of the present disclosure are illustrative and not limitative. Various alternatives and equivalents are possible. The above embodiments are not limited by the type of deposition, etching polishing, and patterning steps described herein. Nor is the embodiment limited to any specific type of semiconductor device. For example, the present disclosure may be implemented in a dynamic random access memory (DRAM) device or non volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.
Claims (17)
1. A power line layout structure for a semiconductor device comprising:
a first power line and a second power line located at a first layer and providing different types of power-supply voltages;
a third power line located at a second layer disposed at a level different from that of the first layer, the third power line being coupled to the first power line through a first contact and extending in the same direction as the first power line;
a fourth power line located at the second layer and coupled to the second power line through a second contact, the fourth power line extending in the same direction as the second power line; and
a fifth power line disposed between the first power line and the second power line in the first layer.
2. The power line layout structure according to claim 1 , wherein the fifth power line is a power-supply line that provides a power-supply voltage different from power-supply voltages the first and second power lines provide.
3. The power line layout structure according to claim 1 , wherein the first power line is smaller in line width than the third power line.
4. The power line layout structure according to claim 3 , wherein the first power line is located to overlap the third power line when seen from above.
5. The power line layout structure according to claim 1 , wherein the second power line is smaller in line width than the fourth power line.
6. The power line layout structure according to claim 5 , wherein the second power line is located to overlap the fourth power line when seen from above.
7. The power line layout structure according to claim 1 , wherein the fifth power line is located to partially overlap at least one of the third power line and the fourth power line when seen from above.
8. The power line layout structure according to claim 1 , wherein the third power line and the fourth power line have the same line width.
9. The power line layout structure according to claim 1 , further comprising:
a sixth power line located at the first layer and providing a power-supply voltage different from power-supply voltages the first power line and the second power line provide;
a seventh power line located at the second layer and coupled to the sixth power line through a third contact, seventh power line extending in the same direction as the sixth power line;
an eighth power line disposed between the second power line and the sixth power line in the first layer.
10. The power line layout structure according to claim 9 , wherein the eighth power line is a power-supply line that provides a power-supply voltage different from power-supply voltages the second and sixth power lines provide.
11. The power line layout structure according to claim 9 , wherein the sixth power line is smaller in line width than the seventh power line.
12. The power line layout structure according to claim 11 , wherein the sixth power line is located to overlap the seventh power line when seen from above.
13. The power line layout structure according to claim 9 , wherein the eighth power line is located to partially overlap at least one of the fourth power line and the seventh power line when seen from above.
14. The power line layout structure according to claim 9 , wherein the seventh power line has the same width as the first power line and the second power line.
15. The power line layout structure according to claim 9 , wherein a spacing between the third power line and the fourth power line is identical to a spacing between the fourth power line and the seventh power line.
16. A power line layout structure for a semiconductor device comprising:
two or more first power lines providing the same type of power-supply voltages, the two or more first power lines being disposed at different levels and extending in the same direction, at least one of the two or more first power lines is narrower in width than another first power line disposed at an adjacent level; and
a second power line disposed next to the at least one of the two or more first power lines at the same level as the at least one of the two or more first power lines, the second power line providing a power supply voltage different from those the two or more first power lines provide.
17. The power line layout structure according to claim 16 , wherein the second power line, when seen from above, partially overlaps the another first power line disposed at the adjacent level.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020160091253A KR102457220B1 (en) | 2016-07-19 | 2016-07-19 | Structure of power line in semiconductor device |
KR1020160091253 | 2016-07-19 | ||
KR10-2016-0091253 | 2016-07-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
US9870992B1 US9870992B1 (en) | 2018-01-16 |
US20180025972A1 true US20180025972A1 (en) | 2018-01-25 |
Family
ID=60935561
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/483,608 Active US9870992B1 (en) | 2016-07-19 | 2017-04-10 | Power line layout structure for semiconductor device |
Country Status (2)
Country | Link |
---|---|
US (1) | US9870992B1 (en) |
KR (1) | KR102457220B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11909708B2 (en) | 2020-05-19 | 2024-02-20 | Marvell Asia Pte Ltd | Protection switching device with link selective switching between host devices for maintenance of communication connection |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102601866B1 (en) * | 2019-01-16 | 2023-11-15 | 에스케이하이닉스 주식회사 | Semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100237508A1 (en) * | 2009-03-17 | 2010-09-23 | Kabushiki Kaisha Toshiba | Power-supply wiring structure for multilayer wiring and method of manufacturing multilayer wiring |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4837870B2 (en) * | 2002-11-05 | 2011-12-14 | 株式会社リコー | Layout design method for semiconductor integrated circuit |
KR101883379B1 (en) | 2012-06-08 | 2018-07-30 | 삼성전자주식회사 | Semiconductor device |
KR102161736B1 (en) * | 2014-08-13 | 2020-10-05 | 삼성전자주식회사 | System on chip, electronic apparatus including system on chip and design method of system on chip |
-
2016
- 2016-07-19 KR KR1020160091253A patent/KR102457220B1/en active IP Right Grant
-
2017
- 2017-04-10 US US15/483,608 patent/US9870992B1/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100237508A1 (en) * | 2009-03-17 | 2010-09-23 | Kabushiki Kaisha Toshiba | Power-supply wiring structure for multilayer wiring and method of manufacturing multilayer wiring |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11909708B2 (en) | 2020-05-19 | 2024-02-20 | Marvell Asia Pte Ltd | Protection switching device with link selective switching between host devices for maintenance of communication connection |
Also Published As
Publication number | Publication date |
---|---|
KR102457220B1 (en) | 2022-10-21 |
US9870992B1 (en) | 2018-01-16 |
KR20180009514A (en) | 2018-01-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7508696B2 (en) | Decoupling capacitor for semiconductor integrated circuit device | |
US11101265B2 (en) | Apparatuses and methods for semiconductor circuit layout | |
JP2008182058A (en) | Semiconductor device and semiconductor device forming method | |
US9806080B2 (en) | Semiconductor devices and methods of manufacturing the same | |
JP2008166495A (en) | Semiconductor integrated circuit device | |
US9837419B2 (en) | 3D semiconductor device with reduced chip size | |
JP2014056989A (en) | Semiconductor storage device | |
WO2016075859A1 (en) | Layout structure of semiconductor integrated circuit | |
US9870992B1 (en) | Power line layout structure for semiconductor device | |
JP7415183B2 (en) | Semiconductor integrated circuit device | |
US8507994B2 (en) | Semiconductor device | |
US8461920B2 (en) | Semiconductor integrated circuit device | |
US8399919B2 (en) | Unit block circuit of semiconductor device | |
US8436474B2 (en) | Semiconductor integrated circuit | |
US20160056161A1 (en) | Memory device | |
JP2011060942A (en) | Semiconductor device, method of fabricating the same, and semiconductor device layout method | |
US20140299920A1 (en) | Semiconductor integrated circuit device | |
US9230913B1 (en) | Metallization layers configured for reduced parasitic capacitance | |
US10083954B2 (en) | Semiconductor device and system including the same | |
US20110227133A1 (en) | Semiconductor device and standard cell | |
JP2007012694A (en) | Semiconductor integrated circuit device of standard cell system | |
US9502423B2 (en) | Semiconductor device layout and method for forming the same | |
TW201620078A (en) | Dynamic random access memory | |
WO2016181609A1 (en) | Semiconductor storage device | |
JP6118923B2 (en) | Semiconductor integrated circuit device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SK HYNIX INC., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KIM, JAE HWAN;REEL/FRAME:041943/0989 Effective date: 20170327 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |