US20170373000A1 - Interconnects having hybrid metallization - Google Patents
Interconnects having hybrid metallization Download PDFInfo
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- US20170373000A1 US20170373000A1 US15/701,480 US201715701480A US2017373000A1 US 20170373000 A1 US20170373000 A1 US 20170373000A1 US 201715701480 A US201715701480 A US 201715701480A US 2017373000 A1 US2017373000 A1 US 2017373000A1
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- 238000001465 metallisation Methods 0.000 title abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 206
- 239000002184 metal Substances 0.000 claims abstract description 206
- 238000000034 method Methods 0.000 claims abstract description 119
- 230000008569 process Effects 0.000 claims abstract description 53
- 238000000151 deposition Methods 0.000 claims abstract description 46
- 230000009977 dual effect Effects 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims description 45
- 230000004888 barrier function Effects 0.000 claims description 42
- 230000004913 activation Effects 0.000 claims description 33
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 23
- 229910017052 cobalt Inorganic materials 0.000 claims description 23
- 239000010941 cobalt Substances 0.000 claims description 23
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 23
- 229910052802 copper Inorganic materials 0.000 claims description 23
- 239000010949 copper Substances 0.000 claims description 23
- 230000005669 field effect Effects 0.000 claims description 20
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 16
- 238000005137 deposition process Methods 0.000 claims description 15
- 125000006850 spacer group Chemical group 0.000 claims description 12
- 229910052763 palladium Inorganic materials 0.000 claims description 8
- 230000003213 activating effect Effects 0.000 claims 2
- 230000008021 deposition Effects 0.000 abstract description 18
- 239000010410 layer Substances 0.000 description 137
- 238000010586 diagram Methods 0.000 description 25
- 239000004065 semiconductor Substances 0.000 description 22
- 238000009792 diffusion process Methods 0.000 description 20
- 229910052721 tungsten Inorganic materials 0.000 description 12
- 239000010937 tungsten Substances 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 6
- 239000004020 conductor Substances 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 4
- 229910003437 indium oxide Inorganic materials 0.000 description 4
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 229910052707 ruthenium Inorganic materials 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- -1 tungsten nitride Chemical class 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000003197 catalytic effect Effects 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 229910001429 cobalt ion Inorganic materials 0.000 description 1
- XLJKHNWPARRRJB-UHFFFAOYSA-N cobalt(2+) Chemical compound [Co+2] XLJKHNWPARRRJB-UHFFFAOYSA-N 0.000 description 1
- 239000008139 complexing agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000006479 redox reaction Methods 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
Definitions
- the present invention relates to integrated circuits (ICs) and, more specifically, to methods of forming IC structures with hybrid metallization interconnects and the resulting IC structures.
- Each field effect transistor (FET) in an integrated circuit (IC) structure will have multiple contacts including: contact plugs (also referred to herein as TS plugs) immediately adjacent to the top surfaces of the source/drain regions of the FET; source/drain contacts (also referred to herein as CA contacts) extending vertically through interlayer dielectric material from wires in a first metal level (referred to herein as M0) to the contact plugs, and a gate contact (also referred to herein as a CB contact) extending vertically from a wire in the first metal level through the interlayer dielectric material to the gate electrode of the FET.
- contact plugs also referred to herein as TS plugs
- CA contacts also referred to herein as CA contacts
- M0 first metal level
- CB contact also referred to herein as a CB contact
- the contact plugs have been tungsten or cobalt contact plugs
- the source/drain contacts and gate contact have been copper contacts and the metal levels have contained copper wires.
- IC structures have been developed that use cobalt for the source/drain and gate contacts instead of copper.
- cobalt for these contacts is the avoidance of copper diffusion at the interface between the gate contact and gate electrode and, thus, the avoidance of performance variations (e.g., changes in threshold voltage) that can result from copper diffusion.
- Disadvantages of using cobalt for the source/drain and gate contacts include both an increase in contact resistance due to the fact that the resistivity of cobalt is higher than copper (e.g., 5 . 6 ⁇ 10 ⁇ 8 as compared to 1.7 ⁇ 10 ⁇ 8 ) and an increase in contact-to-wire interface resistance and/or voids due to overlay misalignment that tends to occur given the currently used fabrication techniques.
- a dual damascene process can be performed to form trenches for metal wires in an upper portion of a dielectric layer and contact holes that extend from the trenches through a lower portion of the dielectric layer (e.g., contact holes for a first contact to a gate electrode of a field effect transistor (FET) and for second contacts to contact plugs on source/drain regions of the FET).
- a first metal can be deposited into the contact holes by an electroless deposition process and a second metal can then be deposited to fill the trenches.
- a single damascene process can be performed to form a first contact hole for a first contact through a dielectric layer to a gate electrode of a FET and a first metal can be deposited into the first contact hole using an electroless deposition process.
- a dual damascene process can be performed to form trenches for metal wires in an upper portion of the dielectric layer, including a trench that traverses the first contact hole, and to form second contact holes for second contacts through a lower portion of the dielectric layer to contact plugs on source/drain region of the FET.
- a second metal can then be deposited to fill the second contact holes and the trenches. Also disclosed herein are the resulting IC structures.
- a field effect transistor can be formed on a semiconductor wafer.
- the FET can be formed so as to have source/drain regions, a channel region between the source/drain regions and a gate electrode on the channel region.
- Contact plugs can be formed on either side of the gate electrode above the source/drain regions.
- a dielectric layer can be formed over the FET and, particularly, over the gate electrode and contact plugs.
- a dual damascene process can be performed in order to form trenches for metal wires in an upper portion of the dielectric layer and contact holes for contacts extending vertically from the trenches through a lower portion of the dielectric layer.
- the contact holes can include, for example, a first contact hole for a first contact extending vertically to the gate electrode and second contact holes for second contacts extending vertically to the contact plugs.
- a field effect transistor in another method of forming an integrated circuit (IC) structure that incorporates hybrid metallization interconnect(s), can similarly be formed on a semiconductor wafer such that it has source/drain regions, a channel region between the source/drain regions and a gate electrode on the channel region.
- Contact plugs can be formed on either side of the gate electrode above the source/drain regions.
- a dielectric layer can be formed over the FET and, particularly, over the gate electrode and contact plugs.
- a single damascene process can be performed to form at least a first contact hole for a first contact extending vertically through the dielectric layer to the gate electrode and a first metal can be deposited into the first contact hole using an electroless deposition process.
- a dual damascene process can be performed in order to form trenches for metal wires in an upper portion of the dielectric layer, including a trench that traverses the first contact hole, as well as second contact holes for second contacts extending vertically from the trenches through a lower portion of the dielectric layer to the contact plugs.
- a second metal which is different from the first metal, can then be deposited to fill the second contact holes and the trenches.
- the IC structures can have a field effect transistor (FET) on a semiconductor wafer.
- FET field effect transistor
- This FET can have source/drain regions, a channel region between the source/drain regions and a gate electrode on the channel region.
- the IC structure can further have contact plugs on the source/drain regions of the FET and a dielectric layer over the FET and, particularly, over the gate electrode and the contact plugs.
- the IC structures can further have metal wires located in an upper portion of the dielectric layer and contacts that extend vertically from the metal wires through a lower portion of the dielectric layer.
- the contacts can include a first contact extending vertically to the gate electrode and second contacts extending vertically to the contact plugs.
- the first contact can have an activation material immediately adjacent to the gate electrode and a first metal immediately adjacent to the activation material.
- the second contacts can similarly have activation material immediately adjacent to the contact plugs and the first metal immediately adjacent to the activation material.
- the second contacts can be devoid of the first metal and instead can be made of a second metal, which is different from the first metal. In either case, the wires can be made of the second metal.
- FIG. 1 is a flow diagram illustrating disclosed methods of forming an integrated circuit (IC) structure that incorporates hybrid metallization interconnect(s);
- FIG. 2A is a cross-section diagram illustrating an exemplary partially completed IC structure, which is formed according to the methods of FIG. 1 and which has two adjacent FETs with a shared source/drain region and a multi-finger gate structure;
- FIG. 2B is another cross-section diagram of the partially completed IC structure shown in FIG. 2A ;
- FIG. 2C is yet another cross-section diagram illustrating the partially completed IC structure shown in FIG. 2A ;
- FIG. 3 is a cross-section diagram illustrating a partially completed IC structure formed according to the methods of FIG. 1 ;
- FIG. 4 is a cross-section diagram illustrating a partially completed IC structure formed according to the methods of FIG. 1 ;
- FIG. 5 is a cross-section diagram illustrating a partially completed IC structure formed according to method embodiment A of FIG. 1 ;
- FIG. 6 is a cross-section diagram illustrating a partially completed IC structure formed according to method embodiment A of FIG. 1 ;
- FIGS. 7A-7C are cross-section diagrams illustrating alternative fill levels for the first metal deposited at process 116 of method embodiment A of FIG. 1 ;
- FIG. 8A is a cross-section diagram illustrating a completed IC structure formed according to method embodiment A of FIG. 1 ;
- FIG. 8B is another cross-section diagram of the IC structure shown in FIG. 8A ;
- FIGS. 9A-9C are cross-section diagrams illustrating alternative hybrid interconnect configurations for the IC structure of FIG. 8A ;
- FIG. 10 is a cross-section diagram illustrating a partially completed IC structure formed according to method embodiment B of FIG. 1 ;
- FIG. 11 is a cross-section diagram illustrating a partially completed IC structure formed according to method embodiment B of FIG. 1 ;
- FIG. 12 is a cross-section diagram illustrating a partially completed IC structure formed according to method embodiment B of FIG. 1 ;
- FIGS. 13A-13B are cross-section diagrams illustrating alternative fill levels for the first metal deposited at process 128 of method embodiment B of FIG. 1 ;
- FIG. 14A is a cross-section diagram illustrating a completed IC structure formed according to method embodiment B of FIG. 1 ;
- FIG. 14B is another cross-section diagram of the IC structure shown in FIG. 8A ;
- FIGS. 15A-15B are cross-section diagrams illustrating alternative hybrid interconnect configurations for the IC structure of FIG. 14A ;
- FIG. 16 is a cross-section diagram illustrating a prior art IC structure.
- each field effect transistor (FET) in an integrated circuit (IC) structure will have multiple contacts including: contact plugs (also referred to herein as TS plugs) immediately adjacent to the top surfaces of the source/drain regions of the FET; source/drain contacts (also referred to herein as CA contacts) extending vertically through interlayer dielectric material from wires in a first metal level (referred to herein as M0) to the contact plugs, and a gate contact (also referred to herein as a CB contact) extending vertically from a wire in the first metal level through the interlayer dielectric material to the gate electrode of the FET.
- contact plugs also referred to herein as TS plugs
- CA contacts also referred to herein as CA contacts
- M0 first metal level
- CB contact also referred to herein as a CB contact
- the contact plugs have been tungsten or cobalt contact plugs
- the source/drain contacts and gate contact have been copper contacts and the metal levels have contained copper wires.
- IC structures have been developed that use cobalt for the source/drain and gate contacts instead of copper.
- cobalt is the avoidance of copper diffusion at the interface between the gate contact and gate electrode and, thus, the avoidance of performance variations (e.g., changes in threshold voltage) that can result from copper diffusion.
- Disadvantages of using cobalt for the source/drain and gate contacts include both an increase in contact resistance due to the fact that the resistivity of cobalt is higher than copper (e.g., 5.6 ⁇ 10 ⁇ 8 as compared to 1.7 ⁇ 10 ⁇ 8 ) and an increase in contact-to-wire interface resistance and/or voids due to overlay misalignment that tends to occur given the currently used fabrication techniques. More specifically, as illustrated in FIG. 16 , semiconductor structures having cobalt source/drain contacts 20 and cobalt gate contacts 30 and copper wires 70 in the first metal level (i.e., the M0 level) are typically fabricated using discrete single damascene processes.
- a single damascene process is used to form contact holes through a layer 61 of interlayer dielectric material down to contact plug(s) 10 on source/drain regions and gate electrode(s) 50 and to fill those contact holes with cobalt 91 , thereby forming source/drain contact(s) 20 and gate contact(s) 30 , respectively.
- an etch stop layer 62 is formed on the layer 61 of interlayer dielectric material over the contacts 20 , 30 and an additional layer 63 of interlayer dielectric material is deposited on the etch stop layer 62 .
- Another single damascene process is then used to form trenches through the additional layer 63 of interlayer dielectric material and the etch stop layer 62 and to fill the trenches with copper 92 , thereby forming wires in a first metal level (M0) above the contacts 20 , 30 .
- M0 first metal level
- using the discrete single damascene processes to form the contacts and wires, as described above, can result in overlay issues and, particularly can result in a given wire only partially overlaying a given contact (as illustrated in circled area 99 ), which effectively increases contact resistance. In extreme cases, overlay misalignment can result in the given wire completely missing the given contact, thereby creating a void or disconnect between the contact and wire (not shown).
- a dual damascene process can be performed to form trenches in an upper portion of a dielectric layer and contact holes that extend from the trenches through a lower portion of the dielectric layer (e.g., contact holes to a gate electrode of a field effect transistor (FET) and to contact plugs on source/drain regions of the FET).
- a first metal can be deposited into the contact holes by an electroless deposition process and a second metal can then be deposited to fill the trenches.
- a single damascene process can be performed to form a first contact hole through a dielectric layer to a gate electrode of a FET and a first metal can be deposited into the first contact hole using an electroless deposition process.
- a dual damascene process can be performed to form trenches in an upper portion of the dielectric layer, including a trench that traverses the first contact hole, and to form second contact holes through a lower portion of the dielectric layer to contact plugs on source/drain region of the FET.
- a second metal can then be deposited to fill the second contact holes and the trenches. Also disclosed herein are the resulting IC structures.
- a field effect transistor can be formed on a semiconductor wafer ( 102 , see FIGS. 2A-2C ).
- Various techniques for forming FETs on a semiconductor wafer are well known in the art and, thus, the details of these techniques have been omitted from the specification in order to allow the reader to focus on the salient aspects of the disclosed methods.
- techniques for forming a FET involve providing a semiconductor layer.
- This semiconductor layer can, for example, be the semiconductor layer 204 of a semiconductor-on-insulator (SOI) wafer 201 , which includes a semiconductor substrate 202 (e.g., a silicon substrate or any other suitable semiconductor substrate), an insulator layer 203 (e.g., a silicon dioxide (SiO2) layer or any other suitable insulator layer) on the semiconductor substrate 202 and the semiconductor layer 204 (e.g., a silicon layer, a silicon germanium layer, a gallium nitride layer or any other suitable semiconductor layer) on the insulator layer 203 .
- SOI semiconductor-on-insulator
- the semiconductor layer can be an upper portion of a bulk semiconductor wafer (e.g., a silicon wafer or any other suitable wafer, such as a hybrid orientation (HOT) wafer), wherein the upper portion is isolated from a lower portion of the wafer, for example, by deep well (not shown).
- a semiconductor body can be defined in the semiconductor layer (e.g., by forming trench isolation regions 205 ).
- a gate structure which includes a gate dielectric layer and a gate electrode 250 on the gate dielectric layer, can be formed above a channel region 207 in the semiconductor body; gate sidewall spacers 240 can be formed on the gate; and source/drain regions 206 and, optionally, other components (e.g., source/drain extension regions, halos, etc.), can be formed within the semiconductor body on opposing sides of the channel region 207 .
- FIG. 2A illustrates an exemplary partially completed IC structure with two adjacent FETs having a shared source/drain region and a multi-finger gate structure (with a gate dielectric layer and gate electrode 250 on the gate dielectric layer).
- This multi-finger gate structure includes two essentially parallel first portions (i.e., two fingers) that traverse the channel regions 207 of the two FETs, respectively (see FIG. 2B ) and a second portion that is above a trench isolation region 205 and essentially perpendicular to and in contact with ends of the first portions (see FIG. 2C ). Additional process steps involved in the disclosed method are described in greater detail below and illustrated with respect to the structure shown in FIG. 2C .
- Contact plugs 210 can be formed above the source/drain regions 206 such that they are electrically isolated from the gate electrode 250 by the gate sidewall spacers 240 ( 104 , see FIG. 3 ). These contact plugs 210 can be, for example, self-aligned metal plugs, such as cobalt or tungsten plugs. Such contact plugs can be formed, for example, using a selective chemical vapor deposition technique or any other suitable deposition technique (e.g., non-selective deposition followed by an etch-back process or a chemical-mechanical polishing (CMP) process. In any case, the contact plugs 210 can be formed so as to have a height that is approximately equal to the height of the gate electrode 250 , as shown.
- CMP chemical-mechanical polishing
- a dielectric layer 260 can be formed over the FET and, particularly, over the gate electrode 250 , gate sidewall spacers 240 and contact plugs 210 ( 106 , see FIG. 4 ).
- the dielectric layer 260 can include one or more layers of interlayer dielectric (ILD) material.
- ILD material can be, for example, silicon oxide or any other suitable ILD material (e.g., borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), fluorinated tetraethyl orthosilicate (FTEOS), etc.).
- BPSG borophosphosilicate glass
- TEOS tetraethyl orthosilicate
- FTEOS fluorinated tetraethyl orthosilicate
- a dual damascene process can be performed in order to form trenches 280 for metal wires in an upper portion of the dielectric layer 260 and contact holes for contacts extending vertically from the trenches 280 through a lower portion of the dielectric layer 260 ( 112 , see FIG. 5 ).
- a first photolithography and etch pass is performed followed by a second photolithography and etch pass in order to define the trenches and the contact holes in the dielectric layer, respectively.
- the dual damascene processing can specifically be performed so that the resulting contact holes include, for example, at least one first contact hole 281 for at least one first contact (i.e., at least one CB contact) extending vertically from a trench through the lower portion of the dielectric layer 260 to the gate electrode 250 and second contact holes 282 for second contacts (i.e., CA contacts) extending vertically from trenches through the lower portion of the dielectric layer 260 to the contact plugs 210 on the source/drain regions 206 .
- FIG. 5 shows a first contact hole 281 and a second contact hole 282 extending vertically from different trenches 280 such that the first contact and second contact, once formed as discussed in greater detail below, will be electrically connected to different wires.
- first contact hole 281 and a second contact hole 282 could, alternatively, extend from the same trench such that the first contact and second contact, once formed as discussed in greater detail below, will be electrically connected to the same wire (e.g., in the case where the drain voltage controls the gate electrode).
- a thin film of activation material 293 e.g., palladium or other suitable activation material
- activation material 293 can be deposited on the bottom surface of the contact holes 281 - 282 (i.e., on gate electrode 250 and contact plugs 210 ) in order to selectively activate the bottom surfaces of the contact holes 281 - 282 (i.e., to improve the catalytic activity of the bottom surfaces) ( 114 , see FIG. 6 ).
- the thin film of activation material 293 can be deposited onto the bottom surfaces of the contact holes 281 - 282 by, for example, a wet, electroless plating process, which can selectively coat an activation material, such as palladium, on a metal surface.
- a first metal e.g., cobalt
- an electroless deposition process 116 , see FIG. 6 .
- an electroless deposition also referred to as electroless plating or auto-catalytic plating
- the electroless bath typically includes an aqueous solution of metal ions (e.g., cobalt ions), complexing agents, and reducing agents.
- the bath may also include stabilizers, various additives, and buffers, as well as rate promoters to speed up or slow down the deposition process.
- Metal deposition occurs as a result of a redox reaction and no electrical current or power supply, anodes, batteries, or rectifiers are required.
- Deposition of the first metal 291 can continue at process 116 until the first metal 291 completely fills portions of the contact holes 281 - 282 above the activation material and can stop when the level of the top surface of the first metal 291 is approximately co-planar with the level of the bottom surface of the trenches 280 (e.g., as shown in FIG. 6 and also as illustrated in FIG. 7A ).
- deposition of the first metal 291 can continue at process 116 until the first metal 291 partially fills the portions of the contact holes 281 - 282 above the activation material and can stop when the level of the top surface of the first metal 291 is some predetermined distance below the level of the bottom surface of the trenches 280 (e.g., as illustrated in FIG. 7B ).
- deposition of the first metal 291 can continue at process 116 until the first metal 291 completely fills the portions of the contact holes 281 - 282 above the activation material and partially fills the trenches 280 (i.e., overfills the contact holes) and can stop when the level of the top surface of the first metal 291 is some predetermined distance above the level of the bottom surface of the trenches 280 (e.g., as illustrated in FIG. 7C ).
- a diffusion barrier layer 295 can, optionally, be conformally deposited and a second metal 292 , which is different from the first metal 291 , can be deposited on the diffusion barrier layer 295 ( 118 - 120 , see FIG. 8A ).
- a suitable conductive material that exhibits high atomic diffusion resistance i.e., that exhibits low atomic diffusivity
- PVD physical vapor deposition
- CVD chemical vapor deposition
- Such a diffusion barrier layer 295 can be relatively thin and can be, for example, a chromium layer, a ruthenium layer, a tantalum layer, a tantalum nitride layer, an indium oxide layer, a tungsten layer, a tungsten nitride layer, a titanium layer, a titanium nitride layer, or any other suitable conductive barrier material as described above.
- FIG. 8B is a cross-section diagram of the resulting IC structure shown in FIG. 8A and shows an exemplary position of the first contact 230 to the gate structure relative to the second contacts 220 to the contact plugs 210 above the source/drain regions.
- the Figures are not intended to be limiting and the position of the first contact 230 may vary (e.g., the first contact 230 may not be aligned with either of the second contacts 220 ). Additionally, those skilled in the art will recognize that in a different FET configuration, for example, in a FET configuration wherein a discrete, essentially, rectangular gate structure traverses the channel region of the FET, the first contact to the gate structure may be positioned at one end of the gate structure, offset from the second contacts to the contact plugs on the source/drain regions.
- the barrier layer 295 will be immediately adjacent to the top surface of the first metal 291 and will line exposed surfaces of the contact holes (if any) and exposed surfaces of the trenches 280 . That is, if the top surface of the first metal 291 is level with the bottom surface of a trench, the barrier layer 295 will be immediately adjacent to the top surface of the first metal 291 and will line the exposed sidewalls and bottom surface of the trench (see FIG. 9A ).
- the barrier layer 295 will be immediately adjacent to the top surface of the first metal 291 , will line the exposed sidewalls of the upper portion of the contact hole and will further line the exposed sidewalls and bottom surface of the trench (see FIG. 9B ). If the top surface of the first metal 291 is above the level of the bottom surface of a trench, the barrier layer 295 will be immediately adjacent to the top surface of the first metal 291 and will line the exposed sidewalls of the upper portion of the trench (see FIG. 9C ).
- the second metal 292 deposited at process 120 can be copper.
- a copper seed layer (not shown) can be deposited onto the barrier layer 295 (e.g., by physical vapor deposition (PVD) or other suitable technique). Then, additional copper can further be deposited using an electroplating process.
- the second metal 292 can be any suitable metal material for metal level wire formation. In any case, the process of depositing the second metal 292 can continue until the trenches 280 are filled.
- all conductive material can be removed from the top surface of the dielectric layer 260 (e.g., using a chemical mechanical polishing (CMP) process) ( 122 ), thereby completing formation of the wires 270 in the trenches, formation of the at least one first contact 230 (i.e., the at least one CB contact), which extends to the gate electrode 250 , in the at least one first contact hole and formation of the second contacts 220 (i.e., the CA contacts), which extend to the contact plugs 210 on the source/drain regions, in the second contact holes.
- CMP chemical mechanical polishing
- a hybrid metallization interconnect is an interconnect (i.e., a contact, a wire, or a combined contact/wire structure) that contains different metals including at least the first metal 291 and the second metal 292 .
- contacts 220 - 230 may be hybrid metallization interconnects (e.g., as shown in FIG. 9B ); the wires 270 may be hybrid metallization interconnects (e.g., as shown in FIG. 9C ); or the combined contact 220 or 230 /wire 270 structures may be hybrid metallization interconnects (e.g., as shown in FIG. 9A ). It should be understood that the location of the hybrid metallization will depend upon when deposition of the first metal 291 is stopped at process 116 .
- a single damascene process can be performed to form at least one first contact hole 281 for at least one first contact (i.e., at least one CB contact) extending vertically through the dielectric layer 260 from the top surface to the gate electrode 250 ( 124 , see FIG. 10 ).
- first contact i.e., at least one CB contact
- a thin film of activation material 293 (e.g., palladium or other suitable activation material) can be deposited on the bottom surface of the first contact hole 281 (i.e., on the gate electrode 250 ) in order to selectively activate the bottom surface of the first contact hole 281 (i.e., to improve the catalytic activity of the bottom surfaces) ( 126 , see FIG. 11 ).
- the thin film of activation material 293 can be deposited onto the bottom surface of the first contact hole 281 by, for example, a wet, electroless plating process, which can selectively coat an activation material, such as palladium, on a metal surface.
- a first metal 291 e.g., cobalt
- an electroless deposition process 128 , see FIG. 11 . See detailed discussion above regarding electroless deposition of cobalt at process step 116 of method embodiment A.
- Deposition of the first metal 291 can continue at process 128 until the first metal 291 completely fills the portion of the first contact hole 281 above the activation material 293 .
- deposition of the first metal 291 can continue at process 128 until the first metal 291 partially fills the portion of the first contact hole 281 above the activation material 293 and can stop some predetermined distance below the level of the top surface of the dielectric layer 260 (as illustrated in FIG. 11 ).
- a dual damascene process can be performed in order to form both trenches 280 for metal wires in an upper portion of the dielectric layer 260 , including a trench that traverses the first contact hole 281 (i.e., that encompasses or etches through the upper portion of the first contact hole 281 ), and second contact holes 282 for second contacts (i.e., for CA contacts) extending vertically from the trenches 280 through a lower portion of the dielectric layer 260 to the contact plugs 210 on the source/drain regions 206 ( 130 , see FIG. 12 ).
- FIG. 12 shows the first contact hole 281 being traversed by one trench and the second contact hole 282 extending vertically from a different trench such that the first contact and second contact, once formed as discussed in greater detail below, will be electrically connected to different wires.
- a second contact hole 282 could extend vertically from the same trench that traverses the first contact hole 281 such that the first contact and second contact, once formed as discussed in greater detail below, will be electrically connected to the same wire (e.g., in the case where the drain voltage controls the gate electrode).
- the top surface of the first metal 291 in the first contact hole 281 may be essentially co-planar with the bottom surface of the trench that traverses it (e.g., as shown in FIGS. 12 and 13A ) or some distance below that bottom surface (e.g., as shown in FIG. 13B ).
- a diffusion barrier layer 295 can, optionally, be conformally deposited and a second metal 292 , which is different from the first metal 291 , can be deposited on the diffusion barrier layer 295 ( 132 - 134 , see FIG. 14A ).
- a second metal 292 which is different from the first metal 291
- any suitable conductive material that exhibits high atomic diffusion resistance i.e., that exhibits low atomic diffusivity
- PVD physical vapor deposition
- CVD chemical vapor deposition
- Such a diffusion barrier layer 295 can be relatively thin and can be, for example, a chromium layer, a ruthenium layer, a tantalum layer, a tantalum nitride layer, an indium oxide layer, a tungsten layer, a tungsten nitride layer, a titanium layer, a titanium nitride layer, or any other suitable conductive barrier material as described above.
- FIG. 14B is a cross-section diagram of the resulting IC structure shown in FIG. 14A and shows an exemplary position of the first contact 230 to the gate electrode 250 relative to the second contacts 220 to the contact plugs 210 above the source/drain regions.
- the Figures are not intended to be limiting and the position of the first contact 230 may vary (e.g., the first contact 230 may not be aligned with either of the second contacts 220 ). Additionally, those skilled in the art will recognize that in a different FET configuration, for example, in a FET configuration wherein a discrete, essentially, rectangular gate structure traverses the channel region of the FET, the first contact to the gate structure may be positioned at one end of the gate structure, offset from the second contacts to the contact plugs on the source/drain regions.
- the barrier layer 295 will line the second contact holes 282 and the trenches. Additionally, the barrier layer 295 will be immediately adjacent to the top surface of the first metal 291 in the first contact hole 281 and will line exposed surfaces of first contact hole 281 (if any) and exposed surfaces of the trench above. That is, if the top surface of the first metal 291 is level with the bottom surface of a trench above the first contact hole 281 , the barrier layer 295 will be immediately adjacent to the top surface of the first metal 291 and will line the exposed sidewalls and bottom surface of the trench above the first contact hole 281 (see FIG. 15A ).
- the second metal 292 deposited at process 134 can be copper.
- a copper seed layer (not shown) can be deposited onto the barrier layer 295 (e.g., by physical vapor deposition (PVD) or other suitable technique). Then, additional copper can further be deposited using an electroplating process.
- the second metal 292 can be any suitable metal material for metal level wire formation. In any case, the process of depositing the second metal 292 can continue until the trenches 280 are filled.
- all conductive material can be removed from the top surface of the dielectric layer 260 (e.g., using a chemical mechanical polishing (CMP) process), thereby completing formation of the metal wires 270 in the trenches, formation of at least one first contact 230 (i.e., at least one CB contact), which extends to the gate electrode 250 , in the at least one first contact hole and formation of second contacts 220 (i.e., CA contacts), which extend to the contact plugs 210 on the source/drain regions, in the second contact holes.
- CMP chemical mechanical polishing
- a hybrid metallization interconnect is an interconnect (i.e., a contact, a wire, or a combined contact/wire structure) that contains different metals including at least the first metal 291 and the second metal 292 .
- the first contact 230 may be a hybrid metallization interconnect (e.g., as shown in FIG. 15B ) or the combined first contact 220 /wire 270 structure may be a hybrid metallization interconnect (e.g., as shown in FIG. 15A ). It should be understood that the location of the hybrid metallization will depend upon when deposition of the first metal 291 is stopped at process 128 and the depth of the trenches etched at process 130 .
- FIGS. 8A-8B illustrate an exemplary IC structure 200 A that can be formed according to a method disclosed herein and FIGS. 9A-9C further illustrate various alternative fill configurations for the contacts 220 , 230 and metal wires 270 within that IC structure 200 A.
- FIGS. 14A-14B illustrate another exemplary IC structure 200 B that can be formed according to a method disclosed herein and FIGS. 15A-15B further illustrate various alternative fill configurations for the contacts 220 , 230 and metal wires 270 within that IC structure 200 B.
- Each of the IC structures 200 A and 200 B can incorporate a field effect transistor (FET) on a semiconductor wafer.
- FET field effect transistor
- the FET can have source/drain regions 206 , a channel region 207 between the source/drain regions 206 , a gate (including a gate dielectric layer and a gate electrode 250 ) on the channel region 207 , and gate sidewall spacers 240 on opposing sidewalls of the gate.
- the FET configuration shown in FIGS. 2A-2C includes two adjacent FETs with a shared source/drain region and a multi-finger gate structure (with a gate dielectric layer and a gate electrode 250 on the gate dielectric layer).
- the multi-finger gate structure includes two essentially parallel first portions (i.e., two fingers) that traverse the channel regions 207 of the two FETs, respectively (see FIG. 2B ) and a second portion that is above a trench isolation region 205 and essentially perpendicular to and in contact with ends of the first portions (see FIG. 2C ).
- this FET configuration is provided for illustration purposes only and is not intended to be limiting.
- any other suitable FET configuration could be incorporated into the disclosed IC structures and contacted with the novel hybrid metallization interconnects, discussed in greater detail below.
- the FET configuration could be a simple FET configuration, wherein a discrete, essentially, rectangular gate structure traverses the channel region of the FET.
- the IC structures 200 A of FIGS. 8A-8B and 200B of FIGS. 14A-14B can further have contact plugs 210 on the source/drain regions 206 of the FET. These contact plugs 210 can be electrically isolated from the gate electrode 250 by the gate sidewall spacers 240 and can be, for example, self-aligned metal plugs, such as cobalt or tungsten plugs.
- the IC structures 200 A of FIGS. 8A-8B and 200B of FIGS. 14A-14B can further have a dielectric layer 260 over the FET and, particularly, over the gate electrode 250 , gate sidewall spacers 240 and contact plugs 210 .
- the dielectric layer 260 can include one or more layers of interlayer dielectric (ILD) material.
- ILD material can be, for example, silicon oxide or any other suitable ILD material (e.g., borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), fluorinated tetraethyl orthosilicate (FTEOS), etc.).
- BPSG borophosphosilicate glass
- TEOS tetraethyl orthosilicate
- FTEOS fluorinated tetraethyl orthosilicate
- the IC structure 200 A of FIGS. 8A-8B can further include metal wires 270 located in an upper portion of the dielectric layer 260 and contacts 220 , 230 that extend vertically from the metal wires 270 through a lower portion of the dielectric layer 260 .
- the contacts can include at least one first contact 230 (i.e., at least one CB contact) extending vertically to the gate electrode 250 and second contacts 220 (i.e., CA contacts) extending vertically to the contact plugs 210 above the source/drain regions 206 .
- the first contact 230 (i.e., the CB contact) can include an activation material 293 (e.g., palladium) immediately adjacent to the gate electrode 250 and a first metal 291 (e.g., cobalt) immediately adjacent to the activation material 293 .
- the second contacts 220 i.e., the CA contacts
- the metal wires 270 can include a second metal 292 that is different from the first metal 291 .
- the first metal 291 can have a top surface that is approximately co-planar with the bottom surfaces of the metal wires 270 above (e.g., as shown in FIG. 8A and also as illustrated in FIG. 9A ).
- the contacts 220 , 230 are devoid of the second metal 292 and the metal wires 270 are devoid of the first metal 291 .
- the first metal 291 can have a top surface that is some predetermined distance below the bottom surfaces of the metal wires 270 above (e.g., as illustrated in FIG. 9B ).
- the contacts 220 , 230 have the second metal 292 above the first metal 291 and the metal wires 270 are devoid of the first metal 291 .
- the first metal 291 can overfill the contact holes for the contacts 220 , 230 (e.g., as illustrated in FIG. 9C ).
- the contacts 220 , 230 are devoid of the second metal 292 and the metal wires 270 have the first metal 291 and the second metal 292 above the first metal 291 .
- a diffusion barrier layer 295 can be positioned immediately adjacent to the top surface of the first metal 291 and can line exposed surfaces of the contact holes (if any) for the contacts 220 and 230 and exposed surfaces of the trenches for the metal wires 270 .
- the diffusion barrier layer 295 can be any suitable conductive material that exhibits high atomic diffusion resistance (i.e., that exhibits low atomic diffusivity).
- the diffusion barrier layer 295 can be a chromium layer, a ruthenium layer, a tantalum layer, a tantalum nitride layer, an indium oxide layer, a tungsten layer, a tungsten nitride layer, a titanium layer, a titanium nitride layer, or any other suitable conductive barrier material as described above.
- the IC structure 200 B of FIGS. 14A-14B can further include metal wires 270 located in an upper portion of the dielectric layer 260 and contacts 220 , 230 that extend vertically from the metal wires 270 through a lower portion of the dielectric layer 260 .
- the contacts can include at least one first contact 230 (i.e., at least one CB contact) extending vertically to the gate electrode 250 and second contacts 220 (i.e., CA contacts) extending vertically to the contact plugs 210 on the source/drain regions 206 .
- the first contact 230 (i.e., the CB contact) can include an activation material 293 (e.g., palladium) immediately adjacent to the gate electrode 250 and a first metal 291 (e.g., cobalt) immediately adjacent to the activation material 293 .
- the second contacts 220 i.e., the CA contacts
- the metal wires 270 can include a second metal 292 , which is different from the first metal 291 , and can further be devoid of the first metal 291 .
- the first metal 291 within the first contact 230 can have a top surface that is approximately co-planar with the bottom surface of the metal wire 270 above (e.g., as shown in FIG. 14A and also as illustrated in FIG. 15A ). In this case, the first contact 230 is devoid of the second metal 292 . Alternatively, the first metal 291 can have a top surface that is some predetermined distance below the bottom surface of the metal wire 270 above (e.g., as illustrated in FIG. 15B ). In this case, the first contact 230 has the second metal 292 above the first metal 291 .
- a diffusion barrier layer 295 can be positioned immediately adjacent to the top surface of the first metal 291 and can line exposed surfaces of the first contact hole (if any) for the first contact 230 , exposed surfaces of the second contact holes for the second contacts 220 and exposed surfaces of the trenches for the metal wires 270 .
- the diffusion barrier layer 295 can be any suitable conductive material that exhibits high atomic diffusion resistance (i.e., that exhibits low atomic diffusivity).
- the diffusion barrier layer 295 can be a chromium layer, a ruthenium layer, a tantalum layer, a tantalum nitride layer, an indium oxide layer, a tungsten layer, a tungsten nitride layer, a titanium layer, a titanium nitride layer, or any other suitable conductive barrier material as described above.
- the methods as described above are used in the fabrication of integrated circuit chips.
- the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
- the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections).
- the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product.
- the end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
- a dual damascene process can be performed to form trenches in an upper portion of a dielectric layer and contact holes that extend from the trenches through a lower portion of the dielectric layer (e.g., contact holes to a gate electrode of a field effect transistor (FET) and to contact plugs on source/drain regions of the FET).
- a first metal can be deposited into the contact holes by an electroless deposition process and a second metal can then be deposited to fill the trenches.
- a single damascene process can be performed to form a first contact hole through a dielectric layer to a gate electrode of a FET and a first metal can be deposited into the first contact hole using an electroless deposition process.
- a dual damascene process can be performed to form trenches in an upper portion of the dielectric layer, including a trench that traverses the first contact hole, and to form second contact holes through a lower portion of the dielectric layer to contact plugs on source/drain region of the FET.
- a second metal can then be deposited to fill the second contact holes and the trenches. Also disclosed herein are the resulting IC structures.
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Abstract
Description
- This application is a Continuation of U.S. application Ser. No. 15/193,300 filed Jun. 27, 2016, the complete disclosure of which, in its entirety, is herein incorporated by reference.
- The present invention relates to integrated circuits (ICs) and, more specifically, to methods of forming IC structures with hybrid metallization interconnects and the resulting IC structures.
- Each field effect transistor (FET) in an integrated circuit (IC) structure will have multiple contacts including: contact plugs (also referred to herein as TS plugs) immediately adjacent to the top surfaces of the source/drain regions of the FET; source/drain contacts (also referred to herein as CA contacts) extending vertically through interlayer dielectric material from wires in a first metal level (referred to herein as M0) to the contact plugs, and a gate contact (also referred to herein as a CB contact) extending vertically from a wire in the first metal level through the interlayer dielectric material to the gate electrode of the FET. Historically, the contact plugs have been tungsten or cobalt contact plugs, the source/drain contacts and gate contact have been copper contacts and the metal levels have contained copper wires. However, recently, IC structures have been developed that use cobalt for the source/drain and gate contacts instead of copper. One advantage of using cobalt for these contacts is the avoidance of copper diffusion at the interface between the gate contact and gate electrode and, thus, the avoidance of performance variations (e.g., changes in threshold voltage) that can result from copper diffusion. Disadvantages of using cobalt for the source/drain and gate contacts include both an increase in contact resistance due to the fact that the resistivity of cobalt is higher than copper (e.g., 5.6×10 −8 as compared to 1.7×10−8) and an increase in contact-to-wire interface resistance and/or voids due to overlay misalignment that tends to occur given the currently used fabrication techniques.
- In view of the foregoing, disclosed are methods of forming integrated circuit (IC) structures that incorporate hybrid metallization interconnect(s). In one method, a dual damascene process can be performed to form trenches for metal wires in an upper portion of a dielectric layer and contact holes that extend from the trenches through a lower portion of the dielectric layer (e.g., contact holes for a first contact to a gate electrode of a field effect transistor (FET) and for second contacts to contact plugs on source/drain regions of the FET). A first metal can be deposited into the contact holes by an electroless deposition process and a second metal can then be deposited to fill the trenches. In another method, a single damascene process can be performed to form a first contact hole for a first contact through a dielectric layer to a gate electrode of a FET and a first metal can be deposited into the first contact hole using an electroless deposition process. After deposition of the first metal, a dual damascene process can be performed to form trenches for metal wires in an upper portion of the dielectric layer, including a trench that traverses the first contact hole, and to form second contact holes for second contacts through a lower portion of the dielectric layer to contact plugs on source/drain region of the FET. A second metal can then be deposited to fill the second contact holes and the trenches. Also disclosed herein are the resulting IC structures.
- More particularly, in one method of forming an integrated circuit (IC) structure that incorporates hybrid metallization interconnect(s), a field effect transistor (FET) can be formed on a semiconductor wafer. Specifically, the FET can be formed so as to have source/drain regions, a channel region between the source/drain regions and a gate electrode on the channel region. Contact plugs can be formed on either side of the gate electrode above the source/drain regions. Then, a dielectric layer can be formed over the FET and, particularly, over the gate electrode and contact plugs. Subsequently, a dual damascene process can be performed in order to form trenches for metal wires in an upper portion of the dielectric layer and contact holes for contacts extending vertically from the trenches through a lower portion of the dielectric layer. The contact holes can include, for example, a first contact hole for a first contact extending vertically to the gate electrode and second contact holes for second contacts extending vertically to the contact plugs. After the trenches and contact holes are formed, a first metal can be deposited into the contact holes using an electroless deposition process and, then, a second metal, which is different from the first metal, can be deposited to fill the trenches.
- In another method of forming an integrated circuit (IC) structure that incorporates hybrid metallization interconnect(s), a field effect transistor (FET) can similarly be formed on a semiconductor wafer such that it has source/drain regions, a channel region between the source/drain regions and a gate electrode on the channel region. Contact plugs can be formed on either side of the gate electrode above the source/drain regions. Then, a dielectric layer can be formed over the FET and, particularly, over the gate electrode and contact plugs. Subsequently, a single damascene process can be performed to form at least a first contact hole for a first contact extending vertically through the dielectric layer to the gate electrode and a first metal can be deposited into the first contact hole using an electroless deposition process. Next, a dual damascene process can be performed in order to form trenches for metal wires in an upper portion of the dielectric layer, including a trench that traverses the first contact hole, as well as second contact holes for second contacts extending vertically from the trenches through a lower portion of the dielectric layer to the contact plugs. A second metal, which is different from the first metal, can then be deposited to fill the second contact holes and the trenches.
- Also disclosed are integrated circuit (IC) structures that incorporate hybrid metallization interconnect(s) and that are formed according to the above-described methods. Specifically, the IC structures can have a field effect transistor (FET) on a semiconductor wafer. This FET can have source/drain regions, a channel region between the source/drain regions and a gate electrode on the channel region. The IC structure can further have contact plugs on the source/drain regions of the FET and a dielectric layer over the FET and, particularly, over the gate electrode and the contact plugs. The IC structures can further have metal wires located in an upper portion of the dielectric layer and contacts that extend vertically from the metal wires through a lower portion of the dielectric layer. The contacts can include a first contact extending vertically to the gate electrode and second contacts extending vertically to the contact plugs. The first contact can have an activation material immediately adjacent to the gate electrode and a first metal immediately adjacent to the activation material. In one of the IC structures, the second contacts can similarly have activation material immediately adjacent to the contact plugs and the first metal immediately adjacent to the activation material. In another of the IC structures, the second contacts can be devoid of the first metal and instead can be made of a second metal, which is different from the first metal. In either case, the wires can be made of the second metal.
- The present invention will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which:
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FIG. 1 is a flow diagram illustrating disclosed methods of forming an integrated circuit (IC) structure that incorporates hybrid metallization interconnect(s); -
FIG. 2A is a cross-section diagram illustrating an exemplary partially completed IC structure, which is formed according to the methods ofFIG. 1 and which has two adjacent FETs with a shared source/drain region and a multi-finger gate structure; -
FIG. 2B is another cross-section diagram of the partially completed IC structure shown inFIG. 2A ; -
FIG. 2C is yet another cross-section diagram illustrating the partially completed IC structure shown inFIG. 2A ; -
FIG. 3 is a cross-section diagram illustrating a partially completed IC structure formed according to the methods ofFIG. 1 ; -
FIG. 4 is a cross-section diagram illustrating a partially completed IC structure formed according to the methods ofFIG. 1 ; -
FIG. 5 is a cross-section diagram illustrating a partially completed IC structure formed according to method embodiment A ofFIG. 1 ; -
FIG. 6 is a cross-section diagram illustrating a partially completed IC structure formed according to method embodiment A ofFIG. 1 ; -
FIGS. 7A-7C are cross-section diagrams illustrating alternative fill levels for the first metal deposited atprocess 116 of method embodiment A ofFIG. 1 ; -
FIG. 8A is a cross-section diagram illustrating a completed IC structure formed according to method embodiment A ofFIG. 1 ; -
FIG. 8B is another cross-section diagram of the IC structure shown inFIG. 8A ; -
FIGS. 9A-9C are cross-section diagrams illustrating alternative hybrid interconnect configurations for the IC structure ofFIG. 8A ; -
FIG. 10 is a cross-section diagram illustrating a partially completed IC structure formed according to method embodiment B ofFIG. 1 ; -
FIG. 11 is a cross-section diagram illustrating a partially completed IC structure formed according to method embodiment B ofFIG. 1 ; -
FIG. 12 is a cross-section diagram illustrating a partially completed IC structure formed according to method embodiment B ofFIG. 1 ; -
FIGS. 13A-13B are cross-section diagrams illustrating alternative fill levels for the first metal deposited atprocess 128 of method embodiment B ofFIG. 1 ; -
FIG. 14A is a cross-section diagram illustrating a completed IC structure formed according to method embodiment B ofFIG. 1 ; -
FIG. 14B is another cross-section diagram of the IC structure shown inFIG. 8A ; -
FIGS. 15A-15B are cross-section diagrams illustrating alternative hybrid interconnect configurations for the IC structure ofFIG. 14A ; and -
FIG. 16 is a cross-section diagram illustrating a prior art IC structure. - As mentioned above, each field effect transistor (FET) in an integrated circuit (IC) structure will have multiple contacts including: contact plugs (also referred to herein as TS plugs) immediately adjacent to the top surfaces of the source/drain regions of the FET; source/drain contacts (also referred to herein as CA contacts) extending vertically through interlayer dielectric material from wires in a first metal level (referred to herein as M0) to the contact plugs, and a gate contact (also referred to herein as a CB contact) extending vertically from a wire in the first metal level through the interlayer dielectric material to the gate electrode of the FET. Historically, the contact plugs have been tungsten or cobalt contact plugs, the source/drain contacts and gate contact have been copper contacts and the metal levels have contained copper wires. However, recently, IC structures have been developed that use cobalt for the source/drain and gate contacts instead of copper. One advantage of using cobalt for these contacts is the avoidance of copper diffusion at the interface between the gate contact and gate electrode and, thus, the avoidance of performance variations (e.g., changes in threshold voltage) that can result from copper diffusion.
- Disadvantages of using cobalt for the source/drain and gate contacts include both an increase in contact resistance due to the fact that the resistivity of cobalt is higher than copper (e.g., 5.6×10−8 as compared to 1.7×10−8) and an increase in contact-to-wire interface resistance and/or voids due to overlay misalignment that tends to occur given the currently used fabrication techniques. More specifically, as illustrated in
FIG. 16 , semiconductor structures having cobalt source/drain contacts 20 andcobalt gate contacts 30 andcopper wires 70 in the first metal level (i.e., the M0 level) are typically fabricated using discrete single damascene processes. That is, a single damascene process is used to form contact holes through alayer 61 of interlayer dielectric material down to contact plug(s) 10 on source/drain regions and gate electrode(s) 50 and to fill those contact holes withcobalt 91, thereby forming source/drain contact(s) 20 and gate contact(s) 30, respectively. Subsequently, anetch stop layer 62 is formed on thelayer 61 of interlayer dielectric material over thecontacts additional layer 63 of interlayer dielectric material is deposited on theetch stop layer 62. Another single damascene process is then used to form trenches through theadditional layer 63 of interlayer dielectric material and theetch stop layer 62 and to fill the trenches withcopper 92, thereby forming wires in a first metal level (M0) above thecontacts - In view of the foregoing, disclosed are methods of forming integrated circuit (IC) structures that incorporate hybrid metallization interconnect(s). In one method, a dual damascene process can be performed to form trenches in an upper portion of a dielectric layer and contact holes that extend from the trenches through a lower portion of the dielectric layer (e.g., contact holes to a gate electrode of a field effect transistor (FET) and to contact plugs on source/drain regions of the FET). A first metal can be deposited into the contact holes by an electroless deposition process and a second metal can then be deposited to fill the trenches. In another method, a single damascene process can be performed to form a first contact hole through a dielectric layer to a gate electrode of a FET and a first metal can be deposited into the first contact hole using an electroless deposition process. After deposition of the first metal, a dual damascene process can be performed to form trenches in an upper portion of the dielectric layer, including a trench that traverses the first contact hole, and to form second contact holes through a lower portion of the dielectric layer to contact plugs on source/drain region of the FET. A second metal can then be deposited to fill the second contact holes and the trenches. Also disclosed herein are the resulting IC structures.
- More particularly, referring to the flow diagram of
FIG. 1 , disclosed herein are methods of forming an integrated circuit (IC) structure that incorporates hybrid metallization interconnect(s). In each of these methods, a field effect transistor (FET) can be formed on a semiconductor wafer (102, seeFIGS. 2A-2C ). Various techniques for forming FETs on a semiconductor wafer are well known in the art and, thus, the details of these techniques have been omitted from the specification in order to allow the reader to focus on the salient aspects of the disclosed methods. Generally, however, techniques for forming a FET involve providing a semiconductor layer. This semiconductor layer can, for example, be thesemiconductor layer 204 of a semiconductor-on-insulator (SOI)wafer 201, which includes a semiconductor substrate 202 (e.g., a silicon substrate or any other suitable semiconductor substrate), an insulator layer 203 (e.g., a silicon dioxide (SiO2) layer or any other suitable insulator layer) on thesemiconductor substrate 202 and the semiconductor layer 204 (e.g., a silicon layer, a silicon germanium layer, a gallium nitride layer or any other suitable semiconductor layer) on theinsulator layer 203. Alternatively, the semiconductor layer can be an upper portion of a bulk semiconductor wafer (e.g., a silicon wafer or any other suitable wafer, such as a hybrid orientation (HOT) wafer), wherein the upper portion is isolated from a lower portion of the wafer, for example, by deep well (not shown). A semiconductor body can be defined in the semiconductor layer (e.g., by forming trench isolation regions 205). Subsequently, a gate structure, which includes a gate dielectric layer and agate electrode 250 on the gate dielectric layer, can be formed above achannel region 207 in the semiconductor body;gate sidewall spacers 240 can be formed on the gate; and source/drain regions 206 and, optionally, other components (e.g., source/drain extension regions, halos, etc.), can be formed within the semiconductor body on opposing sides of thechannel region 207.FIG. 2A illustrates an exemplary partially completed IC structure with two adjacent FETs having a shared source/drain region and a multi-finger gate structure (with a gate dielectric layer andgate electrode 250 on the gate dielectric layer). This multi-finger gate structure includes two essentially parallel first portions (i.e., two fingers) that traverse thechannel regions 207 of the two FETs, respectively (seeFIG. 2B ) and a second portion that is above atrench isolation region 205 and essentially perpendicular to and in contact with ends of the first portions (seeFIG. 2C ). Additional process steps involved in the disclosed method are described in greater detail below and illustrated with respect to the structure shown inFIG. 2C . However, it should be understood that the Figures are not intended to be limiting and that the additional process steps could, alternatively, be performed with respect to any FET, which is formed on a semiconductor wafer, which has source/drain regions, a channel region between the source/drain regions and a gate structure on the channel region, and which requires contacts to the source/drain regions and the gate structure. - Contact plugs 210 can be formed above the source/
drain regions 206 such that they are electrically isolated from thegate electrode 250 by the gate sidewall spacers 240 (104, seeFIG. 3 ). These contact plugs 210 can be, for example, self-aligned metal plugs, such as cobalt or tungsten plugs. Such contact plugs can be formed, for example, using a selective chemical vapor deposition technique or any other suitable deposition technique (e.g., non-selective deposition followed by an etch-back process or a chemical-mechanical polishing (CMP) process. In any case, the contact plugs 210 can be formed so as to have a height that is approximately equal to the height of thegate electrode 250, as shown. - Following formation of the contact plugs 210, a
dielectric layer 260 can be formed over the FET and, particularly, over thegate electrode 250,gate sidewall spacers 240 and contact plugs 210 (106, seeFIG. 4 ). Thedielectric layer 260 can include one or more layers of interlayer dielectric (ILD) material. This ILD material can be, for example, silicon oxide or any other suitable ILD material (e.g., borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), fluorinated tetraethyl orthosilicate (FTEOS), etc.). - In one method embodiment (referred to in the flow diagram of
FIG. 1 as embodiment A), after thedielectric layer 260 is formed over the FET atprocess 106, a dual damascene process can be performed in order to formtrenches 280 for metal wires in an upper portion of thedielectric layer 260 and contact holes for contacts extending vertically from thetrenches 280 through a lower portion of the dielectric layer 260 (112, seeFIG. 5 ). Those skilled in the art will recognize that in dual damascene processing a first photolithography and etch pass is performed followed by a second photolithography and etch pass in order to define the trenches and the contact holes in the dielectric layer, respectively. The dual damascene processing can specifically be performed so that the resulting contact holes include, for example, at least onefirst contact hole 281 for at least one first contact (i.e., at least one CB contact) extending vertically from a trench through the lower portion of thedielectric layer 260 to thegate electrode 250 and second contact holes 282 for second contacts (i.e., CA contacts) extending vertically from trenches through the lower portion of thedielectric layer 260 to the contact plugs 210 on the source/drain regions 206.FIG. 5 shows afirst contact hole 281 and asecond contact hole 282 extending vertically fromdifferent trenches 280 such that the first contact and second contact, once formed as discussed in greater detail below, will be electrically connected to different wires. However, it is anticipated that thefirst contact hole 281 and asecond contact hole 282 could, alternatively, extend from the same trench such that the first contact and second contact, once formed as discussed in greater detail below, will be electrically connected to the same wire (e.g., in the case where the drain voltage controls the gate electrode). - After the
trenches 280 and contact holes 281-282 are formed atprocess 112, a thin film of activation material 293 (e.g., palladium or other suitable activation material) can be deposited on the bottom surface of the contact holes 281-282 (i.e., ongate electrode 250 and contact plugs 210) in order to selectively activate the bottom surfaces of the contact holes 281-282 (i.e., to improve the catalytic activity of the bottom surfaces) (114, seeFIG. 6 ). The thin film ofactivation material 293 can be deposited onto the bottom surfaces of the contact holes 281-282 by, for example, a wet, electroless plating process, which can selectively coat an activation material, such as palladium, on a metal surface. Next, a first metal (e.g., cobalt) can be deposited into the contact holes 281-282 directly on the thin film ofactivation material 293 also by using an electroless deposition process (116, seeFIG. 6 ). - Those skilled in the art will recognize that in an electroless deposition (also referred to as electroless plating or auto-catalytic plating) the partially completed structure is placed in an electroless plating bath. The electroless bath typically includes an aqueous solution of metal ions (e.g., cobalt ions), complexing agents, and reducing agents. The bath may also include stabilizers, various additives, and buffers, as well as rate promoters to speed up or slow down the deposition process. Metal deposition occurs as a result of a redox reaction and no electrical current or power supply, anodes, batteries, or rectifiers are required.
- Deposition of the
first metal 291 can continue atprocess 116 until thefirst metal 291 completely fills portions of the contact holes 281-282 above the activation material and can stop when the level of the top surface of thefirst metal 291 is approximately co-planar with the level of the bottom surface of the trenches 280 (e.g., as shown inFIG. 6 and also as illustrated inFIG. 7A ). Alternatively, deposition of thefirst metal 291 can continue atprocess 116 until thefirst metal 291 partially fills the portions of the contact holes 281-282 above the activation material and can stop when the level of the top surface of thefirst metal 291 is some predetermined distance below the level of the bottom surface of the trenches 280 (e.g., as illustrated inFIG. 7B ). Alternatively, deposition of thefirst metal 291 can continue atprocess 116 until thefirst metal 291 completely fills the portions of the contact holes 281-282 above the activation material and partially fills the trenches 280 (i.e., overfills the contact holes) and can stop when the level of the top surface of thefirst metal 291 is some predetermined distance above the level of the bottom surface of the trenches 280 (e.g., as illustrated inFIG. 7C ). - Following deposition of the
first metal 291, adiffusion barrier layer 295 can, optionally, be conformally deposited and asecond metal 292, which is different from thefirst metal 291, can be deposited on the diffusion barrier layer 295 (118-120, seeFIG. 8A ). Specifically, any suitable conductive material that exhibits high atomic diffusion resistance (i.e., that exhibits low atomic diffusivity) can be conformally deposited, using conventional deposition techniques (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable technique). Such adiffusion barrier layer 295 can be relatively thin and can be, for example, a chromium layer, a ruthenium layer, a tantalum layer, a tantalum nitride layer, an indium oxide layer, a tungsten layer, a tungsten nitride layer, a titanium layer, a titanium nitride layer, or any other suitable conductive barrier material as described above.FIG. 8B is a cross-section diagram of the resulting IC structure shown inFIG. 8A and shows an exemplary position of thefirst contact 230 to the gate structure relative to thesecond contacts 220 to the contact plugs 210 above the source/drain regions. Those skilled in the art will recognize that the Figures are not intended to be limiting and the position of thefirst contact 230 may vary (e.g., thefirst contact 230 may not be aligned with either of the second contacts 220). Additionally, those skilled in the art will recognize that in a different FET configuration, for example, in a FET configuration wherein a discrete, essentially, rectangular gate structure traverses the channel region of the FET, the first contact to the gate structure may be positioned at one end of the gate structure, offset from the second contacts to the contact plugs on the source/drain regions. - Additionally, as illustrated
FIGS. 9A-9C , thebarrier layer 295 will be immediately adjacent to the top surface of thefirst metal 291 and will line exposed surfaces of the contact holes (if any) and exposed surfaces of thetrenches 280. That is, if the top surface of thefirst metal 291 is level with the bottom surface of a trench, thebarrier layer 295 will be immediately adjacent to the top surface of thefirst metal 291 and will line the exposed sidewalls and bottom surface of the trench (seeFIG. 9A ). If the top surface of thefirst metal 291 is below the level of the bottom surface of a trench, thebarrier layer 295 will be immediately adjacent to the top surface of thefirst metal 291, will line the exposed sidewalls of the upper portion of the contact hole and will further line the exposed sidewalls and bottom surface of the trench (seeFIG. 9B ). If the top surface of thefirst metal 291 is above the level of the bottom surface of a trench, thebarrier layer 295 will be immediately adjacent to the top surface of thefirst metal 291 and will line the exposed sidewalls of the upper portion of the trench (seeFIG. 9C ). Thesecond metal 292 deposited atprocess 120 can be copper. For example, a copper seed layer (not shown) can be deposited onto the barrier layer 295 (e.g., by physical vapor deposition (PVD) or other suitable technique). Then, additional copper can further be deposited using an electroplating process. Alternatively, thesecond metal 292 can be any suitable metal material for metal level wire formation. In any case, the process of depositing thesecond metal 292 can continue until thetrenches 280 are filled. - Following deposition of the second metal at
process 120, all conductive material can be removed from the top surface of the dielectric layer 260 (e.g., using a chemical mechanical polishing (CMP) process) (122), thereby completing formation of thewires 270 in the trenches, formation of the at least one first contact 230 (i.e., the at least one CB contact), which extends to thegate electrode 250, in the at least one first contact hole and formation of the second contacts 220 (i.e., the CA contacts), which extend to the contact plugs 210 on the source/drain regions, in the second contact holes. Thus, the resultingIC structure 200A shown inFIGS. 8A-8B has hybrid metallization interconnects. For purposes of this disclosure, a hybrid metallization interconnect is an interconnect (i.e., a contact, a wire, or a combined contact/wire structure) that contains different metals including at least thefirst metal 291 and thesecond metal 292. In theIC structure 200A, contacts 220-230 may be hybrid metallization interconnects (e.g., as shown inFIG. 9B ); thewires 270 may be hybrid metallization interconnects (e.g., as shown inFIG. 9C ); or the combinedcontact wire 270 structures may be hybrid metallization interconnects (e.g., as shown inFIG. 9A ). It should be understood that the location of the hybrid metallization will depend upon when deposition of thefirst metal 291 is stopped atprocess 116. - In another method embodiment (referred to in the flow diagram of
FIG. 1 as embodiment B), after thedielectric layer 260 is formed over the FET atprocess 106, a single damascene process can be performed to form at least onefirst contact hole 281 for at least one first contact (i.e., at least one CB contact) extending vertically through thedielectric layer 260 from the top surface to the gate electrode 250 (124, seeFIG. 10 ). Those skilled in the art will recognize that in single damascene processing a single photolithography and etch pass is performed. - After the
first contact hole 281 is formed atprocess 124, a thin film of activation material 293 (e.g., palladium or other suitable activation material) can be deposited on the bottom surface of the first contact hole 281 (i.e., on the gate electrode 250) in order to selectively activate the bottom surface of the first contact hole 281 (i.e., to improve the catalytic activity of the bottom surfaces) (126, seeFIG. 11 ). The thin film ofactivation material 293 can be deposited onto the bottom surface of thefirst contact hole 281 by, for example, a wet, electroless plating process, which can selectively coat an activation material, such as palladium, on a metal surface. Next, a first metal 291 (e.g., cobalt) can be deposited into thefirst contact hole 281 directly on the thin film ofactivation material 293 also by using an electroless deposition process (128, seeFIG. 11 ). See detailed discussion above regarding electroless deposition of cobalt atprocess step 116 of method embodiment A. - Deposition of the
first metal 291 can continue atprocess 128 until thefirst metal 291 completely fills the portion of thefirst contact hole 281 above theactivation material 293. Alternatively, deposition of thefirst metal 291 can continue atprocess 128 until thefirst metal 291 partially fills the portion of thefirst contact hole 281 above theactivation material 293 and can stop some predetermined distance below the level of the top surface of the dielectric layer 260 (as illustrated inFIG. 11 ). - Next, a dual damascene process can be performed in order to form both
trenches 280 for metal wires in an upper portion of thedielectric layer 260, including a trench that traverses the first contact hole 281 (i.e., that encompasses or etches through the upper portion of the first contact hole 281), and second contact holes 282 for second contacts (i.e., for CA contacts) extending vertically from thetrenches 280 through a lower portion of thedielectric layer 260 to the contact plugs 210 on the source/drain regions 206 (130, seeFIG. 12 ). Those skilled in the art will recognize that in dual damascene processing a first photolithography and etch pass is performed followed by a second photolithography and etch pass in order to define trenches and contact holes in the dielectric layer, respectively.FIG. 12 shows thefirst contact hole 281 being traversed by one trench and thesecond contact hole 282 extending vertically from a different trench such that the first contact and second contact, once formed as discussed in greater detail below, will be electrically connected to different wires. However, alternatively, asecond contact hole 282 could extend vertically from the same trench that traverses thefirst contact hole 281 such that the first contact and second contact, once formed as discussed in greater detail below, will be electrically connected to the same wire (e.g., in the case where the drain voltage controls the gate electrode). It also should be noted that, depending upon the fill level for thefirst metal 291 in thefirst contact hole 281 and the depth of thetrenches 280, afterprocess 130 is completed, the top surface of thefirst metal 291 in thefirst contact hole 281 may be essentially co-planar with the bottom surface of the trench that traverses it (e.g., as shown inFIGS. 12 and 13A ) or some distance below that bottom surface (e.g., as shown inFIG. 13B ). - Next, a
diffusion barrier layer 295 can, optionally, be conformally deposited and asecond metal 292, which is different from thefirst metal 291, can be deposited on the diffusion barrier layer 295 (132-134, seeFIG. 14A ). Specifically, any suitable conductive material that exhibits high atomic diffusion resistance (i.e., that exhibits low atomic diffusivity) can be conformally deposited, using conventional deposition techniques (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable technique). Such adiffusion barrier layer 295 can be relatively thin and can be, for example, a chromium layer, a ruthenium layer, a tantalum layer, a tantalum nitride layer, an indium oxide layer, a tungsten layer, a tungsten nitride layer, a titanium layer, a titanium nitride layer, or any other suitable conductive barrier material as described above.FIG. 14B is a cross-section diagram of the resulting IC structure shown inFIG. 14A and shows an exemplary position of thefirst contact 230 to thegate electrode 250 relative to thesecond contacts 220 to the contact plugs 210 above the source/drain regions. Those skilled in the art will recognize that the Figures are not intended to be limiting and the position of thefirst contact 230 may vary (e.g., thefirst contact 230 may not be aligned with either of the second contacts 220). Additionally, those skilled in the art will recognize that in a different FET configuration, for example, in a FET configuration wherein a discrete, essentially, rectangular gate structure traverses the channel region of the FET, the first contact to the gate structure may be positioned at one end of the gate structure, offset from the second contacts to the contact plugs on the source/drain regions. - Additionally, as illustrated in
FIG. 14A , thebarrier layer 295 will line the second contact holes 282 and the trenches. Additionally, thebarrier layer 295 will be immediately adjacent to the top surface of thefirst metal 291 in thefirst contact hole 281 and will line exposed surfaces of first contact hole 281 (if any) and exposed surfaces of the trench above. That is, if the top surface of thefirst metal 291 is level with the bottom surface of a trench above thefirst contact hole 281, thebarrier layer 295 will be immediately adjacent to the top surface of thefirst metal 291 and will line the exposed sidewalls and bottom surface of the trench above the first contact hole 281 (seeFIG. 15A ). If the top surface of thefirst metal 291 in thefirst contact hole 281 is below the level of the bottom surface of the trench above, thebarrier layer 295 will be immediately adjacent to the top surface of thefirst metal 291, will line the exposed sidewalls of the upper portion of the first contact hole and will further line the exposed sidewalls and bottom surface of the trench above (seeFIG. 15B ). Thesecond metal 292 deposited atprocess 134 can be copper. For example, a copper seed layer (not shown) can be deposited onto the barrier layer 295 (e.g., by physical vapor deposition (PVD) or other suitable technique). Then, additional copper can further be deposited using an electroplating process. Alternatively, thesecond metal 292 can be any suitable metal material for metal level wire formation. In any case, the process of depositing thesecond metal 292 can continue until thetrenches 280 are filled. - Following deposition of the
second metal 292 atprocess 136, all conductive material can be removed from the top surface of the dielectric layer 260 (e.g., using a chemical mechanical polishing (CMP) process), thereby completing formation of themetal wires 270 in the trenches, formation of at least one first contact 230 (i.e., at least one CB contact), which extends to thegate electrode 250, in the at least one first contact hole and formation of second contacts 220 (i.e., CA contacts), which extend to the contact plugs 210 on the source/drain regions, in the second contact holes. Thus, the resultingIC structure 200B shown inFIGS. 14A-14B has a hybrid metallization interconnect. As mentioned above, a hybrid metallization interconnect is an interconnect (i.e., a contact, a wire, or a combined contact/wire structure) that contains different metals including at least thefirst metal 291 and thesecond metal 292. In theIC structure 200B, thefirst contact 230 may be a hybrid metallization interconnect (e.g., as shown inFIG. 15B ) or the combinedfirst contact 220/wire 270 structure may be a hybrid metallization interconnect (e.g., as shown inFIG. 15A ). It should be understood that the location of the hybrid metallization will depend upon when deposition of thefirst metal 291 is stopped atprocess 128 and the depth of the trenches etched atprocess 130. - Also disclosed are integrated circuit (IC) structures that incorporate hybrid metallization interconnect(s) and that are formed according to the above-described methods. For example,
FIGS. 8A-8B illustrate anexemplary IC structure 200A that can be formed according to a method disclosed herein andFIGS. 9A-9C further illustrate various alternative fill configurations for thecontacts metal wires 270 within thatIC structure 200A. Similarly,FIGS. 14A-14B illustrate anotherexemplary IC structure 200B that can be formed according to a method disclosed herein andFIGS. 15A-15B further illustrate various alternative fill configurations for thecontacts metal wires 270 within thatIC structure 200B. - Each of the
IC structures FIGS. 2A-2C , the FET can have source/drain regions 206, achannel region 207 between the source/drain regions 206, a gate (including a gate dielectric layer and a gate electrode 250) on thechannel region 207, andgate sidewall spacers 240 on opposing sidewalls of the gate. The FET configuration shown inFIGS. 2A-2C includes two adjacent FETs with a shared source/drain region and a multi-finger gate structure (with a gate dielectric layer and agate electrode 250 on the gate dielectric layer). The multi-finger gate structure includes two essentially parallel first portions (i.e., two fingers) that traverse thechannel regions 207 of the two FETs, respectively (seeFIG. 2B ) and a second portion that is above atrench isolation region 205 and essentially perpendicular to and in contact with ends of the first portions (seeFIG. 2C ). It should be understood that this FET configuration is provided for illustration purposes only and is not intended to be limiting. Thus, any other suitable FET configuration could be incorporated into the disclosed IC structures and contacted with the novel hybrid metallization interconnects, discussed in greater detail below. For example, the FET configuration could be a simple FET configuration, wherein a discrete, essentially, rectangular gate structure traverses the channel region of the FET. In any case, theIC structures 200A ofFIGS. 8A-8B and 200B ofFIGS. 14A-14B can further have contact plugs 210 on the source/drain regions 206 of the FET. These contact plugs 210 can be electrically isolated from thegate electrode 250 by thegate sidewall spacers 240 and can be, for example, self-aligned metal plugs, such as cobalt or tungsten plugs. TheIC structures 200A ofFIGS. 8A-8B and 200B ofFIGS. 14A-14B can further have adielectric layer 260 over the FET and, particularly, over thegate electrode 250,gate sidewall spacers 240 and contact plugs 210. Thedielectric layer 260 can include one or more layers of interlayer dielectric (ILD) material. This ILD material can be, for example, silicon oxide or any other suitable ILD material (e.g., borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), fluorinated tetraethyl orthosilicate (FTEOS), etc.). - The
IC structure 200A ofFIGS. 8A-8B can further includemetal wires 270 located in an upper portion of thedielectric layer 260 andcontacts metal wires 270 through a lower portion of thedielectric layer 260. The contacts can include at least one first contact 230 (i.e., at least one CB contact) extending vertically to thegate electrode 250 and second contacts 220 (i.e., CA contacts) extending vertically to the contact plugs 210 above the source/drain regions 206. The first contact 230 (i.e., the CB contact) can include an activation material 293 (e.g., palladium) immediately adjacent to thegate electrode 250 and a first metal 291 (e.g., cobalt) immediately adjacent to theactivation material 293. Similarly, the second contacts 220 (i.e., the CA contacts) can include theactivation material 293 immediately adjacent to the contact plugs 210 and thefirst metal 291 immediately adjacent to theactivation material 293. Themetal wires 270 can include asecond metal 292 that is different from thefirst metal 291. - In each of the
contacts structure 200A, thefirst metal 291 can have a top surface that is approximately co-planar with the bottom surfaces of themetal wires 270 above (e.g., as shown inFIG. 8A and also as illustrated inFIG. 9A ). In this case, thecontacts second metal 292 and themetal wires 270 are devoid of thefirst metal 291. Alternatively, thefirst metal 291 can have a top surface that is some predetermined distance below the bottom surfaces of themetal wires 270 above (e.g., as illustrated inFIG. 9B ). In this case, thecontacts second metal 292 above thefirst metal 291 and themetal wires 270 are devoid of thefirst metal 291. Alternatively, thefirst metal 291 can overfill the contact holes for thecontacts 220, 230 (e.g., as illustrated inFIG. 9C ). In this case, thecontacts second metal 292 and themetal wires 270 have thefirst metal 291 and thesecond metal 292 above thefirst metal 291. - Optionally, a
diffusion barrier layer 295 can be positioned immediately adjacent to the top surface of thefirst metal 291 and can line exposed surfaces of the contact holes (if any) for thecontacts metal wires 270. Thediffusion barrier layer 295 can be any suitable conductive material that exhibits high atomic diffusion resistance (i.e., that exhibits low atomic diffusivity). For example, thediffusion barrier layer 295 can be a chromium layer, a ruthenium layer, a tantalum layer, a tantalum nitride layer, an indium oxide layer, a tungsten layer, a tungsten nitride layer, a titanium layer, a titanium nitride layer, or any other suitable conductive barrier material as described above. - The
IC structure 200B ofFIGS. 14A-14B can further includemetal wires 270 located in an upper portion of thedielectric layer 260 andcontacts metal wires 270 through a lower portion of thedielectric layer 260. The contacts can include at least one first contact 230 (i.e., at least one CB contact) extending vertically to thegate electrode 250 and second contacts 220 (i.e., CA contacts) extending vertically to the contact plugs 210 on the source/drain regions 206. The first contact 230 (i.e., the CB contact) can include an activation material 293 (e.g., palladium) immediately adjacent to thegate electrode 250 and a first metal 291 (e.g., cobalt) immediately adjacent to theactivation material 293. The second contacts 220 (i.e., the CA contacts) and themetal wires 270 can include asecond metal 292, which is different from thefirst metal 291, and can further be devoid of thefirst metal 291. - In the
structure 200B, thefirst metal 291 within thefirst contact 230 can have a top surface that is approximately co-planar with the bottom surface of themetal wire 270 above (e.g., as shown inFIG. 14A and also as illustrated inFIG. 15A ). In this case, thefirst contact 230 is devoid of thesecond metal 292. Alternatively, thefirst metal 291 can have a top surface that is some predetermined distance below the bottom surface of themetal wire 270 above (e.g., as illustrated inFIG. 15B ). In this case, thefirst contact 230 has thesecond metal 292 above thefirst metal 291. - Optionally, a
diffusion barrier layer 295 can be positioned immediately adjacent to the top surface of thefirst metal 291 and can line exposed surfaces of the first contact hole (if any) for thefirst contact 230, exposed surfaces of the second contact holes for thesecond contacts 220 and exposed surfaces of the trenches for themetal wires 270. Thediffusion barrier layer 295 can be any suitable conductive material that exhibits high atomic diffusion resistance (i.e., that exhibits low atomic diffusivity). For example, thediffusion barrier layer 295 can be a chromium layer, a ruthenium layer, a tantalum layer, a tantalum nitride layer, an indium oxide layer, a tungsten layer, a tungsten nitride layer, a titanium layer, a titanium nitride layer, or any other suitable conductive barrier material as described above. - The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
- It should be understood that the terminology used herein is for the purpose of describing the disclosed methods and structures and is not intended to be limiting. For example, as used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Additionally, as used herein, the terms “comprises” “comprising”, “includes” and/or “including” specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Furthermore, as used herein, terms such as “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, “upper”, “lower”, “under”, “below”, “underlying”, “over”, “overlying”, “parallel”, “perpendicular”, etc., are intended to describe relative locations as they are oriented and illustrated in the drawings (unless otherwise indicated) and terms such as “touching”, “on”, “in direct contact”, “abutting”, “directly adjacent to”, etc., are intended to indicate that at least one element physically contacts another element (without other elements separating the described elements). The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.
- The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
- Disclosed above are methods of forming integrated circuit (IC) structures that incorporate hybrid metallization interconnects. In one method, a dual damascene process can be performed to form trenches in an upper portion of a dielectric layer and contact holes that extend from the trenches through a lower portion of the dielectric layer (e.g., contact holes to a gate electrode of a field effect transistor (FET) and to contact plugs on source/drain regions of the FET). A first metal can be deposited into the contact holes by an electroless deposition process and a second metal can then be deposited to fill the trenches. In another method, a single damascene process can be performed to form a first contact hole through a dielectric layer to a gate electrode of a FET and a first metal can be deposited into the first contact hole using an electroless deposition process. After deposition of the first metal, a dual damascene process can be performed to form trenches in an upper portion of the dielectric layer, including a trench that traverses the first contact hole, and to form second contact holes through a lower portion of the dielectric layer to contact plugs on source/drain region of the FET. A second metal can then be deposited to fill the second contact holes and the trenches. Also disclosed herein are the resulting IC structures.
Claims (20)
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US15/701,480 US20170373000A1 (en) | 2016-06-27 | 2017-09-12 | Interconnects having hybrid metallization |
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US15/193,300 US9824970B1 (en) | 2016-06-27 | 2016-06-27 | Methods that use at least a dual damascene process and, optionally, a single damascene process to form interconnects with hybrid metallization and the resulting structures |
US15/701,480 US20170373000A1 (en) | 2016-06-27 | 2017-09-12 | Interconnects having hybrid metallization |
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US15/193,300 Continuation US9824970B1 (en) | 2016-06-27 | 2016-06-27 | Methods that use at least a dual damascene process and, optionally, a single damascene process to form interconnects with hybrid metallization and the resulting structures |
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US15/701,480 Abandoned US20170373000A1 (en) | 2016-06-27 | 2017-09-12 | Interconnects having hybrid metallization |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10290639B2 (en) * | 2017-09-12 | 2019-05-14 | Globalfoundries Inc. | VNW SRAM with trinity cross-couple PD/PU contact and method for producing the same |
CN112970110A (en) * | 2018-11-07 | 2021-06-15 | 华为技术有限公司 | Integrated circuit and standard cell thereof |
EP4210094A1 (en) * | 2022-01-07 | 2023-07-12 | Samsung Electronics Co., Ltd. | Semiconductor device and method for manufacturing the same |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9824970B1 (en) * | 2016-06-27 | 2017-11-21 | Globalfoundries Inc. | Methods that use at least a dual damascene process and, optionally, a single damascene process to form interconnects with hybrid metallization and the resulting structures |
US9793206B1 (en) * | 2016-09-29 | 2017-10-17 | International Business Machines Corporation | Heterogeneous metallization using solid diffusion removal of metal interconnects |
US10553481B2 (en) * | 2017-08-31 | 2020-02-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Vias for cobalt-based interconnects and methods of fabrication thereof |
US10340183B1 (en) * | 2018-01-02 | 2019-07-02 | Globalfoundries Inc. | Cobalt plated via integration scheme |
US10923393B2 (en) * | 2018-09-24 | 2021-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contacts and interconnect structures in field-effect transistors |
US11101171B2 (en) | 2019-08-16 | 2021-08-24 | Micron Technology, Inc. | Apparatus comprising structures including contact vias and conductive lines, related methods, and memory devices |
WO2022198674A1 (en) * | 2021-03-26 | 2022-09-29 | 华为技术有限公司 | Chip, electronic device, and forming method for film perforation |
Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6028362A (en) * | 1997-05-12 | 2000-02-22 | Yamaha Corporation | Damascene wiring with flat surface |
US6245670B1 (en) * | 1999-02-19 | 2001-06-12 | Advanced Micro Devices, Inc. | Method for filling a dual damascene opening having high aspect ratio to minimize electromigration failure |
US20050029010A1 (en) * | 2003-08-04 | 2005-02-10 | Jeong-Hoon Ahn | Void-free metal interconnection steucture and method of forming the same |
US20050136573A1 (en) * | 2003-09-17 | 2005-06-23 | Chartered Semiconductor Manufacturing Ltd. | Method of making direct contact on gate by using dielectric stop layer |
US7074709B2 (en) * | 2002-06-28 | 2006-07-11 | Texas Instruments Incorporated | Localized doping and/or alloying of metallization for increased interconnect performance |
US20070235392A1 (en) * | 2006-04-04 | 2007-10-11 | Edwards David P | Method and apparatus for recycling process fluids |
US20110156270A1 (en) * | 2009-12-31 | 2011-06-30 | Robert Seidel | Contact elements of semiconductor devices formed on the basis of a partially applied activation layer |
US20110272765A1 (en) * | 2010-05-08 | 2011-11-10 | International Business Machines Corporation | Mosfet gate and source/drain contact metallization |
US20120273851A1 (en) * | 2011-04-29 | 2012-11-01 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor device and manufacturing method thereof |
US20130252419A1 (en) * | 2011-11-07 | 2013-09-26 | International Business Machines Corporation | Metal Alloy Cap Integration |
US20140183738A1 (en) * | 2012-12-28 | 2014-07-03 | Christopher J. Jezewski | Cobalt based interconnects and methods of fabrication thereof |
US20140210041A1 (en) * | 2013-01-31 | 2014-07-31 | International Business Machines Corporation | Electronic fuse having an insulation layer |
US20160189966A1 (en) * | 2008-09-07 | 2016-06-30 | Lam Research Corporation | Pre-fill wafer cleaning formulation |
US20160276267A1 (en) * | 2015-03-18 | 2016-09-22 | Jong-Jin Lee | Methods of forming wiring structures in a semiconductor device |
US9824970B1 (en) * | 2016-06-27 | 2017-11-21 | Globalfoundries Inc. | Methods that use at least a dual damascene process and, optionally, a single damascene process to form interconnects with hybrid metallization and the resulting structures |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6087706A (en) | 1998-04-07 | 2000-07-11 | Advanced Micro Devices, Inc. | Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls |
US6534866B1 (en) * | 2000-04-13 | 2003-03-18 | Micron Technology, Inc. | Dual damascene interconnect |
US6821879B2 (en) | 2002-10-30 | 2004-11-23 | Xerox Corporation | Copper interconnect by immersion/electroless plating in dual damascene process |
KR100641502B1 (en) * | 2002-12-30 | 2006-10-31 | 동부일렉트로닉스 주식회사 | Method for forming a contact using dual damascene process in semiconductor fabrication |
US6794288B1 (en) | 2003-05-05 | 2004-09-21 | Blue29 Corporation | Method for electroless deposition of phosphorus-containing metal films onto copper with palladium-free activation |
KR100621630B1 (en) * | 2004-08-25 | 2006-09-19 | 삼성전자주식회사 | Damascene processs using metals of two kinds |
DE102006001253B4 (en) * | 2005-12-30 | 2013-02-07 | Advanced Micro Devices, Inc. | A method of forming a metal layer over a patterned dielectric by wet-chemical deposition with an electroless and a power controlled phase |
DE102007004884A1 (en) * | 2007-01-31 | 2008-08-14 | Advanced Micro Devices, Inc., Sunnyvale | A method of forming a metal layer over a patterned dielectric by electroless deposition using a selectively provided activation layer |
US8952547B2 (en) * | 2007-07-09 | 2015-02-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with contact structure with first/second contacts formed in first/second dielectric layers and method of forming same |
US20090045515A1 (en) * | 2007-08-16 | 2009-02-19 | Texas Instruments Incorporated | Monitoring the magnetic properties of a metal layer during the manufacture of semiconductor devices |
US8765600B2 (en) * | 2010-10-28 | 2014-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure for reducing gate resistance and method of making the same |
WO2013095377A1 (en) | 2011-12-20 | 2013-06-27 | Intel Corporation | Self-aligned contact metallization for reduced contact resistance |
US20130193489A1 (en) | 2012-01-30 | 2013-08-01 | Globalfoundries Inc. | Integrated circuits including copper local interconnects and methods for the manufacture thereof |
JP2013165224A (en) * | 2012-02-13 | 2013-08-22 | Fujitsu Semiconductor Ltd | Semiconductor device and method of manufacturing the same |
KR102057067B1 (en) * | 2013-01-29 | 2019-12-18 | 삼성전자주식회사 | Metal interconnect structure of a semiconductor device and method for forming the same |
US8907410B2 (en) * | 2013-04-25 | 2014-12-09 | International Business Machines Corporation | TSV structure with a built-in U-shaped FET transistor for improved characterization |
US9514986B2 (en) * | 2013-08-28 | 2016-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device with capped through-substrate via structure |
US9236437B2 (en) | 2014-02-20 | 2016-01-12 | Globalfoundries Inc. | Method for creating self-aligned transistor contacts |
KR102264160B1 (en) * | 2014-12-03 | 2021-06-11 | 삼성전자주식회사 | Method of Fabricating Semiconductor Devices Having Via Structures and Interconnection Structures |
-
2016
- 2016-06-27 US US15/193,300 patent/US9824970B1/en active Active
-
2017
- 2017-02-10 TW TW106104431A patent/TWI631661B/en not_active IP Right Cessation
- 2017-04-27 CN CN201710286177.6A patent/CN107546172A/en active Pending
- 2017-09-12 US US15/701,480 patent/US20170373000A1/en not_active Abandoned
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6028362A (en) * | 1997-05-12 | 2000-02-22 | Yamaha Corporation | Damascene wiring with flat surface |
US6245670B1 (en) * | 1999-02-19 | 2001-06-12 | Advanced Micro Devices, Inc. | Method for filling a dual damascene opening having high aspect ratio to minimize electromigration failure |
US7074709B2 (en) * | 2002-06-28 | 2006-07-11 | Texas Instruments Incorporated | Localized doping and/or alloying of metallization for increased interconnect performance |
US20050029010A1 (en) * | 2003-08-04 | 2005-02-10 | Jeong-Hoon Ahn | Void-free metal interconnection steucture and method of forming the same |
US20050136573A1 (en) * | 2003-09-17 | 2005-06-23 | Chartered Semiconductor Manufacturing Ltd. | Method of making direct contact on gate by using dielectric stop layer |
US20070235392A1 (en) * | 2006-04-04 | 2007-10-11 | Edwards David P | Method and apparatus for recycling process fluids |
US20160189966A1 (en) * | 2008-09-07 | 2016-06-30 | Lam Research Corporation | Pre-fill wafer cleaning formulation |
US20110156270A1 (en) * | 2009-12-31 | 2011-06-30 | Robert Seidel | Contact elements of semiconductor devices formed on the basis of a partially applied activation layer |
US20110272765A1 (en) * | 2010-05-08 | 2011-11-10 | International Business Machines Corporation | Mosfet gate and source/drain contact metallization |
US20120273851A1 (en) * | 2011-04-29 | 2012-11-01 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor device and manufacturing method thereof |
US20130252419A1 (en) * | 2011-11-07 | 2013-09-26 | International Business Machines Corporation | Metal Alloy Cap Integration |
US20140183738A1 (en) * | 2012-12-28 | 2014-07-03 | Christopher J. Jezewski | Cobalt based interconnects and methods of fabrication thereof |
US20140210041A1 (en) * | 2013-01-31 | 2014-07-31 | International Business Machines Corporation | Electronic fuse having an insulation layer |
US20160276267A1 (en) * | 2015-03-18 | 2016-09-22 | Jong-Jin Lee | Methods of forming wiring structures in a semiconductor device |
US9824970B1 (en) * | 2016-06-27 | 2017-11-21 | Globalfoundries Inc. | Methods that use at least a dual damascene process and, optionally, a single damascene process to form interconnects with hybrid metallization and the resulting structures |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10290639B2 (en) * | 2017-09-12 | 2019-05-14 | Globalfoundries Inc. | VNW SRAM with trinity cross-couple PD/PU contact and method for producing the same |
CN112970110A (en) * | 2018-11-07 | 2021-06-15 | 华为技术有限公司 | Integrated circuit and standard cell thereof |
EP4210094A1 (en) * | 2022-01-07 | 2023-07-12 | Samsung Electronics Co., Ltd. | Semiconductor device and method for manufacturing the same |
Also Published As
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CN107546172A (en) | 2018-01-05 |
TW201801242A (en) | 2018-01-01 |
US9824970B1 (en) | 2017-11-21 |
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