CN112970110A - Integrated circuit and standard cell thereof - Google Patents

Integrated circuit and standard cell thereof Download PDF

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Publication number
CN112970110A
CN112970110A CN201880099162.1A CN201880099162A CN112970110A CN 112970110 A CN112970110 A CN 112970110A CN 201880099162 A CN201880099162 A CN 201880099162A CN 112970110 A CN112970110 A CN 112970110A
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gate
integrated circuit
isolation
diffusion layer
standard cell
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CN112970110B (en
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斯蒂芬·巴德尔
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Abstract

The present invention relates to integrated circuits, and more particularly, to a CMOS integrated circuit. The integrated circuit includes at least one diffusion layer. The diffusion layer may in particular be a continuous diffusion layer. The invention accordingly provides an integrated circuit comprising: at least one power rail; the at least one diffusion layer; at least one isolation gate disposed on the diffusion layer and electrically isolating a first region of the diffusion layer from a second region of the diffusion layer; and at least one gate via vertically connecting the isolation gate to the power rail.

Description

Integrated circuit and standard cell thereof
Technical Field
The present invention relates to the field of integrated circuits, in particular CMOS integrated circuits comprising a plurality of transistors and/or a plurality of standard cells. These integrated circuits include one or more diffusion layers. The invention relates in particular to the construction of transistors, for example in such diffusion layers, in particular in continuous diffusion layers without interruptions. The invention therefore proposes an integrated circuit comprising an isolation gate for providing electrical isolation between different regions of at least one such diffusion layer. The isolation gates may provide electrical isolation between different transistors and/or between different standard cells of the integrated circuit.
Background
In CMOS integrated circuits, variations in the manufacturing process cause variations in the parameters of the transistors, which is one of the main causes of power, performance, and yield degradation. These changes tend to increase as the technology scales up.
One of the main sources of these variations is the interruption of diffusion in the diffusion layer, which is usually necessary to electrically isolate the different transistors of the integrated circuit from each other. Diffusion discontinuities can cause transistor parameter variations because:
● are relieved by intentional stress applied to the channel by source/drain epitaxy or stress liners, etc. As a result, the final stress depends on the size of the diffusion layer and the location of each transistor in the diffusion layer.
● the diffusion break is typically filled with oxide. Thus, the material mismatch causes additional stress, which also varies depending on the location of the transistor, e.g., whether the transistor is close to or far from the diffusion break.
If the diffusion break is eliminated, i.e. a continuous diffusion layer is formed, the source of parameter variations can be eliminated. In this case, however, another way must be provided to achieve electrical isolation between the different transistors of the integrated circuit formed in the diffusion layer. For example, a transistor may be formed when the diffusion break is eliminated, and the transistor may be forced into an off state to achieve the desired electrical isolation.
Accordingly, conventional integrated circuit structures have been proposed having an isolation gate connected to power/ground to force the isolation gate into an open state. However, in these conventional integrated circuits, the electrical isolation by means of the isolation gate is achieved at the expense of an increase in the area of the entire integrated circuit (in particular of each standard cell), or at the expense of placement constraints, which ultimately also leads to an increase in area.
Fig. 9 shows a standard cell of a conventional integrated circuit with a diffusion break. The integrated circuit includes:
● two horizontal power rails, one on the top of the standard cell and the other on the bottom of the standard cell.
● regularly spaced vertical active grids.
● are provided in the top and bottom portions of the standard cell, respectively.
● vertical local interconnects that act as contacts to a portion of the diffusion layer that acts as a source/drain.
● a via layer between the gate, local interconnect and metal layer.
A transistor is defined at the intersection of the active gate and the diffusion layer. The diffusion layer is interrupted (diffusion breaks) at the left and right edges of the cell to electrically isolate it from any other standard cells that may be placed nearby. In addition, the diffusion layer may be interrupted in the standard cell region when electrically needed.
However, if modified to make the diffusion layer continuous, i.e. to eliminate diffusion discontinuities, the same standard cell is shown in fig. 10. The modification extends all diffusion layers in the left-right direction, thereby forming a continuous diffusion layer. Instead of the diffusion break of fig. 9, an isolation gate is inserted into the standard cell. These isolation gates are not physically distinct from conventional active gates, but their function is to provide electrical isolation between two diffusion layer regions adjacent to their left and right sides. To provide electrical isolation, the isolation gate of fig. 10 must be connected to the highest or lowest potential, depending on the type of diffusion layer (P or N, respectively). This can be achieved by connecting the isolation gate to one power supply rail (in practice one rail called "power supply" is at the highest potential and one rail called "ground" is at the lowest potential, e.g. ground).
To make this connection, two conventional schemes are shown in fig. 11 and 12, respectively. In each scheme, the isolation gate is connected to the power rail by a local interconnect. However, this requires an increase in cell area, which is disadvantageous.
In particular, a first scheme is shown in fig. 11. As shown in particular in (a) and (B), the solution introduces a second local interconnect to connect the isolation gate to the adjacent first local interconnect (on either side (B), or on both sides (a)). However, this scheme is only applicable when at least one adjacent local interconnect, which is typically used for interconnection of the source (S), is connected to the power rail. If this is not the case, as shown in (C), two local interconnects for the drain (D) are adjacent to the isolation gate and are not connected to the power rail, then an additional local interconnect (here (S)) and gate need to be inserted, as shown in (D). This results in an increase in the area of the integrated circuit, which needs to be avoided.
A second scheme is shown in fig. 12. The scheme introduces a second local interconnect to connect the isolation gate to an adjacent power rail. However, since the first and second local interconnects are not electrically isolated from each other, a certain minimum spacing is required between the second local interconnect connecting the isolation gate to the power rail and any adjacent first local interconnect at a different potential.
Furthermore, a minimum overlap of the second local interconnect with the isolation gate and the power rail, respectively, is required. These requirements also typically require an increase in the area of the integrated circuit.
Disclosure of Invention
In view of the above-described problems and disadvantages, the present invention is directed to improvements in conventional integrated circuits and conventional schemes to eliminate diffusion discontinuities. It is therefore an object to provide a new solution to electrically isolate regions of a diffusion layer from each other without using diffusion breaks and without increasing the cell or circuit area. The solution should also be applied in a flexible way, i.e. there should be no case where the solution does not work. The goal of the scheme should be to reduce or eliminate sensitivity to process variations that can affect performance or yield. In particular, the performance of the integrated circuit according to the inventive solution should not be worse, preferably better, than the performance of conventional integrated circuits. Finally, no placement constraints should be introduced.
Said object is achieved by embodiments according to the invention as provided in the appended independent claims. Advantageous embodiments of the invention are also defined in the dependent claims.
In particular, the invention proposes to obtain a diffusion layer with less or even no diffusion discontinuities by modifying the integrated circuit, in particular its standard cells. An isolation gate is used instead of a diffusion break. The isolation gate is connected to an adjacent power rail ("power" or "ground"). This is achieved by processing the gate via through which the power rail is directly connected to the isolation gate. In particular, the processing of the gate vias ensures minimum spacing from adjacent local interconnects, thereby improving the reliability of the integrated circuit.
A first aspect of the invention provides an integrated circuit comprising: the semiconductor device includes at least one power rail, at least one diffusion layer, at least one isolation gate disposed on the diffusion layer and electrically isolating a first region of the diffusion layer from a second region of the diffusion layer, and at least one gate via vertically connecting the isolation gate to the power rail.
The power rail may be at the highest potential ("power") or the lowest potential ("ground"), depending on the type of diffusion layer (P or N). In particular, the diffusion layer may be a continuous diffusion layer extending from one edge of the integrated circuit to an opposite edge, or from one edge of a standard cell of the integrated circuit to an opposite edge thereof. The gate via may connect the layer of the integrated circuit on which the power rail is formed with the layer on which the isolation gate is formed, in particular at the intersection of the isolation gate and the power rail when the integrated circuit is viewed from the top.
The isolation gates provide electrical isolation, for example, between the transistors or between cells of the integrated circuit, instead of diffusion breaks. Accordingly, the above-described disadvantage of the diffusion interruption can be eliminated or suppressed. The gate via makes unnecessary an additional interconnect (see fig. 9 or 10) as provided in conventional schemes and allows the isolation gate and power rail to be connected without increasing the integrated circuit or cell area.
In one implementation form of the first aspect, the gate via connects a bottom side of the power rail directly to a top of the isolation gate.
In this way, the isolation gate can be connected to the power supply rail in a simple manner without increasing the area.
In another implementation form of the first aspect, a width of the gate via is smaller than a width of the isolation gate and is disposed within the width of the isolation gate.
In this way, shorts between the isolation gate and local interconnects adjacent to the isolation gate, for example, through misaligned gate vias, may be avoided.
In another implementation form of the first aspect, the integrated circuit further comprises at least one local interconnect vertically connecting the diffusion layers, wherein the gate via is electrically isolated from the local interconnect.
Such local interconnects, for example, are connected to the diffusion layer regions as sources or drains of transistors.
In another implementation form of the first aspect, the shape of the gate vias provides a minimum determined pitch for the local interconnects regardless of the location of the gate vias on top of the isolation gates.
Therefore, a short circuit between the isolation gate and the local interconnection can be avoided by carefully designing the shape of the gate via.
In a further embodiment of the first aspect, the isolation gate is covered with a dielectric, and/or the local interconnect is covered with a dielectric, and/or the isolation gate is covered with a dielectric different from the local interconnect.
The dielectric can avoid shorts between the isolation gate and the local interconnect caused by the gate via and/or vias connecting the local interconnect to the power rail.
In another implementation form of the first aspect, a top of the local interconnect is disposed at a lower level of the integrated circuit than the top of the isolation gate, or the top of the local interconnect is disposed at a higher level of the integrated circuit than the top of the isolation gate.
In this way, even if the gate via is misaligned on the isolation gate, a short circuit between the isolation gate and the local interconnect may be avoided.
In another implementation form of the first aspect, the gate via includes a step defining a narrower lower portion and a wider upper portion, the narrower lower portion being connected to the top of the isolation gate and the wider upper portion being connected to the bottom side of the power rail, the bottom side of the wider upper portion being disposed at a higher level of the integrated circuit than the top of the local interconnect.
In this way, a minimum spacing between the gate via and the local interconnect is provided and shorts between the isolation gate and the local interconnect may be avoided.
In a further implementation form of the first aspect, the isolation gate extends perpendicular to the power rail, and the gate via is arranged in an intersection region of the isolation gate and the power rail in a top view of the integrated circuit.
In another implementation of the first aspect, the integrated circuit includes a plurality of standard cells, wherein at least one standard cell includes at least one power rail, at least one diffusion layer, at least one isolation gate, and at least one gate via vertically connecting the isolation gate to the power rail.
In another embodiment of the first aspect, at least one isolation gate is disposed and configured to electrically isolate a first region of the diffusion layer in a standard cell from a second region of the diffusion layer in an adjacent standard cell.
In another implementation of the first aspect, at least one isolation gate is disposed and configured to electrically isolate a first region of the diffusion layer associated with a transistor in a standard cell from a second region of the diffusion layer associated with an adjacent transistor in the same standard cell.
In another implementation of the first aspect, an integrated circuit includes: in at least one standard cell, at least two power rails extending from a first edge to a second opposite edge of the standard cell, at least two diffusion layers extending from the first edge towards the second edge of the standard cell, wherein one diffusion layer is disposed proximate to one of the power rails and another diffusion layer is disposed proximate to another of the power rails, and a plurality of isolation gates, wherein one or more of the isolation gates of a first set of isolation gates are connected to one of the power rails by gate vias and one or more of the isolation gates of a second set of isolation gates are connected to another of the power rails by gate vias.
In another embodiment of the first aspect, in at least one standard cell, two of the isolation gates are arranged and configured to electrically isolate a first region of a diffusion layer in the standard cell from a second region of the diffusion layer in a first adjacent standard cell adjacent to the first edge and from a third region of the diffusion layer in a second adjacent standard cell adjacent to the second edge.
In another implementation of the first aspect, the integrated circuit includes at least one active gate defining a transistor, and at least two local interconnects defining a source and a drain of the transistor, respectively.
The device of the first aspect may be fabricated by using a self-aligned gate via contact process. The gate via provides a connection directly from the power rail to the isolation gate without adding an additional second local interconnect, and, thanks to its particular shape and/or other measures described above, the resulting gate via is electrically isolated from any adjacent local interconnect (e.g., for a source or drain diffusion region). Thus, the following benefits can be obtained using the integrated circuit:
● may provide a continuous diffusion layer or at least reduce a certain number of diffusion discontinuities to improve circuit performance by enhancing channel stress.
● the continuous diffusion layer can eliminate any variation or sensitivity (e.g., layout-dependent effects (LDEs)) traditionally caused by diffusion discontinuities.
● may reduce or at least not increase the area of the standard cell and not introduce placement constraints (e.g., forbidden drain-drain bridge).
It has to be noted that all devices, elements, units and means described in the present application may be implemented as software or hardware elements or any kind of combination thereof. All steps performed by the various entities described in the present application and the functions described to be performed by the various entities are intended to indicate that the respective entities are adapted or arranged to perform the respective steps and functions. Although in the following description of specific embodiments specific functions or steps performed by an external entity are not reflected in the description of specific elements of the entity performing the specific steps or functions, it should be clear to a skilled person that these methods and functions may be implemented in respective hardware or software elements or any combination thereof.
Drawings
The aspects of the invention described above and the embodiments thereof will be elucidated by the following description of specific embodiments in conjunction with the accompanying drawings, in which:
FIG. 1 illustrates an integrated circuit according to an embodiment of the invention;
FIG. 2 illustrates an integrated circuit according to an embodiment of the invention;
FIG. 3 illustrates an integrated circuit having a plurality of standard cells according to an embodiment of the present invention;
FIG. 4 illustrates a gate via in an integrated circuit according to an embodiment of the invention;
FIG. 5 illustrates a gate via in an integrated circuit according to an embodiment of the invention;
FIG. 6 illustrates an isolation gate, diffusion layer and local interconnect in an integrated circuit according to an embodiment of the present invention;
FIG. 7 illustrates an isolation gate, diffusion layer and local interconnect in an integrated circuit according to an embodiment of the present invention;
FIG. 8 illustrates an isolation gate, diffusion layer and local interconnect in an integrated circuit according to an embodiment of the present invention;
FIG. 9 illustrates a conventional integrated circuit with a diffusion break;
FIG. 10 illustrates an exemplary integrated circuit without a diffusion break;
FIG. 11 illustrates a first conventional approach to eliminating diffusion discontinuities; and
fig. 12 shows a second conventional scheme of eliminating the diffusion break.
Detailed Description
Fig. 1 illustrates an integrated circuit 100 according to a general embodiment of the invention, wherein the integrated circuit 100 is shown in a top view. The integrated circuit 100 may specifically be a CMOS integrated circuit, wherein a plurality of transistors are defined by a diffusion layer, gates and interconnects with source/drain regions of the diffusion layer, respectively. Further, the integrated circuit 100 may include a plurality of standard cells, wherein each standard cell may have the same design, and the standard cells may be disposed adjacent to each other.
In particular, the integrated circuit 100 shown in fig. 1 comprises at least one power supply rail 101 (hereinafter the power supply rail 101 may be at a highest potential "power" or a lowest potential "ground"), at least one diffusion layer 102, and at least one isolation gate 103 disposed on the diffusion layer 102 and electrically isolating a first region 102a of the diffusion layer 102 from a second region 102b of the diffusion layer 102. To this end, the isolation gate 103 may be brought to an "off state" by connecting it to the power rail 101. Thereby, the diffusion layer 102 under the isolation gate 103 is depleted, thereby separating the first diffusion layer region 102a on one side of the isolation gate 103 from the second diffusion layer region 102b on the other side of the isolation gate 103.
The isolation gate 103 is connected to the power rail 101 through at least one gate via 104 of the integrated circuit, which vertically connects the isolation gate 103 and the power rail 101 (wherein the vertical direction is the direction in which the layers of the integrated circuit 100 are manufactured/arranged; in fig. 1, the vertical direction is the direction into the page).
As exemplarily shown in fig. 1, in particular, the isolation gate 103 may extend perpendicular to the power rail 101. Furthermore, in a top view of the integrated circuit 100, the gate via 104 may be disposed in an intersection region of the isolation gate 103 and the power rail 101.
In particular, the integrated circuit 101 may comprise a plurality of standard cells, whereby each cell may comprise the elements as shown in fig. 1, i.e. at least one diffusion layer 102, at least one isolation gate 103, and at least one gate via 104 vertically connecting the isolation gate 103 and the power rail 101.
Fig. 2 shows an integrated circuit 100 according to an embodiment of the invention in a top view, which is based on the integrated circuit 100 shown in fig. 1. Like elements of fig. 1 and 2 are correspondingly labeled with the same reference characters and serve the same function. In particular, fig. 2 shows in more detail some relevant features of the proposed integrated circuit 100, and these features are exemplarily shown in a (simplified) standard cell 200 of the integrated circuit 100. The standard cell 200 includes:
● extend continuously between the left and right edges of the standard cell 200.
●, each gate 103 overlaps either the left or right edge of the cell, and each gate 103 is connected to one of two power rails 101 (i.e., "power" (P-type) or "ground" (N-type)), specifically, each through one gate via 104.
In particular, the four isolation gates 103 shown in fig. 2 are arranged and configured to electrically isolate the diffusion layer 102 within a standard cell 200 from the same diffusion layer 102 extending into an adjacent standard cell 200. That is, the diffusion layer 102 may be continuous over more than one standard cell 200 of the integrated circuit 100.
Fig. 3 shows an integrated circuit 100 according to an embodiment of the invention in a top view, which is based on the integrated circuit 100 shown in fig. 2. Like elements of fig. 2 and 3 are correspondingly labeled with the same reference characters and serve the same function. In particular, fig. 3 shows a more complex standard cell 200 of an integrated circuit 100 (having a plurality of standard cells 200), wherein the standard cell 200 comprises:
● extend horizontally continuously from one edge of the cell 200 to the opposite edge, i.e., there are no diffusion discontinuities within the cell 200.
● multiple isolation gates 103 are placed where needed, particularly between transistors in cell 200, and at the edge of cell 200, i.e., between cell 200 and an adjacent cell. For example, the isolation gates 103 are respectively connected to the power rails 101 ("power or ground") by placing the gate vias 104 directly under the power rails 101.
Based on the cell 200 shown in fig. 2, diffusion breaks are reduced or eliminated, which helps to minimize LDE and sensitivity to process variations, and in the example, the area required for the cell 200 can be reduced from 7 gate pitches to 5 gate pitches, i.e., a 28% reduction in area is achieved.
Fig. 3 also shows that the integrated circuit 100 may include a local interconnect 300 that is vertically connected to one of the diffusion layers 102. Some local interconnects may be connected to the power rail 101 through vias 301. The gate via 104 is electrically isolated from the local interconnect 300. Furthermore, the integrated circuit 100 may comprise at least one active gate 303 for defining a transistor, wherein a source and/or a drain of the transistor is defined by at least two local interconnects 300 arranged on opposite sides of the active gate 303 on the diffusion layer 102.
A portion of the isolation gates 103 (four isolation gates 103 at the edge of the cell in fig. 3) may be arranged and configured to electrically isolate the first region 102a of the diffusion layer 102 in a cell 200 from the second region 102b of the diffusion layer 102 in an adjacent standard cell 200 or from the third region 102c of the diffusion layer 102 in another adjacent standard cell 200, i.e., to provide electrical isolation between adjacent cells.
Some other isolation gates 103 (two isolation gates 103 shown in the middle of fig. 3) may be arranged and configured to electrically isolate a first diffusion layer region associated with a transistor from a second diffusion layer region associated with an adjacent transistor in the same cell 200.
Fig. 4 shows details of a gate via 104 in an integrated circuit 100, and in particular, the integrated circuit 100 shown in fig. 2, according to an embodiment of the invention. In particular, fig. 4 shows a cross-section along the cutting line shown in fig. 2.
As can be seen in fig. 4, a gate via 104 is formed at/through the power rail 101 and connected to the top of the isolation gate 103. However, the gate via 104 may also be connected directly to the bottom side of the power rail 101 and the top of the isolation gate 103. Further, the power rail 101 and the gate via 104 may be integrally formed.
The particular shape of the gate via 104 may show a step 201. The step 201 defines a narrower lower portion of the gate via 104 and a wider upper portion of the gate via 104. It can be seen that the gate via 104 may be connected to the top of the isolation gate 103 through the narrower lower portion, in particular the bottom thereof. The wider upper portion of the gate via 104 may enter/pass through the power rail 101 and may therefore connect the isolation gate 103 to the power rail 101. The wider upper portion may also be connected to the bottom side of the power rail 101 (as exemplarily shown in fig. 5).
Fig. 5 also shows a gate via 104 in the integrated circuit 100 of an embodiment of the invention. In particular, fig. 5 illustrates how a particular gate via shape can guarantee a certain minimum spacing from an adjacent interconnect 300 (e.g., for drain contact) even in the presence of via misalignment or other edge placement errors. Thus, if there is no pitch, misalignment will result in an unnecessary short between the interconnect 300 and the power rail 101, or at least for reliability considerations, such as time-dependent dielectric breakdown (TDDB) due to the extremely small pitch.
For example, as shown in fig. 5, a bottom side of a wider upper portion of the gate via 104 defined by the step 201 may be disposed at a higher level of the integrated circuit 100 than a top of the local interconnect 300 (in a vertical direction). As such, the shape of the gate vias 104 may provide a minimum determined pitch for the local interconnects 300 regardless of the location of the gate vias 104 on top of the isolation gates 103.
Fig. 6, 7 and 8 illustrate other ways of avoiding shorts in the integrated circuit 100, particularly for shorts between the isolation gate 103 and the local interconnect 300 that may result from the isolation gate 103 being contacted by the gate via 104 and/or the local interconnect 300 being contacted by the via 301.
Fig. 6 shows portions of an integrated circuit 100 in accordance with an embodiment of the present invention in (a) - (D), respectively. In particular, one diffusion layer 102, one isolation gate 103, two local interconnects 300, and one interconnect 300 on each side of the isolation gate 103 are shown. By means of these portions, a transistor can be formed.
The isolation gate 103 may be covered with a dielectric 600. The dielectric 600 can avoid short circuits based on the fabrication process of the integrated circuit 100. In particular, as shown in (C) and (D), when the via hole 301 is constructed, the dielectric 600 may resist the manufacturing process of the via hole 301, for example, the etching step thereof. Therefore, even if the via 301 is misaligned on the local interconnect 300 (shown in (D), while the via 301 is aligned in (C)), it is not connected to the isolation gate 103.
However, when the gate via 104 is constructed, the dielectric 600 is not resistant to the fabrication process of the gate via 104, e.g., its etching step. Fig. 6 also shows that the top of the local interconnect 300 may be disposed at a lower level of the integrated circuit 100 than the top of the isolation gate 103. As such, even if the gate via 104 is misaligned on top of the isolation gate 103 (as shown in (B), while the gate via 104 is aligned in (a)), it is not connected to the local interconnect 300.
Fig. 7 shows portions of an integrated circuit 100 according to an embodiment of the present invention in (a) - (D), respectively. In particular, one diffusion layer 102, one isolation gate 103, two local interconnects 300, and one interconnect 300 on each side of the isolation gate 103 are shown. By means of these portions, a transistor can be formed.
The local interconnect 300 may be covered with a first dielectric 700 and the isolation gate 103 may be covered with a second, different dielectric 701. Optionally, a third dielectric 702 may be disposed between the isolation gate 103 and the local interconnect 300. The second dielectric 701 and the third dielectric 703 may also be a single common dielectric. Dielectrics 700, 701, and 702 can still avoid shorts based on the manufacturing process of integrated circuit 100.
In particular, as shown in (C) and (D), when the via hole 301 is constructed, the dielectric 701 disposed on top of the isolation gate 103 may resist the manufacturing process of the via hole 301, for example, the etching step thereof. Therefore, even if the via 301 is misaligned on the local interconnect 300 (shown in (D), while the via 301 is aligned in (C)), it is not connected to the isolation gate 103. Further, as shown in (a) and (B), when the gate via 104 is constructed, the dielectric 700 disposed on top of the local interconnect 300 may resist the manufacturing process of the gate via 104, for example, the etching step thereof. Therefore, even if the gate via 104 is misaligned in the isolation gate 103 (as shown in (B), while the gate via 104 is aligned in (a)), it is not connected to the interconnect 300. The optional third dielectric 702 may resist the manufacturing process of the via 301 and the gate via 104 to further avoid shorting the isolation gate 103 and the local interconnect 300 if either of the gate via 104 or the via 301 is misaligned.
Fig. 8 shows a portion of an integrated circuit 100 according to an embodiment of the invention. In particular, one diffusion layer 102, one isolation gate 103, two local interconnects 300, and one interconnect 300 on each side of the isolation gate 103 are shown. By means of these portions, a transistor can be formed.
In particular, fig. 8 shows that the width of the gate via 104 may be less than the width of the isolation gate 103. In the integrated circuit 100, the width of the gate via 104 is preferably set within the width of the isolation gate 103. This is a simple way to avoid shorting the isolation gate 103 and the local interconnect 300 even if the gate via 104 is misaligned. The minimum spacing between the isolation gate 103 and the local interconnect 300 may be controlled during relevant manufacturing steps of the integrated circuit 100.
A method of manufacturing an integrated circuit 100 according to an embodiment of the invention may include: forming a diffusion layer 102, e.g. in or on a substrate, forming an isolation gate 103 on the diffusion layer 102, e.g. in a layer above the diffusion layer 102, forming a power rail 101, e.g. in a layer above the isolation gate 103, and finally vertically connecting the power rail 101 and the isolation gate, e.g. through a gate via 104, from layer to layer. The gate via may be formed by etching through the power rail 101 to the underlying isolation gate 103 and filling the trench with a via material, such as a metal.
The invention has been described in connection with various embodiments and implementations as examples. Other variations will be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the independent claims. In the claims and in the description, the term "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims (15)

1. An integrated circuit (100), comprising:
at least one power rail (101);
at least one diffusion layer (102);
at least one isolation gate (103) disposed on the diffusion layer (102) and configured to electrically isolate a first region (102a) of the diffusion layer (102) from a second region (102b) of the diffusion layer (102);
at least one gate via (104) vertically connecting the isolation gate (103) to the power rail (101).
2. The integrated circuit (100) of claim 1,
the gate via (104) connects a bottom side of the power rail (101) directly to a top of the isolation gate (103).
3. The integrated circuit (100) of claim 1 or 2,
the width of the gate via (104) is smaller than the width of the isolation gate (103) and is arranged within the width of the isolation gate (103).
4. The integrated circuit (100) of any of claims 1 to 3, further comprising:
at least one local interconnect (300) vertically connecting the diffusion layers (102),
wherein the gate via (104) is electrically isolated from the local interconnect (300).
5. The integrated circuit (100) of claim 4, wherein the integrated circuit is configured as a semiconductor device
The shape of the gate vias (104) provides a minimum determined pitch for the local interconnects (300) regardless of the location of the gate vias (104) on top of the isolation gate (103).
6. The integrated circuit (100) of claim 4 or 5,
the isolation gate (103) is covered with a dielectric (600, 701), and/or
The local interconnects (300) are covered with a dielectric (700), and/or
The isolation gate (103) and the local interconnect (300) are covered with different dielectrics (600, 701).
7. The integrated circuit (100) of any of claims 4 to 6,
a top of the local interconnect (300) is disposed at a lower level of the integrated circuit (100) than the top of the isolation gate (103), or
The top of the local interconnect (300) is disposed at a higher level of the integrated circuit (100) than the top of the isolation gate (103).
8. The integrated circuit (100) of any of claims 4 to 7,
the gate via (104) includes a step (201) defining a narrower lower portion and a wider upper portion, the narrower lower portion being connected to the top of the isolation gate (103) and the wider upper portion being connected to the bottom side of the power rail (101), an
The bottom side of the wider upper portion is disposed at a higher level of the integrated circuit (100) than the top of the local interconnect (300).
9. The integrated circuit (100) of any of claims 1 to 8,
the isolation gate (103) extends perpendicular to the power rail (101), an
In a top view of the integrated circuit (100), the gate via (104) is disposed in an intersection region of the isolation gate (103) and the power rail (101).
10. The integrated circuit of any of claims 1 to 9, comprising:
a plurality of standard cells (200), wherein
At least one standard cell (200) comprises at least one power rail (101), at least one diffusion layer (102), at least one isolation gate (103), and at least one gate via (104) vertically connecting the isolation gate (103) to the power rail (101).
11. The integrated circuit (100) of claim 10,
at least one isolation gate (103) is arranged and configured to electrically isolate a first region (102a) of the diffusion layer (102) in a standard cell (200) from a second region (102b) of the diffusion layer (102) in an adjacent standard cell (200).
12. The integrated circuit (100) of claim 10 or 11,
at least one isolation gate (103) is arranged and configured to electrically isolate a first region (102a) of the diffusion layer (102) associated with a transistor in a standard cell (200) from a second region (102b) of the diffusion layer (102) associated with an adjacent transistor in the same standard cell (200).
13. The integrated circuit (100) of any of claims 10 to 12, comprising, in at least one standard cell (200),
at least two power rails (101) extending from a first edge to a second opposite edge of the standard cell (200),
at least two diffusion layers (102) extending in a direction from the first edge towards the second edge of the standard cell (200), wherein one diffusion layer (102) is arranged adjacent to one of the power rails (101) and the other diffusion layer (102) is arranged adjacent to the other of the power rails (101), and
a plurality of isolation gates (103), wherein one or more isolation gates (103) of a first set of isolation gates (103) are connected to one of the power rails (101) through gate vias (104), and one or more isolation gates (103) of a second set of isolation gates (103) are connected to another of the power rails (101) through gate vias (104).
14. The integrated circuit (100) of claim 13, wherein, in at least one standard cell (200),
two of the isolation gates (103) are arranged and configured to electrically isolate a first region (102a) of the diffusion layer (102) in the standard cell (200) from a second region (102b) of the diffusion layer (102) in a first adjacent standard cell (200) adjacent to the first edge and from a third region (102c) of the diffusion layer (102) in a second adjacent standard cell (200) adjacent to the second edge.
15. The integrated circuit (100) of any of claims 1 to 14, comprising:
at least one active gate (303) defining a transistor, an
At least two local interconnects (300) defining a source and a drain of the transistor, respectively.
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