US20170330615A1 - Fast sense amplifier with bit-line pre-charging - Google Patents
Fast sense amplifier with bit-line pre-charging Download PDFInfo
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- US20170330615A1 US20170330615A1 US15/416,191 US201715416191A US2017330615A1 US 20170330615 A1 US20170330615 A1 US 20170330615A1 US 201715416191 A US201715416191 A US 201715416191A US 2017330615 A1 US2017330615 A1 US 2017330615A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0026—Bit-line or column circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0061—Timing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0042—Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
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Abstract
A bit-line of a resistive memory cell includes a reference branch including a reference resistor having a predetermined value and a cell branch including an adjustable memory resistor having a variable value. The reference branch generates a reference current based on the predetermined value of the reference resistor and the cell branch generates a cell branch current based on a selected value of the adjustable memory resistor. A sense amplifier has a first input coupled to the reference branch and a second input coupled to the cell branch. A first pre-charge transistor is coupled to a first pre-charge voltage and the cell branch. The first pre-charge transistor is configured to pre-charge the cell branch to the first pre-charge voltage prior to a read operation.
Description
- This application is a continuation of U.S. patent application Ser. No. 15/150,478, filed on May 10, 2016, and entitled “FAST SENSE AMPLIFIER WITH BIT-LINE CHARGING,” the disclosure of which is incorporated herein in its entirety.
- Current emerging memory read operations convert a resistance state stored in a bit-cell into one or more current signals on a cell current branch. A conventional current sense amplifier includes two-stage amplification. The first stage includes two branches, a reference branch and cell branch. The reference branch generates a reference current (Iref) and a reference voltage (Vref) input for a sense amplifier. The cell branch generates a cell current (Icell) and includes an adjustable resistor RRAM. The current difference between the cell current and the reference current generates a voltage signal (Vdi) second input of the sense amplifier. If Vdi is greater than Vref, a logic “1” is read during the read operation. If Vdi is less than Vref, a logic “0” is read during the read operation.
- Because Vdi is pulled down from VDD to a final stabilized level for a logic “1”, the conventional current sense amplifier requires a substantial (>10 nanoseconds) stabilization time to settle the current signal to a reference level. After the current signal is settled, the sense amplifier compares Vdi and Vref to generate a logic output . The stabilization time needed in conventional current sense amplifiers prevents read operations from being performed at high-speeds (such as <10 nanoseconds). Further, conventional current sense amplifiers produce a high spike current during a read operation.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not necessarily drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
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FIG. 1 illustrates an emerging memory cell having a pre-charged bit-line, in accordance with some embodiments. -
FIG. 2 is a chart illustrating the read performance of a conventional current sense bit-line. -
FIG. 3 is a chart illustrating the read performance of the bit-line illustrated inFIG. 1 . -
FIG. 4 illustrates an emerging memory cell having a cascode pre-charged bit-line, in accordance with some embodiments. -
FIG. 5 illustrates emerging memory cell having a complimentary pass-gate as a pre-charger for pre-charging a bit-line, in accordance with some embodiments. -
FIG. 6 is a chart illustrating response times for pre-charged memory cells having different Rout schemes, in accordance with some embodiments. - The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- In various embodiments, a memory cell including a pre-charged bit-line is disclosed. The bit-line includes a first pre-charge transistor and a second pre-charge transistor coupled to a read signal. Prior to performing a read operation, the cell branch bit-line is pre-charged by the first pre-charge transistor to a first pre-charge voltage VBL. The second pre-charge transistor provides a second pre-charge voltage VRBL to the cell branch of the memory cell to pre-charge the cell branch. The voltage at the cell branch input (Vdi) is pulled up or pulled down from the pre-charge voltage based on the resistive state of the cell branch. The sense amplifier generates an output based on the difference between the cell branch voltage Vdi and the reference voltage Vref. In some embodiments, the pre-charge voltage is equal to VCL-Vthn, where VCL is a clamping voltage and Vthn is a threshold voltage of a clamping device.
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FIG. 1 illustrates one embodiment of a resistive memory cell including a pre-charged bit-line 2. The bit-line 2 includes areference branch 6 a and acell branch 6 b. Thereference branch 6 a is configured to generate a reference voltage Vref at afirst input 8 of thesense amplifier 4. Thereference branch 6 a includes adisconnect transistor 10 a, amirror transistor 10 b, acontrol transistor 10 c, and acurrent transistor 10 d. In some embodiments, thedisconnect transistor 10 a includes a source coupled to a voltage supply VDD, a gate coupled to ground, and a drain coupled to the source of themirror transistor 10 b. Themirror transistor 10 b can further include a gate coupled to amirror transistor 16 b of thecell branch 6 b (as described in more detail below) and a drain coupled to the source of acontrol transistor 10 c. Thecontrol transistor 10 c can further include a gate coupled to a control voltage VCL and a drain coupled to acurrent transistor 10 d. Thecurrent transistor 10 d can further include a gate coupled to VDD and a drain coupled to areference resistor Rref 22. When thememory cell 2 is accessed for a read operation, thereference branch 6 a develops a predetermined reference current Iref based on the value of VDD and the resistive value of thememory resistor Rref 22. For example, in some embodiments, VDD is equal to 1.1 volts, although it will be appreciated that other values of VDD may be used. - In some embodiments, the
cell branch 6 b is configured to generate a cell voltage Vdi at asecond input 12 of thesense amplifier 4. The voltage difference between the first input 8 (Vref) and the second input 12 (Vdi) determines theoutput 14 of thesense amplifier 4. For example, in some embodiments, if Vref is less than Vdi, a voltage value corresponding to a logic “1” is output and if Vref is greater than Vdi a voltage value corresponding to a logic “0” is output. In some embodiments, thecell branch 6 b includes adisconnect transistor 16 a, amirror transistor 16 b, acontrol transistor 16 c, and a word-line transistor 16 d. A gate of thedisconnect transistor 16 a is coupled to a read signal line (RD_B) 18, the source is coupled to VDD, and the drain is coupled to a source of amirror transistor 16 b. The gate of themirror transistor 16 b is coupled to the gate of themirror transistor 10 b of thereference branch 6 a to form a current mirror. The drain of themirror transistor 16 b is coupled to thesecond input 12 of the sense amplifier and further coupled to the source of thecontrol transistor 16 c. The gate of thecontrol transistor 16 c is coupled to a control voltage VCL and the drain of thecontrol transistor 16 c is coupled to the source of the word-line transistor 16 d. The gate of the word-line transistor 16 d is coupled to a word-line for addressing thememory cell 2. The drain of the word-line transistor 16 d is coupled to theRRAM resistor 24. The resistive value of theRRAM resistor 24 is adjusted by the memory cell based on the data state (e.g., logic “1” or logic “0”) stored in the memory cell. - In some embodiments, the read signal (RD_B) 18 is also provided to a gate of a first
pre-charge transistor 20 a. The source of the first pre-charge transistor is coupled to a first pre-charge voltage VRBL. The firstpre-charge transistor 20 b pre-charges thecell branch 6 b bit-line to at least a portion of the first pre-charge voltage VRBL when the firstpre-charge transistor 20 b is placed in an active and/or saturation mode by theread signal 18. A read operation pulls thecell branch 6 b voltage up or down based on the resistive value of theRRAM resistor 24. The voltage VRBL pre-charges thecell branch 6 b such that thecell branch 6 b is not pulled up and/or pulled down from a voltage close to zero, but instead is pulled up/pulled down from a voltage equal to VRBL (or some portion thereof). Thus, thepre-charged cell branch 6 b reduces the stabilization time required to stabilize the cell branch voltage (Vdi) at thesecond input 12, reducing read time for the bit-line 2 compared to conventional current sense amplifier memory cells - In some embodiments, the read signal (RD_B) 18 is further provided to a gate of a second
pre-charge transistor 20 b. The source of the secondpre-charge transistor 20 a is coupled to a second pre-charge voltage VBL and the drain is coupled to thesecond input 12 of thesense amplifier 4. When the secondpre-charge transistor 20 a is placed in an active and/or saturation mode, for example when RD_B has a value of logic “0,” thesecond input 14 of thesense amplifier 4 is pre-charged to at least a portion of the second pre-charge voltage VBL. The voltage VBL pre-charges thesecond input 12 such that thecell branch 6 b does not have to pull up and/or pull down the voltage at thesecond input 12 from zero or VDD, but instead pulls up/pulls down the voltage from VBL. The pre-charged second input further reduces the stabilization time required to stabilize the cell branch voltage (Vdi) at thesecond input 12, reducing read time for the bit-line 2 compared to conventional current sense amplifier memory cells. - The
cell branch 6 b is normally disconnected from the voltage source VDD bydisconnect transistor 16 a. When a read operation is performed, the read signal (RD_B) 18 couples thecell branch 6 b to the voltage source VDD by placing thedisconnect transistor 16 a in an active and/or saturation mode. Simultaneously, the read signal RD_B is provided to the gate of the firstpre-charge transistor 20 b, which transitions to an active and/or saturation mode and pre-charges thecell branch 6 b to a predetermined level less than or equal to VBL (such as, for example, VCL-Vthn). - In some embodiments, simultaneously with the pre-charging of the
cell branch 6 b, the read signal (RD_B) 18 is provided to the gate of the firstpre-charge transistor 20 b, which transitions to an active and/or saturation mode andpre-charges cell branch 6 b at a source of the word-line transistor 16 d to a predetermined value less than or equal to VRBL. - Thus, the read signal (RD_B) 18 places the
disconnect transistor 16 a into an active and/or saturation mode, connecting thecell branch 6 b to the voltage source VDD. The gate of thedisconnect transistor 10 a in thereference branch 6 a is coupled to ground and maintained in saturation mode, coupling thereference branch 6 a to the voltage source VDD. A reference current Iref is developed on thereference branch 6 a and is mirrored to thecell branch 6 b by themirror transistors RRAM resistor 24. The voltage Vdi is pulled up or pulled down based on the value of Icell. Because the second input 12 (Vdi) is pre-charged by the firstpre-charge transistor 20 a, the branch voltage is generated by pulling Vdi up from and/or down from the first pre-charge voltage VBL. The difference between the reference voltage Vref and Vdi is detected by thesense amplifier 4 and a logic value is generated at theoutput 14 based on the difference in values. For example, in some embodiments, if Vdi is greater than Vref, thesense amplifier 4 generates a voltage corresponding to a logic “0” and if Vdi is less than Vref, the sense amplifier generates a voltage corresponding to a logic “1”. -
FIG. 2 is achart 50 a illustrating a conventional resistive cell response andFIG. 3 is achart 50 b illustrating response times for the bit-line 2 with pre-charging illustrated inFIG. 1 .FIG. 2 andFIG. 3 each illustrate a plurality of simulated digital signals 52 a-52 i corresponding to digital signals received during operation of a resistive memory cell. For example, the simulated digital signals include a firstread signal RD 52 a (discussed in more detail below with respect toFIGS. 4 and 5 ), a first word-line voltage 52 b, a second word-line voltage 52 c, bit array signals 52 d, 52 e, a redundant bit-line signal BL_RD 52 f, a second read signal RD_B 52 g, aread clock signal 52 h, and aresistor voltage signal 52 i corresponding to a resistive value of theRRAM resistor 24. -
FIG. 2 andFIG. 3 each further illustrate process corner case responses 54 a-54 e for an RRAM memory chip without pre-charging (FIG. 2 ) and with pre-charging (FIG. 3 ), based on the digital input signals 52 a-52 i.FIG. 2 andFIG. 3 illustrate five process corner case responses: a typical-typical corner 54 a, a slow-slow corner (54 b), a fast-fast corner (54 c), a fast-slow corner (54 d), and a slow-fast corner (54 e). Each of the corners 54 a-54 e correspond to one or more process variations during semiconductor fabrication. As shown inFIG. 2 , a response time 56 (e.g., stabilization time during a pull-down and/or pull-up operation) of the non-pre-charged memory cell is at least 16 ns for each of the corner cases 54 a-54 e. In contrast, as shown inFIG. 3 , theresponse time 56 of thepre-charged memory cell 2 illustrated inFIG. 1 is less than 10 ns for each corner case 54 a-54 e. Thus, theshorter response time 56 provides shorter stabilization (less than 10 ns), allowing read operations faster than conventional resistive memory cell, which typically requires at least 16 ns per read for stabilization. -
FIG. 4 illustrates an emerging memory cell having a cascode pre-charged bit-line, in accordance with some embodiments. Thecascode memory cell 2 a includes areference branch 6 a and acell branch 6 b. Thecascode memory cell 2 a is similar to thememory cell 2 described with respect toFIG. 1 and a description of the same or similar components or features is not repeated here. Thecascode memory cell 2 a further includescascode transistors cascode transistors cascode transistor 10 e in thereference branch 6 a is coupled to the drain of amirror transistor 10 b and the source of thecascode transistor 16 e in thecell branch 6 b is coupled to the drain of themirror transistor 16 b. The drain of thecascode transistor 10 e in thereference branch 6 a is coupled to the source of thecontrol transistor 10 c and the drain of thecascode transistor 16 e in thecell branch 6 b is coupled to the source of thecontrol transistor 16 c. The biasing voltage VBIAS is selected to provide a predetermined source-emitter voltage over thecascode transistor cascode transistor control transistors sense amplifier 4. The cascode transistor provides a higher input impedance based on the selection of VBIAS, which increases the output impedance, Rout, of the bit-line 2. - In some embodiments, the cascode bit-
line 2 a includessecond read transistors second read transistor 10 f of thereference branch 6 a has a gate coupled to the voltage source VDD, a source coupled to the drain of thecontrol transistor 10 c, and a drain coupled to the source of thecurrent transistor 10 d. Thesecond read transistor 16 f of thecell branch 6 b includes a gate coupled to a second read signal RD 26, a source coupled to the drain of thecontrol transistor 16 c, and a drain coupled to the source of the word-line transistor 16 d. The second read signal RD 26 can be a redundant read signal, a complimentary read signal, and/or an additional read signal with respect to theread signal RD_B 18 discussed above. For example, in some embodiments, the second read signal RD 26 is a complimentary read signal with respect to the firstread signal RD_B 18. A read operation is performed on the bit-line only when the firstread signal RD_B 18 has a complimentary (e.g., opposite) value of the second read signal 26. -
FIG. 5 illustrates one embodiment of a memory cell bit-line 2 b including complementary pass-gate 30 a as asense amplifier 4 pre-charger. The memory cell bit-line 2 b is similar to the cascode memory cell bit-line 2 b illustrated inFIG. 4 , and descriptions of the same or similar components or features is not repeated here. The memory cell bit-line 2 b replaces at least one of thepre-charging transistors 20 a with a pre-charging pass-gate 30 a. The pass-gate 30 a can comprise any suitable pass-gate, such as, for example, aCMOS pass gate 30 a as illustrated inFIG. 5 . The pass-gate 30 a functions similarly to the secondpre-charge transistor 20 a but provides faster pull-up time for pre-charging Vdi to the pre-charge voltage VBL and a slower pull-down response than the secondpre-charge transistor 20 a. -
FIG. 6 is a chart illustrating response times for pre-charged memory cells having different Rout schemes.FIG. 6 illustrates the same plurality of simulated digital signals 52 a-52 i corresponding to digital signals received during operation of a resistive memory cell as illustrated inFIGS. 2 and 3 , and similar description is not repeated herein.FIG. 6 further illustrates the typical-typical (TT) response times for a pre-chargedresistive memory cell 58 a and a pre-charged cascoderesistive memory cell 58 b. As can be seen inFIG. 6 , however, the cascodememory cell response 58 b provides a lower peak voltage than the pre-charged resistivememory cell response 58 a, corresponding to a higher impedance and higher output resistance generated by thecascode transistor 10 e in the cascode memory cell. - Although specific embodiments have been discussed herein having specific transistor arrangements (e.g., gate-source-drain connections), it will be appreciated by those skilled in the art that the various circuits disclosed and discussed herein can be implemented using a variety of transistors (e.g., PMOS, NMOS, CMOS) each having a variety of arrangements (e.g., gate-source-drain connections), such as, for example, replacing one or more NMOS transistors with one or more PMOS transistors, in any of the illustrated circuits.
- In various embodiments, a bit-line of a resistive memory cell includes a reference branch including a reference resistor having a predetermined value and a cell branch including an adjustable memory resistor having a variable value. The reference branch generates a reference current based on the predetermined value of the reference resistor and the cell branch generates a cell branch current based on a selected value of the adjustable memory resistor. A sense amplifier has a first input coupled to the reference branch and a second input coupled to the cell branch. A first pre-charge transistor is coupled to a first pre-charge voltage and cell branch. The first pre-charge transistor is configured to pre-charge the cell branch to the first pre-charge voltage prior to a read operation.
- In various embodiments, a bit-line of a resistive memory cell includes a reference branch including a reference resistor having a predetermined value and a cell branch including an adjustable memory resistor having a variable value. The reference branch generates a reference current based on the predetermined value of the reference resistor and the cell branch generates a cell branch current based on a selected value of the adjustable memory resistor. A sense amplifier has a first input coupled to the reference branch and a second input coupled to the cell branch. A pre-charge transistor is coupled to a pre-charge voltage and the cell branch. The pre-charge transistor is configured to pre-charge the cell branch to the pre-charge voltage prior to a read operation, where the first-pre charge voltage is equal to VCL-Vthn, where VCL is a clamping voltage of a clamping device of the cell branch and Vthn is a threshold voltage of the clamping device.
- In various embodiments, a bit-line of a resistive memory cell includes a reference branch including a reference resistor having a predetermined value and a cell branch including an adjustable memory resistor having a variable value. The reference branch generates a reference current based on the predetermined value of the reference resistor and the cell branch generates a cell branch current based on a selected value of the adjustable memory resistor. A sense amplifier has a first input coupled to the reference branch and a second input coupled to the cell branch. A first pre-charge transistor is coupled to a first pre-charge voltage and the cell branch. The first pre-charge transistor is configured to pre-charge the cell branch to the first pre-charge voltage prior to a read operation. A second pre-charge transistor is coupled to a second pre-charge voltage and the second input of the sense amplifier. The second pre-charge transistor is configured to pre-charge the second input of the sense amplifier to the second pre-charge voltage prior to a read operation. A gate of each of the first pre-charge transistor and the second pre-charge transistor are coupled to a read signal.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
1. A resistive memory cell bit-line, comprising:
a cell branch including an adjustable memory resistor having a variable value, wherein the cell branch generates a cell branch current based on a selected value of the adjustable memory resistor; and
a first pre-charge transistor configured to pre-charge the cell-branch to a first pre-charge voltage.
2. The resistive memory cell bit-line of claim 1 , comprising a reference branch including a reference resistor having a predetermined value, wherein the reference branch generates a reference current based on the predetermined value of the reference resistor.
3. The resistive memory cell bit-line of claim 1 , wherein the first pre-charge transistor is coupled between a first voltage source and the cell-branch.
4. The resistive memory cell bit-line of claim 3 , wherein the first voltage source has a voltage equal to the first pre-charge voltage.
5. The resistive memory cell bit-line of claim 1 , wherein a gate of the first pre-charge transistor is coupled to a read control signal.
6. The resistive memory cell bit-line of claim 1 , comprising a sense amplifier having a first input coupled to the cell branch.
7. The resistive memory cell bit-line of claim 6 , comprising a second pre-charge transistor coupled to the sense amplifier, wherein the second pre-charge transistor is configured to pre-charge the sense amplifier to a second pre-charge voltage.
8. The resistive memory cell bit-line of claim 1 , wherein the cell branch includes at least one cascode transistor.
9. The resistive memory cell bit-line of claim 8 , wherein the at least one cascode transistor includes at least one transistor having a gate coupled to a biasing voltage.
10. The resistive memory cell bit-line of claim 8 , wherein the at least one cascode transistor in the cell branch includes at least one transistor having a gate coupled to a read bit signal.
11. The resistive memory cell bit-line of claim 1 , wherein the first-pre charge voltage is equal to VCL-Vthn, where VCL is a clamping voltage of a clamping device of the cell branch and Vthn is a threshold voltage of the clamping device.
12. A resistive memory cell bit-line, comprising:
a cell branch including an adjustable memory resistor having a variable value, wherein the cell branch generates a cell branch current based on a selected value of the adjustable memory resistor; and
a pre-charge transistor coupled to a pre-charge voltage and the cell branch, wherein the pre-charge transistor is configured to pre-charge the cell branch to the pre-charge voltage prior to a read operation, wherein the first-pre charge voltage is equal to VCL-Vthn, VCL is a clamping voltage of a clamping device of the cell branch and Vthn is a threshold voltage of the clamping device.
13. The resistive memory cell bit-line of claim 10 , comprising a reference branch including a reference resistor having a predetermined value, wherein the reference branch generates a reference current based on the predetermined value of the reference resistor.
14. The resistive memory cell bit-line of claim 12 , wherein a gate of the pre-charge transistor is coupled to a read control signal.
15. The resistive memory cell bit-line of claim 10 , wherein the cell branch include at least one cascode transistor.
16. A resistive memory cell, comprising:
a cell branch including an adjustable memory resistor having a variable value, wherein the cell branch generates a cell branch current based on a selected value of the adjustable memory resistor;
a sense amplifier having a first input coupled to the cell branch;
a first pre-charge transistor coupled to a first pre-charge voltage and the cell branch, wherein the first pre-charge transistor is configured to pre-charge the cell branch to the first pre-charge voltage prior to a read operation; and
a second pre-charge transistor coupled to the sense amplifier, wherein the second pre-charge transistor is configured to pre-charge an input of the sense amplifier to a second pre-charge voltage prior to a read operation.
17. The resistive memory cell of claim 13 , wherein the cell branch includes at least one cascode transistor.
18. The resistive memory cell of claim 17 , wherein the at least one cascode transistor includes at least one transistor having a gate coupled to a biasing voltage.
19. The resistive memory cell of claim 17 , wherein the at least one cascode transistor in the cell branch includes at least one transistor having a gate coupled to a read bit signal.
20. The resistive memory cell of claim 13 , wherein the cell branch comprises a word-line transistor having a gate coupled to a word-line.
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US10643713B1 (en) | 2019-02-08 | 2020-05-05 | Sandisk Technologies Llc | Toggling power supply for faster bit line settling during sensing |
US10643677B2 (en) | 2018-06-26 | 2020-05-05 | Sandisk Technologies Llc | Negative kick on bit line control transistors for faster bit line settling during sensing |
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US9576653B1 (en) | 2017-02-21 |
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