US20170317071A1 - Fin diode with increased junction area - Google Patents
Fin diode with increased junction area Download PDFInfo
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- US20170317071A1 US20170317071A1 US15/139,644 US201615139644A US2017317071A1 US 20170317071 A1 US20170317071 A1 US 20170317071A1 US 201615139644 A US201615139644 A US 201615139644A US 2017317071 A1 US2017317071 A1 US 2017317071A1
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- 238000000034 method Methods 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 238000002513 implantation Methods 0.000 claims description 12
- 239000002019 doping agent Substances 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 125000006850 spacer group Chemical group 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0814—Diodes only
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Definitions
- the present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to a fin diode with increased junction area and methods for making same.
- FETs field effect transistors
- MOS metal-oxide-semiconductor
- FETs field effect transistors
- MOS metal-oxide-semiconductor
- FETs field effect transistors
- NMOS and PMOS transistors are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state).
- FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as finFET devices.
- a so-called finFET device has a three-dimensional (3D) structure.
- a fin topology also provides the potential of increased density for diode devices.
- the dopant implantation process can damage the tip portions of the fin, resulting in increased defects and reduced junction area.
- the aspect ratio of the fins also makes it difficult to implant dopants on the lower portions of the fin, which also reduces the junction area.
- the present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.
- a method includes forming a first plurality of fins having a first width in a first region of a semiconductor substrate.
- a second plurality of fins having a second width greater than the first width is formed in a second region of a semiconductor substrate.
- a doped region is formed in a surface portion of the second plurality of fins to define an anode region of a diode.
- a junction is defined between the doped region and a cathode region of the second plurality of fins.
- a first contact interfacing with the anode region is formed.
- Another method includes forming a plurality of fins in a semiconductor substrate.
- a doped region is formed in a surface portion of the plurality of fins and in a surface portion of the semiconductor substrate disposed between adjacent fins in the plurality of fins to define an anode region of a diode.
- a junction is defined between the doped region and a cathode region of the plurality of fins.
- a first contact interfacing with the anode region is formed.
- One illustrative semiconductor diode includes, among other things, a plurality of fins defined in a semiconductor substrate.
- a doped region is defined in a surface portion defined in the plurality of fins and in a surface portion of the semiconductor substrate disposed between adjacent fins in the plurality of fins to define an anode region of the diode.
- a junction is defined between the doped region and a cathode region of the plurality of fins.
- a first contact interfaces with the anode region.
- FIGS. 1A-1J depict various methods disclosed herein of forming a fin diode device.
- the present disclosure generally relates to various methods of forming a fin diode device with increased junction area.
- the present method is applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc.
- various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.
- FIGS. 1A-1J illustrate various methods for forming an integrated circuit product 100 on a substrate 105 .
- the product 100 includes a transistor region 110 and a diode region 115 .
- FIGS. 1A-1J show a cross-sectional view perpendicular to a long axis of fins to be formed in the product 100 (i.e., in the gate width direction of transistors in the transistor region 110 ).
- the substrate 105 may have a variety of configurations, such as the depicted bulk silicon configuration.
- the substrate 105 may also have a silicon-on-insulator (SOI) configuration that includes a bulk silicon layer, a buried insulation layer and an active layer, wherein semi-conductor devices are formed in and above the active layer.
- SOI silicon-on-insulator
- the substrate 105 may be formed of silicon or silicon germanium or it may be made of materials other than silicon, such as germanium. Thus, the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconducting materials and all forms of such materials.
- the substrate 105 may have different layers. For example, the substrate 105 may include a process layer formed above a base layer.
- a hard mask layer 120 is formed above the substrate 105 .
- a first mandrel 125 having elements 130 with a first width 130 W is formed above the hard mask layer 120 in the transistor region 110
- a second mandrel 135 having elements 140 with a second width 140 W is formed above the hard mask layer 120 in the diode region 115 .
- the mandrels 125 , 135 may be formed by patterning an amorphous silicon layer.
- a spacer layer 145 is formed above the mandrels 125 , 130 . The portions of the spacer layer 145 on the sidewalls of the elements 140 merge, in at least the region contacting the hard mask layer 120 .
- FIG. 1B illustrates the product 100 after an anisotropic etch process was performed on the spacer layer 145 to define spacers 150 , 155 on the sidewalls of the elements 130 , 140 , respectively. Due to the merging of the spacer layer 145 proximate the elements 140 , the spacers 155 have a width 155 W approximately twice the width 150 W of the spacers 150 .
- FIG. 1C illustrates the product 100 after an etch process was performed to remove the mandrels 125 , 135 .
- FIG. 1D illustrates the product 100 after an etch process was performed to pattern the hard mask layer 120 using the spacers 150 , 155 as an etch mask.
- FIG. 1E illustrates the product 100 after an anisotropic etch process was performed to define fins 160 in the transistor region 110 of the substrate 105 and fins 165 in the diode region 115 of the substrate 105 .
- the fins 165 have a width 165 W that is approximately twice a width 160 W of the fins 160 .
- the fins 165 have a pitch and a width that are approximately double that of the fins 160 .
- Figure 1F illustrates the product 100 after one or more etch processes were performed to remove the remaining portions of the cap layer 120 and the spacers 150 , 155 .
- the subsequent steps illustrate the processing of the diode region 115 . Separate processing may be performed to fabricate devices in the transistor region 110 with appropriate masking steps to separate the process flows for the regions 110 , 115 .
- FIG. 1G illustrates the product 100 after an implantation process was performed to form a doped surface region 170 on the fins 165 .
- the doped surface region 170 has the opposite dopant type as compared to the fins 165 , thereby creating a PN junction 175 at the interface between the doped surface region 170 and the fins 165 .
- the doped surface region 170 may define an anode region of a diode device and the portions of the fins opposite the PN junction 175 define a cathode region of the diode device.
- the implantation process may be a hot implantation process, where the implantation is performed at an elevated temperature (e.g., >150° C.).
- the implant energy may be between about 0.3-2 kV (e.g., 0.6 kV) and the dose may be between about 1E15/cm 2 and 2E16/cm 2 (e.g., 2E15/cm 2 ).
- FIG. 1H illustrates the product 100 after a plurality of processes was performed to define an isolation structure 185 between the fins 165 .
- a deposition process was performed to deposit a dielectric material and an etch process was performed to recess the dielectric material to expose upper portions of the fins 165 .
- These processes may also be performed to define similar isolation structures (not shown) in the transistor region 110 .
- one or more liner layers e.g., silicon nitride, silicon dioxide or a stack thereof
- Any such liners may be removed after the recessing of the dielectric material.
- FIG. 1I illustrates the product 100 after a plurality of processes was performed to form a contact structure 190 (e.g., anode contact) interfacing with the doped surface region 170 .
- the processes may include one or more deposition processes to form one or more conductive layers (e.g., barrier layers, seed layers, fill layers) that will be part of the contact structure 190 (layers not separately shown).
- the conductive material may be planarized.
- FIG. 1J illustrates the product 100 after a plurality of processes was performed to form a contact structure 195 (e.g., cathode contact) interfacing with an undoped region of the fins 165 .
- the processes may include one or more deposition processes to form one or more conductive layers (e.g., barrier layers, seed layers, fill layers) that will be part of the contact structure 195 (layers not separately shown).
- the conductive material may be planarized.
- the processes to form the contact structures 190 , 195 may be integrated with the processes for forming gate electrodes or contacts in the transistor region 110 .
- a gate insulation layer (not shown) (e.g., silicon dioxide, hafnium oxide or a high-k material) may be formed in both regions 110 and 115 , and the gate insulation layer may be selectively removed in the diode region 115 prior to forming the conductive material.
- line type contact structures 190 , 195 are illustrated, in some embodiments, via or plug type contacts may be used.
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Abstract
Description
- The present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to a fin diode with increased junction area and methods for making same.
- In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Diodes are another common device found in many integrated circuits.
- In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as finFET devices.
- To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. A so-called finFET device has a three-dimensional (3D) structure.
- A fin topology also provides the potential of increased density for diode devices. However, as fin sizes decrease, the dopant implantation process can damage the tip portions of the fin, resulting in increased defects and reduced junction area. The aspect ratio of the fins also makes it difficult to implant dopants on the lower portions of the fin, which also reduces the junction area.
- The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.
- The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
- Generally, the present disclosure is directed to various methods of forming semiconductor devices. A method includes forming a first plurality of fins having a first width in a first region of a semiconductor substrate. A second plurality of fins having a second width greater than the first width is formed in a second region of a semiconductor substrate. A doped region is formed in a surface portion of the second plurality of fins to define an anode region of a diode. A junction is defined between the doped region and a cathode region of the second plurality of fins. A first contact interfacing with the anode region is formed.
- Another method includes forming a plurality of fins in a semiconductor substrate. A doped region is formed in a surface portion of the plurality of fins and in a surface portion of the semiconductor substrate disposed between adjacent fins in the plurality of fins to define an anode region of a diode. A junction is defined between the doped region and a cathode region of the plurality of fins. A first contact interfacing with the anode region is formed.
- One illustrative semiconductor diode includes, among other things, a plurality of fins defined in a semiconductor substrate. A doped region is defined in a surface portion defined in the plurality of fins and in a surface portion of the semiconductor substrate disposed between adjacent fins in the plurality of fins to define an anode region of the diode. A junction is defined between the doped region and a cathode region of the plurality of fins. A first contact interfaces with the anode region.
- The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
-
FIGS. 1A-1J depict various methods disclosed herein of forming a fin diode device. - While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
- Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
- The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
- The present disclosure generally relates to various methods of forming a fin diode device with increased junction area. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.
-
FIGS. 1A-1J illustrate various methods for forming anintegrated circuit product 100 on asubstrate 105. Theproduct 100 includes atransistor region 110 and adiode region 115.FIGS. 1A-1J show a cross-sectional view perpendicular to a long axis of fins to be formed in the product 100 (i.e., in the gate width direction of transistors in the transistor region 110). Thesubstrate 105 may have a variety of configurations, such as the depicted bulk silicon configuration. Thesubstrate 105 may also have a silicon-on-insulator (SOI) configuration that includes a bulk silicon layer, a buried insulation layer and an active layer, wherein semi-conductor devices are formed in and above the active layer. Thesubstrate 105 may be formed of silicon or silicon germanium or it may be made of materials other than silicon, such as germanium. Thus, the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconducting materials and all forms of such materials. Thesubstrate 105 may have different layers. For example, thesubstrate 105 may include a process layer formed above a base layer. - As illustrated in
FIG. 1A , ahard mask layer 120 is formed above thesubstrate 105. Afirst mandrel 125 havingelements 130 with afirst width 130W is formed above thehard mask layer 120 in thetransistor region 110, and asecond mandrel 135 havingelements 140 with asecond width 140W is formed above thehard mask layer 120 in thediode region 115. In some embodiments, themandrels spacer layer 145 is formed above themandrels spacer layer 145 on the sidewalls of theelements 140 merge, in at least the region contacting thehard mask layer 120. -
FIG. 1B illustrates theproduct 100 after an anisotropic etch process was performed on thespacer layer 145 to definespacers elements spacer layer 145 proximate theelements 140, thespacers 155 have awidth 155W approximately twice thewidth 150W of thespacers 150. -
FIG. 1C illustrates theproduct 100 after an etch process was performed to remove themandrels -
FIG. 1D illustrates theproduct 100 after an etch process was performed to pattern thehard mask layer 120 using thespacers -
FIG. 1E illustrates theproduct 100 after an anisotropic etch process was performed to definefins 160 in thetransistor region 110 of thesubstrate 105 andfins 165 in thediode region 115 of thesubstrate 105. Thefins 165 have awidth 165 W that is approximately twice awidth 160W of thefins 160. Hence, as compared to thefins 160, thefins 165 have a pitch and a width that are approximately double that of thefins 160. -
Figure 1F illustrates theproduct 100 after one or more etch processes were performed to remove the remaining portions of thecap layer 120 and thespacers diode region 115 is illustrated inFIG. 1F . The subsequent steps illustrate the processing of thediode region 115. Separate processing may be performed to fabricate devices in thetransistor region 110 with appropriate masking steps to separate the process flows for theregions -
FIG. 1G illustrates theproduct 100 after an implantation process was performed to form a dopedsurface region 170 on thefins 165. The dopedsurface region 170 has the opposite dopant type as compared to thefins 165, thereby creating aPN junction 175 at the interface between thedoped surface region 170 and thefins 165. The dopedsurface region 170 may define an anode region of a diode device and the portions of the fins opposite thePN junction 175 define a cathode region of the diode device. Providing thefins 165 with increased width and pitch allows the implantation process to reach the lower portions of thefins 165 and thesurface portions 180 of thesubstrate 105, thereby providing that thePN junction 175 spansmultiple fins 165. In addition, the increased width reduces the likelihood that the portions of the dopedsurface region 170 intip regions 165T of thefins 165 will merge, thereby reducing the junction area. In some embodiments, the implantation process may be a hot implantation process, where the implantation is performed at an elevated temperature (e.g., >150° C.). In one embodiment, the implant energy may be between about 0.3-2 kV (e.g., 0.6 kV) and the dose may be between about 1E15/cm2 and 2E16/cm2 (e.g., 2E15/cm2). -
FIG. 1H illustrates theproduct 100 after a plurality of processes was performed to define anisolation structure 185 between thefins 165. A deposition process was performed to deposit a dielectric material and an etch process was performed to recess the dielectric material to expose upper portions of thefins 165. These processes may also be performed to define similar isolation structures (not shown) in thetransistor region 110. In some embodiments, one or more liner layers (e.g., silicon nitride, silicon dioxide or a stack thereof) (not shown) may be formed above thefins 165 prior to forming theisolation structure 185. Any such liners may be removed after the recessing of the dielectric material. -
FIG. 1I illustrates theproduct 100 after a plurality of processes was performed to form a contact structure 190 (e.g., anode contact) interfacing with the dopedsurface region 170. The processes may include one or more deposition processes to form one or more conductive layers (e.g., barrier layers, seed layers, fill layers) that will be part of the contact structure 190 (layers not separately shown). The conductive material may be planarized. -
FIG. 1J illustrates theproduct 100 after a plurality of processes was performed to form a contact structure 195 (e.g., cathode contact) interfacing with an undoped region of thefins 165. The processes may include one or more deposition processes to form one or more conductive layers (e.g., barrier layers, seed layers, fill layers) that will be part of the contact structure 195 (layers not separately shown). The conductive material may be planarized. - The processes to form the
contact structures transistor region 110. For example, if the processes are part of the gate electrode process, a gate insulation layer (not shown) (e.g., silicon dioxide, hafnium oxide or a high-k material) may be formed in bothregions diode region 115 prior to forming the conductive material. - Although line
type contact structures - The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.
Claims (15)
Priority Applications (2)
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US15/139,644 US9793262B1 (en) | 2016-04-27 | 2016-04-27 | Fin diode with increased junction area |
US15/686,523 US10056368B2 (en) | 2016-04-27 | 2017-08-25 | Fin diode with increased junction area |
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US15/139,644 US9793262B1 (en) | 2016-04-27 | 2016-04-27 | Fin diode with increased junction area |
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US15/686,523 Division US10056368B2 (en) | 2016-04-27 | 2017-08-25 | Fin diode with increased junction area |
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US9793262B1 US9793262B1 (en) | 2017-10-17 |
US20170317071A1 true US20170317071A1 (en) | 2017-11-02 |
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US15/139,644 Expired - Fee Related US9793262B1 (en) | 2016-04-27 | 2016-04-27 | Fin diode with increased junction area |
US15/686,523 Active US10056368B2 (en) | 2016-04-27 | 2017-08-25 | Fin diode with increased junction area |
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FR3052291B1 (en) * | 2016-06-03 | 2018-11-23 | Stmicroelectronics (Rousset) Sas | METHOD FOR MANUFACTURING A DIODE NETWORK, IN PARTICULAR FOR A NONVOLATILE MEMORY, AND CORRESPONDING DEVICE. |
US11462648B2 (en) * | 2019-12-05 | 2022-10-04 | Globalfoundries U.S. Inc. | Fin-based Schottky diode for integrated circuit (IC) products and methods of making such a Schottky diode |
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US20090085163A1 (en) * | 2007-09-27 | 2009-04-02 | Christian Russ | Vertical diode using silicon formed by selective epitaxial growth |
US20090280582A1 (en) * | 2008-05-09 | 2009-11-12 | Interuniversitair Microelektronica Centrum | Design Methodology for MuGFET ESD Protection Devices |
US20130285208A1 (en) * | 2012-04-26 | 2013-10-31 | International Business Machines Corporation | Finfet diode with increased junction area |
US20140124863A1 (en) * | 2012-11-07 | 2014-05-08 | International Business Machines Corporation | Method and structure for forming a localized soi finfet |
US9318621B2 (en) * | 2013-03-08 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Rotated STI diode on FinFET technology |
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US7560784B2 (en) * | 2007-02-01 | 2009-07-14 | International Business Machines Corporation | Fin PIN diode |
US8682116B2 (en) * | 2007-08-08 | 2014-03-25 | Infineon Technologies Ag | Integrated circuit including non-planar structure and waveguide |
KR101006527B1 (en) * | 2008-11-10 | 2011-01-07 | 주식회사 하이닉스반도체 | Phase change memory device and method for manufacturing the same |
US8610241B1 (en) * | 2012-06-12 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Homo-junction diode structures using fin field effect transistor processing |
US20140131831A1 (en) * | 2012-11-12 | 2014-05-15 | GlobalFoundries, Inc. | Integrated ciruit including an fin-based diode and methods of its fabrication |
TWI523084B (en) * | 2014-11-11 | 2016-02-21 | 漢辰科技股份有限公司 | Method for ion implantation |
US9318622B1 (en) * | 2015-06-23 | 2016-04-19 | International Business Machines Corporation | Fin-type PIN diode array |
US9704966B1 (en) * | 2016-07-25 | 2017-07-11 | Globalfoundries Inc. | Fin-based RF diodes |
US9799647B1 (en) * | 2016-08-22 | 2017-10-24 | International Business Machines Corporation | Integrated device with P-I-N diodes and vertical field effect transistors |
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- 2016-04-27 US US15/139,644 patent/US9793262B1/en not_active Expired - Fee Related
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US20090085163A1 (en) * | 2007-09-27 | 2009-04-02 | Christian Russ | Vertical diode using silicon formed by selective epitaxial growth |
US20090280582A1 (en) * | 2008-05-09 | 2009-11-12 | Interuniversitair Microelektronica Centrum | Design Methodology for MuGFET ESD Protection Devices |
US20130285208A1 (en) * | 2012-04-26 | 2013-10-31 | International Business Machines Corporation | Finfet diode with increased junction area |
US20140124863A1 (en) * | 2012-11-07 | 2014-05-08 | International Business Machines Corporation | Method and structure for forming a localized soi finfet |
US9318621B2 (en) * | 2013-03-08 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Rotated STI diode on FinFET technology |
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US20180006019A1 (en) | 2018-01-04 |
US9793262B1 (en) | 2017-10-17 |
US10056368B2 (en) | 2018-08-21 |
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