US20170256455A1 - Methods to form multi threshold-voltage dual channel without channel doping - Google Patents

Methods to form multi threshold-voltage dual channel without channel doping Download PDF

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US20170256455A1
US20170256455A1 US15/599,026 US201715599026A US2017256455A1 US 20170256455 A1 US20170256455 A1 US 20170256455A1 US 201715599026 A US201715599026 A US 201715599026A US 2017256455 A1 US2017256455 A1 US 2017256455A1
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Hoon Kim
Min-Gyu Sung
Ruilong Xie
Chanro Park
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GlobalFoundries Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Definitions

  • the present disclosure relates generally to designing and fabricating integrated circuit (IC) devices.
  • the present disclosure is particularly applicable to forming multi threshold-voltage (V t ) dual channels in an IC device for 7 nanometer (nm) technology node and beyond.
  • various advanced processes may be utilized in the design and fabrication of IC devices, particularly to aid with forming multi V t channels in an IC device.
  • Current processes for example, utilizing lanthanum-oxide (La 2 O 3 ) and channel doping in 10 nm node devices, may cause performance degradation and be unsuitable in smaller technology nodes.
  • Such processes may include higher thermal ranges as well as a chemical reaction to achieve uniform V t shift in short and long channels in an IC device.
  • a plasma channel doping process may be inconsistent due to plasma life time difference in short and long channels.
  • different work-function (WF) materials are utilized in different device types (e.g. n-type or p-type) that may require additional lithography steps.
  • An aspect of the present disclosure is a method of forming multi V t channels in an IC device, including a single type of WF material, utilizing lower annealing temperatures.
  • An aspect of the present disclosure is an IC device including multi V t channels and a single type of WF material.
  • some technical effects may be achieved in part by a method including providing an interfacial layer on an upper surface of a semiconductor substrate; forming conformally a first high-k dielectric layer on the interfacial layer; forming conformally a second high-k dielectric layer and a first cap layer, respectively, on the first high-k dielectric layer; removing the second high-k dielectric and first cap layers in first and second regions; forming a second cap layer on the first high-k dielectric layer in the first and second regions and on the first cap layer in a third region; performing an annealing process; removing the second cap layer from all regions and the first cap layer from the third region; forming a third high-k dielectric layer over all regions; forming conformally a work-function composition layer and a barrier layer, respectively, on the third high-k dielectric layer in all regions; removing the barrier layer from the first region; and forming a gate electrode over all regions.
  • a high-voltage threshold region is formed in the first region
  • a low-voltage threshold region is formed in the second region
  • a super low-voltage threshold region is formed in the third region.
  • a super low-voltage threshold region is formed in the first region, a low-voltage threshold region is formed in the second region, and a high-voltage threshold region is formed in the third region.
  • An additional aspect includes forming the third high-k dielectric layer based on a leakage current behavior of the second high-k dielectric layer.
  • One aspect includes forming the second high-k dielectric layer based on a threshold-voltage shift target.
  • a further aspect includes forming the work-function composition layer by sandwiching a work-function metal layer between two layers of titanium nitride (TiN).
  • Another aspect includes forming the first high-k dielectric layer of hafnium-oxide (HfO 2 ) to a thickness of 10 to 30 angstroms ( ⁇ ), for example 17 ⁇ .
  • HfO 2 hafnium-oxide
  • One aspect includes forming the second high-k dielectric layer of La 2 O 3 to a thickness of 0.1 to 20 ⁇ , for example 10 ⁇ .
  • the second high-k dielectric layer is driven into the first high-k dielectric layer with a higher concentration in proximity to the semiconductor substrate than near the gate electrode.
  • An additional aspect includes determining an annealing temperature based on a concentration level of a metalloid in the second high-k dielectric layer.
  • Another aspect of the present disclosure is a device including: an interfacial layer on a semiconductor substrate; a first high-k dielectric layer on the interfacial layer; a second high-k dielectric layer, different from the first, defused through the first high-k dielectric layer and into the interfacial layer in a third of three regions; a third high-k dielectric layer over the first high-k dielectric layer in first and second regions and over the second high-k dielectric in the third region; a work-function composition layer on the third high-k dielectric layer in all regions; a barrier layer on the work-function composition layer in the second and third regions; and a gate electrode over all regions.
  • the semiconductor substrate is n-type and includes a high-voltage threshold region in the first region, a low-voltage threshold region in the second region, and a super low-voltage threshold region in the third region.
  • the semiconductor substrate is p-type and includes a super low-voltage threshold region in the first region, a low-voltage threshold region in the second region, and a high-voltage threshold region in the third region.
  • the second high-k dielectric layer is based on a threshold-voltage shift target
  • the third high-k dielectric layer is based on a leakage current behavior of the second high-k dielectric layer.
  • the work-function composition layer includes a work-function metal layer sandwiched between two layers of TiN.
  • the first high-k dielectric layer includes HfO 2 with a thickness of 10 to 30 ⁇ , for example 17 ⁇ .
  • the second high-k dielectric layer includes La 2 O 3 with a thickness of 0.1 to 20 ⁇ , for example 10 ⁇ .
  • the second high-k dielectric layer is driven into the first high-k dielectric layer with a higher concentration in proximity to the semiconductor substrate than near the gate electrode.
  • FIGS. 1A through 1J illustrate a process for forming multi V t channels in an IC device, in accordance with an exemplary embodiment.
  • the present disclosure addresses and solves the problem of variations and inaccuracies attendant upon forming multi V t channels in an IC device.
  • the present disclosure addresses and solves such problems, for instance, by, inter alia, including a single type of WF material (e.g. for p and n type channels), utilizing lower annealing temperatures (e.g. less than 900 degrees Celsius (900° C.)), wherein a low-voltage channel does not require channel doping or doping of a high-k dielectric.
  • the proposed method provides for a reduction in the number of lithography masks (e.g. two masks) utilized in the proposed process.
  • FIG. 1A illustrates a semiconductor substrate 101 (e.g., silicon (Si), silicon-germanium (SiGe), etc.), an interfacial layer 103 (e.g. oxide) on an upper surface of the semiconductor substrate 101 , and a first high-k dielectric layer 105 (e.g. HfO 2 with a thickness of 10 to 30 ⁇ ) on an upper surface of the interfacial layer 103 .
  • a semiconductor substrate 101 e.g., silicon (Si), silicon-germanium (SiGe), etc.
  • an interfacial layer 103 e.g. oxide
  • a first high-k dielectric layer 105 e.g. HfO 2 with a thickness of 10 to 30 ⁇
  • n-type semiconductor substrate 101 e.g. for n-type field-effect-transistor (nFET)
  • there may be first, 107 , second, 109 , and third, 111 regions corresponding, respectively, to a high (RVT
  • a high threshold voltage corresponds to a voltage greater than 300 millivolts (mV)
  • a super low VT corresponds to a voltage less than 200 mV
  • a low VT corresponds to a voltage between 225 mV and 300 mV.
  • a second high-k dielectric layer 113 e.g. La 2 O 3 with a thickness of 0.1 to 20 ⁇
  • a first cap layer 115 e.g. TiN with a thickness of 10 to 20 ⁇ , for example 15 ⁇
  • the second high-k dielectric layer may be based on a threshold-voltage shift target.
  • the second high-k dielectric 113 and first cap layer 115 may be removed from the first and second, 107 / 109 , regions.
  • a second cap layer including layers 117 and 119 (e.g., TiN and amorphous-silicon), may be formed on the first high-k dielectric layer 105 in the first and second regions 107 / 109 , and on the first cap layer 115 in the third region 111 .
  • layers 117 and 119 e.g., TiN and amorphous-silicon
  • an annealing process may be performed to drive a concentration of the second high-k dielectric layer 113 through the first high-k dielectric layer 105 and into the interfacial layer 103 in the third region 111 .
  • the annealing temperature (e.g. less than 900° C.) may be based on a concentration level of a metalloid in the semiconductor substrate 101 .
  • Concentration of the second high-k dielectric layer is at a closer proximity to the semiconductor substrate than to the gate electrode.
  • the second cap layer, 117 / 119 may be removed from all regions, and the first cap layer 115 may be removed from the third region 111 .
  • a third high-k dielectric layer 121 (e.g. HfO 2 ) may be formed over all three regions to a thickness of 0.1 to 20 ⁇ .
  • a work-function composition layer 123 and a barrier layer 125 e.g. fluorine barrier such as 20 to 30 ⁇ of titanium-aluminum-carbide (TiAlC)
  • TiAlC titanium-aluminum-carbide
  • the work-function composition layer 123 may be formed by sandwiching a work-function metal layer 127 (e.g. TiAlC for an n-type work-function (nWF) metal) between two TiN layers 129 and 131 . Formation and/or material of the third high-k dielectric layer 121 may be based on a leakage current behavior of the second high-k dielectric layer.
  • a section of the barrier layer 125 may be removed from the first region 107 , for example, by a removal (e.g. etching) process selective to the TiN layer 123 .
  • a wetting layer 133 e.g. 10 ⁇ TiN layer formed by chemical vapor deposition
  • a gate electrode 135 may be formed over the work-function composition layer 123 (e.g. on the TiN layer 131 ) in all regions.
  • FIG. 1J illustrates a similar structure to that of FIG. 1I , wherein if the semiconductor substrate 137 is a p-type, then first, 139 , second, 141 , and third, 143 , regions, respectively, correspond to SLVT, LVT, and RVT regions. It is noted that due to properties/characteristics of the substrate 137 (e.g. band offset of SiGe), an n-type WF metal (e.g. TiAlC) may still be utilized as a WF metal in a pFET device.
  • n-type WF metal e.g. TiAlC
  • the embodiments of the present disclosure can achieve several technical effects including utilizing efficient and reliable processes to form multi V t channels, including a single type of WF material, with a reduced annealing temperature budget. Furthermore, the embodiments enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, digital cameras, or other devices utilizing logic or high-voltage technology nodes. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices, including devices that use SRAM cells (e.g., liquid crystal display (LCD) drivers, digital processors, etc.), particularly for the 7 nm technology node and beyond.
  • SRAM cells e.g., liquid crystal display (LCD) drivers, digital processors, etc.

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Abstract

Methods to form multi Vt channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed. Embodiments include providing an interfacial-layer on a semiconductor substrate; forming a first high-k dielectric-layer on the interfacial-layer; forming a second high-k dielectric-layer and a first cap-layer, respectively, on the first high-k dielectric-layer; removing the second high-k dielectric and first cap layers in first and second regions; forming a second cap-layer on the first high-k dielectric-layer in the first and second regions and on the first cap-layer in a third region; performing an annealing process; removing the second cap-layer from all regions and the first cap-layer from the third region; forming a third high-k dielectric-layer over all regions; forming a work-function composition-layer and a barrier-layer on the third high-k dielectric-layer in all regions; removing the barrier-layer from the first region; and forming a gate electrode over all regions.

Description

    RELATED APPLICATION
  • The present application is a Divisional of application No. Ser. 15/014,150, filed on Feb. 3, 2016, which is incorporated herein by reference in its entirety.
    • TECHNICAL FIELD
  • The present disclosure relates generally to designing and fabricating integrated circuit (IC) devices. The present disclosure is particularly applicable to forming multi threshold-voltage (Vt) dual channels in an IC device for 7 nanometer (nm) technology node and beyond.
    • BACKGROUND
  • Generally, various advanced processes may be utilized in the design and fabrication of IC devices, particularly to aid with forming multi Vt channels in an IC device. Current processes, for example, utilizing lanthanum-oxide (La2O3) and channel doping in 10 nm node devices, may cause performance degradation and be unsuitable in smaller technology nodes. Such processes may include higher thermal ranges as well as a chemical reaction to achieve uniform Vt shift in short and long channels in an IC device. A plasma channel doping process may be inconsistent due to plasma life time difference in short and long channels. Additionally, different work-function (WF) materials are utilized in different device types (e.g. n-type or p-type) that may require additional lithography steps.
  • Therefore, a need exists for a methodology enabling formation of multi Vt channels in an IC device, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices.
    • SUMMARY
  • An aspect of the present disclosure is a method of forming multi Vt channels in an IC device, including a single type of WF material, utilizing lower annealing temperatures.
  • An aspect of the present disclosure is an IC device including multi Vt channels and a single type of WF material.
  • Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.
  • According to the present disclosure some technical effects may be achieved in part by a method including providing an interfacial layer on an upper surface of a semiconductor substrate; forming conformally a first high-k dielectric layer on the interfacial layer; forming conformally a second high-k dielectric layer and a first cap layer, respectively, on the first high-k dielectric layer; removing the second high-k dielectric and first cap layers in first and second regions; forming a second cap layer on the first high-k dielectric layer in the first and second regions and on the first cap layer in a third region; performing an annealing process; removing the second cap layer from all regions and the first cap layer from the third region; forming a third high-k dielectric layer over all regions; forming conformally a work-function composition layer and a barrier layer, respectively, on the third high-k dielectric layer in all regions; removing the barrier layer from the first region; and forming a gate electrode over all regions.
  • In one aspect where the semiconductor substrate is n-type, a high-voltage threshold region is formed in the first region, a low-voltage threshold region is formed in the second region, and a super low-voltage threshold region is formed in the third region.
  • In another aspect where the semiconductor substrate is p-type, a super low-voltage threshold region is formed in the first region, a low-voltage threshold region is formed in the second region, and a high-voltage threshold region is formed in the third region.
  • An additional aspect includes forming the third high-k dielectric layer based on a leakage current behavior of the second high-k dielectric layer.
  • One aspect includes forming the second high-k dielectric layer based on a threshold-voltage shift target.
  • A further aspect includes forming the work-function composition layer by sandwiching a work-function metal layer between two layers of titanium nitride (TiN).
  • Another aspect includes forming the first high-k dielectric layer of hafnium-oxide (HfO2) to a thickness of 10 to 30 angstroms (Å), for example 17 Å.
  • One aspect includes forming the second high-k dielectric layer of La2O3to a thickness of 0.1 to 20 Å, for example 10 Å.
  • In one aspect, after the annealing process, the second high-k dielectric layer is driven into the first high-k dielectric layer with a higher concentration in proximity to the semiconductor substrate than near the gate electrode.
  • An additional aspect includes determining an annealing temperature based on a concentration level of a metalloid in the second high-k dielectric layer.
  • Another aspect of the present disclosure is a device including: an interfacial layer on a semiconductor substrate; a first high-k dielectric layer on the interfacial layer; a second high-k dielectric layer, different from the first, defused through the first high-k dielectric layer and into the interfacial layer in a third of three regions; a third high-k dielectric layer over the first high-k dielectric layer in first and second regions and over the second high-k dielectric in the third region; a work-function composition layer on the third high-k dielectric layer in all regions; a barrier layer on the work-function composition layer in the second and third regions; and a gate electrode over all regions.
  • In another aspect, the semiconductor substrate is n-type and includes a high-voltage threshold region in the first region, a low-voltage threshold region in the second region, and a super low-voltage threshold region in the third region.
  • In another aspect, the semiconductor substrate is p-type and includes a super low-voltage threshold region in the first region, a low-voltage threshold region in the second region, and a high-voltage threshold region in the third region.
  • In one aspect, the second high-k dielectric layer is based on a threshold-voltage shift target, and the third high-k dielectric layer is based on a leakage current behavior of the second high-k dielectric layer.
  • In an additional aspect, the work-function composition layer includes a work-function metal layer sandwiched between two layers of TiN.
  • In a further aspect, the first high-k dielectric layer includes HfO2 with a thickness of 10 to 30 Å, for example 17 Å.
  • In one aspect, the second high-k dielectric layer includes La2O3with a thickness of 0.1 to 20 Å, for example 10 Å.
  • In another aspect, the second high-k dielectric layer is driven into the first high-k dielectric layer with a higher concentration in proximity to the semiconductor substrate than near the gate electrode.
  • Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:
  • FIGS. 1A through 1J illustrate a process for forming multi Vt channels in an IC device, in accordance with an exemplary embodiment.
    •  DETAILED DESCRIPTION
  • For the purposes of clarity, in the following description, numerous specific details are set forth to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”
  • The present disclosure addresses and solves the problem of variations and inaccuracies attendant upon forming multi Vt channels in an IC device. The present disclosure addresses and solves such problems, for instance, by, inter alia, including a single type of WF material (e.g. for p and n type channels), utilizing lower annealing temperatures (e.g. less than 900 degrees Celsius (900° C.)), wherein a low-voltage channel does not require channel doping or doping of a high-k dielectric. Additionally, the proposed method provides for a reduction in the number of lithography masks (e.g. two masks) utilized in the proposed process.
  • FIG. 1A illustrates a semiconductor substrate 101 (e.g., silicon (Si), silicon-germanium (SiGe), etc.), an interfacial layer 103 (e.g. oxide) on an upper surface of the semiconductor substrate 101, and a first high-k dielectric layer 105 (e.g. HfO2 with a thickness of 10 to 30 Å) on an upper surface of the interfacial layer 103. In an n-type semiconductor substrate 101 (e.g. for n-type field-effect-transistor (nFET)), there may be first, 107, second, 109, and third, 111, regions corresponding, respectively, to a high (RVT), low (LVT), and super low (SLVT) threshold voltage. A high threshold voltage (VT) corresponds to a voltage greater than 300 millivolts (mV), a super low VT corresponds to a voltage less than 200 mV, and a low VT corresponds to a voltage between 225 mV and 300 mV.
  • In FIG. 1B, a second high-k dielectric layer 113 (e.g. La2O3 with a thickness of 0.1 to 20 Å) and a first cap layer 115 (e.g. TiN with a thickness of 10 to 20 Å, for example 15 Å), respectively, may be formed conformally on the first high-k dielectric layer 105 across all three regions 107, 109, and 111. The second high-k dielectric layer may be based on a threshold-voltage shift target.
  • illustrated in FIG. 1C, the second high-k dielectric 113 and first cap layer 115 may be removed from the first and second, 107/109, regions.
  • Adverting to FIG. 1D, a second cap layer, including layers 117 and 119 (e.g., TiN and amorphous-silicon), may be formed on the first high-k dielectric layer 105 in the first and second regions 107/109, and on the first cap layer 115 in the third region 111.
  • As illustrated in FIG. 1E, an annealing process may be performed to drive a concentration of the second high-k dielectric layer 113 through the first high-k dielectric layer 105 and into the interfacial layer 103 in the third region 111. The annealing temperature (e.g. less than 900° C.) may be based on a concentration level of a metalloid in the semiconductor substrate 101. Concentration of the second high-k dielectric layer is at a closer proximity to the semiconductor substrate than to the gate electrode. The second cap layer, 117/119, may be removed from all regions, and the first cap layer 115 may be removed from the third region 111.
  • In FIG. 1F, a third high-k dielectric layer 121 (e.g. HfO2) may be formed over all three regions to a thickness of 0.1 to 20 Å. In FIG. 1G, a work-function composition layer 123 and a barrier layer 125 (e.g. fluorine barrier such as 20 to 30 Å of titanium-aluminum-carbide (TiAlC)), respectively, may be formed on the third high-k dielectric layer 121 in all regions. The work-function composition layer 123 may be formed by sandwiching a work-function metal layer 127 (e.g. TiAlC for an n-type work-function (nWF) metal) between two TiN layers 129 and 131. Formation and/or material of the third high-k dielectric layer 121 may be based on a leakage current behavior of the second high-k dielectric layer.
  • In FIG. 1H, a section of the barrier layer 125 may be removed from the first region 107, for example, by a removal (e.g. etching) process selective to the TiN layer 123. As illustrated in FIG. 1I, a wetting layer 133 (e.g. 10 Å TiN layer formed by chemical vapor deposition) and a gate electrode 135, respectively, may be formed over the work-function composition layer 123 (e.g. on the TiN layer 131) in all regions.
  • FIG. 1J illustrates a similar structure to that of FIG. 1I, wherein if the semiconductor substrate 137 is a p-type, then first, 139, second, 141, and third, 143, regions, respectively, correspond to SLVT, LVT, and RVT regions. It is noted that due to properties/characteristics of the substrate 137 (e.g. band offset of SiGe), an n-type WF metal (e.g. TiAlC) may still be utilized as a WF metal in a pFET device.
  • The embodiments of the present disclosure can achieve several technical effects including utilizing efficient and reliable processes to form multi Vt channels, including a single type of WF material, with a reduced annealing temperature budget. Furthermore, the embodiments enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, digital cameras, or other devices utilizing logic or high-voltage technology nodes. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices, including devices that use SRAM cells (e.g., liquid crystal display (LCD) drivers, digital processors, etc.), particularly for the 7 nm technology node and beyond.
  • In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.

Claims (20)

What is claimed is:
1. A semiconductor device comprising:
an interfacial layer on a semiconductor substrate;
a first high-k dielectric layer on the interfacial layer;
a second high-k dielectric layer, different from the first, diffused through the first high-k dielectric layer and into the interfacial layer in a third of three regions;
a third high-k dielectric layer over the first high-k dielectric layer in first and second regions and over the second high-k dielectric in the third region;
a work-function composition layer on the third high-k dielectric layer in all regions;
a barrier layer on the work-function composition layer in the second and third regions; and
a gate electrode over all regions.
2. The semiconductor device according to claim 1, wherein the semiconductor substrate is n-type, the semiconductor device comprising:
a high-voltage threshold region in the first region;
a low-voltage threshold region in the second region; and
a super low-voltage threshold region in the third region.
3. The semiconductor device according to claim 1, wherein the semiconductor substrate is p-type, the semiconductor device comprising:
a super low-voltage threshold region in the first region;
a low-voltage threshold region in the second region; and
a high-voltage threshold region in the third region.
4. The semiconductor device according to claim 1, wherein:
the second high-k dielectric layer is based on a threshold-voltage shift target, and
the third high-k dielectric layer is based on a leakage current behavior of the second high-k dielectric layer.
5. The semiconductor device according to claim 1, wherein:
the work-function composition layer comprises a work-function metal layer sandwiched between two layers of titanium nitride.
6. The semiconductor device according to claim 1, wherein the first high-k dielectric layer comprises hafnium-oxide with a thickness of 10 to 30 Å.
7. The semiconductor device according to claim 1, wherein the second high-k dielectric layer comprises lanthanum-oxide with a thickness of 0.1 to 20 Å.
8. The semiconductor device according to claim 1, wherein the second high-k dielectric layer is driven into the first high-k dielectric layer with a higher concentration in proximity to the semiconductor substrate than near the gate electrode.
9. A semiconductor device comprising:
an interfacial layer along the entirety of and on an upper surface of a semiconductor substrate;
a first conformal high-k dielectric layer along the entirety of and on the interfacial layer in first, second, and third regions;
a second conformal high-k dielectric layer along and on the first high-k dielectric layer in only the third region, wherein the second conformal high-k dielectric layer is based on a threshold-voltage shift target;
a third high-k dielectric layer over the first, second, and third regions, wherein the third high-k dielectric layer is based on a leakage current behavior of the second high-k dielectric layer;
a conformal work-function composition layer on the third high-k dielectric layer in the first, second, and third regions;
a barrier layer on only the second and third regions; and
a gate electrode over the first, second, and third regions.
10. The semiconductor device according to claim 9, wherein the semiconductor substrate is n-type and includes a high-voltage threshold region in the first region, a low-voltage threshold region in the second region, and a super low-voltage threshold region in the third region, and
Figure US20170256455A1-20170907-P00999
11. A semiconductor device comprising:
an interfacial layer along the entirety of and on an upper surface of a semiconductor substrate;
a first conformal high-k dielectric layer along the entirety of and on the interfacial layer in first, second, and third regions;
a second conformal high-k dielectric layer along and on the first high-k dielectric layer in only the third region;
a third high-k dielectric layer over the first, second, and third regions;
a conformal work-function composition layer on the third high-k dielectric layer in the first, second, and third regions;
a barrier layer on the conformal work-function composition layer only in the second and third regions; and
a gate electrode over the first, second, and third regions.
12. The semiconductor device according to claim 11, wherein the semiconductor substrate is n-type, the first region comprises a high-voltage threshold region; the second region comprises a low-voltage threshold region, and the third region comprises a super low-voltage threshold region.
13. The semiconductor device according to claim 11, wherein the semiconductor substrate is p-type, the first region comprises a super low-voltage threshold region, the second region comprises a low-voltage threshold region, and the third region comprises a high-voltage threshold region.
14. The semiconductor device according to claim 11, wherein
the third high-k dielectric layer is chosen based on a leakage current behavior of the second high-k dielectric layer.
15. The semiconductor device according to claim 11, wherein the second high-k dielectric layer is chosen based on a threshold-voltage shift target.
16. The semiconductor device according to claim 11, wherein the work-function composition layer comprises a work-function metal layer sandwiched between two layers of titanium nitride.
17. The semiconductor device according to claim 11, wherein the first high-k dielectric layer comprises hafnium-oxide to a thickness of 10 to 30 Å.
18. The semiconductor device according to claim 11, wherein the second high-k dielectric layer comprises lanthanum-oxide to a thickness of 0.1 to 20 Å.
19. The semiconductor device according to claim 11, wherein the second high-k dielectric layer is driven into the first high-k dielectric layer with a higher concentration in proximity to the semiconductor substrate than near the gate electrode.
20. The semiconductor device according to claim 9, wherein the semiconductor substrate is p-type and includes a super low-voltage threshold region in the first region, a low-voltage threshold region in the second region, and a high-voltage threshold region in the third region.
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