US20170250250A1 - Method, apparatus and system for improved nanowire/nanosheet spacers - Google Patents
Method, apparatus and system for improved nanowire/nanosheet spacers Download PDFInfo
- Publication number
- US20170250250A1 US20170250250A1 US15/056,966 US201615056966A US2017250250A1 US 20170250250 A1 US20170250250 A1 US 20170250250A1 US 201615056966 A US201615056966 A US 201615056966A US 2017250250 A1 US2017250250 A1 US 2017250250A1
- Authority
- US
- United States
- Prior art keywords
- layers
- spacer material
- sidewalls
- fin
- portions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 125000006850 spacer group Chemical group 0.000 title claims abstract description 106
- 238000000034 method Methods 0.000 title claims abstract description 82
- 239000002135 nanosheet Substances 0.000 title description 10
- 239000002070 nanowire Substances 0.000 title description 5
- 239000000463 material Substances 0.000 claims abstract description 164
- 239000004065 semiconductor Substances 0.000 claims abstract description 102
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 230000001590 oxidative effect Effects 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 239000003989 dielectric material Substances 0.000 claims description 8
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 8
- 230000008569 process Effects 0.000 description 23
- 238000012545 processing Methods 0.000 description 19
- 238000004519 manufacturing process Methods 0.000 description 18
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 10
- 235000012431 wafers Nutrition 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 239000000725 suspension Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- 238000003860 storage Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910020751 SixGe1-x Inorganic materials 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000013100 final test Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 150000004756 silanes Chemical class 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Definitions
- the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods, structures, and systems for preparing semiconductor devices comprising fins with improved nanosheet spacers.
- the manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material.
- the various processes from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
- a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot, using semiconductor-manufacturing tools, such as exposure tool or a stepper.
- semiconductor-manufacturing tools such as exposure tool or a stepper.
- an etch process may be performed on the semiconductor wafers to shape objects on the semiconductor wafer, such as polysilicon lines, each of which may function as a gate electrode for a transistor.
- a plurality of metal lines e.g., aluminum or copper, may be formed that serve as conductive lines that connect one conductive region on the semiconductor wafer to another. In this manner, integrated circuit chips may be fabricated.
- Fin field-effect transistors have been developed to replace conventional planar bulk MOSFETs in advanced CMOS technology by improving electrostatic control of the channel. Extending the concept of the finFET to further improve electrostatics involves developing structures where the gate wraps around the complete channel to form “gate-all-around” (GAA) devices.
- GAA devices the surrounded channels may comprise wires with rectangular or circular cross section, or sheets with a rectangular cross-section, which may be termed “nanowire devices” or “nanosheet devices”. To improve current density per footprint, these sheets or wires can be formed in a vertically stacked fashion, where multiple channels are formed one atop the other.
- Such nanowire/nanosheet devices therefore comprise multiple stacked semiconductor channel layers separated by sacrificial suspension material that is removed when performing a replacement metal gate (RMG) process in order to release the channel layers, which requires the devices to complete the majority of the FEOL flow similarly to a FinFET with sacrificial suspension layers remaining.
- RMG replacement metal gate
- Nanosheet devices generally require, during intermediate processing stages, spacer formation. If the spacer is misformed, subsequent epitaxial growth of source/drain elements from semiconductor sheets may at least in part nucleate from the sacrificial suspension material instead of the semiconductor sheets. Epitaxially-grown source/drain elements resulting from nucleation from sacrificial suspension material may therefore be unintentionally etched away during the channel release process, cause undesirable shorting or the introduction of unintended leakage paths in the final device.
- the present disclosure may address and/or at least reduce one or more of the problems identified above regarding the prior art and/or provide one or more of the desirable features listed above.
- the present disclosure is directed to various methods, apparatus, and systems for fabricating a semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers.
- FIG. 1A illustrates a stylized cross-sectional depiction of a semiconductor device after a first stage of processing in accordance with embodiments herein;
- FIG. 1B illustrates a stylized cross-sectional depiction of the semiconductor device of FIG. 1A after a second stage of processing in accordance with embodiments herein;
- FIG. 1C illustrates a stylized cross-sectional depiction of the semiconductor device of FIGS. 1A-1B after a third stage of processing in accordance with embodiments herein;
- FIG. 1D illustrates a stylized cross-sectional depiction of the semiconductor device of FIGS. 1A-1C after a fourth stage of processing in accordance with embodiments herein;
- FIG. 1E illustrates a stylized cross-sectional depiction of the semiconductor device of FIGS. 1A-1D after a fifth stage of processing in accordance with embodiments herein;
- FIG. 1F illustrates a stylized cross-sectional depiction of the semiconductor device of FIGS. 1A-1E after a sixth stage of processing in accordance with embodiments herein;
- FIG. 2A illustrates a stylized cross-sectional depiction of a semiconductor device after a first stage of processing in accordance with embodiments herein;
- FIG. 2B illustrates a stylized cross-sectional depiction of the semiconductor device of FIG. 2A after a second stage of processing in accordance with embodiments herein;
- FIG. 2C illustrates a stylized cross-sectional depiction of the semiconductor device of FIGS. 2A-2B after a third stage of processing in accordance with embodiments herein;
- FIG. 2D illustrates a stylized cross-sectional depiction of the semiconductor device of FIGS. 2A-2C after a fourth stage of processing in accordance with embodiments herein;
- FIG. 2E illustrates a stylized cross-sectional depiction of the semiconductor device of FIGS. 2A-2D after a fifth stage of processing in accordance with embodiments herein;
- FIG. 3 illustrates a semiconductor device manufacturing system for manufacturing a device in accordance with embodiments herein;
- FIG. 4 illustrates a flowchart of a method in accordance with embodiments herein.
- FIG. 5 illustrates a flowchart of a method in accordance with embodiments herein.
- Embodiments herein provide for forming nanosheet and/or nanosheet devices.
- Embodiments herein provide form a signal spacer material resulting from forming nanosheet/nanowire devices.
- An oxidation-based recessing of a suspension material used for forming nanosheet/nanowire devices is performed.
- Embodiments provide for laterally recessing the suspension material and performing an anisotropic spacer etchback of the laterally recessed suspension material.
- a first material may be fully removed after performing a suspension layer etchback process.
- the first material may be re-deposited and further etched to form spacers that are of a single material. Accordingly, these embodiments provide for a reduction of unwanted capacitance as a result of the elimination of spacers of dissimilar materials.
- Embodiments herein provide for a semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers.
- FIG. 1A a simplified view of a semiconductor structure, generally denoted by 100 , obtained during an intermediate stage of semiconductor fabrication is depicted.
- the semiconductor structure 100 comprises a semiconductor substrate layer 110 .
- the semiconductor substrate layer 110 may comprise a bulk semiconductor material, for example, bulk silicon; a silicon-on-insulator (SOI) structure; or other material known to the person of ordinary skill in the art for use a semiconductor substrate.
- SOI silicon-on-insulator
- the semiconductor structure 100 depicted in FIG. 1A also comprises at least one fin 120 comprising one or more first layers 130 and one or more second layers 140 , wherein the first layers and the second layers are interspersed and each of the second layers is more susceptible to oxidation than any of the first layers.
- the depicted embodiment shows three first layers 130 A, 130 B, and 130 C, and two first layers 140 A and 140 B, the person of ordinary skill in the art having the benefit of the present disclosure will through the exercise of routine skill be able to prepare a fin 120 comprising one, two, three, four, five, etc. first layers 130 and one, two, three, four, five, etc. second layers 140 .
- each of the first layers may comprise any material and each of the second layers may also comprise any material, provided that each of the second layers is more susceptible to oxidation than any of the first layers.
- each of the first layers may comprise a first material and each of the second layers may comprise a second material.
- the first material is silicon and the second material is silicon-germanium (SiGe) having a formula Si x Ge 1-x , wherein 0 ⁇ x ⁇ 1.
- x may be chosen such that 0.1 ⁇ x ⁇ 0.5.
- x ⁇ 0.5 i.e., the second material comprises about 50 mol % germanium).
- both layers 130 and 140 could be SiGe as long as the selection of x permits etch selectivity, e.g., layers 130 may each comprise Si x Ge 1-x and layers 140 may each comprise Si y Ge -y , wherein y>x.
- the first layers 130 and the second layers 140 may be formed by any appropriate processes.
- the second layers 140 may be formed, for example, by various epitaxial growth processes such as ultra-high vacuum chemical vapor deposition (UHV-CVD), low-pressure CVD (LPCVD), reduced-pressure CVD (RPCVD), rapid thermal CVD (RTCVD) and molecular beam epitaxy (MBE).
- UHV-CVD ultra-high vacuum chemical vapor deposition
- LPCVD low-pressure CVD
- RPCVD reduced-pressure CVD
- RTCVD rapid thermal CVD
- MBE molecular beam epitaxy
- the CVD-based epitaxial growth may take place at a temperature of between about 400° C. to about 1100° C., while molecular beam epitaxy may use a lower temperature.
- selective epitaxial growth of SiGe may be performed using halogermanes and silanes as the source gases at temperatures around 600° C.
- the first layers 130 and the second layers 140 may have any desired thickness, bearing in mind considerations which will be set forth below.
- the semiconductor structure 100 also comprises a dummy gate structure 124 comprising a first spacer material 170 disposed on sidewalls of the dummy gate.
- the first spacer material 170 may comprise any known spacer material.
- the first spacer material comprises a low-k dielectric material.
- the dummy gate structure 124 may also comprise an oxide layer 150 , which may comprise silicon oxide; a first material region 130 U, which may comprise amorphous silicon; and a nitride layer 160 , which may comprise silicon nitride.
- oxide layer 150 which may comprise silicon oxide
- first material region 130 U which may comprise amorphous silicon
- nitride layer 160 which may comprise silicon nitride.
- one or more of layers/regions 130 U, 150 , or 160 may be omitted or replaced with other materials, and/or additional layers/regions (not shown) known to the person of ordinary skill in the art for use in dummy gate structures in FinFETs and/or FinFET processing may be included.
- FIG. 1B a stylized depiction of the semiconductor structure 100 is shown after selectively oxidizing two portions 155 of each of the second layers 140 A, 140 B, wherein the two portions are exposed on the sidewalls of the fin 120 .
- the selective oxidation may be performed by any technique known in the art and which may be found by the application of routine skill to selectively oxidize the second material in preference to the first material to yield oxidized portions 155 .
- selectively oxidizing may comprise a prolonged annealing process in the presence of oxygen gas.
- selectively oxidizing may comprise a wet oxidation technique.
- oxidizing is performed, oxidizing the second layers 140 A, 140 B of a fin 120 converts the portions 155 into oxides, e.g., (in the case of the second material being SiGe) silicon oxide with some according volume expansion.
- FIG. 1C depicts semiconductor structure 100 after selectively stripping the two oxidized portions 155 of each of the second layers 140 , to yield a plurality of second layer recesses 145 .
- Any selective stripping technique known in the art may be used, provided it is sufficiently selective to the first layers 130 A, 130 B, 130 C and first spacer material 170 , as well as any of oxide layer 150 , first material region 130 U, and/or nitride layer 160 that may be present in dummy gate structure 124 .
- the semiconductor structure 100 is shown after depositing a second spacer material 180 on at least the sidewalls of the fins 120 , and in the depicted embodiment, on the dummy gate structures 124 as well, wherein the second spacer material 180 fills the plurality of second layer recesses 145 .
- the second spacer material 180 may be deposited by any appropriate technique, such as atomic layer deposition (ALD).
- the second spacer material 180 may be a low-k dielectric or a silicon nitride.
- the second spacer material 180 may be the same as the first spacer material 170 or may be different, and may be selected based on various considerations discussed in more detail below.
- the second spacer material 180 is shown covering the entirety of the sidewalls of the fin 120 and the dummy gate structure 124 , along with the top of the dummy gate structure 124 and the surface of semiconductor substrate 110 .
- the second spacer material 180 may be etched back to yield the structure depicted in FIG. 1E .
- the second spacer material 180 may be etched back from at least the portions of the first layers 130 A, 130 B, 120 C exposed on the sidewalls of the fin 120 .
- the second spacer material 180 may also be etched back from first spacer material 170 and/or nitride layer 160 .
- any etching technique known in the art may be used for etching back the second spacer material 180 from at least the portions of the first layers 130 A, 130 B, 120 C exposed on the sidewalls of the fin 120 . If the first spacer material 170 and the second spacer material 180 are the same material, then etching process parameters may be selected to retain at least some of first spacer material 170 on the sidewalls of the dummy gate structure 124 . If the first spacer material 170 and the second spacer material 180 are different materials, then an etch selective to the first spacer material 170 may be performed.
- the semiconductor structure 100 is depicted after epitaxially growing a source/drain material 190 from at least portions of the first layers 130 A, 130 B, and 130 C exposed on the sidewalls of the fin 120 .
- the source/drain material 190 is further epitaxially grown from the semiconductor substrate 110 .
- Techniques for epitaxial growth are known to the person of ordinary skill in the art and can be routinely implemented upon having the benefit of the present disclosure.
- the process parameters of the epitaxial growth such as the duration of growth, may be selected such that the epitaxially grown source/drain material 190 may merge. In other embodiments, the epitaxially grown source/drain material 190 may not be merged.
- the semiconductor structure 100 depicted in FIG. 1F may then undergo additional, known processing steps to form various desired semiconductor devices.
- the semiconductor structure 100 may undergo replacement of one or more of the second layers 140 A, 140 B with a gate.
- FIG. 2A a second embodiment of a semiconductor structure, generally indicated as 200 , is depicted.
- FIGS. 2A-2E numerous depicted elements may be comparable to elements set forth in FIGS. 1A-1F and the accompanying discussion of those figures, above. Such comparable elements will be indicated in FIGS. 2A-2E with reference numerals having the same final two digits (and letter suffix, if any) as the corresponding reference numeral in FIGS. 1A-1F .
- the comparable elements in FIGS. 2A-2E will have a first digit of “2,” compared to a first digit of “1” in FIGS. 1A-1F .
- FIGS. 2A-2E will focus on differences relative to FIGS. 1A-1F .
- FIG. 2A shows the semiconductor structure 200 comprising a plurality of second layer recesses 145 , which may be produced by any known technique, such as those described above as leading to the semiconductor structure 100 shown in FIG. 1C .
- each of the first layers 130 A, 130 B, and 130 C may comprise silicon and each of the second layers 140 A, 140 B may comprise silicon/germanium (SiGe). If the second material is SiGe, it may have the germanium mole percentages described above.
- the first spacer material 170 may comprise a low-k dielectric material.
- FIG. 2B depicts the semiconductor structure 200 after removal of the first spacer material 170 from the dummy gate structure 124 .
- the first spacer material 170 may be removed by any appropriate technique, such as stripping of oxide or low-k dielectric selective to nitride or vice versa.
- FIG. 2C depicts the semiconductor structure 200 after deposition of a second spacer material 270 on at least the sidewalls of the fin 120 , wherein the second spacer material 270 fills the plurality of second layer recesses 145 .
- the second spacer material 270 may be a low-k dielectric material.
- the second spacer material 270 may be the same or may be different from the first spacer material 170 .
- the second spacer material 270 may be deposited by ALD.
- the semiconductor structure 200 is shown after etching back the second spacer material 270 from at least portions of each of the first layers 130 A, 130 B, 130 C extending laterally beyond the plurality of second layer recesses 145 , thereby exposing the portions of each of the first layers 130 A, 130 B, 130 C on the sidewalls of the fin 120 .
- Any etching technique known in the art may be used.
- second spacer material 270 is retained not only in recesses 145 adjacent to the remaining portions of the second layers 140 A, 140 B, but also on the sidewalls of the dummy gate structure 124 . In this case, an anisotropic etchback process may be desirable.
- FIG. 2E depicts the semiconductor structure 200 after epitaxial growth of the source/drain material 190 from at least the portions of the first layers 130 A, 130 B, 130 C exposed on the sidewalls of the fin 120 . Thereafter, the semiconductor structure 200 may undergo additional processing, such as replacing one or more of the second layers 140 A, 140 B with a gate, to yield a semiconductor device (not shown).
- a method of the present invention may produce a semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers.
- the system 300 of FIG. 3 may comprise a semiconductor device manufacturing system 310 and a process controller 320 .
- the semiconductor device manufacturing system 310 may manufacture semiconductor devices based upon one or more instruction sets provided by the process controller 320 .
- a first instruction set may comprise instructions to provide a semiconductor structure comprising a semiconductor substrate; at least one fin comprising one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and each of the second layers is more susceptible to oxidation than any of the first layers; and a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; selectively oxidize two portions of each of the second layers, wherein the two portions are exposed on the sidewalls of the fin; selectively strip the two portions of each of the second layers, to yield a plurality of second layer recesses; deposit a second spacer material on at least the sidewalls of the fin, wherein the second spacer material fills the plurality of second layer recesses; and epitaxially grow a source/drain material from at least portions of each of the first layers exposed on the sidewalls of the fin.
- the first instruction set may further comprise instructions to etch back the second spacer material from at least the portions of the first layers exposed on the sidewalls of the fin.
- the first instruction set may further comprise instructions to epitaxially grow the first material further comprises growing the first material from the semiconductor substrate.
- the first instruction set may further comprise instructions to replace one or more of the second layers with a gate.
- a second instruction set may comprise instructions to provide a semiconductor structure comprising a semiconductor substrate; at least one fin comprising one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and each second layer comprises two recesses along sidewalls of the fin; and a dummy gate structure comprising first spacer material disposed on the sidewalls of the dummy gate; remove the first spacer material; deposit a second spacer material on at least the sidewalls of the fins, wherein the second spacer material fills the plurality of second layer recesses; etch back the second spacer material from at least portions of each of the first layers extending laterally beyond the plurality of second layer recesses, thereby exposing the portions of each of the first layers on the sidewalls of the fin; and epitaxially grow a source/drain material from at least the portions of the first layers exposed on the sidewalls of the fin.
- the second instruction set may further comprise instructions to epitaxially grow the first material further comprises growing the first material
- the semiconductor device manufacturing system 310 may comprise various processing stations, such as etch process stations, photolithography process stations, CMP process stations, etc. One or more of the processing steps performed by the semiconductor device manufacturing system 310 may be controlled by the process controller 320 .
- the process controller 320 may be a workstation computer, a desktop computer, a laptop computer, a tablet computer, or any other type of computing device comprising one or more software products that are capable of controlling processes, receiving process feedback, receiving test results data, performing learning cycle adjustments, performing process adjustments, etc.
- the semiconductor device manufacturing system 310 may produce semiconductor devices 301 (e.g., integrated circuits) on a medium, such as silicon wafers.
- the semiconductor device manufacturing system 310 may provide processed semiconductor devices 301 on a transport mechanism 350 , such as a conveyor system.
- the conveyor system may be sophisticated clean room transport systems that are capable of transporting semiconductor wafers.
- the semiconductor device manufacturing system 310 may comprise a plurality of processing steps, e.g., the 1 st process step, the 2 nd process step, etc.
- the items labeled “ 301 ” may represent individual wafers, and in other embodiments, the items 301 may represent a group of semiconductor wafers, e.g., a “lot” of semiconductor wafers.
- the semiconductor device 301 may comprise one or more of a transistor, a capacitor, a resistor, a memory cell, a processor, and/or the like.
- the system 300 may be capable of manufacturing various products involving various technologies.
- the system 300 may produce devices of CMOS technology, Flash technology, BiCMOS technology, power devices, memory devices (e.g., DRAM devices), NAND memory devices, and/or various other semiconductor technologies.
- the method 400 comprises providing (at 410 ) a semiconductor structure 100 comprising a semiconductor substrate 110 ; at least one fin 120 comprising one or more first layers 130 A, 130 B, 130 C and one or more second layers 140 A, 140 B, wherein the first layers 130 A, 130 B, 130 C and the second layers 140 A, 140 B are interspersed and each of the second layers is more susceptible to oxidation than any of the first layers; and a dummy gate structure 124 comprising first spacer material 170 disposed on sidewalls of the fin 120 .
- the first material may be silicon and the second material may be silicon/germanium (SiGe).
- the first spacer material 170 may comprise a low-k dielectric material.
- the method 400 may further comprise selectively oxidizing (at 420 ) two portions of each of the second layers 140 A, 140 B, wherein the two portions are exposed on the sidewalls of the fin 120 .
- the two portions of each of the second layers 140 A, 140 B may be selectively stripped (at 430 ) to yield a plurality of second layer recesses 145 .
- the method 400 may comprise depositing (at 440 ) a second spacer material 180 on at least the sidewalls of the fin 120 , wherein the second spacer material 180 fills the plurality of second layer recesses 145 .
- the second spacer material 180 may be a low-k dielectric or a nitride, such as silicon nitride. In one embodiment, the second spacer material differs from the first spacer material.
- the method 400 may comprise etching back (at 445 ) the second spacer material 180 from at least the portions of the first layers 130 A, 130 B, 130 C exposed on the sidewalls of the fin 120 . In other embodiments, etching back (at 445 ) may not be required and may be omitted.
- the method 400 may then comprise epitaxially growing (at 450 ) a source/drain material 190 from at least portions of the first layers 130 A, 130 B, 130 C exposed on the sidewalls of the fin 120 .
- Epitaxially growing (at 450 ) may further comprise growing the source/drain material 190 from the semiconductor substrate 110 .
- the semiconductor structure produced by elements 410 - 450 may be used in subsequent steps of method 400 or other methods.
- the method 400 may further comprise replacing (at 455 ) one or more of the second layers with a gate.
- the method 500 comprises providing (at 500 ) a semiconductor structure 200 comprising a semiconductor substrate 110 and at least one fin 120 comprising one or more first layers 130 A, 130 B, 130 C and one or more second layers 140 A, 140 B, wherein the first layers and the second layers are interspersed and each second layer 140 A, 140 B comprises two recesses 145 along sidewalls of the fin 120 , and a dummy gate structure comprising first spacer material 170 disposed on the sidewalls of the dummy gate.
- the first material may be silicon and the second material may be silicon/germanium (SiGe).
- the first spacer material 170 may comprise a low-k dielectric material.
- providing (at 500 ) may comprise the providing (at 410 ), selectively oxidizing (at 420 ) and selectively stripping (at 430 ) elements of method 400 described above.
- the method 500 may further comprise removing (at 520 ) the first spacer material 170 , which may be followed by depositing (at 530 ) a second spacer material 270 on at least the sidewalls of the fins 120 , wherein the second spacer material 270 fills the plurality of second layer recesses 145 .
- the second spacer material 270 may be a low-k dielectric or a nitride, such as silicon nitride. In one embodiment, the second spacer material 270 differs from the first spacer material 170 .
- the method 500 may also comprise etching back (at 540 ) the second spacer material 270 from at least portions of each of the first layers 130 A, 130 B, 130 C extending laterally beyond the plurality of second layer recesses 145 , thereby exposing the portions of each of the first layers 130 A, 130 B, 130 C on the sidewalls of the fin 120 .
- the method 500 may comprise epitaxially growing (at 550 ) a source/drain material 190 from at least the portions of the first layers 130 A, 130 B, 130 C exposed on the sidewalls of the fin 120 .
- Epitaxially growing (at 550 ) may further comprise growing the source/drain material 190 from the semiconductor substrate 110 .
- the semiconductor structure produced by elements 510 - 550 may be used in subsequent steps of method 500 or other methods.
- the method 500 may further comprise replacing (at 555 ) one or more of the second layers with a gate.
- the methods described above may be governed by instructions that are stored in a non-transitory computer readable storage medium and that are executed by, e.g., a processor in a computing device.
- Each of the operations described herein may correspond to instructions stored in a non-transitory computer memory or computer readable storage medium.
- the non-transitory computer readable storage medium includes a magnetic or optical disk storage device, solid state storage devices such as flash memory, or other non-volatile memory device or devices.
- the computer readable instructions stored on the non-transitory computer readable storage medium may be in source code, assembly language code, object code, or other instruction format that is interpreted and/or executable by one or more processors.
Abstract
Description
- 1. Field of the Invention
- Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods, structures, and systems for preparing semiconductor devices comprising fins with improved nanosheet spacers.
- 2. Description of the Related Art
- The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
- Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot, using semiconductor-manufacturing tools, such as exposure tool or a stepper. As an example, an etch process may be performed on the semiconductor wafers to shape objects on the semiconductor wafer, such as polysilicon lines, each of which may function as a gate electrode for a transistor. As another example, a plurality of metal lines, e.g., aluminum or copper, may be formed that serve as conductive lines that connect one conductive region on the semiconductor wafer to another. In this manner, integrated circuit chips may be fabricated.
- Fin field-effect transistors (FinFET) devices have been developed to replace conventional planar bulk MOSFETs in advanced CMOS technology by improving electrostatic control of the channel. Extending the concept of the finFET to further improve electrostatics involves developing structures where the gate wraps around the complete channel to form “gate-all-around” (GAA) devices. In GAA devices, the surrounded channels may comprise wires with rectangular or circular cross section, or sheets with a rectangular cross-section, which may be termed “nanowire devices” or “nanosheet devices”. To improve current density per footprint, these sheets or wires can be formed in a vertically stacked fashion, where multiple channels are formed one atop the other. Such nanowire/nanosheet devices therefore comprise multiple stacked semiconductor channel layers separated by sacrificial suspension material that is removed when performing a replacement metal gate (RMG) process in order to release the channel layers, which requires the devices to complete the majority of the FEOL flow similarly to a FinFET with sacrificial suspension layers remaining.
- Nanosheet devices generally require, during intermediate processing stages, spacer formation. If the spacer is misformed, subsequent epitaxial growth of source/drain elements from semiconductor sheets may at least in part nucleate from the sacrificial suspension material instead of the semiconductor sheets. Epitaxially-grown source/drain elements resulting from nucleation from sacrificial suspension material may therefore be unintentionally etched away during the channel release process, cause undesirable shorting or the introduction of unintended leakage paths in the final device.
- The present disclosure may address and/or at least reduce one or more of the problems identified above regarding the prior art and/or provide one or more of the desirable features listed above.
- The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
- Generally, the present disclosure is directed to various methods, apparatus, and systems for fabricating a semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers.
- The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
-
FIG. 1A illustrates a stylized cross-sectional depiction of a semiconductor device after a first stage of processing in accordance with embodiments herein; -
FIG. 1B illustrates a stylized cross-sectional depiction of the semiconductor device ofFIG. 1A after a second stage of processing in accordance with embodiments herein; -
FIG. 1C illustrates a stylized cross-sectional depiction of the semiconductor device ofFIGS. 1A-1B after a third stage of processing in accordance with embodiments herein; -
FIG. 1D illustrates a stylized cross-sectional depiction of the semiconductor device ofFIGS. 1A-1C after a fourth stage of processing in accordance with embodiments herein; -
FIG. 1E illustrates a stylized cross-sectional depiction of the semiconductor device ofFIGS. 1A-1D after a fifth stage of processing in accordance with embodiments herein; -
FIG. 1F illustrates a stylized cross-sectional depiction of the semiconductor device ofFIGS. 1A-1E after a sixth stage of processing in accordance with embodiments herein; -
FIG. 2A illustrates a stylized cross-sectional depiction of a semiconductor device after a first stage of processing in accordance with embodiments herein; -
FIG. 2B illustrates a stylized cross-sectional depiction of the semiconductor device ofFIG. 2A after a second stage of processing in accordance with embodiments herein; -
FIG. 2C illustrates a stylized cross-sectional depiction of the semiconductor device ofFIGS. 2A-2B after a third stage of processing in accordance with embodiments herein; -
FIG. 2D illustrates a stylized cross-sectional depiction of the semiconductor device ofFIGS. 2A-2C after a fourth stage of processing in accordance with embodiments herein; -
FIG. 2E illustrates a stylized cross-sectional depiction of the semiconductor device ofFIGS. 2A-2D after a fifth stage of processing in accordance with embodiments herein; -
FIG. 3 illustrates a semiconductor device manufacturing system for manufacturing a device in accordance with embodiments herein; -
FIG. 4 illustrates a flowchart of a method in accordance with embodiments herein; and -
FIG. 5 illustrates a flowchart of a method in accordance with embodiments herein. - While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
- Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
- The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
- Embodiments herein provide for forming nanosheet and/or nanosheet devices. Embodiments herein provide form a signal spacer material resulting from forming nanosheet/nanowire devices. An oxidation-based recessing of a suspension material used for forming nanosheet/nanowire devices is performed. Embodiments provide for laterally recessing the suspension material and performing an anisotropic spacer etchback of the laterally recessed suspension material.
- Other embodiments herein provide for forming nanosheet devices using a sacrificial spacer process. A first material may be fully removed after performing a suspension layer etchback process. The first material may be re-deposited and further etched to form spacers that are of a single material. Accordingly, these embodiments provide for a reduction of unwanted capacitance as a result of the elimination of spacers of dissimilar materials.
- Embodiments herein provide for a semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers.
- Turning to
FIG. 1A , a simplified view of a semiconductor structure, generally denoted by 100, obtained during an intermediate stage of semiconductor fabrication is depicted. At the stage of fabrication depicted inFIG. 1A , thesemiconductor structure 100 comprises asemiconductor substrate layer 110. Thesemiconductor substrate layer 110 may comprise a bulk semiconductor material, for example, bulk silicon; a silicon-on-insulator (SOI) structure; or other material known to the person of ordinary skill in the art for use a semiconductor substrate. - The
semiconductor structure 100 depicted inFIG. 1A also comprises at least onefin 120 comprising one or more first layers 130 and one or more second layers 140, wherein the first layers and the second layers are interspersed and each of the second layers is more susceptible to oxidation than any of the first layers. Although the depicted embodiment shows threefirst layers first layers fin 120 comprising one, two, three, four, five, etc. first layers 130 and one, two, three, four, five, etc. second layers 140. - Each of the first layers may comprise any material and each of the second layers may also comprise any material, provided that each of the second layers is more susceptible to oxidation than any of the first layers. In one embodiment, each of the first layers may comprise a first material and each of the second layers may comprise a second material. In one embodiment, the first material is silicon and the second material is silicon-germanium (SiGe) having a formula SixGe1-x, wherein 0≦x≦1. In accordance with embodiments herein, x may be chosen such that 0.1≦x≦0.5. In one embodiment, x≈0.5 (i.e., the second material comprises about 50 mol % germanium). It should be noted that both layers 130 and 140 could be SiGe as long as the selection of x permits etch selectivity, e.g., layers 130 may each comprise SixGe1-x and layers 140 may each comprise SiyGe-y, wherein y>x.
- The first layers 130 and the second layers 140 may be formed by any appropriate processes. The second layers 140 may be formed, for example, by various epitaxial growth processes such as ultra-high vacuum chemical vapor deposition (UHV-CVD), low-pressure CVD (LPCVD), reduced-pressure CVD (RPCVD), rapid thermal CVD (RTCVD) and molecular beam epitaxy (MBE). In one example, the CVD-based epitaxial growth may take place at a temperature of between about 400° C. to about 1100° C., while molecular beam epitaxy may use a lower temperature. In a specific example, wherein the second layers 140 comprise SiGe, selective epitaxial growth of SiGe may be performed using halogermanes and silanes as the source gases at temperatures around 600° C.
- The first layers 130 and the second layers 140 may have any desired thickness, bearing in mind considerations which will be set forth below.
- As shown in
FIG. 1A , thesemiconductor structure 100 also comprises adummy gate structure 124 comprising afirst spacer material 170 disposed on sidewalls of the dummy gate. Thefirst spacer material 170 may comprise any known spacer material. In one embodiment, the first spacer material comprises a low-k dielectric material. - As depicted, the
dummy gate structure 124 may also comprise anoxide layer 150, which may comprise silicon oxide; afirst material region 130U, which may comprise amorphous silicon; and anitride layer 160, which may comprise silicon nitride. In other embodiments, one or more of layers/regions - Turning now to
FIG. 1B , a stylized depiction of thesemiconductor structure 100 is shown after selectively oxidizing twoportions 155 of each of thesecond layers fin 120. The selective oxidation may be performed by any technique known in the art and which may be found by the application of routine skill to selectively oxidize the second material in preference to the first material to yieldoxidized portions 155. In one example, selectively oxidizing may comprise a prolonged annealing process in the presence of oxygen gas. In another example, selectively oxidizing may comprise a wet oxidation technique. However oxidizing is performed, oxidizing thesecond layers fin 120 converts theportions 155 into oxides, e.g., (in the case of the second material being SiGe) silicon oxide with some according volume expansion. -
FIG. 1C depictssemiconductor structure 100 after selectively stripping the twooxidized portions 155 of each of the second layers 140, to yield a plurality of second layer recesses 145. Any selective stripping technique known in the art may be used, provided it is sufficiently selective to thefirst layers first spacer material 170, as well as any ofoxide layer 150,first material region 130U, and/ornitride layer 160 that may be present indummy gate structure 124. - Referring to
FIG. 1D , thesemiconductor structure 100 is shown after depositing asecond spacer material 180 on at least the sidewalls of thefins 120, and in the depicted embodiment, on thedummy gate structures 124 as well, wherein thesecond spacer material 180 fills the plurality of second layer recesses 145. Thesecond spacer material 180 may be deposited by any appropriate technique, such as atomic layer deposition (ALD). - The
second spacer material 180 may be a low-k dielectric or a silicon nitride. Thesecond spacer material 180 may be the same as thefirst spacer material 170 or may be different, and may be selected based on various considerations discussed in more detail below. - In the embodiment shown in
FIG. 1D , thesecond spacer material 180 is shown covering the entirety of the sidewalls of thefin 120 and thedummy gate structure 124, along with the top of thedummy gate structure 124 and the surface ofsemiconductor substrate 110. In embodiments such as the depicted one, wherein thesecond spacer material 180 is deposited in locations in addition to the second layer recesses 145, thesecond spacer material 180 may be etched back to yield the structure depicted inFIG. 1E . Specifically, thesecond spacer material 180 may be etched back from at least the portions of thefirst layers fin 120. Thesecond spacer material 180 may also be etched back fromfirst spacer material 170 and/ornitride layer 160. - Any etching technique known in the art may be used for etching back the
second spacer material 180 from at least the portions of thefirst layers fin 120. If thefirst spacer material 170 and thesecond spacer material 180 are the same material, then etching process parameters may be selected to retain at least some offirst spacer material 170 on the sidewalls of thedummy gate structure 124. If thefirst spacer material 170 and thesecond spacer material 180 are different materials, then an etch selective to thefirst spacer material 170 may be performed. - Turning to
FIG. 1F , thesemiconductor structure 100 is depicted after epitaxially growing a source/drain material 190 from at least portions of thefirst layers fin 120. In the depicted embodiment, the source/drain material 190 is further epitaxially grown from thesemiconductor substrate 110. Techniques for epitaxial growth are known to the person of ordinary skill in the art and can be routinely implemented upon having the benefit of the present disclosure. The process parameters of the epitaxial growth, such as the duration of growth, may be selected such that the epitaxially grown source/drain material 190 may merge. In other embodiments, the epitaxially grown source/drain material 190 may not be merged. - The
semiconductor structure 100 depicted inFIG. 1F may then undergo additional, known processing steps to form various desired semiconductor devices. For example, in one embodiment, (not shown), thesemiconductor structure 100 may undergo replacement of one or more of thesecond layers - Turning now to
FIG. 2A , a second embodiment of a semiconductor structure, generally indicated as 200, is depicted. ThroughoutFIGS. 2A-2E , numerous depicted elements may be comparable to elements set forth inFIGS. 1A-1F and the accompanying discussion of those figures, above. Such comparable elements will be indicated inFIGS. 2A-2E with reference numerals having the same final two digits (and letter suffix, if any) as the corresponding reference numeral inFIGS. 1A-1F . The comparable elements inFIGS. 2A-2E will have a first digit of “2,” compared to a first digit of “1” inFIGS. 1A-1F . For the sake of brevity, such comparable elements will not be described in detail below. The description ofFIGS. 2A-2E will focus on differences relative toFIGS. 1A-1F . -
FIG. 2A shows thesemiconductor structure 200 comprising a plurality of second layer recesses 145, which may be produced by any known technique, such as those described above as leading to thesemiconductor structure 100 shown inFIG. 1C . In one embodiment, each of thefirst layers second layers first spacer material 170 may comprise a low-k dielectric material. -
FIG. 2B depicts thesemiconductor structure 200 after removal of thefirst spacer material 170 from thedummy gate structure 124. Thefirst spacer material 170 may be removed by any appropriate technique, such as stripping of oxide or low-k dielectric selective to nitride or vice versa. -
FIG. 2C depicts thesemiconductor structure 200 after deposition of asecond spacer material 270 on at least the sidewalls of thefin 120, wherein thesecond spacer material 270 fills the plurality of second layer recesses 145. Thesecond spacer material 270 may be a low-k dielectric material. Thesecond spacer material 270 may be the same or may be different from thefirst spacer material 170. Thesecond spacer material 270 may be deposited by ALD. - Turning to
FIG. 2D , thesemiconductor structure 200 is shown after etching back thesecond spacer material 270 from at least portions of each of thefirst layers first layers fin 120. Any etching technique known in the art may be used. Desirably,second spacer material 270 is retained not only inrecesses 145 adjacent to the remaining portions of thesecond layers dummy gate structure 124. In this case, an anisotropic etchback process may be desirable. - Finally,
FIG. 2E depicts thesemiconductor structure 200 after epitaxial growth of the source/drain material 190 from at least the portions of thefirst layers fin 120. Thereafter, thesemiconductor structure 200 may undergo additional processing, such as replacing one or more of thesecond layers - Regardless of how a
semiconductor structure - Turning now to
FIG. 3 , a stylized depiction of a system for fabricating asemiconductor device 100, in accordance with embodiments herein, is illustrated. Thesystem 300 ofFIG. 3 may comprise a semiconductordevice manufacturing system 310 and aprocess controller 320. The semiconductordevice manufacturing system 310 may manufacture semiconductor devices based upon one or more instruction sets provided by theprocess controller 320. In one embodiment, a first instruction set may comprise instructions to provide a semiconductor structure comprising a semiconductor substrate; at least one fin comprising one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and each of the second layers is more susceptible to oxidation than any of the first layers; and a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; selectively oxidize two portions of each of the second layers, wherein the two portions are exposed on the sidewalls of the fin; selectively strip the two portions of each of the second layers, to yield a plurality of second layer recesses; deposit a second spacer material on at least the sidewalls of the fin, wherein the second spacer material fills the plurality of second layer recesses; and epitaxially grow a source/drain material from at least portions of each of the first layers exposed on the sidewalls of the fin. The first instruction set may further comprise instructions to etch back the second spacer material from at least the portions of the first layers exposed on the sidewalls of the fin. The first instruction set may further comprise instructions to epitaxially grow the first material further comprises growing the first material from the semiconductor substrate. The first instruction set may further comprise instructions to replace one or more of the second layers with a gate. - In one embodiment, a second instruction set may comprise instructions to provide a semiconductor structure comprising a semiconductor substrate; at least one fin comprising one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and each second layer comprises two recesses along sidewalls of the fin; and a dummy gate structure comprising first spacer material disposed on the sidewalls of the dummy gate; remove the first spacer material; deposit a second spacer material on at least the sidewalls of the fins, wherein the second spacer material fills the plurality of second layer recesses; etch back the second spacer material from at least portions of each of the first layers extending laterally beyond the plurality of second layer recesses, thereby exposing the portions of each of the first layers on the sidewalls of the fin; and epitaxially grow a source/drain material from at least the portions of the first layers exposed on the sidewalls of the fin. The second instruction set may further comprise instructions to epitaxially grow the first material further comprises growing the first material from the semiconductor substrate. The second instruction set may further comprise instructions to replace one or more of the second layers with a gate.
- The semiconductor
device manufacturing system 310 may comprise various processing stations, such as etch process stations, photolithography process stations, CMP process stations, etc. One or more of the processing steps performed by the semiconductordevice manufacturing system 310 may be controlled by theprocess controller 320. Theprocess controller 320 may be a workstation computer, a desktop computer, a laptop computer, a tablet computer, or any other type of computing device comprising one or more software products that are capable of controlling processes, receiving process feedback, receiving test results data, performing learning cycle adjustments, performing process adjustments, etc. - The semiconductor
device manufacturing system 310 may produce semiconductor devices 301 (e.g., integrated circuits) on a medium, such as silicon wafers. The semiconductordevice manufacturing system 310 may provide processedsemiconductor devices 301 on atransport mechanism 350, such as a conveyor system. In some embodiments, the conveyor system may be sophisticated clean room transport systems that are capable of transporting semiconductor wafers. In one embodiment, the semiconductordevice manufacturing system 310 may comprise a plurality of processing steps, e.g., the 1st process step, the 2nd process step, etc. - In some embodiments, the items labeled “301” may represent individual wafers, and in other embodiments, the
items 301 may represent a group of semiconductor wafers, e.g., a “lot” of semiconductor wafers. Thesemiconductor device 301 may comprise one or more of a transistor, a capacitor, a resistor, a memory cell, a processor, and/or the like. - The
system 300 may be capable of manufacturing various products involving various technologies. For example, thesystem 300 may produce devices of CMOS technology, Flash technology, BiCMOS technology, power devices, memory devices (e.g., DRAM devices), NAND memory devices, and/or various other semiconductor technologies. - Turning to
FIG. 4 , a flowchart of amethod 400 in accordance with embodiments herein is depicted. Themethod 400 comprises providing (at 410) asemiconductor structure 100 comprising asemiconductor substrate 110; at least onefin 120 comprising one or morefirst layers second layers first layers second layers dummy gate structure 124 comprisingfirst spacer material 170 disposed on sidewalls of thefin 120. In one embodiment, the first material may be silicon and the second material may be silicon/germanium (SiGe). In one embodiment, thefirst spacer material 170 may comprise a low-k dielectric material. - The
method 400 may further comprise selectively oxidizing (at 420) two portions of each of thesecond layers fin 120. The two portions of each of thesecond layers - The
method 400 may comprise depositing (at 440) asecond spacer material 180 on at least the sidewalls of thefin 120, wherein thesecond spacer material 180 fills the plurality of second layer recesses 145. Thesecond spacer material 180 may be a low-k dielectric or a nitride, such as silicon nitride. In one embodiment, the second spacer material differs from the first spacer material. Thereafter, in one embodiment, themethod 400 may comprise etching back (at 445) thesecond spacer material 180 from at least the portions of thefirst layers fin 120. In other embodiments, etching back (at 445) may not be required and may be omitted. - The
method 400 may then comprise epitaxially growing (at 450) a source/drain material 190 from at least portions of thefirst layers fin 120. Epitaxially growing (at 450) may further comprise growing the source/drain material 190 from thesemiconductor substrate 110. - The semiconductor structure produced by elements 410-450 may be used in subsequent steps of
method 400 or other methods. In one embodiment, themethod 400 may further comprise replacing (at 455) one or more of the second layers with a gate. - Turning to
FIG. 5 , a flowchart of amethod 500 in accordance with embodiments herein is depicted. Themethod 500 comprises providing (at 500) asemiconductor structure 200 comprising asemiconductor substrate 110 and at least onefin 120 comprising one or morefirst layers second layers second layer recesses 145 along sidewalls of thefin 120, and a dummy gate structure comprisingfirst spacer material 170 disposed on the sidewalls of the dummy gate. In one embodiment, the first material may be silicon and the second material may be silicon/germanium (SiGe). In one embodiment, thefirst spacer material 170 may comprise a low-k dielectric material. In one embodiment, providing (at 500) may comprise the providing (at 410), selectively oxidizing (at 420) and selectively stripping (at 430) elements ofmethod 400 described above. - Regardless how the
semiconductor structure 200 is provided (at 510), themethod 500 may further comprise removing (at 520) thefirst spacer material 170, which may be followed by depositing (at 530) asecond spacer material 270 on at least the sidewalls of thefins 120, wherein thesecond spacer material 270 fills the plurality of second layer recesses 145. Thesecond spacer material 270 may be a low-k dielectric or a nitride, such as silicon nitride. In one embodiment, thesecond spacer material 270 differs from thefirst spacer material 170. - The
method 500 may also comprise etching back (at 540) thesecond spacer material 270 from at least portions of each of thefirst layers first layers fin 120. - In addition, the
method 500 may comprise epitaxially growing (at 550) a source/drain material 190 from at least the portions of thefirst layers fin 120. Epitaxially growing (at 550) may further comprise growing the source/drain material 190 from thesemiconductor substrate 110. - The semiconductor structure produced by elements 510-550 may be used in subsequent steps of
method 500 or other methods. In one embodiment, themethod 500 may further comprise replacing (at 555) one or more of the second layers with a gate. - The methods described above may be governed by instructions that are stored in a non-transitory computer readable storage medium and that are executed by, e.g., a processor in a computing device. Each of the operations described herein may correspond to instructions stored in a non-transitory computer memory or computer readable storage medium. In various embodiments, the non-transitory computer readable storage medium includes a magnetic or optical disk storage device, solid state storage devices such as flash memory, or other non-volatile memory device or devices. The computer readable instructions stored on the non-transitory computer readable storage medium may be in source code, assembly language code, object code, or other instruction format that is interpreted and/or executable by one or more processors.
- The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is, therefore, evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
Claims (21)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/056,966 US9748335B1 (en) | 2016-02-29 | 2016-02-29 | Method, apparatus and system for improved nanowire/nanosheet spacers |
US15/652,873 US10249710B2 (en) | 2016-02-29 | 2017-07-18 | Methods, apparatus, and system for improved nanowire/nanosheet spacers |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/056,966 US9748335B1 (en) | 2016-02-29 | 2016-02-29 | Method, apparatus and system for improved nanowire/nanosheet spacers |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/652,873 Division US10249710B2 (en) | 2016-02-29 | 2017-07-18 | Methods, apparatus, and system for improved nanowire/nanosheet spacers |
Publications (2)
Publication Number | Publication Date |
---|---|
US9748335B1 US9748335B1 (en) | 2017-08-29 |
US20170250250A1 true US20170250250A1 (en) | 2017-08-31 |
Family
ID=59654820
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/056,966 Active US9748335B1 (en) | 2016-02-29 | 2016-02-29 | Method, apparatus and system for improved nanowire/nanosheet spacers |
US15/652,873 Active 2036-08-17 US10249710B2 (en) | 2016-02-29 | 2017-07-18 | Methods, apparatus, and system for improved nanowire/nanosheet spacers |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/652,873 Active 2036-08-17 US10249710B2 (en) | 2016-02-29 | 2017-07-18 | Methods, apparatus, and system for improved nanowire/nanosheet spacers |
Country Status (1)
Country | Link |
---|---|
US (2) | US9748335B1 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10032867B1 (en) * | 2017-03-07 | 2018-07-24 | International Business Machines Corporation | Forming bottom isolation layer for nanosheet technology |
US10269983B2 (en) * | 2017-05-09 | 2019-04-23 | Globalfoundries Inc. | Stacked nanosheet field-effect transistor with air gap spacers |
US10418449B2 (en) * | 2018-01-10 | 2019-09-17 | Globalfoundries Inc. | Circuits based on complementary field-effect transistors |
US10600641B2 (en) * | 2016-07-29 | 2020-03-24 | Applied Materials, Inc. | Silicon germanium selective oxidation process |
US11056574B2 (en) | 2018-11-27 | 2021-07-06 | Imec Vzw | Stacked semiconductor device and method of forming same |
US11107812B2 (en) | 2018-11-27 | 2021-08-31 | Imec Vzw | Method of fabricating stacked semiconductor device |
US20220052187A1 (en) * | 2017-09-13 | 2022-02-17 | Samsung Electronics Co., Ltd. | Semiconductor device |
US20220344516A1 (en) * | 2021-04-23 | 2022-10-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low ge isolated epitaxial layer growth over nano-sheet architecture design for rp reduction |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10115807B2 (en) * | 2015-11-18 | 2018-10-30 | Globalfoundries Inc. | Method, apparatus and system for improved performance using tall fins in finFET devices |
US10410931B2 (en) * | 2017-01-09 | 2019-09-10 | Samsung Electronics Co., Ltd. | Fabricating method of nanosheet transistor spacer including inner spacer |
US9847391B1 (en) * | 2017-04-05 | 2017-12-19 | Globalfoundries Inc. | Stacked nanosheet field-effect transistor with diode isolation |
US10332965B2 (en) | 2017-05-08 | 2019-06-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of fabricating the same |
US10014390B1 (en) * | 2017-10-10 | 2018-07-03 | Globalfoundries Inc. | Inner spacer formation for nanosheet field-effect transistors with tall suspensions |
US10553495B2 (en) * | 2017-10-19 | 2020-02-04 | International Business Machines Corporation | Nanosheet transistors with different gate dielectrics and workfunction metals |
US10685887B2 (en) * | 2017-12-04 | 2020-06-16 | Tokyo Electron Limited | Method for incorporating multiple channel materials in a complimentary field effective transistor (CFET) device |
US10600889B2 (en) | 2017-12-22 | 2020-03-24 | International Business Machines Corporation | Nanosheet transistors with thin inner spacers and tight pitch gate |
US10727320B2 (en) | 2017-12-29 | 2020-07-28 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method of manufacturing at least one field effect transistor having epitaxially grown electrodes |
US10170638B1 (en) * | 2018-01-23 | 2019-01-01 | International Business Machines Corporation | Nanosheet substrate isolated source/drain epitaxy by dual bottom spacer |
US10192867B1 (en) * | 2018-02-05 | 2019-01-29 | Globalfoundries Inc. | Complementary FETs with wrap around contacts and method of forming same |
US10566445B2 (en) | 2018-04-03 | 2020-02-18 | International Business Machines Corporation | Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates |
US10971585B2 (en) | 2018-05-03 | 2021-04-06 | International Business Machines Corporation | Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between adjacent gates |
CN110767549B (en) * | 2018-07-26 | 2023-05-16 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
US11031502B2 (en) | 2019-01-08 | 2021-06-08 | Samsung Electronics Co., Ltd. | Semiconductor devices |
US11239363B2 (en) | 2019-01-08 | 2022-02-01 | Samsung Electronics Co., Ltd. | Semiconductor devices |
US10665669B1 (en) | 2019-02-26 | 2020-05-26 | Globalfoundries Inc. | Insulative structure with diffusion break integral with isolation layer and methods to form same |
KR20200142765A (en) | 2019-06-13 | 2020-12-23 | 삼성전자주식회사 | Semiconductor device |
US11295983B2 (en) | 2020-05-27 | 2022-04-05 | International Business Machines Corporation | Transistor having source or drain formation assistance regions with improved bottom isolation |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6744094B2 (en) * | 2001-08-24 | 2004-06-01 | Micron Technology Inc. | Floating gate transistor with horizontal gate layers stacked next to vertical body |
US7705345B2 (en) * | 2004-01-07 | 2010-04-27 | International Business Machines Corporation | High performance strained silicon FinFETs device and method for forming same |
US7098477B2 (en) * | 2004-04-23 | 2006-08-29 | International Business Machines Corporation | Structure and method of manufacturing a finFET device having stacked fins |
US8030709B2 (en) * | 2007-12-12 | 2011-10-04 | International Business Machines Corporation | Metal gate stack and semiconductor gate stack for CMOS devices |
DE112011105979B4 (en) * | 2011-12-20 | 2022-09-15 | Intel Corporation | Semiconductor device with isolated semiconductor body parts and manufacturing method |
US8846490B1 (en) * | 2013-03-12 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a FinFET device |
US8969149B2 (en) * | 2013-05-14 | 2015-03-03 | International Business Machines Corporation | Stacked semiconductor nanowires with tunnel spacers |
KR102050779B1 (en) * | 2013-06-13 | 2019-12-02 | 삼성전자 주식회사 | Semiconductor device and method for fabricating the same |
US9190466B2 (en) * | 2013-12-27 | 2015-11-17 | International Business Machines Corporation | Independent gate vertical FinFET structure |
US10199502B2 (en) * | 2014-08-15 | 2019-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure of S/D contact and method of making same |
CN105826257B (en) * | 2015-01-06 | 2019-03-12 | 中芯国际集成电路制造(上海)有限公司 | Fin formula field effect transistor and forming method thereof |
US9882026B2 (en) * | 2015-01-13 | 2018-01-30 | Tokyo Electron Limited | Method for forming a nanowire structure |
US9287135B1 (en) * | 2015-05-26 | 2016-03-15 | International Business Machines Corporation | Sidewall image transfer process for fin patterning |
US9754941B2 (en) * | 2015-06-03 | 2017-09-05 | Globalfoundries Inc. | Method and structure to form tensile strained SiGe fins and compressive strained SiGe fins on a same substrate |
US10068920B2 (en) * | 2016-04-14 | 2018-09-04 | Globalfoundries Inc. | Silicon germanium fins on insulator formed by lateral recrystallization |
-
2016
- 2016-02-29 US US15/056,966 patent/US9748335B1/en active Active
-
2017
- 2017-07-18 US US15/652,873 patent/US10249710B2/en active Active
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10600641B2 (en) * | 2016-07-29 | 2020-03-24 | Applied Materials, Inc. | Silicon germanium selective oxidation process |
US10032867B1 (en) * | 2017-03-07 | 2018-07-24 | International Business Machines Corporation | Forming bottom isolation layer for nanosheet technology |
US20180261670A1 (en) * | 2017-03-07 | 2018-09-13 | International Business Machines Corporation | Forming bottom isolation layer for nanosheet technology |
US10361269B2 (en) * | 2017-03-07 | 2019-07-23 | International Business Machines Corporation | Forming bottom isolation layer for nanosheet technology |
US10269983B2 (en) * | 2017-05-09 | 2019-04-23 | Globalfoundries Inc. | Stacked nanosheet field-effect transistor with air gap spacers |
US20220052187A1 (en) * | 2017-09-13 | 2022-02-17 | Samsung Electronics Co., Ltd. | Semiconductor device |
US10418449B2 (en) * | 2018-01-10 | 2019-09-17 | Globalfoundries Inc. | Circuits based on complementary field-effect transistors |
US11056574B2 (en) | 2018-11-27 | 2021-07-06 | Imec Vzw | Stacked semiconductor device and method of forming same |
US11107812B2 (en) | 2018-11-27 | 2021-08-31 | Imec Vzw | Method of fabricating stacked semiconductor device |
US20220344516A1 (en) * | 2021-04-23 | 2022-10-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low ge isolated epitaxial layer growth over nano-sheet architecture design for rp reduction |
Also Published As
Publication number | Publication date |
---|---|
US9748335B1 (en) | 2017-08-29 |
US10249710B2 (en) | 2019-04-02 |
US20170317169A1 (en) | 2017-11-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10249710B2 (en) | Methods, apparatus, and system for improved nanowire/nanosheet spacers | |
US11201152B2 (en) | Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor | |
US9589848B2 (en) | FinFET structures having silicon germanium and silicon channels | |
US9799748B1 (en) | Method of forming inner spacers on a nano-sheet/wire device | |
US10103264B2 (en) | Channel strain control for nonplanar compound semiconductor devices | |
US10014389B2 (en) | Methods of forming IC products comprising a nano-sheet device and a transistor device having first and second replacement gate structures | |
US8703557B1 (en) | Methods of removing dummy fin structures when forming finFET devices | |
US20170047432A1 (en) | Integrated Circuit Structure with Substrate Isolation and Un-Doped Channel | |
US9786502B2 (en) | Method for forming fin structures for non-planar semiconductor device | |
US20150333145A1 (en) | High density finfet devices with unmerged fins | |
US10727345B2 (en) | Silicon germanium fin immune to epitaxy defect | |
US10461173B1 (en) | Methods, apparatus, and manufacturing system for forming source and drain regions in a vertical field effect transistor | |
CN106910713B (en) | Semiconductor device and method for manufacturing the same | |
US9793378B2 (en) | Fin field effect transistor device with reduced overlap capacitance and enhanced mechanical stability | |
US9312180B2 (en) | Method for forming semiconductor structure | |
US10644156B2 (en) | Methods, apparatus, and system for reducing gate cut gouging and/or gate height loss in semiconductor devices | |
US20130181301A1 (en) | Method for manufacturing a field-effect semiconductor device following a replacement gate process | |
US9236312B2 (en) | Preventing EPI damage for cap nitride strip scheme in a Fin-shaped field effect transistor (FinFET) device | |
US9754938B1 (en) | Semiconductor device and method of fabricating the same | |
US20170309623A1 (en) | Method, apparatus, and system for increasing drive current of finfet device | |
US9324618B1 (en) | Methods of forming replacement fins for a FinFET device | |
US9536990B2 (en) | Methods of forming replacement fins for a FinFET device using a targeted thickness for the patterned fin etch mask | |
US20170133406A1 (en) | Method, apparatus, and system for stacked cmos logic circuits on fins | |
US20180033789A1 (en) | Method, apparatus, and system for reducing dopant concentrations in channel regions of finfet devices | |
US9590040B2 (en) | Methods of forming fins for a FinFET device by forming and replacing sacrificial fin structures with alternative materials |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BENTLEY, STEVEN;NAYAK, DEEPAK;SIGNING DATES FROM 20160219 TO 20160221;REEL/FRAME:037859/0984 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001 Effective date: 20181127 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:054633/0001 Effective date: 20201022 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001 Effective date: 20201117 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |