US20170244433A1 - Broadband digital transmitter using pi/4 phase offset local oscillator (lo) signals - Google Patents
Broadband digital transmitter using pi/4 phase offset local oscillator (lo) signals Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
Definitions
- the present disclosure relates generally to digital power amplification and transmission.
- FIG. 1 illustrates an example analog Cartesian transmitter.
- FIG. 2 illustrates an example hybrid polar transmitter.
- FIG. 3 illustrates an example digital Cartesian transmitter.
- FIG. 4 illustrates example local oscillator (LO) signals used in digital Cartesian transmitters.
- LO local oscillator
- FIG. 5 illustrates an example digital transmitter using ⁇ /4 phase offset LO signals.
- FIG. 6 illustrates an example decomposition of a phasor into a phase offset component and a non-phase offset component.
- FIG. 7 illustrates example 8-phase LO signals.
- FIG. 8 illustrates an example vector decomposer circuit.
- FIG. 9 illustrates an example phase selector circuit.
- FIG. 10 illustrates an example digital transmitter using it/N phase offset LO signals.
- FIG. 1 illustrates an example analog Cartesian transmitter 100 .
- Example analog Cartesian transmitter 100 is provided for the purpose of illustration only.
- transmitter 100 includes digital-to-analog converters (DACs) 102 a - b , low pass filters (LPFs) 104 a - b , mixers 106 a - b , a combiner 108 , a power amplifier (PA) driver 110 , and a PA 112 .
- DACs digital-to-analog converters
- LPFs low pass filters
- PA power amplifier
- Transmitter 100 is configured to receive digital baseband in-phase (I) and quadrature (Q) signals 116 a and 116 b via DACs 102 a and 102 b respectively.
- DACs 102 a and 102 b convert digital baseband I and Q signals 116 a and 116 b into analog baseband I and Q signals 118 a and 118 b respectively.
- LPFs 104 a and 104 b filter respectively analog baseband I and Q signals 118 a and 118 b to generate filtered analog signals 120 a and 120 b.
- Filtered analog signals 120 a and 120 b are then mixed respectively in mixers 106 a and 106 b .
- signal 120 a is mixed with a first local oscillator (LO) signal 122 to generate a first frequency up-converted signal 126 a
- signal 120 b is mixed with a second LO signal 124 to generate a second frequency up-converted signal 126 b
- LO signals 122 and 124 share the same 90 degrees phase offset relationship as I and Q signals 116 a and 116 b .
- LO signal 122 may include a cos(cot) wave and LO signal 124 may include a sin( ⁇ t) wave.
- Signals 126 a and 126 b are then combined by combiner 108 to generate a signal 128 .
- signal 128 is amplified by PA driver 110 to generate a signal 130 .
- PA 112 acts on signal 130 to generate an amplified output signal 132 .
- Output signal 132 is forwarded to an antenna 114 for transmission.
- DACs 102 a - b , LPFs 104 a - b , mixers 106 a - b , combiner 108 , PA driver 110 , and PA 112 are all implemented using analog circuitry.
- transmitter 100 has several drawbacks, including higher power consumption and greater chip area.
- Transmitter 100 also may not benefit as much from technology process scale down since analog blocks are typically more difficult to shrink than digital blocks.
- the analog circuitry may have difficulty accommodating higher bandwidth waveforms, e.g., greater than 100 MHz.
- FIG. 2 illustrates an example hybrid polar transmitter 200 .
- Example hybrid polar transmitter 200 is provided for the purpose of illustration only.
- transmitter 200 includes a Field Programmable Gate Array (FPGA) circuit 202 , a phase modulator 204 , and a PA 206 .
- Phase modulator 204 includes DACs 212 a - b , mixers 214 a - b , and a combiner 216 .
- FPGA 202 is a digital circuit
- PA 206 is a mixed signal circuit (like a DAC)
- phase modulator 204 is implemented using analog circuitry.
- FPGA 202 provides digital I and Q phase signals 210 a and 210 b to phase modulator 204 and an envelope signal 208 to PA 206 .
- FPGA 202 performs a Cartesian to Polar transformation of Cartesian I and Q signals to generate I and Q phase signals 210 a - b and envelope signal 208 .
- Phase modulator 204 processes I and Q phase signals 210 a and 210 b to produce a phase signal 218 , which is provided to PA 206 .
- DACs 212 a - b convert respectively digital I and Q phase signals 210 a and 210 b to generate analog I and Q phase signals 222 a and 222 b .
- Analog I and Q phase signals 222 a and 222 b are mixed with respective (90 degrees phase offset) LO signals in mixers 214 a and 214 b , respectively, to generate frequency up-converted analog I and Q phase signals 224 a and 224 b .
- Signals 224 a and 224 b are combined using combiner 216 to generate phase signal 218 .
- PA 206 processes envelope signal 208 and phase signal 218 to generate a radio frequency (RF) output signal 220 .
- PA 206 is a digital PA (DPA) that includes a plurality of RF DAC cells (not shown). Each of the plurality of RF DAC cells is configured to receive a digital version of phase signal 218 and to produce an analog output signal.
- Envelope signal 208 determines how many of the plurality of RF DAC cells are turned on at each instant of time, thereby amplitude modulating phase signal 218 .
- transmitter 200 Despite implementing some circuitry digitally, transmitter 200 still requires a significant amount of analog circuitry. In addition, because Cartesian to Polar transformation increases signal bandwidth, higher bandwidth waveforms may be difficult to achieve in transmitter 200 . In addition, transmitter 200 requires precise delay matching between the envelope signal and the phase signal. Significant transmission performance degradation can result due to delay mismatch between the envelope signal and the phase signal.
- FIG. 3 illustrates an example digital Cartesian transmitter 300 .
- Example digital Cartesian transmitter 300 is provided for the purpose of illustration only.
- transmitter 300 includes a DPA 302 and phase multiplexers 318 a - b .
- DPA 302 may include an in-phase DPA (I-DPA) 304 a , a quadrature DPA (Q-DPA 304 b ), and a combiner 306 .
- DPA 302 may be connected to an antenna 328 .
- Transmitter 300 may be implemented entirely as digitized circuitry. As such, significant power consumption and area savings can be realized using transmitter 300 .
- a baseband processor (not shown) generates an I envelope signal 310 a and a Sign_I signal 312 a from a baseband I signal, and a Q envelope signal 310 b and a Sign_Q signal 312 b from a baseband Q signal.
- Sign_I signal 312 a and Sign_Q signal 312 b represent the respective polarities of the baseband I and Q signals.
- I envelope signal 310 a and Q envelope signal 310 b are provided to DPA 302 , where the envelope signals represent the respective envelopes of the baseband I and Q signals.
- Phase multiplexers 318 a and 318 b receive respectively (90 degrees phase offset) LO signals 314 p - n and 316 p - n .
- LO signals 314 p - n and 316 p - n are each differential signals (e.g., each composed of two 180 degrees phase shifted square waves).
- Phase multiplexer 318 a outputs differential LO signal 320 p - n at the control of Sign_I signal 312 a .
- Sign_I signal 312 a is a logic high
- phase multiplexer 318 a outputs differential input component 314 p as differential output component 320 p and differential input component 314 n as differential output component 320 n .
- phase multiplexer 318 a outputs differential input component 314 p as differential output component 320 n and differential input component 314 n as differential output component 320 p .
- the reversal of differential input components 314 p and 314 n when Sign_I signal 312 a is low accounts for the negative polarity of the baseband I signal.
- Phase multiplexer 318 b acts in a similar manner on differential LO signal 316 p - n , at the control of Sign_Q signal 312 b , to generate differential LO signal 322 p - n .
- Phase multiplexers 318 a and 318 b provide differential LO signals 320 p - n and 322 p - n to DPA 302 .
- I-DPA 304 a processes I envelope signal 310 a and LO signal 320 p - n to generate an output signal 324
- Q-DPA 304 b processes Q envelope signal 310 b and LO signal 322 p - n to generate an output signal 326
- Combiner 306 combines output signals 324 and 326 to generate an output signal 308 of transmitter 300 .
- Output signal 308 is forwarded to antenna 328 for transmission.
- I-DPA 304 a and Q-DPA 304 b may each include a PA such as PA 206 described above with reference to FIG. 2 .
- each of I-DPA 304 a and Q-DPA 304 b includes a differential PA having a positive PA branch and a negative PA branch.
- the positive PA branch turns on when the positive component (e.g., 320 p or 322 p ) of the LO signal is a logic high and turns off when the positive component of the LO signal is a logic low.
- the negative component (e.g., 320 n or 322 n ) of the LO signal controls the negative PA branch similarly. Because the positive and negative components of the LO signal are differential (negatives of each other), only one of the positive and negative PA branches is on or off at any time.
- I-DPA 304 a and Q-DPA 304 b are not supposed to turn on at the same time.
- 90 degrees phase offset 50% duty cycle LO signals may be inefficient to use in digital transmitter 300 as they can result in 25% overlap in a given duty cycle (when both I and Q are logic high), which reduces significantly the power efficiency and linearity of transmitter 300 .
- Reducing the duty cycle to 25% eliminates any potential duty cycle overlap between I-DPA 304 a and Q-DPA 304 b .
- the asymmetric 25% duty cycle results in a strong second harmonic frequency component in the LO signals (when either I or Q is a logic high), which reduces significantly the power efficiency and linearity of transmitter 300 .
- a solution includes reducing the duty cycle overlap by utilizing a greater number of symmetric LO signals with a smaller phase offset between them. For example, instead of using four 90 degrees phase offset LO signals as shown in FIG. 4 , eight 45 degrees phase offset LO signals (or more than eight with even lower phase offset) may be used. This reduces the potential duty cycle overlap by at least 50%. At the same time, high power efficiency can be ensured by the use of symmetric LO signals.
- FIG. 5 illustrates an example digital transmitter 500 according to an embodiment of the present disclosure.
- Example digital transmitter 500 is provided for the purpose of illustration only.
- digital transmitter 500 includes a ⁇ /4 vector decomposer circuit 502 , a phase selector circuit 504 , and a DPA 506 .
- Digital transmitter 500 may be connected to an antenna 508 .
- ⁇ /4 vector decomposer circuit 502 is configured to receive baseband in-phase (I) and quadrature (Q) signals 516 a and 516 b .
- I and Q signals 516 a and 516 b are generated by a baseband processor (not shown) based on an information modulated complex waveform containing desired information to be transmitted.
- I and Q signals 516 a and 516 b include a representation of an instantaneous magnitude and an instantaneous phase of the complex waveform.
- ⁇ /4 vector decomposer circuit 502 is configured to decompose I and Q signals 516 a and 516 b into a non-offset envelope signal 518 and an offset envelope signal 520 .
- non-offset envelope signal 518 corresponds to a non-offset component of the instantaneous magnitude of the complex waveform, obtained by projecting a phasor representation of the complex waveform onto a selected non-offset axis (e.g., 0, 90, 180, and 270 degrees).
- Offset envelope signal 520 corresponds to an offset component of the instantaneous magnitude of the complex waveform, obtained by projecting the phasor representation of the complex waveform onto a selected offset axis.
- the selected offset axis and non-offset axis depend on the magnitudes and polarities (signs) of I and Q signals 516 a and 516 b.
- FIG. 6 illustrates an example decomposition 600 of a phasor 606 into an offset component 610 and a non-offset component 608 according to an embodiment.
- Phasor 606 may represent a time instant of a complex waveform having a time-varying magnitude and phase.
- the magnitude of phasor 606 represents the instantaneous magnitude of the complex waveform
- the phase angle (q) of phasor 606 relative to a reference axis e.g., positive x axis
- the vector space is divided into eight octants by four non-offset axes 602 a , 602 b , 602 c , and 602 d (e.g., 0, 90, 180, and 270 degrees, though other values may be used) and four offset axes 604 a , 604 b , 604 c , and 604 d (e.g., 45, 135, 225, and 315 degrees, though other values may be used).
- the vector space may be divided into more than eight octants (e.g., 16, 32, or more angular portions).
- offset component 610 is obtained by projecting phasor 606 onto offset axis 604 a (45 degrees axis). Offset component 610 may correspond to offset envelope signal 520 , for example.
- Non-offset component 608 is obtained by projecting phasor 606 onto non-offset axis 602 a (0 degrees axis). Non-offset component 608 may correspond to non-offset envelope signal 518 , for example.
- the offset axis and the non-offset axis used depend on the phase angle (q) of phasor 606 (or the octant of the unit circle within which phasor 606 falls).
- ⁇ /4 vector decomposer circuit 502 provides non-offset envelope signal 518 and offset envelope signal 520 to DPA 506 . Based on I and Q signals 516 a and 516 b, ⁇ / 4 vector decomposer circuit 502 also generates a phase control signal 522 . ⁇ /4 vector decomposer circuit 502 provides phase control signal 522 to phase selector circuit 504 . As discussed further below with reference to FIG. 8 , phase control signal 522 may include a plurality of control signals.
- Phase selector circuit 504 is configured to receive a plurality of phase offset local oscillator (LO) signals 524 a - h .
- LO signals 524 a - h provide 8-phase ⁇ /4 offset LO signals.
- LO signals 524 a - h may correspond to LO signals that are shifted by 0, 45, 90, 135, 180, 225, 270, and 315 degrees respectively relative to a reference LO signal.
- LO signals 524 a - h may be as shown by example 700 in FIG. 7 .
- a first set of LO signals 524 a - h represent non-offset LO signals (e.g., LO signals shifted by 0, 90, 180, and 270 degrees) and a second set of LO signals 524 a - h represent offset LO signals (e.g., LO signals shifted by 45, 135, 225, and 315 degrees).
- phase selector circuit 504 selects two of the first set of LO signals as non-offset LO output signals 526 a and 526 b and two of the second set of LO signals as offset LO output signals 528 a and 528 b.
- Output signals 526 a , 526 b , 528 a , and 528 b of phase selector circuit 504 are provided to DPA 506 .
- DPA 506 is configured to process non-offset envelope signal 518 , offset envelope signal 520 , non-offset LO signals 526 a - b , and offset LO signals 528 a - b to generate an output signal 534 of digital transmitter 500 .
- DPA 506 includes a non-offset DPA circuit 510 , an offset DPA circuit 512 , and a combiner circuit 514 .
- Non-offset DPA circuit 510 is configured to process non-offset envelope signal 518 and non-offset LO signals 526 a - b to generate a first signal 530 .
- Offset DPA circuit 512 is configured to process offset envelope signal 520 and offset LO signals 528 a - b to generate a second signal 532 .
- Combiner circuit 514 is configured to combine first signal 530 and second signal 532 to generate output signal 534 of digital transmitter 500 .
- Output signal 534 is forwarded to antenna 508 for transmission.
- FIG. 8 illustrates an example vector decomposer circuit 800 according to an embodiment.
- Example vector decomposer circuit 800 is provided for the purpose of illustration only.
- Example vector decomposer circuit 800 may be an embodiment of ⁇ /4 vector decomposer circuit 502 described above with reference to FIG. 5 .
- vector decomposer circuit 800 may include a plurality of circuits, including circuits 802 a - b , 808 , 810 , 812 , 814 , 818 , 822 , and 826 .
- Vector decomposer circuit 800 is configured to receive baseband I and Q signals 516 a and 516 b via envelope/sign extraction circuits 802 a and 802 b respectively.
- Circuit 802 a is configured to generate an I envelope signal 804 a and a Sign_I signal 806 a based on baseband I signal 516 a .
- Circuit 802 b is configured to generate a Q envelope signal 804 b and a Sign_Q signal 806 b based on baseband Q signal 516 b .
- I envelope signal 804 a and Q envelope signal 804 b represent respectively the magnitudes of baseband I and Q signals 516 a and 516 b .
- Sign_I signal 806 a and Sign_Q signal 806 b represent respectively the polarities of baseband I and Q signals 516 a and 516 b.
- Circuitry 808 , 810 , 812 , and 814 are configured to generate offset envelope signal 520 and non-offset envelope signal 518 from I envelope signal 804 a and Q envelope signal 804 b .
- comparator circuit 808 is configured to determine the smaller signal between I envelope signal 804 a and Q envelope signal 804 b and to provide the result to circuit 810 .
- Multiplier circuit 810 is configured to multiply the result by the square root of two to generate offset envelope signal 520 .
- Subtractor circuit 812 is configured to generate a difference signal between I envelope signal 804 a and Q envelope signal 804 b and to provide the difference signal to circuitry 814 .
- Envelope/sign extraction circuit 814 is configured to extract the envelope and signal of the difference signal to generate non-offset envelope signal 518 and a control signal 816 (Psel_noff_IQ).
- Circuitry 818 , 822 , and 826 are configured to generate additional control signals 820 , 824 , and 828 based on Sign_I signal 806 a and Sign_Q signal 806 b .
- circuitry 818 is configured to select between Sign_I signal 806 a and Sign_Q signal 806 b , responsive to control signal 816 , to generate control signal 820 (Psel_noff_PN).
- circuitry 818 outputs, as control signal 820 , Sign_I signal 806 a when control signal 816 is a logic high and Sign_Q signal 806 b when control signal 816 is a logic low.
- circuitry 818 may include a 2:1 multiplexer.
- Circuitry 822 is configured to implement an XNOR logic function on Sign_I signal 806 a and Sign_Q signal 806 b to generate control signal 824 (Psel_off IQ).
- Circuitry 826 is configured to select between Sign_I signal 806 a and Sign_Q signal 806 b , responsive to control signal 824 , to generate control signal 828 (Psel_off_PN).
- circuitry 826 outputs, as control signal 828 , Sign_I signal 806 a when control signal 824 is a logic high and Sign_Q signal 806 b when control signal 824 is a logic low.
- circuitry 826 may include a 2:1 multiplexer.
- control signals 816 , 820 , 824 , and 828 are provided as control signal 522 to phase selector circuit 504 .
- control signals 816 , 820 , 824 , and 828 enable phase selector circuit 504 to select appropriate LO signals from phase offset LO signals 524 a - h depending on baseband I and Q signals 516 a and 516 b .
- the selected LO signals when mixed with non-offset envelope signal 518 and offset envelope signal 520 within DPA 506 , result in a frequency modulated signal that includes the complex waveform represented by baseband I and Q signals 516 a and 516 b.
- FIG. 9 illustrates an example phase selector circuit 900 according to an embodiment.
- Example phase selector circuit 900 is provided for the purpose of illustration only.
- Example phase selector circuit 900 may be an embodiment of phase selector circuit 504 described above with reference to FIG. 5 .
- phase selector circuit 900 may include multiplexers 902 a - d and coupling circuits 906 a - b.
- Phase selector circuit 900 is configured to receive phase offset LO signals 524 a - h and phase control signals 816 , 820 , 824 , and 828 .
- LO signals 524 a , 524 c , 524 e , and 524 g which represent non-offset LO signals (not offset in phase relative to traditional axes of a unit circle), are received by multiplexers 902 a - b
- LO signals 524 b , 524 d , 524 f , and 524 h which represent offset LO signals are received by multiplexers 902 c - d.
- multiplexers 902 a and 902 b select first and second non-offset LO signals 904 a and 904 b from LO signals 524 a , 524 c , 524 e , and 524 g .
- LO signals 904 a and 904 b correspond to LO signals 524 a and 524 e respectively (0 and 180 degrees).
- LO signals 904 a and 904 b correspond to LO signals 524 c and 524 g respectively (90 and 270 degrees).
- Multiplexers 902 c and 902 d select first and second offset LO signals 904 c and 904 d from LO signals 524 b , 524 d , 524 f , and 524 g based on control signal 824 .
- control signal 824 is a logic high
- LO signals 904 c and 904 d correspond to LO signals 524 b and 524 f respectively (45 and 225 degrees).
- control signal 824 is a logic low
- LO signals 904 c and 904 d correspond to LO signals 524 d and 524 h respectively (135 and 315 degrees).
- Coupling circuits 906 a - b are configured to couple the selected first and second non-offset LO signals 904 a - b and the first and second offset LO signals 904 c - d to output terminals of phase selector circuit 900 to generate non-offset LO output signals 526 a - b and offset LO output signals 528 a - b.
- coupling circuit 906 a is configured to receive non-offset LO signals 904 a - b and to couple non-offset LO signals 904 a - b to non-offset LO output signals 526 a - b responsive to control signal 820 . In an embodiment, when control signal 820 is at a logic high level, coupling circuit 906 a couples non-offset LO signal 904 a to non-offset LO output signal 526 a and non-offset LO signal 904 b to non-offset LO output signal 526 b.
- coupling circuit 906 a swaps non-offset LO signals 904 a and 904 b such that non-offset LO signal 904 a is coupled to non-offset LO output signal 526 a and non-offset LO signal 904 b is coupled to non-offset LO output signal 526 b .
- the swapping of non-offset LO signals 904 a and 904 b results in a 180 degrees phase inversion (or otherwise a polarity reversal) in the signal resulting from mixing non-offset LO output signals 526 a - b with non-offset envelope signal 518 .
- non-offset LO signals 904 a and 904 b are swapped when I envelope signal 804 a is lower than Q envelope signal 804 b and Sign_Q signal 806 b is negative, or when I envelope signal 804 a is greater than Q envelope signal 804 b and Sign_I signal 806 a is negative.
- Coupling circuit 906 b is configured to receive offset LO signals 904 c - d and to couple offset LO signals 904 c - d to offset LO output signals 528 a - b responsive to control signal 828 . In an embodiment, when control signal 828 is at a logic high level, coupling circuit 906 b couples offset LO signal 904 c to offset LO output signal 528 a and offset LO signal 904 d to offset LO output signal 528 b.
- coupling circuit 906 b swaps offset LO signals 904 c and 904 d such that offset LO signal 904 c is coupled to offset LO output signal 528 a and offset LO signal 904 d is coupled to offset LO output signal 528 b .
- the swapping of offset LO signals 904 c and 904 d results in a 180 degrees phase inversion (or otherwise a polarity reversal) in the signal resulting from mixing offset LO output signals 528 a - b with offset envelope signal 520 .
- offset LO signals 904 c and 904 d are swapped whenever Sign_Q signal 806 b is negative.
- example digital transmitter 1000 includes a ⁇ /N vector decomposer circuit 1002 that generates a non-offset envelope signal 1020 and an offset envelope signal 1022 based on a ⁇ /N vector decomposition of baseband I and Q signals 516 a and 516 b .
- ⁇ /N vector decomposer circuit 1002 also generates a phase control signal 1012 for a phase selector circuit 1004 .
- Phase selector circuit 1004 receives 2 ⁇ N ⁇ /N phase offset LO signals 1014 and outputs first and second non-offset LO signals 1016 a - b and first and second offset LO signals 1018 a - b responsive to phase control signal 1012 .
- DPA 1006 includes a non-offset DPA 1008 and a ⁇ /N offset DPA 1010 .
- Non-offset DPA 1008 processes non-offset envelope signal 1020 and non-offset LO signals 1016 a - b to generate output signal 1026 .
- ⁇ /N offset DPA 1010 processes offset envelope signal 1022 and offset LO signals 1018 a - b to generate output signal 1028 .
- Output signals 1026 and 1028 of non-offset DPA 1008 and ⁇ /N offset DPA 1010 are combined using combiner 514 to generate an output signal 1024 of digital transmitter 1000 .
- processor circuitry shall be understood to include one or more: circuit(s), processor(s), or a combination thereof.
- a circuit can include an analog circuit, a digital circuit, state machine logic, other structural electronic hardware, or a combination thereof.
- a processor can include a microprocessor, a digital signal processor (DSP), or other hardware processor.
- DSP digital signal processor
- the processor can be “hard-coded” with instructions to perform corresponding function(s) according to embodiments described herein.
- the processor can access an internal or external memory to retrieve instructions stored in the memory, which when executed by the processor, perform the corresponding function(s) associated with the processor.
Abstract
Description
- This application claims benefit of U.S. Provisional Application No. 62/299,324, filed Feb. 24, 2016, which is incorporated herein by reference in its entirety.
- The present disclosure relates generally to digital power amplification and transmission.
- Power saving and silicon area constraints have made component digitization a key goal in integrated circuits. In the area of radio frequency (RF) transmitters, conventional architectures, while becoming more digitized, continue to suffer from power efficiency degradation and reduced bandwidth.
- The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.
-
FIG. 1 illustrates an example analog Cartesian transmitter. -
FIG. 2 illustrates an example hybrid polar transmitter. -
FIG. 3 illustrates an example digital Cartesian transmitter. -
FIG. 4 illustrates example local oscillator (LO) signals used in digital Cartesian transmitters. -
FIG. 5 illustrates an example digital transmitter using π/4 phase offset LO signals. -
FIG. 6 illustrates an example decomposition of a phasor into a phase offset component and a non-phase offset component. -
FIG. 7 illustrates example 8-phase LO signals. -
FIG. 8 illustrates an example vector decomposer circuit. -
FIG. 9 illustrates an example phase selector circuit. -
FIG. 10 illustrates an example digital transmitter using it/N phase offset LO signals. - The present disclosure will be described with reference to the accompanying drawings. Generally, the drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.
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FIG. 1 illustrates an example analog Cartesiantransmitter 100. Example analog Cartesiantransmitter 100 is provided for the purpose of illustration only. As shown inFIG. 1 ,transmitter 100 includes digital-to-analog converters (DACs) 102 a-b, low pass filters (LPFs) 104 a-b, mixers 106 a-b, a combiner 108, a power amplifier (PA)driver 110, and aPA 112. -
Transmitter 100 is configured to receive digital baseband in-phase (I) and quadrature (Q) signals 116 a and 116 b viaDACs DACs Q signals Q signals LPFs Q signals analog signals - Filtered
analog signals mixers signal 120 a is mixed with a first local oscillator (LO)signal 122 to generate a first frequency up-convertedsignal 126 a, andsignal 120 b is mixed with asecond LO signal 124 to generate a second frequency up-convertedsignal 126 b. LO signals 122 and 124 share the same 90 degrees phase offset relationship as I and Q signals 116 a and 116 b. For example,LO signal 122 may include a cos(cot) wave andLO signal 124 may include a sin(ωt) wave. -
Signals signal 128. Optionally,signal 128 is amplified byPA driver 110 to generate asignal 130. PA 112 acts onsignal 130 to generate an amplifiedoutput signal 132.Output signal 132 is forwarded to anantenna 114 for transmission. - Typically, DACs 102 a-b, LPFs 104 a-b, mixers 106 a-b, combiner 108,
PA driver 110, andPA 112 are all implemented using analog circuitry. As a result,transmitter 100 has several drawbacks, including higher power consumption and greater chip area.Transmitter 100 also may not benefit as much from technology process scale down since analog blocks are typically more difficult to shrink than digital blocks. In addition, the analog circuitry may have difficulty accommodating higher bandwidth waveforms, e.g., greater than 100 MHz. -
FIG. 2 illustrates an example hybridpolar transmitter 200. Example hybridpolar transmitter 200 is provided for the purpose of illustration only. As shown inFIG. 2 ,transmitter 200 includes a Field Programmable Gate Array (FPGA)circuit 202, aphase modulator 204, and aPA 206.Phase modulator 204 includes DACs 212 a-b, mixers 214 a-b, and acombiner 216. In an embodiment,FPGA 202 is a digital circuit,PA 206 is a mixed signal circuit (like a DAC), whilephase modulator 204 is implemented using analog circuitry. - FPGA 202 provides digital I and
Q phase signals phase modulator 204 and anenvelope signal 208 toPA 206. Typically,FPGA 202 performs a Cartesian to Polar transformation of Cartesian I and Q signals to generate I and Q phase signals 210 a-b andenvelope signal 208. -
Phase modulator 204 processes I and Q phase signals 210 a and 210 b to produce aphase signal 218, which is provided toPA 206. Specifically, DACs 212 a-b convert respectively digital I andQ phase signals Q phase signals Q phase signals mixers Q phase signals Signals phase signal 218. -
PA 206 processesenvelope signal 208 andphase signal 218 to generate a radio frequency (RF)output signal 220. In an embodiment,PA 206 is a digital PA (DPA) that includes a plurality of RF DAC cells (not shown). Each of the plurality of RF DAC cells is configured to receive a digital version ofphase signal 218 and to produce an analog output signal.Envelope signal 208 determines how many of the plurality of RF DAC cells are turned on at each instant of time, thereby amplitude modulatingphase signal 218. - Despite implementing some circuitry digitally,
transmitter 200 still requires a significant amount of analog circuitry. In addition, because Cartesian to Polar transformation increases signal bandwidth, higher bandwidth waveforms may be difficult to achieve intransmitter 200. In addition,transmitter 200 requires precise delay matching between the envelope signal and the phase signal. Significant transmission performance degradation can result due to delay mismatch between the envelope signal and the phase signal. -
FIG. 3 illustrates an example digital Cartesiantransmitter 300. Example digital Cartesiantransmitter 300 is provided for the purpose of illustration only. As shown inFIG. 3 ,transmitter 300 includes aDPA 302 and phase multiplexers 318 a-b. DPA 302 may include an in-phase DPA (I-DPA) 304 a, a quadrature DPA (Q-DPA 304 b), and acombiner 306. DPA 302 may be connected to anantenna 328.Transmitter 300 may be implemented entirely as digitized circuitry. As such, significant power consumption and area savings can be realized usingtransmitter 300. - A baseband processor (not shown) generates an I envelope signal 310 a and a
Sign_I signal 312 a from a baseband I signal, and aQ envelope signal 310 b and aSign_Q signal 312 b from a baseband Q signal. Sign_I signal 312 a and Sign_Q signal 312 b represent the respective polarities of the baseband I and Q signals. I envelope signal 310 a andQ envelope signal 310 b are provided toDPA 302, where the envelope signals represent the respective envelopes of the baseband I and Q signals. -
Phase multiplexers Phase multiplexer 318 a outputs differential LO signal 320 p-n at the control of Sign_I signal 312 a. Specifically, when Sign_I signal 312 a is a logic high,phase multiplexer 318 a outputsdifferential input component 314 p asdifferential output component 320 p anddifferential input component 314 n asdifferential output component 320 n. Otherwise, when Sign_I signal 312 a is a logic low,phase multiplexer 318 a outputsdifferential input component 314 p asdifferential output component 320 n anddifferential input component 314 n asdifferential output component 320 p. The reversal ofdifferential input components -
Phase multiplexer 318 b acts in a similar manner on differential LO signal 316 p-n, at the control ofSign_Q signal 312 b, to generate differential LO signal 322 p-n.Phase multiplexers DPA 302. - In an embodiment, I-
DPA 304 a processes I envelope signal 310 a and LO signal 320 p-n to generate anoutput signal 324, and Q-DPA 304 b processesQ envelope signal 310 b and LO signal 322 p-n to generate anoutput signal 326.Combiner 306 combines output signals 324 and 326 to generate anoutput signal 308 oftransmitter 300.Output signal 308 is forwarded toantenna 328 for transmission. - In an embodiment, I-
DPA 304 a and Q-DPA 304 b may each include a PA such asPA 206 described above with reference toFIG. 2 . In another embodiment, each of I-DPA 304 a and Q-DPA 304 b includes a differential PA having a positive PA branch and a negative PA branch. The positive PA branch turns on when the positive component (e.g., 320 p or 322 p) of the LO signal is a logic high and turns off when the positive component of the LO signal is a logic low. The negative component (e.g., 320 n or 322 n) of the LO signal controls the negative PA branch similarly. Because the positive and negative components of the LO signal are differential (negatives of each other), only one of the positive and negative PA branches is on or off at any time. - Because
combiner 306 combines output signals 324 and 326 directly (without isolation), I-DPA 304 a and Q-DPA 304 b are not supposed to turn on at the same time. This places constraints on the LO signals that may be used efficiently withtransmitter 300. For example, 90 degrees phase offset 50% duty cycle LO signals, as illustrated inFIG. 4 , may be inefficient to use indigital transmitter 300 as they can result in 25% overlap in a given duty cycle (when both I and Q are logic high), which reduces significantly the power efficiency and linearity oftransmitter 300. Reducing the duty cycle to 25% eliminates any potential duty cycle overlap between I-DPA 304 a and Q-DPA 304 b. But the asymmetric 25% duty cycle results in a strong second harmonic frequency component in the LO signals (when either I or Q is a logic high), which reduces significantly the power efficiency and linearity oftransmitter 300. - A solution, as further described below in
FIGS. 5-10 , includes reducing the duty cycle overlap by utilizing a greater number of symmetric LO signals with a smaller phase offset between them. For example, instead of using four 90 degrees phase offset LO signals as shown inFIG. 4 , eight 45 degrees phase offset LO signals (or more than eight with even lower phase offset) may be used. This reduces the potential duty cycle overlap by at least 50%. At the same time, high power efficiency can be ensured by the use of symmetric LO signals. -
FIG. 5 illustrates an exampledigital transmitter 500 according to an embodiment of the present disclosure. Exampledigital transmitter 500 is provided for the purpose of illustration only. As shown inFIG. 5 ,digital transmitter 500 includes a π/4vector decomposer circuit 502, aphase selector circuit 504, and aDPA 506.Digital transmitter 500 may be connected to anantenna 508. - π/4
vector decomposer circuit 502 is configured to receive baseband in-phase (I) and quadrature (Q) signals 516 a and 516 b. In an embodiment, I and Q signals 516 a and 516 b are generated by a baseband processor (not shown) based on an information modulated complex waveform containing desired information to be transmitted. I and Q signals 516 a and 516 b include a representation of an instantaneous magnitude and an instantaneous phase of the complex waveform. - π/4
vector decomposer circuit 502 is configured to decompose I and Q signals 516 a and 516 b into anon-offset envelope signal 518 and an offsetenvelope signal 520. In an embodiment,non-offset envelope signal 518 corresponds to a non-offset component of the instantaneous magnitude of the complex waveform, obtained by projecting a phasor representation of the complex waveform onto a selected non-offset axis (e.g., 0, 90, 180, and 270 degrees). Offsetenvelope signal 520 corresponds to an offset component of the instantaneous magnitude of the complex waveform, obtained by projecting the phasor representation of the complex waveform onto a selected offset axis. The selected offset axis and non-offset axis depend on the magnitudes and polarities (signs) of I and Q signals 516 a and 516 b. -
FIG. 6 illustrates anexample decomposition 600 of aphasor 606 into an offsetcomponent 610 and anon-offset component 608 according to an embodiment.Phasor 606 may represent a time instant of a complex waveform having a time-varying magnitude and phase. As such, the magnitude ofphasor 606 represents the instantaneous magnitude of the complex waveform, and the phase angle (q) ofphasor 606 relative to a reference axis (e.g., positive x axis) represents the instantaneous phase of the complex waveform. The vector space is divided into eight octants by fournon-offset axes axes - As shown in
FIG. 6 , offsetcomponent 610 is obtained by projectingphasor 606 onto offsetaxis 604 a (45 degrees axis). Offsetcomponent 610 may correspond to offsetenvelope signal 520, for example.Non-offset component 608 is obtained by projectingphasor 606 ontonon-offset axis 602 a (0 degrees axis).Non-offset component 608 may correspond tonon-offset envelope signal 518, for example. The offset axis and the non-offset axis used depend on the phase angle (q) of phasor 606 (or the octant of the unit circle within which phasor 606 falls). - Returning to
FIG. 5 , π/4vector decomposer circuit 502 providesnon-offset envelope signal 518 and offsetenvelope signal 520 toDPA 506. Based on I and Q signals 516 a and 516 b, π/4vector decomposer circuit 502 also generates aphase control signal 522. π/4vector decomposer circuit 502 providesphase control signal 522 tophase selector circuit 504. As discussed further below with reference toFIG. 8 ,phase control signal 522 may include a plurality of control signals. -
Phase selector circuit 504 is configured to receive a plurality of phase offset local oscillator (LO) signals 524 a-h. In an embodiment, LO signals 524 a-h provide 8-phase π/4 offset LO signals. For example, LO signals 524 a-h may correspond to LO signals that are shifted by 0, 45, 90, 135, 180, 225, 270, and 315 degrees respectively relative to a reference LO signal. In an embodiment, LO signals 524 a-h may be as shown by example 700 inFIG. 7 . - In an embodiment, a first set of LO signals 524 a-h represent non-offset LO signals (e.g., LO signals shifted by 0, 90, 180, and 270 degrees) and a second set of LO signals 524 a-h represent offset LO signals (e.g., LO signals shifted by 45, 135, 225, and 315 degrees). Based on
phase control signal 522,phase selector circuit 504 selects two of the first set of LO signals as non-offset LO output signals 526 a and 526 b and two of the second set of LO signals as offset LO output signals 528 a and 528 b. - Output signals 526 a, 526 b, 528 a, and 528 b of
phase selector circuit 504 are provided toDPA 506.DPA 506 is configured to processnon-offset envelope signal 518, offsetenvelope signal 520, non-offset LO signals 526 a-b, and offset LO signals 528 a-b to generate anoutput signal 534 ofdigital transmitter 500. In an embodiment,DPA 506 includes anon-offset DPA circuit 510, an offsetDPA circuit 512, and acombiner circuit 514.Non-offset DPA circuit 510 is configured to processnon-offset envelope signal 518 and non-offset LO signals 526 a-b to generate afirst signal 530. OffsetDPA circuit 512 is configured to process offsetenvelope signal 520 and offset LO signals 528 a-b to generate asecond signal 532.Combiner circuit 514 is configured to combinefirst signal 530 andsecond signal 532 to generate output signal 534 ofdigital transmitter 500.Output signal 534 is forwarded toantenna 508 for transmission. -
FIG. 8 illustrates an examplevector decomposer circuit 800 according to an embodiment. Examplevector decomposer circuit 800 is provided for the purpose of illustration only. Examplevector decomposer circuit 800 may be an embodiment of π/4vector decomposer circuit 502 described above with reference toFIG. 5 . As shown inFIG. 8 ,vector decomposer circuit 800 may include a plurality of circuits, including circuits 802 a-b, 808, 810, 812, 814, 818, 822, and 826. -
Vector decomposer circuit 800 is configured to receive baseband I and Q signals 516 a and 516 b via envelope/sign extraction circuits Circuit 802 a is configured to generate an I envelope signal 804 a and aSign_I signal 806 a based on baseband I signal 516 a.Circuit 802 b is configured to generate aQ envelope signal 804 b and aSign_Q signal 806 b based onbaseband Q signal 516 b. I envelope signal 804 a andQ envelope signal 804 b represent respectively the magnitudes of baseband I and Q signals 516 a and 516 b. Sign_I signal 806 a and Sign_Q signal 806 b represent respectively the polarities of baseband I and Q signals 516 a and 516 b. -
Circuitry envelope signal 520 andnon-offset envelope signal 518 from I envelope signal 804 a andQ envelope signal 804 b. Specifically,comparator circuit 808 is configured to determine the smaller signal between I envelope signal 804 a andQ envelope signal 804 b and to provide the result tocircuit 810.Multiplier circuit 810 is configured to multiply the result by the square root of two to generate offsetenvelope signal 520.Subtractor circuit 812 is configured to generate a difference signal between I envelope signal 804 a andQ envelope signal 804 b and to provide the difference signal tocircuitry 814. Envelope/sign extraction circuit 814 is configured to extract the envelope and signal of the difference signal to generatenon-offset envelope signal 518 and a control signal 816 (Psel_noff_IQ). -
Circuitry additional control signals circuitry 818 is configured to select between Sign_I signal 806 a and Sign_Q signal 806 b, responsive to controlsignal 816, to generate control signal 820 (Psel_noff_PN). In an embodiment,circuitry 818 outputs, ascontrol signal 820, Sign_I signal 806 a whencontrol signal 816 is a logic high and Sign_Q signal 806 b whencontrol signal 816 is a logic low. In an embodiment,circuitry 818 may include a 2:1 multiplexer. -
Circuitry 822 is configured to implement an XNOR logic function on Sign_I signal 806 a and Sign_Q signal 806 b to generate control signal 824 (Psel_off IQ).Circuitry 826 is configured to select between Sign_I signal 806 a and Sign_Q signal 806 b, responsive to controlsignal 824, to generate control signal 828 (Psel_off_PN). In an embodiment,circuitry 826 outputs, ascontrol signal 828, Sign_I signal 806 a whencontrol signal 824 is a logic high and Sign_Q signal 806 b whencontrol signal 824 is a logic low. In an embodiment,circuitry 826 may include a 2:1 multiplexer. - In an embodiment, control signals 816, 820, 824, and 828 are provided as
control signal 522 tophase selector circuit 504. Together, control signals 816, 820, 824, and 828 enablephase selector circuit 504 to select appropriate LO signals from phase offset LO signals 524 a-h depending on baseband I and Q signals 516 a and 516 b. Specifically, the selected LO signals, when mixed withnon-offset envelope signal 518 and offsetenvelope signal 520 withinDPA 506, result in a frequency modulated signal that includes the complex waveform represented by baseband I and Q signals 516 a and 516 b. -
FIG. 9 illustrates an examplephase selector circuit 900 according to an embodiment. Examplephase selector circuit 900 is provided for the purpose of illustration only. Examplephase selector circuit 900 may be an embodiment ofphase selector circuit 504 described above with reference toFIG. 5 . As shown inFIG. 9 ,phase selector circuit 900 may include multiplexers 902 a-d and coupling circuits 906 a-b. -
Phase selector circuit 900 is configured to receive phase offset LO signals 524 a-h and phase control signals 816, 820, 824, and 828. In an embodiment, LO signals 524 a, 524 c, 524 e, and 524 g, which represent non-offset LO signals (not offset in phase relative to traditional axes of a unit circle), are received by multiplexers 902 a-b, andLO signals multiplexers 902 c-d. - At the control of
control signal 816,multiplexers LO signals control signal 816 is a logic high, LO signals 904 a and 904 b correspond to LO signals 524 a and 524 e respectively (0 and 180 degrees). When control signal 816 is a logic low, LO signals 904 a and 904 b correspond toLO signals -
Multiplexers LO signals control signal 824. Specifically, whencontrol signal 824 is a logic high, LO signals 904 c and 904 d correspond toLO signals LO signals - Coupling circuits 906 a-b are configured to couple the selected first and second non-offset LO signals 904 a-b and the first and second offset LO signals 904 c-d to output terminals of
phase selector circuit 900 to generate non-offset LO output signals 526 a-b and offset LO output signals 528 a-b. - In an embodiment,
coupling circuit 906 a is configured to receive non-offset LO signals 904 a-b and to couple non-offset LO signals 904 a-b to non-offset LO output signals 526 a-b responsive to controlsignal 820. In an embodiment, whencontrol signal 820 is at a logic high level,coupling circuit 906 a couples non-offset LO signal 904 a to non-offset LO output signal 526 a and non-offset LO signal 904 b to non-offsetLO output signal 526 b. - Otherwise, when
control signal 820 is at a logic low level,coupling circuit 906 a swaps non-offset LO signals 904 a and 904 b such that non-offset LO signal 904 a is coupled to non-offset LO output signal 526 a and non-offset LO signal 904 b is coupled to non-offsetLO output signal 526 b. The swapping of non-offset LO signals 904 a and 904 b results in a 180 degrees phase inversion (or otherwise a polarity reversal) in the signal resulting from mixing non-offset LO output signals 526 a-b withnon-offset envelope signal 518. In an embodiment, non-offset LO signals 904 a and 904 b are swapped when I envelope signal 804 a is lower thanQ envelope signal 804 b and Sign_Q signal 806 b is negative, or when I envelope signal 804 a is greater thanQ envelope signal 804 b and Sign_I signal 806 a is negative. -
Coupling circuit 906 b is configured to receive offset LO signals 904 c-d and to couple offset LO signals 904 c-d to offset LO output signals 528 a-b responsive to controlsignal 828. In an embodiment, whencontrol signal 828 is at a logic high level,coupling circuit 906 b couples offset LO signal 904 c to offset LO output signal 528 a and offset LO signal 904 d to offsetLO output signal 528 b. - Otherwise, when
control signal 828 is at a logic low level,coupling circuit 906 b swaps offset LO signals 904 c and 904 d such that offset LO signal 904 c is coupled to offset LO output signal 528 a and offset LO signal 904 d is coupled to offsetLO output signal 528 b. The swapping of offset LO signals 904 c and 904 d results in a 180 degrees phase inversion (or otherwise a polarity reversal) in the signal resulting from mixing offset LO output signals 528 a-b with offsetenvelope signal 520. In an embodiment, offset LO signals 904 c and 904 d are swapped whenever Sign_Q signal 806 b is negative. - As would be understood by a person of skill in the art based on the teachings herein, embodiments are not limited to π/4 vector decomposition of baseband I and Q signals 516 a and 516 b and can be extended generally to it/N vector decomposition, where N=8, 16, 32, etc, as illustrated by example
digital transmitter 1000 ofFIG. 10 . - As shown in
FIG. 10 , exampledigital transmitter 1000 includes a π/Nvector decomposer circuit 1002 that generates anon-offset envelope signal 1020 and an offsetenvelope signal 1022 based on a π/N vector decomposition of baseband I and Q signals 516 a and 516 b. π/Nvector decomposer circuit 1002 also generates aphase control signal 1012 for aphase selector circuit 1004. -
Phase selector circuit 1004 receives 2×N π/N phase offsetLO signals 1014 and outputs first and second non-offset LO signals 1016 a-b and first and second offset LO signals 1018 a-b responsive tophase control signal 1012.DPA 1006 includes anon-offset DPA 1008 and a π/N offsetDPA 1010.Non-offset DPA 1008 processesnon-offset envelope signal 1020 and non-offset LO signals 1016 a-b to generateoutput signal 1026. π/N offsetDPA 1010 processes offsetenvelope signal 1022 and offset LO signals 1018 a-b to generateoutput signal 1028.Output signals non-offset DPA 1008 and π/N offsetDPA 1010 are combined usingcombiner 514 to generate anoutput signal 1024 ofdigital transmitter 1000. - For the purposes of this discussion, the term “processor circuitry” shall be understood to include one or more: circuit(s), processor(s), or a combination thereof. For example, a circuit can include an analog circuit, a digital circuit, state machine logic, other structural electronic hardware, or a combination thereof. A processor can include a microprocessor, a digital signal processor (DSP), or other hardware processor. The processor can be “hard-coded” with instructions to perform corresponding function(s) according to embodiments described herein. Alternatively, the processor can access an internal or external memory to retrieve instructions stored in the memory, which when executed by the processor, perform the corresponding function(s) associated with the processor.
- Embodiments have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.
- The foregoing description of the specific embodiments will so fully reveal the general nature of the disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.
- The breadth and scope of embodiments of the present disclosure should not be limited by any of the above-described exemplary embodiments as other embodiments will be apparent to a person of skill in the art based on the teachings herein.
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