US20170200699A1 - Semiconductor structure and method of making - Google Patents
Semiconductor structure and method of making Download PDFInfo
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- US20170200699A1 US20170200699A1 US14/994,702 US201614994702A US2017200699A1 US 20170200699 A1 US20170200699 A1 US 20170200699A1 US 201614994702 A US201614994702 A US 201614994702A US 2017200699 A1 US2017200699 A1 US 2017200699A1
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- tsvs
- edge connector
- leg
- crackstop
- peripheral edge
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
- H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06551—Conductive connections on the side of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract
Description
- The present invention relates to a semiconductor structure comprising a silicon-containing substrate having a peripheral edge surface and a circuit structure circumscribed by a crackstop structure. Through-silicon conductive vias are configured to connect the circuit structure to the peripheral edge surface without penetrating the crackstop structure.
- Three-dimensional (3D) stacking of integrated circuits have improved circuit performance. More specifically, advancements in the area of semiconductor fabrication have enabled the manufacturing of integrated circuits that have a high density of electronic components.
- Fabrication of 3D integrated circuits includes at least two silicon die stacked vertically. Vertically stacked die can reduce interconnect wiring length and increase semiconductor device density. Deep through-substrate/through-silicon vias (TSVs) may be formed to provide interconnections and electrical connectivity between the electronic components of the 3D integrated circuits. Such TSVs may have high aspect ratios, where the via height is large with respect to the via width, to save valuable area in an integrated circuit design. Therefore, semiconductor device density can be increased and total length of interconnect wiring may be decreased by incorporating TSVs in 3D integrated circuits.
- In accordance with one aspect of the present invention there is provided a semiconductor structure comprising the following components. A silicon-containing substrate has a first surface on which is disposed a circuit structure, an opposite second surface and a peripheral edge surface. A peripheral crackstop structure circumscribes the circuit structure and stops short of the second surface, to thereby leave an accessible portion of the peripheral edge surface free of the crackstop structure. One or more edge connector through-silicon conductive vias (“edge connector TSVs”) connect the circuit structure to the accessible portion of the peripheral edge surface without penetrating the crackstop structure.
- In accordance with another aspect of the present invention there is provided a semiconductor structure comprising the following components. A silicon-containing substrate has a first surface on which is disposed a circuit structure circumscribed by a peripheral crackstop structure, an opposite second surface and a peripheral edge surface. The peripheral crackstop structure stops short of the second surface to thereby leave an accessible portion of the peripheral edge surface free of the crackstop structure. One or more edge connector through-silicon conductive vias (“edge connector TSVs”) connect the circuit structure to the accessible portion of the peripheral edge surface without penetrating the crackstop structure. The one or more edge connector TSVs may be angular edge connector TSVs characterized by having at least a segment of the angular edge connector TSVs extending through the substrate at an acute angle relative to the first surface and extending to the accessible portion of the peripheral edge surface. Alternatively, or in addition, the edge connector TSVs may be orthogonal edge connector TSVs characterized by having at least a first leg and a second leg, the first leg extending substantially perpendicularly to the first surface through the substrate to the second leg, and the second leg extending along the second surface to the accessible portion of the peripheral edge surface.
- A method aspect of the present invention provides for making a plurality of semiconductor structures, the method comprising the following steps. Providing a silicon wafer having a top surface on which are a plurality of mounting areas adapted to receive circuit structures, an opposite bottom surface, and a plurality of peripheral crackstop structures extending about associated ones of the mounting areas. A plurality of conductive through-silicon vias (“TSVs”) are formed in the wafer to extend from respective ones of the mounting areas. The wafer is diced along dicing pathways to form a plurality of dies having respective opposite first and second surfaces and peripheral edge surfaces defining a core of the die. The improvement to the method comprises that the crackstop structure extends below the top surface of the wafer and stops short of the bottom surface of the wafer whereby the peripheral edge surfaces of the dies cut from the wafer comprise accessible portions through which the core is accessible without penetrating the crackstop structure. Further, at least some of the TSVs are edge connector TSVs configured to extend from respective ones of the mounting areas to locations on the dicing pathways which are free of the crackstop structures, so that when the dies are cut from the wafer, the edge connector TSVs terminate at the accessible portions of the peripheral edge surfaces of the dies, without penetrating the crackstop structure.
-
FIG. 1 is a schematic partial plan view of one embodiment of a silicon wafer having thereon a plurality of mounting areas enclosed by crackstop structures and adapted to receive circuit structures; -
FIG. 1A is a cross-sectional view in elevation of a semiconductor structure cut from the wafer ofFIG. 1 after conductive through-silicon vias were formed in the wafer in accordance with a first embodiment of the present invention; -
FIG. 1B is a top plan view, reduced in size relative toFIG. 1A , of the die ofFIG. 1A ; -
FIG. 2 is a schematic cross-sectional view in elevation of a semiconductor structure in accordance with another embodiment of the present invention; -
FIG. 2A is a view in elevation taken along line A-A ofFIG. 2 ; -
FIG. 3 is a schematic cross-sectional view corresponding to that ofFIG. 2 of a semiconductor structure in accordance with another embodiment of the present invention; -
FIG. 3A is a view in elevation taken along line A-A ofFIG. 3 ; -
FIG. 4 is a schematic bottom plan view of a stage of fabrication of a semiconductor structure in accordance with another embodiment of the present invention; -
FIG. 4A is a view corresponding toFIG. 4 but showing a later stage in the fabrication of the semiconductor structure; and -
FIG. 5 is a schematic cross-sectional view in elevation of an assembly of semiconductor structures in accordance with a fifth embodiment of the present invention. - In order to form an electrical connection between the components of two die, stacked one on top of the other, a TSV may extend through the entire thickness of a single die. More specifically, a TSV may extend through multiple interconnect levels and through a semiconductor substrate in which semiconductor devices may be formed. The interconnect levels may generally be located above the substrate, and may include multiple connections to and between the devices formed in the substrate.
- Due to shrinking dimensions for the devices fabricated on an integrated circuit, fabrication processes may utilize different dielectric materials, for example, low or ultra-low-k dielectric materials. Utilization of such dielectric materials may affect reliability due to the material's mechanical properties (e.g., low modulus, low strength, poor adhesion) as compared to other dielectrics, such as silicon dioxide. Dicing of stacked wafers to form 3D TSVs may trigger cracking at the pre-metal dielectric and silicon substrate interface. A crack that begins at an edge may propagate down through the body of the semiconductor device, and may damage underlying conductive lines or enter the active region, which may result in a defect or failure of the device such as an open or shorted connection. Accordingly, crackstop structures are formed within devices as barriers to stop cracks from propagating from peripheral edges and damaging the devices.
- However, semiconductor devices which include a peripheral crackstop structure extending about the circuit structure of the device are limited with respect to portions of the device to which a conductive through-silicon via (“TSV”) may extend. In order to maintain integrity of the crackstop structure, the TSVs generally follow paths which do not penetrate the crackstop structure. The crackstop structure may extend around the entire periphery of a die, including from one major surface of the die to the other, that is, from top to bottom of the die. For this reason, TSVs may be directed between the top and bottom major surfaces of the die, taking care to avoid penetrating the peripheral edge surfaces of the die. Otherwise, the crackstop structure may be compromised by the TSVs.
- Given the ever increasingly crowded structures and limited space available for making connections, the lack of opportunity to make connections through the peripheral edge of the die may be challenging. The structures and method disclosed herein enable directing at least some TSVs from a major surface of the die through a monolithic silicon substrate to and through its peripheral edge surfaces, and not merely upon a major surface to an edge of the peripheral edge surfaces. The edge connector TSVs penetrate an accessible portion of the peripheral edge surfaces without encountering, penetrating or otherwise adversely affecting the structural integrity of the crackstop structure.
-
FIG. 1 shows a portion of asilicon wafer 10 whosetop surface 10 a has a plurality ofmounting areas 12 indicated in dot-dash lines and within which circuit structures (not shown inFIG. 1 ) may be mounted. As used herein, the term “circuit structures” includes passive and active components which may be connected to the TSVs.Crackstop structures 14 are configured to provide a peripheral crackstop circumscribing respective ones of themounting areas 12.Dicing pathways 16 are shown by bold dash lines and indicate the paths which a dicing saw will follow to later cutwafer 10 into a plurality of dies such as dies 18 (FIG. 1A andFIG. 1B ). -
FIG. 1A shows thesilicon core 18′ ofdie 18 bounded byfirst surface 10 a, oppositesecond surface 10 b and peripheral edge surfaces 10 c thereof. Peripheral edge surfaces 10 c ofdie 18 are defined bycrackstop structure 14 and anaccessible portion 10 d of peripheral edge surfaces 10 c. As best seen inFIG. 1A ,crackstop structure 14 stops short of thesecond surface 10 b ofdie 18, thereby providing theaccessible portion 10 d of the peripheral edge surfaces 10 c. The term “accessible portion” is used because that portion of the peripheral edge surfaces 10 c is accessible to TSVs extending throughcore 18′ without encountering or penetratingcrackstop structure 14. -
FIGS. 1A and 1B show a number of TSVs formed within thesilicon core 18′ ofdie 18. The TSVs may be formed by any suitable method. The TSVs may include one or more layers and/or liners. The TSV may include, for example, a dielectric layer, a liner arranged on the dielectric layer, and a metal to fill the trench and form the TSV. The liner may improve adhesion of the metal. The liner may include a metallic compound. The liner may include, for example, tantalum nitride (TaN), followed by an additional layer including tantalum (Ta). Other barrier liners may include cobalt (Co), or ruthenium (Ru) either alone or in combination with any other suitable liner. The liner material may be deposited by a chemical vapor deposition process (CVD), atomic layer deposition (ALD), or other suitable process. The metal may include, for example, copper (Cu), aluminum (Al), or tungsten (W). The metal may be formed using a filling technique such as electroplating, electroless plating, CVD, PVD, or a combination thereof - Angular
edge connector TSV 22 extends from mountingarea 12 and intersectsaccessible portion 10 d ofperipheral edge surface 10 c without encountering or penetratingcrackstop structure 14. Abottom connector TSV 24 extends from mountingarea 12 onfirst surface 10 a tosecond surface 10 b and is substantially perpendicular to bothfirst surface 10 a andsecond surface 10 b. An orthogonaledge connector TSV 26 comprises afirst leg 26 a which extends substantially perpendicularly to bothfirst surface 10 a andsecond surface 10 b.First leg 26 a is connected to asecond leg 26 b which extends alongsecond surface 10 b to anaccessible portion 10 d of thedie 18. - All the through-
silicon vias edge connector TSV 22.Circuit structure 20 is connected by angularedge connector TSV 22 and by orthogonaledge connector TSV 26 to penetrate theaccessible portion 10 d ofdie 18. - In the description of
FIGS. 2 through 3A , parts comparable to the parts illustrated inFIGS. 1 through 1B are identically numbered except for the addition of an initial numeral 1 (FIGS. 2 and 2A ) or an initial numeral 2 (FIGS. 3 and 3A ). - Referring to
FIGS. 2 and 2A , die 118, in a construction similar to that of die 18 ofFIGS. 1A and 1B , has acrackstop structure 114, afirst surface 110 a, a second surface 110,peripheral edge surface 110 c defined bycrackstop surface 114 andaccessible portion 110 d ofperipheral edge surface 110 c. A pair of angularedge connector TSVs FIG. 2A ) extend fromcircuit structure 120 throughcore 118′ to theaccessible portion 110 d of theperipheral edge surface 110 c (FIG. 2 ) ofdie 118. OnlyTSV 122 a is visible inFIG. 2 .FIG. 2A shows the intersection of angularedge connector TSVs accessible portion 110 d ofperipheral edge surface 110 c. - Referring to
FIGS. 3 and 3A , adie 218 has orthogonal edge connector TSV 226 (FIG. 3 ) comprised of afirst leg 226 a which extends substantially perpendicularly relative tofirst surface 210 a andsecond surface 210 b to intersectsecond leg 226 b. The latter extends alongsecond surface 210 b to theaccessible portion 210 d ofperipheral edge surface 210 c. Adielectric layer 228 is applied tosecond surface 210 b in order to insulatesecond leg 226 b of orthogonal edge connector TSV 226.Dielectric layer 228 also serves to insulate additionalsecond legs FIG. 3A ) which also extend fromfirst leg 226 a (FIG. 3 ) in a direction opposite from that in whichsecond leg 226 b extends. - The
dielectric layer 228 may include one or more dielectric materials. Thedielectric layer 228 may include, for example, dielectric oxides (e.g., silicon oxide), dielectric nitrides (e.g., silicon nitride), dielectric oxynitrides, or any combination thereof. - The dielectric material may be deposited by a deposition process, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD).
- Built-up
layers 38 are formed in additional back-side processing which is carried out post-thinning. The layers may be built up by etching or dual damescene processing, resulting in the square cross-sectional configuration of additionalsecond legs 227 and 277 b and the rectangular cross-sectional configuration ofleg 227 a. Obviously, instead of or in addition to branched second legs extending alongsecond surface 210 b ofdie 218 one or more additional orthogonal first legs (not shown inFIG. 3 or 3A ) could be utilized to connect with second leg segments. -
FIGS. 4 and 4A show thesecond surface 310 b of adie 318 havingaccessible portion 310 d ofperipheral edge surface 310 c.Peripheral edge surface 310 c of course extends around the entire perimeter ofdie 318. A pair ofbottom connector TSVs FIGS. 4 and 4A ) ofdie 318 and thesecond surface 310 b ofdie 318. The first surface ofdie 318 corresponds tofirst surface 210 a of die 218 (FIG. 3 ).Bottom connector TSVs die 318 tosecond surface 310 b. The first surface and circuit structure are not shown inFIGS. 4 and 4A but correspond to corresponding structures in the other embodiments, for example,first surface 10 a ofFIGS. 1A and 1B andcircuit structure 20 ofFIG. 1A . - Four orthogonal edge connector TSVs 326 are each comprised, respectively, of
first legs second legs accessible portion 310 d ofdie 318. As shown inFIG. 4A , adielectric layer 328 is applied oversecond surface 310 b leavingbottom connector TSVs first leg 326 a″ uninsulated. In this way,bottom connector TSVs first leg 326 a″ may effectuate both a bottom connection and, viasecond leg 326 b″, an edge connection ofdie 318. -
FIG. 5 shows three dies 418, 418 a and 418 b supported on asubstrate 30 and interconnected with each other and withsubstrate circuit structures substrate 30. Each of dies 418, 418 a and 418 b comprises arespective crackstop structure circuit structures 420 may be identical, others may differ from each other. Dies 418, 418 a and 418 b each have respectiveaccessible portions 410 d and respective first surfaces (not shown inFIG. 5 ) andsecond surfaces 410 b. The first surfaces correspond tofirst surfaces FIG. 1A andFIG. 2 - Dies 418, 418 a and 418 b each have three identically numbered bottom connector TSVs, respectively numbered 424, 424 a and 424 b.
Die 418 has an angularedge connector TSV 422, die 418 a has an angularedge connector TSV 422 a and die 418 b has an orthogonaledge connector TSV 426. Dies 418, 418 a and 418 b are connected in series to each other and tosubstrate circuit structures solder ball connectors 34. - Connections are also made by wire bonds.
Wire bond 36 a connects angularedge connector TSV 422 to orthogonaledge connector TSV 426, which is in turn connected bywire bond 36 b tosubstrate circuit structure 32 d.Wire bond 36 c connects angularedge connector TSV 422 a tosubstrate circuit structure 32 e. It is seen that the ability to utilize edge connector TSVs such asTSVs FIG. 5 provides versatility and the ability to provide additional connections in a crowded space. - Although
FIG. 5 illustrates edge connector TSVs only for TSVs which are adjacent toaccessible portions 410 d of the peripheral edges (unnumbered inFIG. 5 ) of the dies, it is also feasible that edge connector TSVs need not be disposed immediately adjacent toaccessible portions 410 d. - Results are noted in
FIG. 5 that the horizontal leg (as viewed in the drawing) of orthogonaledge connector TSV 426 is somewhat removed fromsurface 410 b ofdie 418 b. Normally, the horizontal leg will be formed atbottom surface 410 b but in the illustrated embodiment reflects the option of building up the bottom ofdie 418 with dielectric or other layers so that in the finished product the horizontal leg of orthogonaledge connector TSV 426 penetratesaccessible portion 410 d at a distance somewhat removed from the built-upsecond surface 410 b. In this way, a stacked array of dies 418, 418 a and 418 b mounted on asubstrate 30 may be interconnected both via wire bonds and solder balls into a compact array of semiconductor structures. - The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
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US5657537A (en) * | 1995-05-30 | 1997-08-19 | General Electric Company | Method for fabricating a stack of two dimensional circuit modules |
US6037044A (en) * | 1998-01-08 | 2000-03-14 | International Business Machines Corporation | Direct deposit thin film single/multi chip module |
SG102639A1 (en) * | 2001-10-08 | 2004-03-26 | Micron Technology Inc | Apparatus and method for packing circuits |
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US9385228B2 (en) | 2013-11-27 | 2016-07-05 | Infineon Technologies Ag | Semiconductor device with cell trench structures and contacts and method of manufacturing a semiconductor device |
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