US20170178916A1 - Enhanced lateral cavity etch - Google Patents

Enhanced lateral cavity etch Download PDF

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US20170178916A1
US20170178916A1 US15/429,403 US201715429403A US2017178916A1 US 20170178916 A1 US20170178916 A1 US 20170178916A1 US 201715429403 A US201715429403 A US 201715429403A US 2017178916 A1 US2017178916 A1 US 2017178916A1
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cavity
semiconductor device
substrate
under
etch
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Brian E. Goodlin
Karen H. R. Kirmse
Iqbal R. Saraf
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Texas Instruments Inc
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Texas Instruments Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
    • G01J5/02—Constructional details
    • G01J5/0225—Shape of the cavity itself or of elements contained in or suspended over the cavity
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
    • G01J5/02—Constructional details
    • G01J5/0225—Shape of the cavity itself or of elements contained in or suspended over the cavity
    • G01J5/024—Special manufacturing steps or sacrificial layers or layer structures
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
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    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
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    • H10N15/00—Thermoelectric devices without a junction of dissimilar materials; Thermomagnetic devices, e.g. using the Nernst-Ettingshausen effect
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    • H10N15/00—Thermoelectric devices without a junction of dissimilar materials; Thermomagnetic devices, e.g. using the Nernst-Ettingshausen effect
    • H10N15/10—Thermoelectric devices using thermal change of the dielectric constant, e.g. working above and below the Curie point
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching

Definitions

  • This invention relates to the field of semiconductor devices and more specifically to the formation of a cavity wherein the width of the cavity exceeds the depth in a semiconductor device.
  • Cavities are frequently formed in semiconductor circuits to reduce coupling of a device such as an inductor, heater, or bolometer to the substrate.
  • a cavity is etched into a substrate material such silicon or SiGe through an opening in a dielectric layer overlying the substrate using a substantially isotropic etch.
  • the substantially isotropic etch etches the cavity vertically faster than it does laterally. Consequently a very deep cavity may need to be formed to completely remove the substrate laterally from under the device to reduce coupling.
  • the deep cavity may weaken the substrate resulting in breakage and yield loss.
  • One method to avoid etching a deep cavity is to build an etch stop layer into the substrate under the device with the coupling issue. This method may add significant complexity, cycle time, and cost to the manufacturing flow.
  • a cavity is formed in a semiconductor substrate wherein the width of the cavity is greater than the depth of the cavity and wherein the depth of the cavity is non uniform across the width of the cavity.
  • the cavity may be formed under an electronic device in the semiconductor substrate.
  • the cavity is formed in the substrate by performing a first cavity etch followed by repeated cycles of polymer deposition, cavity etch, and polymer removal.
  • FIG. 1A through FIG. 1J are cross sections illustrating the formation of a cavity in an integrated circuit in successive stages of fabrication according to principles of the invention.
  • FIG. 2 is flow diagram for the steps in a process of forming a cavity in a substrate according to principles of the invention.
  • FIG. 1F A structure with a cavity that is etched according to embodiments is illustrated in FIG. 1F .
  • the cavity is etched into the substrate 100 using an etch that is substantially isotropic.
  • the cavity is wider than it is deep.
  • the cavity depth is non uniform across the width of the cavity.
  • the cavity is deepest under the opening through which the cavity is etched.
  • FIG. 1A shows a substrate 100 that may be etched using an etchant that etches substantially isotropically, that is, etches laterally as well as vertically.
  • a hard mask (layers 102 and 104 ) overlies the substrate.
  • the etchant may be introduced through an opening 106 in the hard mask 102 / 104 to etch a cavity in the substrate 100 (step 200 in FIG. 2 ).
  • the substrate 100 is single crystal silicon and the hard mask is comprised of a layer of silicon nitride 104 which overlies a layer of silicon dioxide 102 .
  • One layer of masking material (silicon dioxide for example) may alternatively be used. Other masking materials and other substrates may also be used.
  • the opening 106 in the example embodiment may be in the range of less than a micron to many microns wide depending upon the details of the device being manufactured. In an example embodiment opening 106 is about 25 microns wide.
  • first cavity etch step 202 of FIG. 2 etchant is introduced through opening 106 and etches the substrate 100 both vertically and laterally to form a cavity with first cavity etch sidewalls 108 as shown in FIG. 1B .
  • the silicon substrate 100 is etched in a substantially isotropic manner using a SF 6 plasma etch.
  • the SF 6 etches the silicon approximately twice as fast vertically as laterally through the opening 106 .
  • Example cavity etch process conditions are 225 mT pressure, 4000 Watts source power, 0 Watts bias power, 1000 sccm SF 6 , and a temperature of 15° C.
  • polymer 110 is formed on the bottom and sidewalls 108 of the first etched cavity as shown in FIG. 1C .
  • the polymer 110 is thicker on the bottom of the cavity under the opening 106 and gets thinner on the sidewalls 108 of the cavity away from under the opening 106 .
  • the polymer deposition step is typically performed using a plasma with a fluorocarbon gas, C x H y F z , such as CH 4 , CHF 3 , CH 2 F 2 , C 2 F 6 , C 3 F 6 , and C 4 F 8 .
  • Example polymer deposition process conditions are 10 mT pressure, 3800 Watts source power, 0 Watts bias power, 200 sccm C 4 F 8 , and a temperature of 15° C.
  • an optional ashing step may be performed to remove the polymer from the sidewalls 108 of the cavity where the polymer is thin as shown in FIG. 1D .
  • a breakthrough etch step to remove minor amounts of polymer may be performed at the beginning of the subsequent SF 6 silicon etch.
  • a plasma ashing step with oxygen is used.
  • Example ashing process conditions are 30 mT pressure, 2500 Watts source power, 0 Watts bias power, 200 sccm oxygen, and a temperature of 15° C.
  • a second cavity etch is performed as shown in FIG. 1E .
  • the polymer 110 covering the bottom of the trench prevents the cavity from being etched deeper into the substrate.
  • the etchant enlarges the cavity laterally forming second cavity etch walls 112 that are spaced at a greater lateral distance from the opening than the lateral walls 108 of the first cavity etch (step 202 ).
  • step 210 of FIG. 2 the polymer may be removed from the cavity using an ashing step, as shown in FIG. 1F .
  • This step is optional if the final trench width has not been achieved.
  • a plasma ashing step containing oxygen is used. The ashing conditions are described previously.
  • step 212 of FIG. 2 a determination may be made to see if the target cavity width has been achieved. If the target cavity width is achieved the wafers may be sent on to the next process step in the manufacturing flow (step 214 in FIG. 2 ).
  • the wafers may be returned to step 204 in FIG. 2 and the process of polymer deposition followed by another cavity etch step may be repeated until the target width is achieved.
  • FIGS. 1G through FIG. 1J A second polymer deposition step followed by a third cavity etch is illustrated in FIGS. 1G through FIG. 1J . More than three cycles of polymer deposition, cavity etch, and polymer removal may be performed to achieve the desired cavity width without etching the cavity deeper.
  • step 204 of FIG. 2 polymer is deposited onto the cavity sidewalls 108 and 112 .
  • an optional ashing step is performed to remove the polymer 114 from the lateral sidewalls 112 of the cavity if it is needed.
  • a third cavity etch is performed.
  • the polymer 114 on the bottom of the cavity walls 108 and 112 prevents the cavity from being etched deeper into the silicon.
  • the exposed second cavity etch walls 112 are etched laterally away from the opening 106 to form third etch cavity walls 116 .
  • the polymer is removed from the cavity by ashing.
  • the width of the cavity is substantially wider than the depth of the cavity.
  • the width may be approximately twice the depth or more.
  • This cavity is formed without the addition of an etch stop layer in the substrate which may add significant complexity and cost to the manufacturing flow. Cavities formed when an etch stop layer is used typically have a uniform depth across the width of the cavity. The depth of the cavity formed using the embodiment process is not uniform in depth across the width of the cavity as is illustrated in FIG. 1F and FIG. 1J .

Abstract

A cavity is formed in a semiconductor substrate wherein the width of the cavity is greater than the depth of the cavity and wherein the depth of the cavity is non uniform across the width of the cavity. The cavity may be formed under an electronic device in the semiconductor substrate. The cavity is formed in the substrate by performing a first cavity etch followed by repeated cycles of polymer deposition, cavity etch, and polymer removal.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of U.S. Nonprovisional Patent Application Ser. No. 14/973,904, filed Dec 18, 2015, the contents of which are herein incorporated by reference in its entirety.
    • FIELD OF THE INVENTION
  • This invention relates to the field of semiconductor devices and more specifically to the formation of a cavity wherein the width of the cavity exceeds the depth in a semiconductor device.
    • BACKGROUND
  • Cavities are frequently formed in semiconductor circuits to reduce coupling of a device such as an inductor, heater, or bolometer to the substrate. Typically a cavity is etched into a substrate material such silicon or SiGe through an opening in a dielectric layer overlying the substrate using a substantially isotropic etch. Typically the substantially isotropic etch, etches the cavity vertically faster than it does laterally. Consequently a very deep cavity may need to be formed to completely remove the substrate laterally from under the device to reduce coupling. The deep cavity may weaken the substrate resulting in breakage and yield loss.
  • One method to avoid etching a deep cavity is to build an etch stop layer into the substrate under the device with the coupling issue. This method may add significant complexity, cycle time, and cost to the manufacturing flow.
    • SUMMARY
  • The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to a more detailed description that is presented later.
  • A cavity is formed in a semiconductor substrate wherein the width of the cavity is greater than the depth of the cavity and wherein the depth of the cavity is non uniform across the width of the cavity. The cavity may be formed under an electronic device in the semiconductor substrate. The cavity is formed in the substrate by performing a first cavity etch followed by repeated cycles of polymer deposition, cavity etch, and polymer removal.
    • DESCRIPTION OF THE VIEWS OF THE DRAWINGS
  • FIG. 1A through FIG. 1J are cross sections illustrating the formation of a cavity in an integrated circuit in successive stages of fabrication according to principles of the invention.
  • FIG. 2 is flow diagram for the steps in a process of forming a cavity in a substrate according to principles of the invention.
    •  DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
  • The present invention is described with reference to the attached figures. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
  • A structure with a cavity that is etched according to embodiments is illustrated in FIG. 1F. The cavity is etched into the substrate 100 using an etch that is substantially isotropic. The cavity is wider than it is deep. The cavity depth is non uniform across the width of the cavity. The cavity is deepest under the opening through which the cavity is etched.
  • The method for forming a cavity wherein the width of the cavity is substantially wider than the depth of the cavity is described in the process flow in FIG. 2 and in the cross sections in FIGS. 1A through 1J.
  • FIG. 1A shows a substrate 100 that may be etched using an etchant that etches substantially isotropically, that is, etches laterally as well as vertically. A hard mask (layers 102 and 104) overlies the substrate. The etchant may be introduced through an opening 106 in the hard mask 102/104 to etch a cavity in the substrate 100 (step 200 in FIG. 2). In an example embodiment, the substrate 100 is single crystal silicon and the hard mask is comprised of a layer of silicon nitride 104 which overlies a layer of silicon dioxide 102. One layer of masking material (silicon dioxide for example) may alternatively be used. Other masking materials and other substrates may also be used. The opening 106 in the example embodiment may be in the range of less than a micron to many microns wide depending upon the details of the device being manufactured. In an example embodiment opening 106 is about 25 microns wide.
  • In first cavity etch step 202 of FIG. 2, etchant is introduced through opening 106 and etches the substrate 100 both vertically and laterally to form a cavity with first cavity etch sidewalls 108 as shown in FIG. 1B. In an example embodiment the silicon substrate 100 is etched in a substantially isotropic manner using a SF6 plasma etch. In the example embodiment, the SF6 etches the silicon approximately twice as fast vertically as laterally through the opening 106.
  • Example cavity etch process conditions are 225 mT pressure, 4000 Watts source power, 0 Watts bias power, 1000 sccm SF6, and a temperature of 15° C.
  • In step 204 of FIG. 2 polymer 110 is formed on the bottom and sidewalls 108 of the first etched cavity as shown in FIG. 1C. Typically the polymer 110 is thicker on the bottom of the cavity under the opening 106 and gets thinner on the sidewalls 108 of the cavity away from under the opening 106. The polymer deposition step is typically performed using a plasma with a fluorocarbon gas, CxHyFz, such as CH4, CHF3, CH2F2, C2F6, C3F6, and C4F8.
  • Example polymer deposition process conditions are 10 mT pressure, 3800 Watts source power, 0 Watts bias power, 200 sccm C4F8, and a temperature of 15° C.
  • In step 206 of FIG. 2 an optional ashing step may be performed to remove the polymer from the sidewalls 108 of the cavity where the polymer is thin as shown in FIG. 1D. In some cases so little polymer may be formed in the sidewalls that a separate ashing step is unnecessary. Instead a breakthrough etch step to remove minor amounts of polymer may be performed at the beginning of the subsequent SF6 silicon etch. In the example embodiment a plasma ashing step with oxygen is used.
  • Example ashing process conditions are 30 mT pressure, 2500 Watts source power, 0 Watts bias power, 200 sccm oxygen, and a temperature of 15° C.
  • In step 208 of FIG. 2, a second cavity etch is performed as shown in FIG. 1E. The polymer 110 covering the bottom of the trench prevents the cavity from being etched deeper into the substrate. The etchant enlarges the cavity laterally forming second cavity etch walls 112 that are spaced at a greater lateral distance from the opening than the lateral walls 108 of the first cavity etch (step 202).
  • In step 210 of FIG. 2 the polymer may be removed from the cavity using an ashing step, as shown in FIG. 1F. This step is optional if the final trench width has not been achieved. In the example embodiment a plasma ashing step containing oxygen is used. The ashing conditions are described previously.
  • In step 212 of FIG. 2, a determination may be made to see if the target cavity width has been achieved. If the target cavity width is achieved the wafers may be sent on to the next process step in the manufacturing flow (step 214 in FIG. 2).
  • If, however, the target cavity width is not achieved, the wafers may be returned to step 204 in FIG. 2 and the process of polymer deposition followed by another cavity etch step may be repeated until the target width is achieved.
  • A second polymer deposition step followed by a third cavity etch is illustrated in FIGS. 1G through FIG. 1J. More than three cycles of polymer deposition, cavity etch, and polymer removal may be performed to achieve the desired cavity width without etching the cavity deeper.
  • In FIG. 1G (step 204 of FIG. 2), polymer is deposited onto the cavity sidewalls 108 and 112.
  • In FIG. 1H (step 206 of FIG. 2), an optional ashing step is performed to remove the polymer 114 from the lateral sidewalls 112 of the cavity if it is needed.
  • In FIG. 1I (step 208 of FIG. 2), a third cavity etch is performed. The polymer 114 on the bottom of the cavity walls 108 and 112 prevents the cavity from being etched deeper into the silicon. The exposed second cavity etch walls 112 are etched laterally away from the opening 106 to form third etch cavity walls 116.
  • In FIG. 1J, (step 210 of FIG. 2) the polymer is removed from the cavity by ashing. As shown in FIG. 1J, the width of the cavity is substantially wider than the depth of the cavity. As an example, the width may be approximately twice the depth or more. This cavity is formed without the addition of an etch stop layer in the substrate which may add significant complexity and cost to the manufacturing flow. Cavities formed when an etch stop layer is used typically have a uniform depth across the width of the cavity. The depth of the cavity formed using the embodiment process is not uniform in depth across the width of the cavity as is illustrated in FIG. 1F and FIG. 1J.
  • While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.

Claims (18)

What is claimed is:
1. A semiconductor device comprising a cavity in a substrate wherein the cavity is wider than it is deep and wherein a depth of the cavity is non-uniform across a width of the cavity.
2. The semiconductor device of claim 1, wherein the substrate is single crystal silicon.
3. The semiconductor device of claim 1, wherein the substrate is single crystal silicon germanium.
4. The semiconductor device of claim 1, wherein the cavity underlies an opening in an overlying masking layer.
5. The semiconductor device of claim 4, wherein the masking layer comprises a layer of silicon nitride overlying a layer of silicon dioxide.
6. The semiconductor device of claim 1, wherein the cavity is under an inductor.
7. The semiconductor device of claim 1, wherein the cavity is under a bolometer.
8. The semiconductor device of claim 1, wherein the cavity is under an electronic device that is sensitive to capacitive coupling to the substrate.
9. A semiconductor device comprising:
a silicon substrate without an etch stop layer within the silicon substrate;
a cavity in the silicon substrate wherein the cavity is at least twice as wide as it is deep.
10. The semiconductor device of claim 9, wherein the silicon substrate is single crystal silicon.
11. The semiconductor device of claim 9, wherein the silicon substrate is single crystal silicon germanium.
12. The semiconductor device of claim 9, wherein the cavity is under an inductor.
13. The semiconductor device of claim 9, wherein the cavity is under a bolometer.
14. The semiconductor device of claim 9, wherein the cavity is under an electronic device that is sensitive to capacitive coupling to the substrate.
15. A semiconductor device comprising:
a substrate of single crystal silicon;
a cavity in the substrate wherein the cavity is at least twice as wide as it is deep, wherein single crystal silicon forms a bottom surface and side surfaces of the cavity and wherein a depth of the cavity is non-uniform across a width of the cavity.
16. The semiconductor device of claim 15, wherein the cavity is under an inductor.
17. The semiconductor device of claim 15, wherein the cavity is under a bolometer.
18. The semiconductor device of claim 15, wherein the cavity is under an electronic device that is sensitive to capacitive coupling to the substrate.
US15/429,403 2015-12-18 2017-02-10 Enhanced lateral cavity etch Pending US20170178916A1 (en)

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