US20170155019A1 - Light-emitting diode chip packages and methods for manufacture thereof - Google Patents
Light-emitting diode chip packages and methods for manufacture thereof Download PDFInfo
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- US20170155019A1 US20170155019A1 US15/166,220 US201615166220A US2017155019A1 US 20170155019 A1 US20170155019 A1 US 20170155019A1 US 201615166220 A US201615166220 A US 201615166220A US 2017155019 A1 US2017155019 A1 US 2017155019A1
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 230000001681 protective effect Effects 0.000 claims abstract description 14
- 238000005520 cutting process Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052594 sapphire Inorganic materials 0.000 claims description 5
- 239000010980 sapphire Substances 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 238000002156 mixing Methods 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000007648 laser printing Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/50—Wavelength conversion elements
- H01L33/501—Wavelength conversion elements characterised by the materials, e.g. binder
- H01L33/502—Wavelength conversion materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
- H01L33/56—Materials, e.g. epoxy or silicone resin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
- H01L33/60—Reflective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0041—Processes relating to semiconductor body packages relating to wavelength conversion elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0058—Processes relating to semiconductor body packages relating to optical field-shaping elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
Definitions
- the subject matter herein generally relates to the field of chip packages, and particularly to light-emitting diode chip packages and methods for manufacturing light-emitting diode chip packages.
- a conventional white light-emitting diode (LED) chip package formed by a blue LED and a phosphor layer includes an LED chip 3 and a substrate 5 .
- the LED chip 3 is soldered on the substrate 5 via a convex element 6 .
- a light-emitting surface of the LED chip 3 is coated with a phosphor layer 2 and then sealed with a silicone lens 1 , gaps between the LED chip 3 and the substrate 5 being filled with filler 4 .
- a number of processes are involved in manufacturing the white LED chip package, including preparing a substrate 5 , manufacturing a convex element 6 , soldering an LED chip 3 to the substrate 5 with the convex element 6 , coating a phosphor layer 2 to the LED chip 3 , and formation of silicone lens 1 and others.
- the investment cost for the manufacturing equipment is high, meanwhile the white LED chip package takes up much more real estate on a printed circuit board than the LED chip 3 .
- FIG. 1 is a view illustrating a conventional white LED chip package.
- FIG. 2 is a schematic view of a light-emitting diode chip package of the disclosure.
- FIG. 3 is a partially enlarged view of portion A of the light-emitting diode chip package in FIG. 2 .
- FIG. 4 is a partial schematic view of a light-emitting diode chip package of the disclosure during manufacturing.
- FIG. 5 schematically illustrates a process step in an embodiment for manufacturing light-emitting diode chip package of the disclosure.
- a light-emitting diode chip package sequentially includes a transparent layer 10 , a fluorescent layer 20 , a wafer layer 40 , a light-emitting diode chip C, a dielectric layer 90 , a metal circuit layer 100 , a protective film 120 , and a plurality of conductive blocks 110 along a predetermined direction.
- the conductive blocks 110 are used to draw out the electrodes of the light-emitting diode chip C and to assemble pins thereto. Outer surfaces of the fluorescent layer 20 and the wafer layer 40 are shrunk from the fluorescent layer 20 to the wafer layer 40 and form a slant S.
- the dielectric layer 90 , the metal circuit layer 100 , and the protective film 120 are extended to cover the slant S.
- the predetermined direction is shown as direction D in FIG. 2 , and in this case, the light-emitting diode chip C is a GaN-based light-emitting diode chip sequentially formed by a GaN layer 50 , an n-type GaN layer 60 , a quantum layer 70 , and a p-type GaN layer 80 along the direction D.
- the light-emitting diode chip C is provided with gaps corresponding to the conductive blocks 110 .
- the dielectric layer 90 , the metal circuit layer 100 , and the protective film 120 respectively define openings corresponding to the gaps to expose the conductive blocks 110 , to achieve electrical connection to external components via the conductive blocks 110 .
- the light-emitting diode chip C can be chosen from numerous and various structures similar to those described above.
- the transparent layer 10 is used as a supporting and light-transmitting unit.
- the monochromatic light emitted from the light-emitting diode chip C can be converted into white light after passing through the fluorescent layer 20 due to the mechanism of fluorescence.
- the dielectric layer 90 is provided to prevent short-circuits on the wafer layer 40 .
- the outer surfaces of the fluorescent layer 20 and the wafer layer 40 retreat along the direction D to form a slant S.
- the slant S can be used as a reflector with the metal circuit layer 100 and the protective film 120 coated on it, so that the light striking the slant S may have a greater chance to be reflected to the light emergent side This will contribute in increasing the efficiency of the light-emitting diode chip, as well as in preventing the color temperature or saturation of the emergent light being affected by light leakage.
- the metal circuit layer 100 can also be used as a reflector when bonded to the wafer layer 40 , to further reduce the loss of light when transmitting.
- the slant S is V-shaped, which can be easily achieved by line or linear cutting. It is understood that the slant S can also be shaped in other declining plane or surface.
- the wafer layer 40 can be a sapphire layer.
- the fluorescent layer 20 is a light conversion layer with a phosphor-mixed ratio.
- the monochromatic light emitted from the light-emitting diode chip of a sapphire layer can be converted into white light on passing through the fluorescent layer 20 .
- the color temperature or saturation of the emergent light can be adjusted by changing the kinds of phosphorescent materials, or the mixing ratio of phosphorescent materials, or the thickness of the fluorescent layer 20 .
- the protective film 120 can be made of silicon oxide, silicon nitride, or a combination of them to form a passivation layer for protecting the metal circuit layer 100 .
- the metal circuit layer 100 can be compounded by multi-layers of patterned metal wires.
- a method for manufacturing light-emitting diode chip packages comprises the following steps.
- step S 1 growing parts are deposited along a predetermined direction on a wafer layer 40 to form a light emitting diode chip C.
- the light-emitting diode chip C is a GaN-based light-emitting diode chip, in which case the step S 1 specifically comprises step S 101 and step S 102 as follows.
- step S 101 a GaN layer 50 , an n-type GaN layer 60 , a quantum layer 70 , and a p-type GaN layer 80 are sequentially grown along the predetermined direction on a wafer layer 40 ;
- step S 102 fixing gaps are opened by etching the GaN layer 50 , the n-type GaN layer 60 , the quantum layer 70 , and the p-type GaN layer 80 to draw out the electrodes of the light-emitting diode chip C.
- a transparent layer 10 is bonded to the wafer layer 40 , wherein the transparent layer 10 is precoated with a fluorescent layer 20 .
- the transparent layer 10 can be bonded to the wafer layer 40 via a bonding layer 30 disposed between them. Alignment equipment is not necessary since there is no precision alignment required in the bonding procedure.
- the transparent layer 10 and the wafer layer 40 may align with each other by their edges.
- step S 3 outer surfaces of the fluorescent layer 20 and the wafer layer 40 are cut to form a slant S so as to retreat along the predetermined direction.
- the slant S may be in V-shaped, which can be easily processed by linear cutting, or the slant S may also be shaped in another declining plane or surface, as long as the light striking the slant S is reflected to the light emergent side.
- step S 4 a dielectric layer 90 , a metal circuit layer 100 and a protective film 120 are sequentially coated on the slant S along the predetermined direction.
- the slant S can be used as a reflector together with the metal circuit layer 100 .
- conductive blocks 110 are formed on the wafer layer 40 to draw out the electrodes of the light-emitting diode chip C.
- the conductive blocks 110 may be formed by soldering or bumping process, or by gold lugs soldered to the wafer layer 40 .
- the wafer layer 40 in the step S 1 may be a sapphire wafer slice. Cutting positions are preset on the fluorescent layer and the wafer layer in step S 3 in accordance with the required dimensions of a light-emitting diode chip package, and further step S 6 after step S 5 is as follows.
- step S 6 individual light-emitting diode chip packages are obtained by laser cutting or blade cutting at the preset cutting positions.
- a fracturing procedure may also be involved after the cutting, thereby reducing the clamping processes and improving the productivity.
- the cutting positions and the fixing gaps can be formed at same time in the step S 1 .
- a step S 401 is comprised between the step S 4 and the step S 5 as follows.
- a traceability mark may be added to the protective film 120 to confer traceability on the light-emitting diode chip packages.
- the traceability mark can be formed by laser printing or lithographic printing.
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Abstract
Description
- The subject matter herein generally relates to the field of chip packages, and particularly to light-emitting diode chip packages and methods for manufacturing light-emitting diode chip packages.
- As shown in
FIG. 1 , a conventional white light-emitting diode (LED) chip package formed by a blue LED and a phosphor layer includes anLED chip 3 and asubstrate 5. TheLED chip 3 is soldered on thesubstrate 5 via aconvex element 6. A light-emitting surface of theLED chip 3 is coated with aphosphor layer 2 and then sealed with asilicone lens 1, gaps between theLED chip 3 and thesubstrate 5 being filled withfiller 4. A number of processes are involved in manufacturing the white LED chip package, including preparing asubstrate 5, manufacturing aconvex element 6, soldering anLED chip 3 to thesubstrate 5 with theconvex element 6, coating aphosphor layer 2 to theLED chip 3, and formation ofsilicone lens 1 and others. On account of the complex manufacturing process, the investment cost for the manufacturing equipment is high, meanwhile the white LED chip package takes up much more real estate on a printed circuit board than theLED chip 3. - The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout several views.
-
FIG. 1 is a view illustrating a conventional white LED chip package. -
FIG. 2 is a schematic view of a light-emitting diode chip package of the disclosure. -
FIG. 3 is a partially enlarged view of portion A of the light-emitting diode chip package inFIG. 2 . -
FIG. 4 is a partial schematic view of a light-emitting diode chip package of the disclosure during manufacturing. -
FIG. 5 schematically illustrates a process step in an embodiment for manufacturing light-emitting diode chip package of the disclosure. - It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts have been exaggerated to better illustrate details and features of the present disclosure.
- The term “comprising”when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like.
- As shown in
FIG. 2 andFIG. 3 , a light-emitting diode chip package provided in an embodiment of the disclosure sequentially includes atransparent layer 10, afluorescent layer 20, awafer layer 40, a light-emitting diode chip C, adielectric layer 90, ametal circuit layer 100, aprotective film 120, and a plurality ofconductive blocks 110 along a predetermined direction. Theconductive blocks 110 are used to draw out the electrodes of the light-emitting diode chip C and to assemble pins thereto. Outer surfaces of thefluorescent layer 20 and thewafer layer 40 are shrunk from thefluorescent layer 20 to thewafer layer 40 and form a slant S. Thedielectric layer 90, themetal circuit layer 100, and theprotective film 120 are extended to cover the slant S. To facilitate understanding, the predetermined direction is shown as direction D inFIG. 2 , and in this case, the light-emitting diode chip C is a GaN-based light-emitting diode chip sequentially formed by aGaN layer 50, an n-type GaN layer 60, aquantum layer 70, and a p-type GaN layer 80 along the direction D. The light-emitting diode chip C is provided with gaps corresponding to theconductive blocks 110. Thedielectric layer 90, themetal circuit layer 100, and theprotective film 120 respectively define openings corresponding to the gaps to expose theconductive blocks 110, to achieve electrical connection to external components via theconductive blocks 110. The light-emitting diode chip C can be chosen from numerous and various structures similar to those described above. - In the embodiment of the disclosure, the
transparent layer 10 is used as a supporting and light-transmitting unit. The monochromatic light emitted from the light-emitting diode chip C can be converted into white light after passing through thefluorescent layer 20 due to the mechanism of fluorescence. Thedielectric layer 90 is provided to prevent short-circuits on thewafer layer 40. The outer surfaces of thefluorescent layer 20 and thewafer layer 40 retreat along the direction D to form a slant S. The slant S can be used as a reflector with themetal circuit layer 100 and theprotective film 120 coated on it, so that the light striking the slant S may have a greater chance to be reflected to the light emergent side This will contribute in increasing the efficiency of the light-emitting diode chip, as well as in preventing the color temperature or saturation of the emergent light being affected by light leakage. Moreover, themetal circuit layer 100 can also be used as a reflector when bonded to thewafer layer 40, to further reduce the loss of light when transmitting. In an illustrated embodiment, the slant S is V-shaped, which can be easily achieved by line or linear cutting. It is understood that the slant S can also be shaped in other declining plane or surface. - In the illustrated embodiment, the
wafer layer 40 can be a sapphire layer. Thefluorescent layer 20 is a light conversion layer with a phosphor-mixed ratio. The monochromatic light emitted from the light-emitting diode chip of a sapphire layer can be converted into white light on passing through thefluorescent layer 20. The color temperature or saturation of the emergent light can be adjusted by changing the kinds of phosphorescent materials, or the mixing ratio of phosphorescent materials, or the thickness of thefluorescent layer 20. - The
protective film 120 can be made of silicon oxide, silicon nitride, or a combination of them to form a passivation layer for protecting themetal circuit layer 100. Themetal circuit layer 100 can be compounded by multi-layers of patterned metal wires. - As shown in
FIG. 4 andFIG. 5 , a method for manufacturing light-emitting diode chip packages comprises the following steps. - In step S1, growing parts are deposited along a predetermined direction on a
wafer layer 40 to form a light emitting diode chip C. In an illustrated embodiment, the light-emitting diode chip C is a GaN-based light-emitting diode chip, in which case the step S1 specifically comprises step S101 and step S102 as follows. - In step S101, a GaN
layer 50, an n-type GaN layer 60, aquantum layer 70, and a p-type GaN layer 80 are sequentially grown along the predetermined direction on awafer layer 40; - In step S102, fixing gaps are opened by etching the
GaN layer 50, the n-type GaN layer 60, thequantum layer 70, and the p-type GaN layer 80 to draw out the electrodes of the light-emitting diode chip C. - In step S2, a
transparent layer 10 is bonded to thewafer layer 40, wherein thetransparent layer 10 is precoated with afluorescent layer 20. In an embodiment, thetransparent layer 10 can be bonded to thewafer layer 40 via abonding layer 30 disposed between them. Alignment equipment is not necessary since there is no precision alignment required in the bonding procedure. Thetransparent layer 10 and thewafer layer 40 may align with each other by their edges. - In step S3, outer surfaces of the
fluorescent layer 20 and thewafer layer 40 are cut to form a slant S so as to retreat along the predetermined direction. The slant S may be in V-shaped, which can be easily processed by linear cutting, or the slant S may also be shaped in another declining plane or surface, as long as the light striking the slant S is reflected to the light emergent side. - In step S4, a
dielectric layer 90, ametal circuit layer 100 and aprotective film 120 are sequentially coated on the slant S along the predetermined direction. The slant S can be used as a reflector together with themetal circuit layer 100. - In step S5,
conductive blocks 110 are formed on thewafer layer 40 to draw out the electrodes of the light-emitting diode chip C. Theconductive blocks 110 may be formed by soldering or bumping process, or by gold lugs soldered to thewafer layer 40. - In an exemplary embodiment of the disclosure, the
wafer layer 40 in the step S1 may be a sapphire wafer slice. Cutting positions are preset on the fluorescent layer and the wafer layer in step S3 in accordance with the required dimensions of a light-emitting diode chip package, and further step S6 after step S5 is as follows. - In step S6, individual light-emitting diode chip packages are obtained by laser cutting or blade cutting at the preset cutting positions. A fracturing procedure may also be involved after the cutting, thereby reducing the clamping processes and improving the productivity. The cutting positions and the fixing gaps can be formed at same time in the step S1.
- In another exemplary embodiment of the disclosure, a step S401 is comprised between the step S4 and the step S5 as follows.
- In step S401, a traceability mark may be added to the
protective film 120 to confer traceability on the light-emitting diode chip packages. The traceability mark can be formed by laser printing or lithographic printing. - The embodiments shown and described above are only examples. Many details are often found in the art such as the other features of a light-emitting diode chip. Therefore, many such details are neither shown nor described. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of the structure and function of the present disclosure, the disclosure is illustrative only, and changes may be made in the detail, including in matters of shape, size, and arrangement of the parts within the principles of the present disclosure, up to and including the full extent established by the broad general meaning of the terms used in the claims. It will therefore be appreciated that the embodiments described above may be modified within the scope of the claims.
Claims (11)
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CN201510867973.XA CN106816513B (en) | 2015-11-30 | 2015-11-30 | The encapsulating structure and its manufacturing method of LED chip |
CN201510867973 | 2015-11-30 | ||
CN201510867973.X | 2015-11-30 |
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US20170155019A1 true US20170155019A1 (en) | 2017-06-01 |
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US5702982A (en) * | 1996-03-28 | 1997-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits |
TW552726B (en) * | 2001-07-26 | 2003-09-11 | Matsushita Electric Works Ltd | Light emitting device in use of LED |
JP3822551B2 (en) * | 2002-09-30 | 2006-09-20 | 日本碍子株式会社 | Light emitting device and field emission display including the same |
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2015
- 2015-11-30 CN CN201510867973.XA patent/CN106816513B/en not_active Expired - Fee Related
-
2016
- 2016-05-10 TW TW105114368A patent/TW201733158A/en unknown
- 2016-05-26 US US15/166,220 patent/US9685595B1/en not_active Expired - Fee Related
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CN106816513A (en) | 2017-06-09 |
TW201733158A (en) | 2017-09-16 |
US9685595B1 (en) | 2017-06-20 |
CN106816513B (en) | 2019-06-28 |
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