US20170148894A1 - Replacement low-k spacer - Google Patents
Replacement low-k spacer Download PDFInfo
- Publication number
- US20170148894A1 US20170148894A1 US14/952,549 US201514952549A US2017148894A1 US 20170148894 A1 US20170148894 A1 US 20170148894A1 US 201514952549 A US201514952549 A US 201514952549A US 2017148894 A1 US2017148894 A1 US 2017148894A1
- Authority
- US
- United States
- Prior art keywords
- low
- spacer portion
- spacer
- dummy gate
- gate stack
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 125000006850 spacer group Chemical group 0.000 title claims abstract description 143
- 238000000034 method Methods 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 230000002093 peripheral effect Effects 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 29
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 22
- 230000008021 deposition Effects 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 17
- 239000010410 layer Substances 0.000 description 39
- 239000000463 material Substances 0.000 description 36
- 230000015572 biosynthetic process Effects 0.000 description 15
- 150000004767 nitrides Chemical class 0.000 description 12
- 239000003989 dielectric material Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- -1 i.e. Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- 229910052582 BN Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910018182 Al—Cu Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910002244 LaAlO3 Inorganic materials 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229920000265 Polyparaphenylene Polymers 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910002370 SrTiO3 Inorganic materials 0.000 description 1
- 229910004491 TaAlN Inorganic materials 0.000 description 1
- 229910010303 TiOxNy Inorganic materials 0.000 description 1
- 229910003134 ZrOx Inorganic materials 0.000 description 1
- CFOAUMXQOCBWNJ-UHFFFAOYSA-N [B].[Si] Chemical compound [B].[Si] CFOAUMXQOCBWNJ-UHFFFAOYSA-N 0.000 description 1
- ZILJFRYKLPPLTO-UHFFFAOYSA-N [C].[B].[Si] Chemical compound [C].[B].[Si] ZILJFRYKLPPLTO-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000000224 chemical solution deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000000313 electron-beam-induced deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000007737 ion beam deposition Methods 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 150000001247 metal acetylides Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
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- H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides
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- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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Definitions
- Embodiments of the invention relate to semiconductor structures, in particular, for field effect transistors including low-k spacers for low capacitance and a method of manufacturing the same.
- Fin field effect transistors typically include a source region and a drain region interconnected by fins which serve as a channel region of the device and a gate that surrounds at least a portion of each of the fins between the source region and the drain region. Epitaxial deposition is typically used to form the source region and the drain region.
- a metal-oxide semiconductor (MOS) FET (MOSFET) pitch of the transistors scales down (e.g., under 100 nm) and a thickness of a silicon nitride spacer of a gate structure also scales to provide a large enough contact area for a source/drain.
- MOS metal-oxide semiconductor
- a thinner spacer induces higher parasitic capacitance that can reduce processing speed.
- the parasitic capacitance may cause slower ring oscillator (RO) speed and eventually lower circuit working frequency.
- C EFF effective capacitance
- circuit performance may degrade and there may be higher power consumption during dynamic operation.
- low-k dielectrics i.e., materials with a dielectric constant lower than silicon nitride, may be used to form the gate spacer.
- Typical low-k materials include SiBN, SiCN and SiBCN.
- a low-k dielectric is conformally deposited and then etched using an anisotropic etch process such as reactive ion etching (RIE).
- RIE reactive ion etching
- An issue with a low-k spacer first results in Carbon/Boron loss during spacer reactive ion etch (RIE) and epitaxial deposition, which can increase the value of K.
- a low-k spacer-last process can be used, where a sacrificial spacer, such as silicon nitride, is first formed, and is subsequently removed after all high temperature processes (typically >600° C.) in the integration flow are executed.
- the gap formed as a result of sacrificial spacer removal is then filled with a low-K dielectric.
- a low-k spacer-last is that the aspect ratio (a structure's height relative to its width) of the sacrificial spacer is too high, and it is not easy to etch down the sacrificial spacer without damaging the oxide inter-layer dielectric (ILD) and dummy polysilicon gate.
- ILD oxide inter-layer dielectric
- a semiconductor structure includes a dummy gate stack formed on a substrate including a sacrificial spacer on the peripheral of the dummy gate stack.
- the dummy gate stack is partially recessed.
- the sacrificial spacer is etched down to the partially recessed dummy gate stack. Remaining portions of the sacrificial spacer are etched leaving gaps around and above a remaining portion of the dummy gate stack.
- a first low-k spacer portion and a second low-k spacer portion are formed to fill gaps around the dummy gate stack and extend vertically along a sidewall of a dummy gate cavity.
- the first low-k spacer portion and the second low-k spacer portion are etched.
- a poly pull process is performed on the dummy gate stack.
- a replacement metal gate (RMG) structure is formed with the first low-k spacer portion and the second low-k spacer portion.
- a method of forming a semiconductor includes forming a dummy gate stack on a substrate including a sacrificial spacer on the peripheral of the dummy gate stack.
- the dummy gate stack is partially recessed.
- the sacrificial spacer is etched down to the partially recessed dummy gate stack. Remaining portions of the sacrificial spacer are etched leaving gaps around and above a remaining portion of the dummy gate stack.
- a first low-k spacer portion and a second low-k spacer portion are formed to fill gaps around the remaining portions of the dummy gate stack and extend vertically along a sidewall of a dummy gate cavity.
- the first low-k spacer portion and the second low-k spacer portion are etched.
- a poly pull process is performed on the remaining portions of the dummy gate stack.
- An RMG structure is formed with the first low-k spacer portion and the second low-k spacer portion.
- a method of forming a semiconductor includes etching a sacrificial spacer down to a partially recessed dummy gate stack formed on a substrate.
- a first low-k spacer portion and a second low-k spacer portion are formed to fill gaps around the dummy gate stack and extend vertically along a sidewall of a dummy gate cavity.
- the first low-k spacer portion and the second low-k spacer portion are etched.
- a poly pull process is performed on the dummy gate stack. Multiple depositions are performed to form an RMG structure with the first low-k spacer portion and the second low-k spacer portion.
- FIG. 1 is a cross-sectional view of an exemplary structure after formation of a deposited and patterned dummy gate stack on a substrate according to an embodiment
- FIG. 2 is a cross-sectional view of the exemplary structure after formation of sacrificial spacers, according to an embodiment
- FIG. 3 is a cross-sectional view of the exemplary structure after formation of source and drain junctions, according to an embodiment
- FIG. 4 is a cross-sectional view of the exemplary structure after depositing and chemical mechanical planarization (CMP) of inter-layer dielectric (ILD) oxide, according to an embodiment
- FIG. 5 is a cross-sectional view of the exemplary structure after performing a dummy gate stack poly partial recess process, according to an embodiment
- FIG. 6 is a cross-sectional view of the exemplary structure after performing etching on the sacrificial spacers, according to an embodiment
- FIG. 7 is a cross-sectional view of the exemplary structure after performing an over etch removing the sacrificial spacers, according to an embodiment
- FIG. 8 is a cross-sectional view of the exemplary structure after formation low-k spacer deposition, according to an embodiment
- FIG. 9 is a cross-sectional view of the exemplary structure after low-k spacer etching, according to an embodiment of the present disclosure.
- FIG. 10 is a cross-sectional view of the exemplary structure after performing dummy gate stack poly pull process, according to an embodiment
- FIG. 11 is a cross-sectional view of the exemplary structure after performing multiple depositions for forming an RMG stack, according to an embodiment
- FIG. 12 is a cross-sectional view of the exemplary structure after recessing the RMG stack, according to an embodiment
- FIG. 13 is a cross-sectional view of an exemplary structure after depositing a nitride cap and performing CMP to stop on the oxide layer, according to an embodiment
- FIG. 14 is a cross-sectional view of another exemplary structure after etching the low-k spacers and depositing a nitride cap and performing CMP to stop on the oxide layer, according to an embodiment
- FIG. 15 is a cross-sectional view of yet another exemplary structure after depositing a low-k material cap, according to an embodiment.
- FIG. 16 illustrates a block diagram for a process for forming a semiconductor with low-k spacers formed prior to RMG stack formation, according to one embodiment.
- a “lengthwise” element is an element that extends along a corresponding lengthwise direction
- a “widthwise” element is an element that extends along a corresponding widthwise direction
- FIG. 1 is a cross-sectional view of an exemplary structure after formation of a deposited and patterned dummy gate stack on a substrate 100 according to an embodiment.
- the dummy gate stack includes at least a vertical stack of an insulator layer 110 and a semiconductor material layer 120 (e.g., amorphous Si layer, poly-Si layer, etc., as an electrode).
- the substrate 100 may be a semiconductor-on-insulator (SOI) substrate (e.g., fully-depleted SOI, partially depleted SOI, etc.).
- the substrate 100 may be a bulk Fin field effect transistor (FinFET), SOI FinFET, Nanowire, etc.
- FinFET Fin field effect transistor
- the dummy stack may be formed using conventional techniques, such as isolation, deposition and patterning processes.
- the insulator layer 110 may include exemplary dielectric materials, for example include, silicon oxide, silicon nitride, and silicon oxynitride.
- the thickness of the insulator layer 110 can be from 1 nm to 5 nm, although lesser and greater thicknesses can also be employed.
- FIG. 2 is a cross-sectional view of the exemplary structure after formation of sacrificial spacers including at least a first sacrificial spacer portion 210 and a second sacrificial spacer portion 211 , according to an embodiment.
- the sacrificial spacers are formed by conformal deposition of a dielectric material layer (e.g., silicon nitride) and performing an anisotropic etch process that removes horizontal portions of the dielectric material layer.
- the sacrificial spacers may have a thickness in a range from 5 nm to 20 nm, although lesser and greater thicknesses may also be employed.
- FIG. 3 is a cross-sectional view of the exemplary structure after formation of source junction 310 and a drain junction 320 , according to an embodiment.
- an ion implant, growth of epitaxial layers, etc. may be employed to form the source junction 310 and the drain junction 320 .
- the source junction and the drain junction are raised source/drain junctions (as shown in FIG. 3 ).
- FIG. 4 is a cross-sectional view of the exemplary structure after depositing and chemical mechanical planarization (CMP) of inter layer dielectric (ILD) oxide layer portions 410 and 411 , according to an embodiment.
- CMP chemical mechanical planarization
- the CMP stops on the semiconductor material layer 120 .
- the semiconductor material layer 120 may have a cap layer (e.g., nitride) on top (e.g., on top of poly-silicon).
- CMP may be used to polish ILD layer portions 410 and 411 to be substantially flat with the top of the nitride cap.
- an additional optional CMP may be used to make ILD oxide layer portions 410 and 411 flat with the top of the semiconductor material layer 120 (e.g., poly-silicon).
- the resulting structure at this point is the same whether or not a nitride cap is used in the process flow.
- FIG. 5 is a cross-sectional view of the exemplary structure after performing a dummy gate stack poly partial recess process, according to an embodiment.
- the poly partial recess process forms a partial recess 510 by removal of a portion of the semiconductor material layer 120 of the dummy gate stack leaving the remaining portion 520 of the semiconductor material layer 120 .
- FIG. 6 is a cross-sectional view of the exemplary structure after performing etching on the first sacrificial spacer portion 210 and the second sacrificial spacer portion 211 , according to an embodiment.
- the etching of the first sacrificial spacer portion 210 and the second sacrificial spacer portion 211 removes the sacrificial spacer material down to the remaining portion 520 of the dummy gate stack.
- the remaining sacrificial spacer portions 610 and 611 have a height at or near the height of the remaining portion 520 .
- FIG. 7 is a cross-sectional view of the exemplary structure after performing an over etch removing the sacrificial spacer remaining portions 610 and 611 , according to an embodiment.
- recesses (or gaps) 710 and 711 are formed after the over etch.
- the recess of the semiconductor layer 120 and the etching of the first sacrificial spacer portion 210 and a second sacrificial spacer portion 211 , and then over etch of the sacrificial spacer remaining portions 610 and 611 are easy to perform as the aspect ratio was reduced.
- the aspect ratio refers to a structure's height relative to its width. Structures on the substrate 100 can be characterized by an aspect ratio. Defined spaces, such as trenches, holes, vias, etc., can also be defined by an aspect ratio. As can be seen, the over etch leaves the gaps around and above the remaining portion 520 .
- FIG. 8 is a top-down view of the exemplary structure after formation low-k spacer deposition, according to an embodiment.
- a low-k spacer material 810 is deposited through any suitable techniques such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and spin-on coating into the recesses 710 and 711 , over the remaining portion 520 , and on the top of and inter portions of the oxide layers 410 and 411 .
- CVD chemical vapor deposition
- ALD atomic layer deposition
- spin-on coating into the recesses 710 and 711 , over the remaining portion 520 , and on the top of and inter portions of the oxide layers 410 and 411 .
- a low-k spacer(s) are formed to fill gaps around the remaining portion 520 and extending vertically along the sidewall of the gate cavity.
- a low-k spacer is a spacer having a dielectric constant less than the dielectric constant of silicon nitride at room temperature, e.g., 7.0 or less, and preferably about, e.g., 5.0.
- low-k materials may include, but are not limited to, silicon boron nitride (SiBN), silicon carbon nitride (SiCN), silicon boron carbon nitride (SiBCN), hydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane polymer (MSQ), polyphenylene oligomer, methyl doped silica or Si0x(CH3)y, SiCxOyHy or SiOCH, organosilicate glass (SiCOH) and porous SiCOH, silicon oxide, boron nitride, silicon oxynitride, etc.
- SiBN silicon boron nitride
- SiCN silicon carbon nitride
- SiBCN silicon boron carbon nitride
- HQ hydrogen silsesquioxane polymer
- MSQ methyl silsesquioxane polymer
- polyphenylene oligomer methyl doped silica or Si0
- FIG. 9 is a cross-sectional view of the exemplary structure after low-k spacer etching, according to an embodiment of the present disclosure.
- the low-k spacer material 810 is etched on the side walls and down below the remaining portion 520 to create a profile for the remaining low-k material 910 , which is also removed from the top of the oxide layers 410 and 411 .
- the profile that is created from the low-k spacer material etch is in such a way that the cavity 510 formed between the remaining low-k material 910 is wider at its top than its bottom and is ideal for work function metal (WFM) fill and multiple depositions that are performed later for creation of the RMG structure.
- WFM work function metal
- the remaining low-k material 910 includes a first low-k spacer portion that has a constant width from a top portion to a bottom portion, and a second low-k spacer portion that has a width that tapers from a bottom portion to a top portion.
- FIG. 10 is a cross-sectional view of the exemplary structure after performing dummy gate stack poly pull process, according to an embodiment.
- the remaining portion 520 from the dummy gate stack is pulled and removed from the structure leaving the recess 1010 .
- the recess 1010 is wider at its top than its bottom and is ideal for work function metal (WFM) fill and multiple depositions that are performed later for creation of the RMG structure.
- WFM work function metal
- FIG. 11 is a cross-sectional view of the exemplary structure after performing multiple depositions for forming an RMG stack, according to an embodiment.
- the RMG stack 1120 is formed after the low-k etching creating the remaining low-k material 910 from processes, such as high-k gate dielectric deposition, WFM (e.g., TiN, TaN, TaAlN, etc.) deposition, low resistance metal (e.g. Al, W, etc.) deposition, CMP stopping on ILD oxide of the oxide layers 1110 and 1111 , etc.
- WFM e.g., TiN, TaN, TaAlN, etc.
- low resistance metal e.g. Al, W, etc.
- the low-k remaining portion 910 forms the low-k spacers for the RMG structure. It is noted that the RMG materials are not depicted separately for simplicity, but should be understood by contemporary RMG formation processing.
- the gate dielectric of the RMG stack 1120 is composed of a high-k material having a dielectric constant greater than silicon oxide.
- exemplary high-k materials include, but are not limited to, HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfOxNy, ZrO x La 2 O x N y , Al 2 OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y 2 0xNy, SiON, SiNx, a silicate thereof, and an alloy thereof.
- Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2.
- the gate cavity formed with the multiple depositions, etc. to form the RMG stack 1120 may be filled with at least one conductive material, such as at least one metallic material and/or at least one doped semiconductor material.
- the conductive metal include, but are not limited to, Al, W, Cu, Pt, Ag, Au, Ru, Ir, Rh and Re, alloys of a conductive metal, e.g., Al—Cu, metal nitrides or carbides such as AN, TiN, TaN, TiC and TaC, silicides of a conductive metal, e.g., W silicide, and Pt silicide, and combinations thereof.
- the gate electrode of the RMG stack 1120 can be formed by depositing the conductive material utilizing a conventional deposition process such as, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), physical vapor deposition (PVD), sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, and chemical solution deposition.
- ALD atomic layer deposition
- CVD chemical vapor deposition
- MOCVD metalorganic chemical vapor deposition
- MBE molecular beam epitaxy
- PVD physical vapor deposition
- sputtering plating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, and chemical solution deposition.
- FIG. 12 is a cross-sectional view of the exemplary structure after recessing the RMG stack 1120 , according to an embodiment.
- the RMG stack 1120 is reduced to the remaining completed RMG stack 1220 by using a wet or dry etch on the metal material.
- the etching removes a portion of the RMG stack 1120 to make room for a cap as follows.
- FIG. 13 is a cross-sectional view of an exemplary structure after depositing a nitride cap 1320 and performing CMP to stop on the oxide layers 1110 and 1111 , according to an embodiment.
- a nitride cap 1320 is deposited and then CMP is stopped on the oxide layers 1110 and 1111 within the vertically profiled low-k spacer material 910 that surrounds the nitride cap 1320 (e.g., silicon nitride, etc.). Also shown are the source junction 1310 and a drain junction 1320 .
- FIG. 14 is a cross-sectional view of another exemplary structure after etching the low-k spacer material 910 and depositing a nitride cap 1420 and performing CMP to stop on the oxide layers 1110 and 1111 , according to an embodiment.
- the low-k spacer material 910 is etched after the completed RMG stack 1220 is recessed.
- the nitride cap 1420 e.g., silicon nitride, etc.
- completely covers the completed RMG stack 1220 which is robust for self-aligned contact formation.
- FIG. 15 is a cross-sectional view of yet another exemplary structure after depositing and etching a low-k spacer material 910 , according to an embodiment.
- a low-k dielectric material is deposited on to the low-k spacer material 910 and used as a cap 1520 to lower the capacitance.
- the low-k cap 1520 material may be the same or different than the low-k spacer 910 material.
- one or more embodiments form the low-k spacer material 910 prior to forming the completed RMG stack 1220 .
- Conventional processing exposes the RMG stack to the spacer replacement process steps, which is avoided by the processing of one or more embodiments. Removal of all the sacrificial layers entails dealing with a high aspect ratio for reactive ion etch (RIE)/etch issues, which is bypassed by the processing of one or more embodiments.
- RIE reactive ion etch
- FIG. 16 illustrates a block diagram for a process 1600 for forming a semiconductor structure, according to one embodiment.
- a dummy gate stack is formed on a substrate (e.g., substrate 100 , FIG. 1 ) including a sacrificial spacer material deposited (e.g., sacrificial spacer portions 210 and 211 , FIG. 2 ) on the peripheral of the dummy gate stack.
- the dummy gate stack is partially recessed.
- the sacrificial spacer is etched down (resulting in remaining sacrificial spacer portions 610 and 611 , FIG. 6 ) to the partially recessed dummy gate stack.
- remaining portions of the sacrificial spacer is etched leaving gaps around and above a remaining portion of the dummy gate stack.
- a first low-k spacer portion and a second low-k spacer portion are formed to fill gaps around the remaining portions of the dummy gate stack and extending vertically along a sidewall of a dummy gate cavity.
- the first low-k spacer portion and the second low-k spacer portion are etched.
- a poly pull process is performed on the remaining portions of the dummy gate stack.
- an RMG structure e.g., RMG stack 1120 , FIG. 11 , completed RMG stack 1220 , FIG. 12
- the first low-k spacer portion and the second low-k spacer portion which are already formed prior to the RMG structure formation).
- process 1600 may provide that forming the dummy gate stack includes forming a source junction on the substrate adjacent the first dielectric spacer portion and a drain junction on the substrate adjacent the second dielectric spacer portion, and depositing an oxide layer over the source junction and the drain junction.
- process 1600 may include forming a silicon nitride cap layer over the RMG structure and between the first low-k spacer portion and the second low-k spacer portion, and performing CMP to reduce a height of the silicon nitride cap layer down to the oxide layer.
- process 1600 may include forming a silicon nitride cap layer over the RMG structure, and performing CMP to reduce a height of the silicon nitride cap layer to the oxide layer (where the silicon nitride cap layer completely covers the RMG structure).
- process 1600 may further include forming a low-k cap layer over the RMG structure and adjacent to the first low-k spacer portion and the second low-k spacer portion, where a height of the low-k cap layer is reduced to the oxide layer.
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Abstract
Description
- Embodiments of the invention relate to semiconductor structures, in particular, for field effect transistors including low-k spacers for low capacitance and a method of manufacturing the same.
- Fin field effect transistors (FinFETs) typically include a source region and a drain region interconnected by fins which serve as a channel region of the device and a gate that surrounds at least a portion of each of the fins between the source region and the drain region. Epitaxial deposition is typically used to form the source region and the drain region. As transistors continue to be reduced in size and have an increased number of transistors per unit of microchip, a metal-oxide semiconductor (MOS) FET (MOSFET) pitch of the transistors scales down (e.g., under 100 nm) and a thickness of a silicon nitride spacer of a gate structure also scales to provide a large enough contact area for a source/drain. A thinner spacer induces higher parasitic capacitance that can reduce processing speed. The parasitic capacitance may cause slower ring oscillator (RO) speed and eventually lower circuit working frequency. With higher effective capacitance (CEFF) of RO, circuit performance may degrade and there may be higher power consumption during dynamic operation. In order to reduce CEFF, low-k dielectrics, i.e., materials with a dielectric constant lower than silicon nitride, may be used to form the gate spacer. Typical low-k materials include SiBN, SiCN and SiBCN. Two integration processes can be used to integrate low-k dielectrics as a gate spacer. In a low-k spacer-first approach, after gate deposition and etch, a low-k dielectric is conformally deposited and then etched using an anisotropic etch process such as reactive ion etching (RIE). An issue with a low-k spacer first results in Carbon/Boron loss during spacer reactive ion etch (RIE) and epitaxial deposition, which can increase the value of K. Alternatively, a low-k spacer-last process can be used, where a sacrificial spacer, such as silicon nitride, is first formed, and is subsequently removed after all high temperature processes (typically >600° C.) in the integration flow are executed. The gap formed as a result of sacrificial spacer removal is then filled with a low-K dielectric. An issue with a low-k spacer-last is that the aspect ratio (a structure's height relative to its width) of the sacrificial spacer is too high, and it is not easy to etch down the sacrificial spacer without damaging the oxide inter-layer dielectric (ILD) and dummy polysilicon gate.
- One or more embodiments relate to field effect transistors including low-k spacers for low capacitance and a method of manufacturing the same. In one embodiment, a semiconductor structure includes a dummy gate stack formed on a substrate including a sacrificial spacer on the peripheral of the dummy gate stack. The dummy gate stack is partially recessed. The sacrificial spacer is etched down to the partially recessed dummy gate stack. Remaining portions of the sacrificial spacer are etched leaving gaps around and above a remaining portion of the dummy gate stack. A first low-k spacer portion and a second low-k spacer portion are formed to fill gaps around the dummy gate stack and extend vertically along a sidewall of a dummy gate cavity. The first low-k spacer portion and the second low-k spacer portion are etched. A poly pull process is performed on the dummy gate stack. A replacement metal gate (RMG) structure is formed with the first low-k spacer portion and the second low-k spacer portion.
- In another embodiment, a method of forming a semiconductor includes forming a dummy gate stack on a substrate including a sacrificial spacer on the peripheral of the dummy gate stack. The dummy gate stack is partially recessed. The sacrificial spacer is etched down to the partially recessed dummy gate stack. Remaining portions of the sacrificial spacer are etched leaving gaps around and above a remaining portion of the dummy gate stack. A first low-k spacer portion and a second low-k spacer portion are formed to fill gaps around the remaining portions of the dummy gate stack and extend vertically along a sidewall of a dummy gate cavity. The first low-k spacer portion and the second low-k spacer portion are etched. A poly pull process is performed on the remaining portions of the dummy gate stack. An RMG structure is formed with the first low-k spacer portion and the second low-k spacer portion.
- In one embodiment, a method of forming a semiconductor includes etching a sacrificial spacer down to a partially recessed dummy gate stack formed on a substrate. A first low-k spacer portion and a second low-k spacer portion are formed to fill gaps around the dummy gate stack and extend vertically along a sidewall of a dummy gate cavity. The first low-k spacer portion and the second low-k spacer portion are etched. A poly pull process is performed on the dummy gate stack. Multiple depositions are performed to form an RMG structure with the first low-k spacer portion and the second low-k spacer portion.
- These and other features, aspects and advantages of the present invention will become understood with reference to the following description, appended claims and accompanying figures.
-
FIG. 1 is a cross-sectional view of an exemplary structure after formation of a deposited and patterned dummy gate stack on a substrate according to an embodiment; -
FIG. 2 is a cross-sectional view of the exemplary structure after formation of sacrificial spacers, according to an embodiment; -
FIG. 3 is a cross-sectional view of the exemplary structure after formation of source and drain junctions, according to an embodiment; -
FIG. 4 is a cross-sectional view of the exemplary structure after depositing and chemical mechanical planarization (CMP) of inter-layer dielectric (ILD) oxide, according to an embodiment; -
FIG. 5 is a cross-sectional view of the exemplary structure after performing a dummy gate stack poly partial recess process, according to an embodiment; -
FIG. 6 . is a cross-sectional view of the exemplary structure after performing etching on the sacrificial spacers, according to an embodiment; -
FIG. 7 is a cross-sectional view of the exemplary structure after performing an over etch removing the sacrificial spacers, according to an embodiment; -
FIG. 8 is a cross-sectional view of the exemplary structure after formation low-k spacer deposition, according to an embodiment; -
FIG. 9 is a cross-sectional view of the exemplary structure after low-k spacer etching, according to an embodiment of the present disclosure; -
FIG. 10 is a cross-sectional view of the exemplary structure after performing dummy gate stack poly pull process, according to an embodiment; -
FIG. 11 is a cross-sectional view of the exemplary structure after performing multiple depositions for forming an RMG stack, according to an embodiment; -
FIG. 12 is a cross-sectional view of the exemplary structure after recessing the RMG stack, according to an embodiment; -
FIG. 13 is a cross-sectional view of an exemplary structure after depositing a nitride cap and performing CMP to stop on the oxide layer, according to an embodiment; -
FIG. 14 is a cross-sectional view of another exemplary structure after etching the low-k spacers and depositing a nitride cap and performing CMP to stop on the oxide layer, according to an embodiment; -
FIG. 15 is a cross-sectional view of yet another exemplary structure after depositing a low-k material cap, according to an embodiment; and -
FIG. 16 illustrates a block diagram for a process for forming a semiconductor with low-k spacers formed prior to RMG stack formation, according to one embodiment. - The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
- As used herein, a “lengthwise” element is an element that extends along a corresponding lengthwise direction, and a “widthwise” element is an element that extends along a corresponding widthwise direction.
-
FIG. 1 is a cross-sectional view of an exemplary structure after formation of a deposited and patterned dummy gate stack on asubstrate 100 according to an embodiment. In one example, the dummy gate stack includes at least a vertical stack of aninsulator layer 110 and a semiconductor material layer 120 (e.g., amorphous Si layer, poly-Si layer, etc., as an electrode). In one embodiment, thesubstrate 100 may be a semiconductor-on-insulator (SOI) substrate (e.g., fully-depleted SOI, partially depleted SOI, etc.). In other embodiments, thesubstrate 100 may be a bulk Fin field effect transistor (FinFET), SOI FinFET, Nanowire, etc. In one embodiment, the dummy stack may be formed using conventional techniques, such as isolation, deposition and patterning processes. In one embodiment, theinsulator layer 110 may include exemplary dielectric materials, for example include, silicon oxide, silicon nitride, and silicon oxynitride. The thickness of theinsulator layer 110 can be from 1 nm to 5 nm, although lesser and greater thicknesses can also be employed. -
FIG. 2 is a cross-sectional view of the exemplary structure after formation of sacrificial spacers including at least a firstsacrificial spacer portion 210 and a secondsacrificial spacer portion 211, according to an embodiment. In one embodiment, the sacrificial spacers are formed by conformal deposition of a dielectric material layer (e.g., silicon nitride) and performing an anisotropic etch process that removes horizontal portions of the dielectric material layer. In one embodiment, the sacrificial spacers may have a thickness in a range from 5 nm to 20 nm, although lesser and greater thicknesses may also be employed. -
FIG. 3 is a cross-sectional view of the exemplary structure after formation ofsource junction 310 and adrain junction 320, according to an embodiment. In one embodiment, an ion implant, growth of epitaxial layers, etc., may be employed to form thesource junction 310 and thedrain junction 320. In one example, the source junction and the drain junction are raised source/drain junctions (as shown inFIG. 3 ). -
FIG. 4 is a cross-sectional view of the exemplary structure after depositing and chemical mechanical planarization (CMP) of inter layer dielectric (ILD)oxide layer portions semiconductor material layer 120. In some embodiments, the semiconductor material layer 120 (gate electrode) may have a cap layer (e.g., nitride) on top (e.g., on top of poly-silicon). In one example, CMP may be used to polishILD layer portions oxide layer portions -
FIG. 5 is a cross-sectional view of the exemplary structure after performing a dummy gate stack poly partial recess process, according to an embodiment. In one embodiment, the poly partial recess process forms apartial recess 510 by removal of a portion of thesemiconductor material layer 120 of the dummy gate stack leaving the remainingportion 520 of thesemiconductor material layer 120. -
FIG. 6 is a cross-sectional view of the exemplary structure after performing etching on the firstsacrificial spacer portion 210 and the secondsacrificial spacer portion 211, according to an embodiment. In one embodiment, the etching of the firstsacrificial spacer portion 210 and the secondsacrificial spacer portion 211 removes the sacrificial spacer material down to the remainingportion 520 of the dummy gate stack. In one example, the remainingsacrificial spacer portions portion 520. -
FIG. 7 is a cross-sectional view of the exemplary structure after performing an over etch removing the sacrificialspacer remaining portions semiconductor layer 120 and the etching of the firstsacrificial spacer portion 210 and a secondsacrificial spacer portion 211, and then over etch of the sacrificialspacer remaining portions substrate 100 can be characterized by an aspect ratio. Defined spaces, such as trenches, holes, vias, etc., can also be defined by an aspect ratio. As can be seen, the over etch leaves the gaps around and above the remainingportion 520. -
FIG. 8 is a top-down view of the exemplary structure after formation low-k spacer deposition, according to an embodiment. In one embodiment, a low-k spacer material 810 is deposited through any suitable techniques such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and spin-on coating into therecesses portion 520, and on the top of and inter portions of the oxide layers 410 and 411. Thus, a low-k spacer(s) are formed to fill gaps around the remainingportion 520 and extending vertically along the sidewall of the gate cavity. In one embodiment, a low-k spacer is a spacer having a dielectric constant less than the dielectric constant of silicon nitride at room temperature, e.g., 7.0 or less, and preferably about, e.g., 5.0. Some examples of low-k materials may include, but are not limited to, silicon boron nitride (SiBN), silicon carbon nitride (SiCN), silicon boron carbon nitride (SiBCN), hydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane polymer (MSQ), polyphenylene oligomer, methyl doped silica or Si0x(CH3)y, SiCxOyHy or SiOCH, organosilicate glass (SiCOH) and porous SiCOH, silicon oxide, boron nitride, silicon oxynitride, etc. -
FIG. 9 is a cross-sectional view of the exemplary structure after low-k spacer etching, according to an embodiment of the present disclosure. In one embodiment, the low-k spacer material 810 is etched on the side walls and down below the remainingportion 520 to create a profile for the remaining low-k material 910, which is also removed from the top of the oxide layers 410 and 411. In one embodiment, the profile that is created from the low-k spacer material etch is in such a way that thecavity 510 formed between the remaining low-k material 910 is wider at its top than its bottom and is ideal for work function metal (WFM) fill and multiple depositions that are performed later for creation of the RMG structure. In one embodiment, the remaining low-k material 910 includes a first low-k spacer portion that has a constant width from a top portion to a bottom portion, and a second low-k spacer portion that has a width that tapers from a bottom portion to a top portion. -
FIG. 10 is a cross-sectional view of the exemplary structure after performing dummy gate stack poly pull process, according to an embodiment. In one embodiment, the remainingportion 520 from the dummy gate stack is pulled and removed from the structure leaving therecess 1010. Therecess 1010 is wider at its top than its bottom and is ideal for work function metal (WFM) fill and multiple depositions that are performed later for creation of the RMG structure. -
FIG. 11 is a cross-sectional view of the exemplary structure after performing multiple depositions for forming an RMG stack, according to an embodiment. In one embodiment, theRMG stack 1120 is formed after the low-k etching creating the remaining low-k material 910 from processes, such as high-k gate dielectric deposition, WFM (e.g., TiN, TaN, TaAlN, etc.) deposition, low resistance metal (e.g. Al, W, etc.) deposition, CMP stopping on ILD oxide of theoxide layers k remaining portion 910 forms the low-k spacers for the RMG structure. It is noted that the RMG materials are not depicted separately for simplicity, but should be understood by contemporary RMG formation processing. - In one embodiment, the gate dielectric of the
RMG stack 1120 is composed of a high-k material having a dielectric constant greater than silicon oxide. Exemplary high-k materials include, but are not limited to, HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfOxNy, ZrOx La2OxNy, Al2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y20xNy, SiON, SiNx, a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2. - In one embodiment, the gate cavity formed with the multiple depositions, etc. to form the
RMG stack 1120 may be filled with at least one conductive material, such as at least one metallic material and/or at least one doped semiconductor material. Examples of the conductive metal include, but are not limited to, Al, W, Cu, Pt, Ag, Au, Ru, Ir, Rh and Re, alloys of a conductive metal, e.g., Al—Cu, metal nitrides or carbides such as AN, TiN, TaN, TiC and TaC, silicides of a conductive metal, e.g., W silicide, and Pt silicide, and combinations thereof. The gate electrode of theRMG stack 1120 can be formed by depositing the conductive material utilizing a conventional deposition process such as, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), physical vapor deposition (PVD), sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, and chemical solution deposition. -
FIG. 12 is a cross-sectional view of the exemplary structure after recessing theRMG stack 1120, according to an embodiment. In one embodiment, theRMG stack 1120 is reduced to the remaining completedRMG stack 1220 by using a wet or dry etch on the metal material. In one embodiment, the etching removes a portion of theRMG stack 1120 to make room for a cap as follows. -
FIG. 13 is a cross-sectional view of an exemplary structure after depositing anitride cap 1320 and performing CMP to stop on theoxide layers RMG stack 1220 formation, anitride cap 1320 is deposited and then CMP is stopped on theoxide layers k spacer material 910 that surrounds the nitride cap 1320 (e.g., silicon nitride, etc.). Also shown are thesource junction 1310 and adrain junction 1320. -
FIG. 14 is a cross-sectional view of another exemplary structure after etching the low-k spacer material 910 and depositing anitride cap 1420 and performing CMP to stop on theoxide layers k spacer material 910 is etched after the completedRMG stack 1220 is recessed. In one embodiment, the nitride cap 1420 (e.g., silicon nitride, etc.) completely covers the completedRMG stack 1220, which is robust for self-aligned contact formation. -
FIG. 15 is a cross-sectional view of yet another exemplary structure after depositing and etching a low-k spacer material 910, according to an embodiment. In one embodiment, after the completedRMG stack 1220 is recessed, a low-k dielectric material is deposited on to the low-k spacer material 910 and used as acap 1520 to lower the capacitance. In one embodiment, the low-k cap 1520 material may be the same or different than the low-k spacer 910 material. - Unlike conventional replacement spacer formation processes, one or more embodiments form the low-
k spacer material 910 prior to forming the completedRMG stack 1220. Conventional processing exposes the RMG stack to the spacer replacement process steps, which is avoided by the processing of one or more embodiments. Removal of all the sacrificial layers entails dealing with a high aspect ratio for reactive ion etch (RIE)/etch issues, which is bypassed by the processing of one or more embodiments. -
FIG. 16 illustrates a block diagram for aprocess 1600 for forming a semiconductor structure, according to one embodiment. In one embodiment, in block 1610 a dummy gate stack is formed on a substrate (e.g.,substrate 100,FIG. 1 ) including a sacrificial spacer material deposited (e.g.,sacrificial spacer portions FIG. 2 ) on the peripheral of the dummy gate stack. Inblock 1620 the dummy gate stack is partially recessed. Inblock 1630, the sacrificial spacer is etched down (resulting in remainingsacrificial spacer portions FIG. 6 ) to the partially recessed dummy gate stack. In one embodiment, inblock 1640 remaining portions of the sacrificial spacer is etched leaving gaps around and above a remaining portion of the dummy gate stack. - In one embodiment, in block 1650 a first low-k spacer portion and a second low-k spacer portion (e.g., the low-
k material 810,FIG. 8 ) are formed to fill gaps around the remaining portions of the dummy gate stack and extending vertically along a sidewall of a dummy gate cavity. In one embodiment, inblock 1660 the first low-k spacer portion and the second low-k spacer portion are etched. In block 1670 a poly pull process is performed on the remaining portions of the dummy gate stack. In one embodiment, inblock 1680 an RMG structure (e.g.,RMG stack 1120,FIG. 11 , completedRMG stack 1220,FIG. 12 ) is formed with the first low-k spacer portion and the second low-k spacer portion (which are already formed prior to the RMG structure formation). - In one embodiment,
process 1600 may provide that forming the dummy gate stack includes forming a source junction on the substrate adjacent the first dielectric spacer portion and a drain junction on the substrate adjacent the second dielectric spacer portion, and depositing an oxide layer over the source junction and the drain junction. In one embodiment,process 1600 may include forming a silicon nitride cap layer over the RMG structure and between the first low-k spacer portion and the second low-k spacer portion, and performing CMP to reduce a height of the silicon nitride cap layer down to the oxide layer. - In one embodiment,
process 1600 may include forming a silicon nitride cap layer over the RMG structure, and performing CMP to reduce a height of the silicon nitride cap layer to the oxide layer (where the silicon nitride cap layer completely covers the RMG structure). In one embodiment,process 1600 may further include forming a low-k cap layer over the RMG structure and adjacent to the first low-k spacer portion and the second low-k spacer portion, where a height of the low-k cap layer is reduced to the oxide layer. - Having described preferred embodiments of a method and device for low-k spacer for RMG FET formation (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims.
- References in the claims to an element in the singular is not intended to mean “one and only” unless explicitly so stated, but rather “one or more.” All structural and functional equivalents to the elements of the above-described exemplary embodiment that are currently known or later come to be known to those of ordinary skill in the art are intended to be encompassed by the present claims. No claim element herein is to be construed under the provisions of 35 U.S.C. section 112, sixth paragraph, unless the element is expressly recited using the phrase “means for” or “step for.”
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, steps, operations, elements, materials, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, materials, components, and/or groups thereof.
- The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims (15)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/952,549 US9660050B1 (en) | 2015-11-25 | 2015-11-25 | Replacement low-k spacer |
US15/462,657 US9892926B2 (en) | 2015-11-25 | 2017-03-17 | Replacement low-k spacer |
US15/462,644 US9985135B2 (en) | 2015-11-25 | 2017-03-17 | Replacement low-k spacer |
US15/825,409 US10361311B2 (en) | 2015-11-25 | 2017-11-29 | Semiconductor structure including low-k spacer material |
US15/936,149 US10217869B2 (en) | 2015-11-25 | 2018-03-26 | Semiconductor structure including low-K spacer material |
US16/242,834 US10629743B2 (en) | 2015-11-25 | 2019-01-08 | Semiconductor structure including low-K spacer material |
Applications Claiming Priority (1)
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US14/952,549 US9660050B1 (en) | 2015-11-25 | 2015-11-25 | Replacement low-k spacer |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/462,644 Continuation US9985135B2 (en) | 2015-11-25 | 2017-03-17 | Replacement low-k spacer |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/462,657 Continuation US9892926B2 (en) | 2015-11-25 | 2017-03-17 | Replacement low-k spacer |
US15/462,644 Division US9985135B2 (en) | 2015-11-25 | 2017-03-17 | Replacement low-k spacer |
Publications (2)
Publication Number | Publication Date |
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US9660050B1 US9660050B1 (en) | 2017-05-23 |
US20170148894A1 true US20170148894A1 (en) | 2017-05-25 |
Family
ID=58708177
Family Applications (6)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/952,549 Expired - Fee Related US9660050B1 (en) | 2015-11-25 | 2015-11-25 | Replacement low-k spacer |
US15/462,644 Active US9985135B2 (en) | 2015-11-25 | 2017-03-17 | Replacement low-k spacer |
US15/462,657 Active US9892926B2 (en) | 2015-11-25 | 2017-03-17 | Replacement low-k spacer |
US15/825,409 Active US10361311B2 (en) | 2015-11-25 | 2017-11-29 | Semiconductor structure including low-k spacer material |
US15/936,149 Active US10217869B2 (en) | 2015-11-25 | 2018-03-26 | Semiconductor structure including low-K spacer material |
US16/242,834 Active US10629743B2 (en) | 2015-11-25 | 2019-01-08 | Semiconductor structure including low-K spacer material |
Family Applications After (5)
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US15/462,644 Active US9985135B2 (en) | 2015-11-25 | 2017-03-17 | Replacement low-k spacer |
US15/462,657 Active US9892926B2 (en) | 2015-11-25 | 2017-03-17 | Replacement low-k spacer |
US15/825,409 Active US10361311B2 (en) | 2015-11-25 | 2017-11-29 | Semiconductor structure including low-k spacer material |
US15/936,149 Active US10217869B2 (en) | 2015-11-25 | 2018-03-26 | Semiconductor structure including low-K spacer material |
US16/242,834 Active US10629743B2 (en) | 2015-11-25 | 2019-01-08 | Semiconductor structure including low-K spacer material |
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US (6) | US9660050B1 (en) |
Families Citing this family (11)
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-
2015
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-
2017
- 2017-03-17 US US15/462,644 patent/US9985135B2/en active Active
- 2017-03-17 US US15/462,657 patent/US9892926B2/en active Active
- 2017-11-29 US US15/825,409 patent/US10361311B2/en active Active
-
2018
- 2018-03-26 US US15/936,149 patent/US10217869B2/en active Active
-
2019
- 2019-01-08 US US16/242,834 patent/US10629743B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US9985135B2 (en) | 2018-05-29 |
US20170194499A1 (en) | 2017-07-06 |
US20180219096A1 (en) | 2018-08-02 |
US10217869B2 (en) | 2019-02-26 |
US10361311B2 (en) | 2019-07-23 |
US9660050B1 (en) | 2017-05-23 |
US10629743B2 (en) | 2020-04-21 |
US9892926B2 (en) | 2018-02-13 |
US20180090327A1 (en) | 2018-03-29 |
US20190148557A1 (en) | 2019-05-16 |
US20170194153A1 (en) | 2017-07-06 |
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