US20170133510A1 - High voltage junctionless field effect device and its method of fabrication - Google Patents

High voltage junctionless field effect device and its method of fabrication Download PDF

Info

Publication number
US20170133510A1
US20170133510A1 US15/012,873 US201615012873A US2017133510A1 US 20170133510 A1 US20170133510 A1 US 20170133510A1 US 201615012873 A US201615012873 A US 201615012873A US 2017133510 A1 US2017133510 A1 US 2017133510A1
Authority
US
United States
Prior art keywords
layer
barrier layer
gate dielectric
field effect
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US15/012,873
Other versions
US9634151B1 (en
Inventor
Deyuan Xiao
Richard R. Chang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zing Semiconductor Corp
Original Assignee
Zing Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zing Semiconductor Corp filed Critical Zing Semiconductor Corp
Assigned to ZING SEMICONDUCTOR CORPORATION reassignment ZING SEMICONDUCTOR CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG, RICHARD R., XIAO, DEYUAN
Application granted granted Critical
Publication of US9634151B1 publication Critical patent/US9634151B1/en
Publication of US20170133510A1 publication Critical patent/US20170133510A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7886—Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02568—Chalcogenide semiconducting materials not being oxides, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H01L21/441—Deposition of conductive or insulating materials for electrodes
    • H01L21/443—Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
    • H01L21/47635—After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/056—Making the transistor the transistor being a FinFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7857—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET of the accumulation type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Definitions

  • the present invention relates to the field of high voltage modulation-doped high electron mobility field effect device.
  • the invention relates to a structure and method of fabrication of a high voltage junctionless field effect device for providing enhancement in performance and reliability.
  • the basic structure of a high electron mobility transistor has a source and drain structure with a heterojunction formed by modulation-doped channel layer and donor-supply layer, typically consisting of an undoped GaAs channel layer and a highly doped n-type AlGaAs donor-supply layer.
  • a single doped AlGaAs and undoped GaAs heterojunction to achieve field effect control of electron accumulation at the interface.
  • the electrons, two dimensional electron gas, 2-DEG, generated in the thin junction layer, confined by quantum effects to a thin sheet, are free to move along this thin layer without hindrance and interference of doped ionized impurities, resulting high electron mobility allowing fast response times and low noise operation.
  • HEMT is commonly used in voltage control and regulation devices, by varying the gate voltage, Vg, to change the depth of hetero-junction potential well, to vary the sheet charge density of 2-DEG achieving the regulation of the working current.
  • the heavily doped n-AlxGal-xAs control layer is depleted.
  • the main influencing factor is the doping density and the especially the thickness of wide band gap semiconductor layer.
  • the purpose of the present invention is to provide a method of forming a high-voltage junctionless field effect device of high electron mobility and high performance.
  • the invention is a non-planar quantum well transistor with 2D electronic layer channel, comprising a source electrode, a drain electrode and a 2D semiconducting channel layer consisting of a single or multi-layered 2-dimensional material and a 2D semiconducting barrier layer;
  • the energy band-gap width of the 2D semiconducting barrier Layer is larger than that of the 2D semiconducting channel layer.
  • the 2D semiconducting material consisting of a single or multi 2-dimensional layer(s) made from one of the following materials: MoS 2 , WS 2 , MoS 2 , MoSe 2 , WS 2 , WSe 2 , MoTe 2 or WTe 2 .
  • the present invention provides a method of fabrication of a high-voltage junctionless field effect device, comprising the steps of:
  • the substrate is silicon on insulator.
  • the channel layer is made of MoS 2 , WS 2 , MoSe 2 , WSe 2 , WTe 2 the MoTe 2 or one.
  • a thickness range of the channel layer is 0.5 nm ⁇ 10 nm.
  • the barrier layer is made of MoS 2 , WS 2 , MoSe 2 , WSe 2 , WTe 2 or one of the MoTe 2 .
  • a thickness of the barrier layer is a range of 0.1 nm ⁇ 5 nm.
  • the channel layer and the barrier layer are made by using the processes of CVD, PVD, ALD, ALE, MBE, MOCVD, UHCVD, RTCVD or MEE.
  • the gate dielectric layer is made of silica, alumina, zirconia or hafnia.
  • the gate dielectric layer are formed using MOCVD, CVD, ALD or MBE process.
  • the metal layer is made of Cr or Au.
  • the metal layer thickness in the range of 100 nm ⁇ 300 nm.
  • the metal layer is formed using PVD, MOCVD or ALD process.
  • the patterned photoresist serves as a mask, in the process of sequentially dry etching the metal layer and the gate dielectric layer, to form a gate structure.
  • the sidewall spacers are made of silicon nitride.
  • the source and drain electrodes are made of Au.
  • a high-pressure junctionless field effect device is proposed, using the above mentioned method of forming a high-voltage junctionless field effect device, characterized by:
  • a substrate provided with a fin-shaped structure, a channel layer, a barrier layer, a gate dielectric layer, a metal layer, spacers and the source and drain electrodes, wherein the said channel layer, the barrier layer and the gate dielectric layer are sequentially formed on the fin-shaped structure, the metal layer located on the surface of the gate dielectric layer, the sidewall spacer structure located on both sides of the gate, the source and drain electrodes located on both sides of the barrier layer sidewall.
  • the beneficial effects of the present invention is mainly in: successively under the gate structure forming a channel layer and the barrier layer and the barrier layer bandgap energy is wider than the band gap width of the channel layer.
  • This structure allows the generation the two-dimensional electron gas on the interface between the channel layer and the barrier layer of the high-voltage junctionless field effect device, having high electron mobility, and high breakdown voltage, resulting in better performance and reliability.
  • FIG. 1 illustrates the flow chart of forming a high voltage junctionless field effect device according to an embodiment of present invention.
  • FIGS. 2A to 9A schematically illustrate the cross-sections parallel to the channel direction of a high voltage junctionless field effect device according to an embodiment of present invention.
  • FIGS. 2B to 9B schematically illustrate the cross-sections perpendicular to the channel direction of a high voltage junctionless field effect device according to an embodiment of present invention.
  • FIGS. 10A and 10B schematically illustrate the generation of two dimensional electron gas in a high voltage junctionless field effect device according to an embodiment of present invention.
  • FIG. 1 is a schematic of the processes of forming the proposed invention of a high-voltage junctionless field effect device, comprising the steps of:
  • Silica insulating layer specific refer to FIGS. 2A and 2B , the substrate in the present embodiment, a silicon-on-insulator made of a substrate, comprising a silicon substrate 100 , is formed on the silicon substrate 100 , and 110 the silicon layer is formed on the insulating layer 110 of silicon dioxide 120 , and then, using the resist coating, exposure, development and other processes, the surface of the silicon layer 120 is a photoresist layer to the patterned photoresist, an abrasive layer on the silicon layer 120 is etched to form a fin-shaped structure, shown in FIG. 2B .
  • the structure of the surface of the fin channel layer 200 is formed sequentially, the barrier layer 300 , wherein the energy gap of the barrier layer 300 is larger than the channel layer 200 bandgap;
  • the channel layer 200 made of MoS 2 , WS 2 , MoSe 2 , WSe 2 , MoTe 2 , or one kind of WTe 2 , for example, WS 2 , with thickness in the range of 0.5 nm ⁇ 10nm, e.g. 5 nm;
  • the barrier layer 300 is made of MoS 2 , WS 2 , MoSe 2 , WSe 2 , WTe 2 .
  • the structure of the surface of the fin channel layer 200 is formed sequentially, the barrier layer 300 , wherein the energy gap of the barrier layer 300 is larger than the channel layer 200 bandgap;
  • the channel layer 200 made of MoS2, WS2, MoSe2, WSe2, MoTe2, or one kind of WTe2, for example, WS2, with thickness in the range of 0.5 nm ⁇ 10 nm, e.g.
  • the barrier layer 300 is made of MoS2, WS2, MoSe2, WSe2, the MoTe2 or one kind of WTe2, having a thickness in the range of 0.1 nm ⁇ 5 nm, for example, 3 nm; for the need to ensure energy band gap of the barrier layer 300 is greater than the bandgap of the channel layer 200 , and therefore, preferably, the material of the barrier layer 300 is different than the material of the channel layer 200 , wherein, the channel layer 200 and the barrier layer 300 can employ CVD (Chemical Vapor Deposition, Chemical Vapor Deposition), PVD (Physical Vapor Deposition, Physical Vapor Deposition), ALD (Atomic Layer Deposition, atomic deposition method), ALE (Atomic Layer Epitaxy, atomic epitaxy), MBE (Molecular Beam Epitaxy, molecular beam epitaxy), MOCVD (Metal-Organic Chemical Vapor Deposition epitaxy, metal organic chemical vapor deposition epitaxy), U
  • a gate dielectric layer 400 is formed on the surface of the barrier layer 300 and silicon dioxide 110 silica.
  • the gate dielectric layer 400 is made of alumina, zirconia or hafnia forming.
  • a metal layer 500 on the surface of the gate dielectric layer 400 , a metal layer 500 , the metal layer 500 made of Cr or Au is formed.
  • FIGS. 7A and FIG. 7B sequentially etching the metal layer 500 and the gate dielectric layer 400 , forming a gate structure, which includes forming a gate metal layer 400 and a surface of the gate dielectric layer 500 , wherein, of the gate dielectric layer 400 portions of silicon dioxide layer 110 and the barrier 300 are exposed.
  • the spacers 600 are formed on both sides of the gate structure, the sidewall spacer 600 is made of silicon nitride.
  • a high-voltage junctionless field effect device formed using the method as described above comprising:
  • a substrate provided with a fin-shaped structure, the channel layer 200 , barrier layer 300 , gate dielectric layer 400 , the metal layer 500 , spacers 600 , and source and drain electrodes 700 , wherein the channel layer 200 , barrier layer 300 and the gate dielectric layer 400 are sequentially formed on the fin-shaped structure.
  • the metal layer 500 is located on the surface of the gate dielectric layer 400 , the sidewall spacer structure 600 located on both sides of the gate, the source and drain electrodes 700 located on the surface of the barrier layer 300 situated on both side of the sidewall spacer 600 .
  • the barrier layer 300 and the channel layer 200 formed have different energy band, thereby two-dimensional electron gas is generated at the interface of the barrier layer 300 and the channel layer 200 .
  • FIGS. 10A and 10B in FIG. 10A , when the gate voltage is not applied to gate electrode 510 , the energy bands of gate dielectric layer 400 , barrier layer 300 and the channel layer 200 have not changed, there is no two-dimensional electron gas produced as shown in FIG.
  • the present invention provides an embodiment of a high voltage junctionless field effect device and method of forming it.
  • the gate structure is sequentially formed beneath the channel layer and the barrier layer.
  • the energy band gap width of the barrier layer is greater than that of the channel layer, this made possible the generation of two-dimensional electron gas at interface between the channel layer and the barrier layer.
  • the formed high-voltage junctionless field effect device of this invention has high electron mobility, and also has a high breakdown voltage, and thus results a better performance and reliability.

Abstract

A structure and a method of fabrication are disclosed of a high voltage junctionless field effect device. A channel layer and a barrier layer are formed sequentially underneath the gate structure. The width of energy band gap of the barrier layer is wider than that of the channel layer. Thus the two dimensional electron gas (2-DEG) generated in the interface between the channel layer and the barrier layer of this junctionless field effect device has higher electron mobility. The structure of the device of this disclosure has a higher breakdown voltage which is advantageous for a high voltage junctionless field device. The structure offers advantages in device performance and reliability.

Description

  • The present application claims the priority to Chinese Patent Applications No. 201510746889.2, filed with the Chinese State Intellectual Property Office on Nov. 6, 2015, which is incorporated herein by reference in its entirety.
    • TECHNICAL FIELD
  • The present invention relates to the field of high voltage modulation-doped high electron mobility field effect device. In particular, the invention relates to a structure and method of fabrication of a high voltage junctionless field effect device for providing enhancement in performance and reliability.
    • BACKGROUND
  • The basic structure of a high electron mobility transistor, HEMT, has a source and drain structure with a heterojunction formed by modulation-doped channel layer and donor-supply layer, typically consisting of an undoped GaAs channel layer and a highly doped n-type AlGaAs donor-supply layer. Using a single doped AlGaAs and undoped GaAs heterojunction to achieve field effect control of electron accumulation at the interface. The electrons, two dimensional electron gas, 2-DEG, generated in the thin junction layer, confined by quantum effects to a thin sheet, are free to move along this thin layer without hindrance and interference of doped ionized impurities, resulting high electron mobility allowing fast response times and low noise operation. HEMT is commonly used in voltage control and regulation devices, by varying the gate voltage, Vg, to change the depth of hetero-junction potential well, to vary the sheet charge density of 2-DEG achieving the regulation of the working current.
  • For GaAs based HEMT, normally the heavily doped n-AlxGal-xAs control layer is depleted. For depletion mode device, the n-AlxGal-xAs is thicker and heavily doped, 2-DEG exist even at Vg=0. Otherwise when the device is enhancement-mode, at Vg=0, Schottky depletion layer extended to GaAs layer; Hence, for HEMT, the main influencing factor is the doping density and the especially the thickness of wide band gap semiconductor layer. The surface density of 2-DEG, Ns, in HEMT, is mainly influenced by the sub-band of potential well of the heterojunction (i=0 and 1). 2-DEG surface charge density is Vg regulated.
    • SUMMARY
  • The purpose of the present invention is to provide a method of forming a high-voltage junctionless field effect device of high electron mobility and high performance. The invention is a non-planar quantum well transistor with 2D electronic layer channel, comprising a source electrode, a drain electrode and a 2D semiconducting channel layer consisting of a single or multi-layered 2-dimensional material and a 2D semiconducting barrier layer; The energy band-gap width of the 2D semiconducting barrier Layer is larger than that of the 2D semiconducting channel layer. The 2D semiconducting material consisting of a single or multi 2-dimensional layer(s) made from one of the following materials: MoS2, WS2, MoS2, MoSe2, WS2, WSe2, MoTe2 or WTe2.
  • The present invention provides a method of fabrication of a high-voltage junctionless field effect device, comprising the steps of:
  • Providing a substrate;
  • Fin-shaped structure formed on the substrate;
  • Sequentially formed on the surface of the fin-shaped structure a channel layer, a barrier layer, a gate dielectric layer and the metal layer, wherein the energy band gap of the barrier layer is greater than the width of the energy band gap of the channel layer;
  • Etching the metal layer and the gate dielectric layer to form a gate structure;
  • Forming spacers on both sides of the gate structure;
  • Formed source and drain electrodes on the side walls on both sides of the barrier layer.
  • Further, in described method of forming the high-voltage junctionless field effect device, the substrate is silicon on insulator.
  • Further, in the high-voltage junctionless field effect device, the channel layer is made of MoS2, WS2, MoSe2, WSe2, WTe2 the MoTe2 or one.
  • Further, in the high-voltage junctionless field effect device, a thickness range of the channel layer is 0.5 nm˜10 nm.
  • Further, in the high-voltage junctionless field effect device, the barrier layer is made of MoS2, WS2, MoSe2, WSe2, WTe2 or one of the MoTe2.
  • Further, in the high-voltage junctionless field effect device, a thickness of the barrier layer is a range of 0.1 nm˜5 nm.
  • Further, in the high-voltage junctionless field effect device, the channel layer and the barrier layer are made by using the processes of CVD, PVD, ALD, ALE, MBE, MOCVD, UHCVD, RTCVD or MEE.
  • Further, in the forming method of the described high-pressure junctionless field effect device, the gate dielectric layer is made of silica, alumina, zirconia or hafnia.
  • Further, in the described high-pressure junctionless field effect device, the gate dielectric layer are formed using MOCVD, CVD, ALD or MBE process.
  • Further, in the high-voltage junctionless field effect device, the metal layer is made of Cr or Au.
  • Further, in the high-voltage junctionless field effect device, the metal layer thickness in the range of 100 nm˜300 nm.
  • Further, in the high-voltage junctionless field effect device, the metal layer is formed using PVD, MOCVD or ALD process.
  • Further, in the high-voltage junctionless field effect device, the steps of etching the metal layer and the gate dielectric layer comprises:
  • Photoresist coating on the metal layer, and the patterning the photoresist;
  • The patterned photoresist serves as a mask, in the process of sequentially dry etching the metal layer and the gate dielectric layer, to form a gate structure.
  • Further, in the high-voltage junctionless field effect device, the sidewall spacers are made of silicon nitride.
  • Further, in the high-voltage junctionless field effect device, the source and drain electrodes are made of Au.
  • In the present invention, a high-pressure junctionless field effect device is proposed, using the above mentioned method of forming a high-voltage junctionless field effect device, characterized by:
  • comprising a substrate provided with a fin-shaped structure, a channel layer, a barrier layer, a gate dielectric layer, a metal layer, spacers and the source and drain electrodes, wherein the said channel layer, the barrier layer and the gate dielectric layer are sequentially formed on the fin-shaped structure, the metal layer located on the surface of the gate dielectric layer, the sidewall spacer structure located on both sides of the gate, the source and drain electrodes located on both sides of the barrier layer sidewall.
  • Compared with the prior art, the beneficial effects of the present invention is mainly in: successively under the gate structure forming a channel layer and the barrier layer and the barrier layer bandgap energy is wider than the band gap width of the channel layer. This structure allows the generation the two-dimensional electron gas on the interface between the channel layer and the barrier layer of the high-voltage junctionless field effect device, having high electron mobility, and high breakdown voltage, resulting in better performance and reliability.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates the flow chart of forming a high voltage junctionless field effect device according to an embodiment of present invention.
  • FIGS. 2A to 9A schematically illustrate the cross-sections parallel to the channel direction of a high voltage junctionless field effect device according to an embodiment of present invention.
  • FIGS. 2B to 9B schematically illustrate the cross-sections perpendicular to the channel direction of a high voltage junctionless field effect device according to an embodiment of present invention.
  • FIGS. 10A and 10B schematically illustrate the generation of two dimensional electron gas in a high voltage junctionless field effect device according to an embodiment of present invention.
    •  DETAILED DESCRIPTION
  • A schematic and more detailed description of a method of fabrication of a high voltage junctionless field effect device, a preferred embodiment of the present invention, is provided. The embodiment is described in sufficient detail to enable those skilled in the art to practice it. It should be understood that the invention described herein may be modified and varied, and still achieve advantageous effects of the present invention. Thus, the fabrication processes described should be understood as widely known to those skilled in the art, but not as a limitation of the present invention.
  • In the following description, not all the features of well-known functions and structures of an actual embodiment are described in detail, as they may entail unnecessary details. It should be understood that in the development of any actual embodiment, the implementation details must be made in order to achieve the specific goals of the developers, such as in accordance with the system or the commercial constraint. In addition, it should be understood that such a development effort might be complex and time-consuming, but for those skilled in the art they are the processes are widely known and standard routine practices.
  • In the following paragraphs with reference to the accompanying drawings by way of example the present invention is described more specifically. According to the following description and claims, advantages and features of the present invention will become apparent. It should be noted that the drawings are used in a very simplified form and are not to scale, only to facilitate and assist the description of an embodiment of the present invention.
  • FIG. 1 is a schematic of the processes of forming the proposed invention of a high-voltage junctionless field effect device, comprising the steps of:
  • S100: providing a substrate;
  • S200: forming a fin-shaped structure on the substrate;
  • S300: sequentially formed on the surface of the fin-shaped structure of the channel layer, a barrier layer, a gate dielectric layer and the metal layer, wherein the energy band gap energy of the barrier layer is greater than the width of the channel layer;
  • S400: etching the metal layer and the gate dielectric layer to form a gate structure;
  • S500: forming spacers on both sides of the gate structure;
  • S600: formed on the side walls on both sides of the barrier layer source and drain.
  • Silica insulating layer specific, refer to FIGS. 2A and 2B, the substrate in the present embodiment, a silicon-on-insulator made of a substrate, comprising a silicon substrate 100, is formed on the silicon substrate 100, and 110 the silicon layer is formed on the insulating layer 110 of silicon dioxide 120, and then, using the resist coating, exposure, development and other processes, the surface of the silicon layer 120 is a photoresist layer to the patterned photoresist, an abrasive layer on the silicon layer 120 is etched to form a fin-shaped structure, shown in FIG. 2B.
  • Next, refer to FIGS. 3A, 3B, 4A and 4B, the structure of the surface of the fin channel layer 200 is formed sequentially, the barrier layer 300, wherein the energy gap of the barrier layer 300 is larger than the channel layer 200 bandgap; In the present embodiment, the channel layer 200 made of MoS2, WS2, MoSe2, WSe2, MoTe2, or one kind of WTe2, for example, WS2, with thickness in the range of 0.5 nm˜10nm, e.g. 5 nm; the barrier layer 300 is made of MoS2, WS2, MoSe2, WSe2, WTe2.
  • Next, refer to FIGS. 3A, 3B, 4A and 4B, the structure of the surface of the fin channel layer 200 is formed sequentially, the barrier layer 300, wherein the energy gap of the barrier layer 300 is larger than the channel layer 200 bandgap; In the present embodiment, the channel layer 200 made of MoS2, WS2, MoSe2, WSe2, MoTe2, or one kind of WTe2, for example, WS2, with thickness in the range of 0.5 nm˜10 nm, e.g. 5 nm; the barrier layer 300 is made of MoS2, WS2, MoSe2, WSe2, the MoTe2 or one kind of WTe2, having a thickness in the range of 0.1 nm˜5 nm, for example, 3 nm; for the need to ensure energy band gap of the barrier layer 300 is greater than the bandgap of the channel layer 200, and therefore, preferably, the material of the barrier layer 300 is different than the material of the channel layer 200, wherein, the channel layer 200 and the barrier layer 300 can employ CVD (Chemical Vapor Deposition, Chemical Vapor Deposition), PVD (Physical Vapor Deposition, Physical Vapor Deposition), ALD (Atomic Layer Deposition, atomic deposition method), ALE (Atomic Layer Epitaxy, atomic epitaxy), MBE (Molecular Beam Epitaxy, molecular beam epitaxy), MOCVD (Metal-Organic Chemical Vapor Deposition epitaxy, metal organic chemical vapor deposition epitaxy), UHCVD (Ultra-High vacuum CVD epitaxy, ultrahigh vacuum vapor deposition), RTCVD (Reduced-Temperature CVD epitaxy, reduce temperature vapor deposition) or MEE (Migration Enhanced Epitaxy, migration enhanced epitaxy) process to form.
  • Next, refer to FIG. 5A and 5B, on the surface of the barrier layer 300 and silicon dioxide 110 silica, a gate dielectric layer 400 is formed. The gate dielectric layer 400 is made of alumina, zirconia or hafnia forming.
  • Refer to FIGS. 6A and 6B, on the surface of the gate dielectric layer 400, a metal layer 500, the metal layer 500 made of Cr or Au is formed.
  • Next, refer to FIGS. 7A and FIG. 7B, sequentially etching the metal layer 500 and the gate dielectric layer 400, forming a gate structure, which includes forming a gate metal layer 400 and a surface of the gate dielectric layer 500, wherein, of the gate dielectric layer 400 portions of silicon dioxide layer 110 and the barrier 300 are exposed.
  • Next, refer to FIGS. 8A and FIG. 8B, the spacers 600 are formed on both sides of the gate structure, the sidewall spacer 600 is made of silicon nitride.
  • Next, refer to FIGS. 9A and 9B, on both sides of the sidewall spacer 600, on the surface of the barrier layer 300, source and drain 700 are formed, thus, a high-voltage junctionless field effect device is formed.
  • Another embodiment of this invention is proposed. A high-voltage junctionless field effect device, formed using the method as described above comprising:
  • a substrate provided with a fin-shaped structure, the channel layer 200, barrier layer 300, gate dielectric layer 400, the metal layer 500, spacers 600, and source and drain electrodes 700, wherein the channel layer 200, barrier layer 300 and the gate dielectric layer 400 are sequentially formed on the fin-shaped structure. The metal layer 500 is located on the surface of the gate dielectric layer 400, the sidewall spacer structure 600 located on both sides of the gate, the source and drain electrodes 700 located on the surface of the barrier layer 300 situated on both side of the sidewall spacer 600.
  • Since, in the present embodiment, the barrier layer 300 and the channel layer 200 formed have different energy band, thereby two-dimensional electron gas is generated at the interface of the barrier layer 300 and the channel layer 200. Specifically, refer to FIGS. 10A and 10B, in FIG. 10A, when the gate voltage is not applied to gate electrode 510, the energy bands of gate dielectric layer 400, barrier layer 300 and the channel layer 200 have not changed, there is no two-dimensional electron gas produced as shown in FIG. 10B, when a voltage is applied to the gate electrode 510, the energy band of the gate dielectric layer 400, a barrier layer 300 and the channel layer are changed, two-dimensional electron gas (2-DEG) 210 is produced at the interface of the barrier layer 300 and the channel layer 200, thereby increasing the carrier mobility, greatly enhance the performance of the device.
  • In summary, the present invention provides an embodiment of a high voltage junctionless field effect device and method of forming it. The gate structure is sequentially formed beneath the channel layer and the barrier layer. The energy band gap width of the barrier layer is greater than that of the channel layer, this made possible the generation of two-dimensional electron gas at interface between the channel layer and the barrier layer. The formed high-voltage junctionless field effect device of this invention has high electron mobility, and also has a high breakdown voltage, and thus results a better performance and reliability.
  • While the present invention has been described in an illustrative manner, it should be understood that the terminology used is intended to be in a nature of words of description rather than of limitation. Many modifications and variations of the present invention and other versions are possible in light of the above teachings, and could be apparent for those skilled in the art. The above described embodiments of the present invention do not limit the present invention in any way. Any person skilled in the art, without departing from the technical scope of the present invention, can modify and vary technical solutions and technical content of the disclosed present invention. The modifications and variations still fall within the scope of the present invention.

Claims (16)

1. A method for forming a high-voltage non-junction field effect device, the method comprising the steps of:
providing a substrate;
forming a fin-shaped structure on the substrate;
sequentially forming on a surface of the fin-shaped structure of a channel layer, a barrier layer, a gate dielectric layer and a metal layer, wherein an energy band gap energy of the barrier layer is greater than a width of the channel layer;
etching the metal layer and the gate dielectric layer to form a gate structure;
forming spacers on both sides of the gate structure;
forming source and drain on side walls on both sides of the barrier layer.
2. The method of claim 1, wherein the substrate is a silicon-on-insulator substrate.
3. The method of claim 1, wherein the channel layer is made of MoS2, WS2, MoSe2, WSe2, WTe2 in or one kind of MoTe2.
4. The method of claim 3, wherein a thickness range of the channel layer is 0.5 nm˜10 nm.
5. The method of claim 1, wherein the barrier layer is made of MoS2, WS2, MoSe2, WSe2, WTe2 or one kind of MoTe2.
6. The method of claim 5, wherein a thickness of the barrier layer is in a range of 0.1 nm˜5 nm.
7. The method of claim 3, wherein the channel layer and the barrier layer are made by the forming processes of CVD, PVD, ALD, ALE, MBE, MOCVD, UHCVD, RTCVD or MEE.
8. The method of claim 1, wherein the gate dielectric layer is made of silica, alumina, zirconia or hafnia.
9. The method of claim 8, wherein the gate dielectric layer using the forming processes of MOCVD, CVD, ALD or MBE.
10. The method of claim 1, wherein the metal layer is made of Cr or Au.
11. The method of claim 10, wherein the metal layer comprising a thickness in a range of 100 nm˜300 nm.
12. The method of claim 10, wherein the metal layer using a forming process of PVD, MOCVD or ALD.
13. The method of claim 1, wherein the step of etching the metal layer and the gate dielectric layer comprises:
coating a photoresist on the metal layer, and then patterning the photoresist and using the patterned photoresist as a mask;
dry etching the metal layer and the gate dielectric layer using the patterned photoresist as the mask to form the gate structure comprising the metal layer and the gate dielectric layer.
14. The method of claim 1, wherein the spacer is made of silicon nitride.
15. The method of claim 1, wherein the source and drain electrodes made of Au.
16. (canceled)
US15/012,873 2015-11-06 2016-02-02 High voltage junctionless field effect device and its method of fabrication Active US9634151B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201510746889 2015-11-06
CN201510746889.2A CN106684138A (en) 2015-11-06 2015-11-06 High-voltage junctionless field-effect device and formation method thereof
CN201510746889.2 2015-11-06

Publications (2)

Publication Number Publication Date
US9634151B1 US9634151B1 (en) 2017-04-25
US20170133510A1 true US20170133510A1 (en) 2017-05-11

Family

ID=58546488

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/012,873 Active US9634151B1 (en) 2015-11-06 2016-02-02 High voltage junctionless field effect device and its method of fabrication

Country Status (3)

Country Link
US (1) US9634151B1 (en)
CN (1) CN106684138A (en)
TW (1) TW201717395A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10756114B2 (en) 2017-12-28 2020-08-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor circuit with metal structure and manufacturing method
CN117253918A (en) * 2023-11-20 2023-12-19 江西兆驰半导体有限公司 HEMT epitaxial wafer and preparation method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160365347A1 (en) * 2015-06-12 2016-12-15 International Business Machines Corporation ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8487378B2 (en) * 2011-01-21 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Non-uniform channel junction-less transistor
CN103943498B (en) * 2013-01-22 2016-08-10 中芯国际集成电路制造(上海)有限公司 Three-dimensional quantum well transistor and forming method thereof
US8912609B2 (en) * 2013-05-08 2014-12-16 International Business Machines Corporation Low extension resistance III-V compound fin field effect transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160365347A1 (en) * 2015-06-12 2016-12-15 International Business Machines Corporation ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs

Also Published As

Publication number Publication date
TW201717395A (en) 2017-05-16
US9634151B1 (en) 2017-04-25
CN106684138A (en) 2017-05-17

Similar Documents

Publication Publication Date Title
US9024357B2 (en) Method for manufacturing a HEMT transistor and corresponding HEMT transistor
US20170222034A1 (en) METHOD FOR FORMATION OF VERTICAL CYLINDRICAL GaN QUANTUM WELL TRANSISTOR
US10910480B2 (en) Transistor with multi-metal gate
US10418474B2 (en) High electron mobility transistor with varying semiconductor layer
US9634133B1 (en) Method of forming fin structure on patterned substrate that includes depositing quantum well layer over fin structure
US9093510B2 (en) Field effect transistor device
EP3549173B1 (en) High electron mobility transistor and method for manufacturing high electron mobility transistor
US9209289B2 (en) Semiconductor device and fabrication method thereof
Verma et al. Design and simulation of a doping-less charge plasma based enhancement mode GaN MOSFET
US10079297B2 (en) Compound semiconductor device
US9634151B1 (en) High voltage junctionless field effect device and its method of fabrication
WO2012029292A1 (en) Semiconductor substrate, insulated gate field effect transistor, and method for manufacturing semiconductor substrate
TWI628747B (en) Method for manufacturing complementary metal-oxide-semiconductor device
TW201327816A (en) Semiconductor device and method of manufacturing the same
US20210151593A1 (en) Process for Scaling a Gate Length
US11489048B2 (en) High electron mobility transistor and fabrication method thereof
CN116613189A (en) High electron mobility transistor and method of manufacturing the same
Matioli et al. GaN-Based Nanowire Transistors

Legal Events

Date Code Title Description
AS Assignment

Owner name: ZING SEMICONDUCTOR CORPORATION, CHINA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:XIAO, DEYUAN;CHANG, RICHARD R.;REEL/FRAME:037679/0982

Effective date: 20160201

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YR, SMALL ENTITY (ORIGINAL EVENT CODE: M2551); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY

Year of fee payment: 4