CN117253918A - HEMT epitaxial wafer and preparation method thereof - Google Patents

HEMT epitaxial wafer and preparation method thereof Download PDF

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Publication number
CN117253918A
CN117253918A CN202311541159.XA CN202311541159A CN117253918A CN 117253918 A CN117253918 A CN 117253918A CN 202311541159 A CN202311541159 A CN 202311541159A CN 117253918 A CN117253918 A CN 117253918A
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layer
growth
sub
temperature
epitaxial wafer
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刘春杨
胡加辉
金从龙
顾伟
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Jiangxi Zhao Chi Semiconductor Co Ltd
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Jiangxi Zhao Chi Semiconductor Co Ltd
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Abstract

The invention discloses an HEMT epitaxial wafer and a preparation method thereof, wherein the HEMT epitaxial wafer comprises a Si substrate, and a composite buffer layer, a GaN high-resistance layer, a GaN channel layer, an AlN insert layer, an AlGaN barrier layer and a GaN cap layer which are sequentially laminated on the Si substrate; the composite buffer layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are sequentially laminated on the Si substrate, wherein the first sub-layer is MoSe 2 The second sub-layer is a low-temperature AlN layer and a high-temperature AlN layer which are sequentially stacked, and the third sub-layer is an AlGaN layer. The invention can improve the crystal quality and reduce the radio frequency loss at the same time, thereby improving the performance of HEMT.

Description

HEMT epitaxial wafer and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a HEMT epitaxial wafer and a preparation method thereof.
Background
As a third-generation semiconductor material, the GaN-based material has the advantages of large forbidden bandwidth, large electron saturation drift speed, radiation resistance, high temperature resistance and the like, and becomes a preferred material for manufacturing high-temperature high-frequency, high-power, radiation resistance and low-loss devices. The GaN-based heterostructure has high carrier concentration and electron mobility, has small on-resistance and large forbidden bandwidth, and can bear high working voltage. Therefore, in the field of radio frequency electronics, gaN-based devices are receiving a growing attention from the scientific and industrial world.
The epitaxial substrate of the GaN-based radio frequency device mainly comprises a SiC substrate, a sapphire substrate and a Si substrate. GaN thin films with good crystal quality can be obtained by epitaxial growth on SiC substrates, however, the SiC substrates have high cost and are not beneficial to industrialization. The sapphire substrate has moderate price, but the wafer has small size, high hardness and low heat conductivity, and is unfavorable for subsequent processing and application. The Si substrate has the advantages of high heat conductivity, large wafer size, low cost, compatibility with Si process lines and the like, and has the capacity of growing GaN-based radio frequency devices on a large scale. However, there is a large lattice mismatch (16.9%) and thermal expansion coefficient mismatch (56%) between Si and GaN crystals, and dislocation and stress generated by the mismatch may seriously affect crystal quality, thereby affecting the performance and reliability of the device. In addition, unlike power electronics devices, in Si-based GaN rf devices, high dislocation density still exists for GaN epitaxial thin film materials grown on high resistivity Si substrates, stress and warpage are difficult to control, and Al in the nucleation layer is easily diffused to the Si substrate and forms a conductive layer at the interface, resulting in large rf loss of the device in a high frequency operating state, severely affecting output power and efficiency.
Disclosure of Invention
The invention aims to solve the technical problem of providing an HEMT epitaxial wafer, which can improve the performance of the HEMT epitaxial wafer.
The invention also aims to solve the technical problem of providing a preparation method of the HEMT epitaxial wafer, which has simple process and good performance of the HEMT epitaxial wafer.
In order to achieve the technical effects, the invention provides an HEMT epitaxial wafer, which comprises a Si substrate, and a buffer layer, a GaN high-resistance layer, a GaN channel layer, an AlN insert layer, an AlGaN barrier layer and a GaN cap layer which are sequentially laminated on the Si substrate;
the buffer layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are sequentially laminated on the Si substrateThe first sublayer is MoSe 2 The second sub-layer is a low-temperature AlN layer and a high-temperature AlN layer which are sequentially laminated, and the third sub-layer is an AlGaN layer;
the growth temperature of the low-temperature AlN layer is 600-700 ℃, and the growth temperature of the high-temperature AlN layer is 1000-1200 ℃.
As an improvement of the technical scheme, the resistivity of the Si substrate is 1000 Ω & cm-5000 Ω & cm.
As an improvement of the technical proposal, the MoSe 2 The thickness of the layer is 1nm-5nm.
As an improvement of the technical scheme, the thickness of the low-temperature AlN layer is 5nm-20nm, and the thickness of the high-temperature AlN layer is 100nm-200nm.
As an improvement of the technical scheme, the Al component of the AlGaN layer accounts for 0.1-0.8, and the thickness of the AlGaN layer is 1-3 mu m.
As an improvement of the technical proposal, the MoSe 2 After the layer growth is completed at H 2 Annealing treatment is carried out in atmosphere.
Correspondingly, the invention also discloses a preparation method of the HEMT epitaxial wafer, which is used for preparing the HEMT epitaxial wafer and comprises the following steps of:
providing a Si substrate, and sequentially growing a buffer layer, a GaN high-resistance layer, a GaN channel layer, an AlN inserting layer, an AlGaN barrier layer and a GaN cap layer on the Si substrate;
the buffer layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are sequentially laminated on the Si substrate, wherein the first sub-layer is MoSe 2 The second sub-layer is a low-temperature AlN layer and a high-temperature AlN layer which are sequentially stacked, and the third sub-layer is an AlGaN layer.
As an improvement of the technical proposal, the MoSe is deposited 2 After the layer at H 2 Annealing treatment is carried out in the atmosphere, the annealing treatment temperature is 500-700 ℃, and the annealing treatment time is 1-5 min.
As an improvement of the technical scheme, the CVD is adopted to prepare MoSe 2 The layer is loaded with Mo source and Se source respectively by Ar as carrier gas, and the growth atmosphere is H 2 The growth temperature is 400-700 ℃ and the growth pressure is40mbar-150mbar, H 2 The flow ratio of Ar is 1 (5-15).
As an improvement of the technical scheme, MOCVD is adopted to prepare a low-temperature AlN layer and a high-temperature AlN layer; the growth temperature of the low-temperature AlN layer is 600-700 ℃, and the growth pressure is 50-100 mbar; the growth temperature of the high-temperature AlN layer is 1000-1200 ℃, and the growth pressure is 50-100 mbar.
The embodiment of the invention has the following beneficial effects:
the composite buffer layer structure can realize better GaN epitaxial growth on the Si substrate, control dislocation and warpage, improve crystal quality, inhibit Al of the AlN layer from diffusing to the Si substrate to form a conductive layer, and reduce radio frequency loss. MoSe in composite buffer layer 2 The lattice matching degree of the layer and the Si substrate is high, and the crystallization quality and the subsequent epitaxial growth quality of the Si substrate can be improved. In MoSe 2 The low-temperature AlN layer grows on the layer, al atoms are prevented from moving to the surface of the Si substrate to form a conductive layer at high temperature, and in addition, the Al atoms in the low-temperature AlN layer can replace MoSe 2 Mo atoms, al atoms and Se vacancies in the layer generate stronger interaction, so that the diffusion of the Al atoms to the Si substrate is further inhibited, and the radio frequency loss is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a HEMT epitaxial wafer provided in an embodiment of the present invention;
fig. 2 is a flowchart of a method for preparing an HEMT epitaxial wafer according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to specific embodiments.
As shown in fig. 1, the embodiment of the invention provides a HEMT epitaxial wafer, which comprises a Si substrate 1, and a composite buffer layer 2, a GaN high-resistance layer 3, a GaN channel layer 4, an AlN insert layer 5, an AlGaN barrier layer 6 and a GaN cap layer 7 which are sequentially laminated on the Si substrate 1; the composite buffer layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are sequentially laminated on the Si substrate, wherein the first sub-layer is MoSe 2 The second sub-layer is a sequential layerAnd the third sub-layer is an AlGaN layer.
The low resistivity Si substrate has severe rf loss at the AlN interface, limiting the development of rf electronics. The introduction of high resistivity Si substrates, while reducing radio frequency losses, still has difficulty in achieving the performance of GaN epitaxial radio frequency electronic devices on SiC substrates, and because of differences in mechanical properties, stress and dislocation of high resistivity Si substrates are more difficult to control. Growth of a layer of MoSe on a high resistivity Si substrate 2 Film, moSe 2 The band gap of the crystal is 1.2eV-1.5eV, and the crystal has almost no lattice mismatch with the Si substrate, so that the stress and dislocation can be well controlled, and the crystallization quality and the subsequent epitaxial growth quality of the crystal can be improved. In addition, due to the high temperature conditions, moSe 2 Is easy to evaporate, thus in MoSe 2 A low-temperature AlN layer grows on the substrate, and Al atoms have limited migration capability at low temperature and are not easy to move to the surface of the Si substrate to form a conductive layer; in addition, when Al atoms in the AlN layer replace MoSe 2 After Mo atom in (C), al atom will be combined with MoSe 2 The Se vacancies in the Si substrate have stronger interaction, so that the diffusion of Al atoms to the Si substrate is further inhibited to form a conductive layer, and the radio frequency loss is further reduced.
In one embodiment, the Si substrate has a resistivity of 1000 Ω.cm to 5000 Ω.cm. The resistivity of the Si substrate is, but not limited to, 1000 Ω·cm, 2000 Ω·cm, 2500 Ω·cm, 3000 Ω·cm, 4000 Ω·cm, or 5000 Ω·cm, for example. High resistivity Si substrates can reduce radio frequency losses to some extent.
In one embodiment, the MoSe 2 The thickness of the layer is 1nm-5nm. If the MoSe is 2 The thickness of the layer is less than 1nm, and the downward diffusion of the Al component cannot be effectively blocked; if the MoSe is 2 The thickness of the layer is larger than 5nm, which causes the reduction of the growth quality and is unfavorable for the epitaxial growth of the subsequent structure. Illustratively, the MoSe 2 The thickness of the layer is 1nm, 1.5nm, 2nm, 2.5nm, 3nm, 4nm or 5nm, but is not limited thereto.
In one embodiment, the low temperature AlN layer has a thickness of 5nm to 20nm, and exemplary, the low temperature AlN layer has a thickness of 5nm, 7nm, 10nm, 12nm, 15nm, 18nm, or 20nm, but is not limited thereto. The high temperature AlN layer has a thickness of 100nm to 200nm, and exemplary, the high temperature AlN layer has a thickness of 100nm, 120nm, 150nm, 160nm, 180nm, or 200nm, but is not limited thereto.
In one embodiment, the AlGaN layer has an Al composition ratio of 0.1 to 0.8, and exemplary AlGaN layers have an Al composition ratio of 0.1, 0.2, 0.4, 0.6, or 0.8, but is not limited thereto. The thickness of the AlGaN layer is 1 μm to 3 μm, and exemplary, but not limited thereto, the thickness of the AlGaN layer is 1 μm, 1.5 μm, 2 μm, 2.5 μm, or 3 μm.
In one embodiment, the MoSe 2 After the layer growth is completed at H 2 Annealing treatment is carried out in atmosphere. The annealing treatment can remove surface oxide and grow MoSe 2 When the film is in use, some defects, dislocation, se vacancies and the like exist, and through rapid thermal annealing, the surface defects can be reduced, and the crystallization quality of the film can be improved.
In addition to the above composite buffer layer, other layered structures of the present invention are characterized as follows:
the GaN high-resistance layer has a thickness of 1 μm-2 μm and a C doping concentration of 1×10 19 cm -3 -1×10 20 cm -3 。
The thickness of the GaN channel layer is 300nm-600nm.
The AlN intercalation layer has a thickness of 0.5nm-2nm.
The thickness of the AlGaN barrier layer is 20nm-25nm, and the Al component accounts for 0.2-0.25.
The thickness of the GaN cap layer is 3nm-5nm.
Correspondingly, as shown in fig. 2, the invention also provides a preparation method of the HEMT epitaxial wafer, which comprises the following steps:
s100 provides a Si substrate.
S200 growth of a composite buffer layer:
specifically, in one embodiment, the growth of the composite buffer layer includes the steps of:
s201 growth of MoSe 2 Layer (c):
placing the Si substrate in a CVD system, wherein the growth temperature is 400-700 ℃,the growth pressure is 40mbar-150mbar, ar is used as carrier gas to load MoO 3 Powder, moO 3 Evaporating the powder into a gaseous state; maintaining the growth temperature and growth pressure unchanged, introducing Se powder with Ar as carrier gas, and introducing H 2 Se powder is evaporated into gas state, gaseous MoO 3 React with gaseous Se to produce MoSe 2 ，H 2 For reducing gas, H 2 The flow ratio of Ar is 1 (5-15).
The growth temperature is too high, which is unfavorable for forming large-sized MoSe 2 A film; the growth temperature is too low, and the obtained MoSe 2 The film has poor crystallization quality, so the growth temperature is controlled to be 400-700 ℃. In addition, H 2 Excessive proportions and growth pressures result in MoSe 2 The reduction of the film size is unfavorable for the improvement of the overall performance of the device.
In one embodiment, the method further comprises:
s201a growth MoSe 2 After the layer at H 2 Annealing treatment is carried out in the atmosphere, the annealing treatment temperature is 500-700 ℃, and the annealing treatment time is 1-5 min. MoSe 2 Annealing treatment in MOCVD after layer growth can reduce MoSe 2 Surface defects of the film improve the crystallization quality.
S202, growing a low-temperature AlN layer:
MOCVD is adopted for growth, the growth temperature is 600 ℃ to 700 ℃, and the growth pressure is 50mbar to 100mbar.
S203 growth of a high temperature AlN layer:
MOCVD is adopted for growth, the growth temperature is 1000 ℃ to 1200 ℃, and the growth pressure is 50mbar to 100mbar.
S204 growth of AlGaN layer:
MOCVD is adopted for growth, the growth temperature is 1000 ℃ to 1200 ℃, and the growth pressure is 30mbar to 100mbar.
S300, growing a GaN high-resistance layer:
MOCVD is adopted for growth, the growth temperature is 950 ℃ to 1050 ℃, and the growth pressure is 50mbar to 100mbar.
S400 growth of GaN channel layer:
MOCVD is adopted for growth, the growth temperature is 1050-1150 ℃, and the growth pressure is 100-300 mbar.
S500 growth of AlN insertion layer:
MOCVD is adopted for growth, the growth temperature is 1050-1150 ℃, and the growth pressure is 30-100 mbar.
S600 growth AlGaN barrier:
MOCVD is adopted for growth, the growth temperature is 1050-1150 ℃, and the growth pressure is 30-100 mbar.
S700 growth of GaN cap layer:
MOCVD is adopted for growth, the growth temperature is 1050-1150 ℃, and the growth pressure is 30-100 mbar. At N 2 And cooling to room temperature in the atmosphere to finish epitaxial growth.
In the growth process, TMAL, TMGa or TEGa is used as a precursor of a III group source, NH 3 As a precursor of a V-group source, H 2 And/or N 2 As the carrier gas, but not limited thereto.
The invention is further illustrated by the following specific examples.
Example 1
The embodiment provides a HEMT epitaxial wafer, which comprises a Si substrate, and a composite buffer layer, a GaN high-resistance layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer and a GaN cap layer which are sequentially laminated on the Si substrate.
The resistivity of the Si substrate was 2000. Omega. Cm.
The composite buffer layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are sequentially laminated on the Si substrate, wherein the first sub-layer is MoSe 2 A layer having a thickness of 5nm; the second sub-layer is a low-temperature AlN layer and a high-temperature AlN layer which are sequentially laminated, the thickness of the low-temperature AlN layer is 10nm, and the thickness of the high-temperature AlN layer is 180nm; the third sub-layer is an AlGaN layer with a thickness of 2 μm and an Al composition ratio of 0.4.
The GaN high-resistance layer has a thickness of 1.5 μm and a C doping concentration of 5×10 19 cm -3 。
The thickness of the GaN channel layer was 400nm.
The AlN intercalated layer had a thickness of 1nm.
The AlGaN barrier layer had a thickness of 25nm and an Al composition ratio of 0.2.
The thickness of the GaN cap layer was 4nm.
The preparation method of the HEMT epitaxial wafer comprises the following steps of:
s100 provides a Si substrate.
S200, growing a composite buffer layer, specifically comprising the following steps:
s201 growth of MoSe 2 Layer (c):
placing Si substrate in CVD system, growing at 400deg.C under 100mbar, loading MoO with Ar as carrier gas 3 Powder, moO 3 Evaporating the powder into a gaseous state; maintaining the growth temperature and growth pressure unchanged, introducing Se powder with Ar as carrier gas, and introducing H 2 Se powder is evaporated into gas state, gaseous MoO 3 React with gaseous Se to produce MoSe 2 ，H 2 For reducing gas, H 2 The flow ratio to Ar was 1:5. Growth of MoSe 2 After the layer at H 2 Annealing treatment is carried out in atmosphere, the annealing treatment temperature is 400 ℃, and the annealing treatment time is 2min.
S202, growing a low-temperature AlN layer:
MOCVD growth was carried out at 650℃and at a growth pressure of 60mbar.
S203 growth of a high temperature AlN layer:
MOCVD is adopted for growth, the growth temperature is 1120 ℃, and the growth pressure is 80mbar.
S204 growth of AlGaN layer:
MOCVD growth was carried out at 1100℃and at a growth pressure of 60mbar.
S300, growing a GaN high-resistance layer:
MOCVD is adopted for growth, the growth temperature is 1000 ℃, and the growth pressure is 60mbar.
S400 growth of GaN channel layer:
MOCVD growth was carried out at 1100℃and at 200mbar.
S500 growth of AlN insertion layer:
MOCVD growth was carried out at 1100℃and at a growth pressure of 80mbar.
S600 growth AlGaN barrier:
MOCVD growth was carried out at 1100℃and at a growth pressure of 60mbar.
S700 growth of GaN cap layer:
MOCVD growth was carried out at 1100℃and at a growth pressure of 60mbar. At N 2 And cooling to room temperature in the atmosphere to finish epitaxial growth.
Example 2
The present embodiment provides a HEMT epitaxial wafer differing from embodiment 1 in MoSe 2 The growth temperature of the layer is 700 ℃ and MoSe is grown 2 The annealing temperature after the layer was completed was 700 ℃. The remainder was the same as in example 1.
Example 3
The present embodiment provides a HEMT epitaxial wafer differing from embodiment 1 in MoSe 2 The growth pressure of the layer was 40mbar. The remainder was the same as in example 1.
Example 4
The present embodiment provides a HEMT epitaxial wafer differing from embodiment 1 in MoSe 2 The growth pressure of the layer was 1200mbar. The remainder was the same as in example 1.
Example 5
The present embodiment provides a HEMT epitaxial wafer differing from embodiment 1 in that MoSe is grown 2 Layer time, H 2 The flow ratio to Ar was 1:13. The remainder was the same as in example 1.
Example 6
The present embodiment provides a HEMT epitaxial wafer differing from embodiment 1 in MoSe 2 The thickness of the layer was 2nm. The remainder was the same as in example 1.
Example 7
The present embodiment provides a HEMT epitaxial wafer differing from embodiment 1 in MoSe 2 The thickness of the layer was 1nm. The remainder was the same as in example 1.
Comparative example 1
This comparative example provides a HEMT epitaxial wafer, differing from example 1 in that the composite buffer layer does not include MoSe 2 A layer; accordingly, moSe is also excluded from the preparation process 2 Preparation of the layer. The remainder was the same as in example 1.
Comparative example 2
This comparative example provides a HEMT epitaxial wafer differing from example 1 in that the second sub-layer is a high temperature AlN layer, and accordingly, in the manufacturing method, the manufacturing step of the low temperature AlN layer is not included. The remainder was the same as in example 1.
Performance test:
the HEMT epitaxial wafers prepared in examples 1 to 7 and comparative examples 1 and 2 were subjected to performance test after being fabricated into HEMT devices, and the results are shown in table 1.
Table 1 HEMT performance test results
As can be seen from the table, the composite buffer layer structure can realize better GaN epitaxial growth on the Si substrate, control dislocation and warpage, improve crystal quality, reduce radio frequency loss and improve breakdown voltage.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.

Claims (10)

1. The HEMT epitaxial wafer is characterized by comprising a Si substrate, and a composite buffer layer, a GaN high-resistance layer, a GaN channel layer, an AlN inserting layer, an AlGaN barrier layer and a GaN cap layer which are sequentially laminated on the Si substrate;
the composite buffer layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are sequentially laminated on the Si substrate, wherein the first sub-layer is MoSe 2 The second sub-layer is a low-temperature AlN layer and a high-temperature AlN layer which are sequentially laminated, and the third sub-layer is an AlGaN layer;
the growth temperature of the low-temperature AlN layer is 600-700 ℃, and the growth temperature of the high-temperature AlN layer is 1000-1200 ℃.
2. The HEMT epitaxial wafer of claim 1, wherein the Si substrate has a resistivity of 1000 Ω.cm-5000 Ω.cm.
3. The HEMT epitaxial wafer of claim 1, wherein the MoSe 2 The thickness of the layer is 1nm-5nm.
4. The HEMT epitaxial wafer of claim 1, wherein the low-temperature AlN layer has a thickness of 5nm to 20nm and the high-temperature AlN layer has a thickness of 100nm to 200nm.
5. The HEMT epitaxial wafer of claim 1, wherein the AlGaN layer has an Al composition ratio of 0.1 to 0.8 and a thickness of 1 μm to 3 μm.
6. The HEMT epitaxial wafer of claim 1, wherein the MoSe 2 After the layer growth is completed at H 2 Annealing treatment is carried out in atmosphere.
7. A method for preparing a HEMT epitaxial wafer, which is used for preparing the HEMT epitaxial wafer according to any one of claims 1 to 6, and is characterized by comprising the following steps:
providing a Si substrate, and sequentially growing a buffer layer, a GaN high-resistance layer, a GaN channel layer, an AlN inserting layer, an AlGaN barrier layer and a GaN cap layer on the Si substrate;
the buffer layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are sequentially laminated on the Si substrate, wherein the first sub-layer is MoSe 2 The second sub-layer is a low-temperature AlN layer and a high-temperature AlN layer which are sequentially stacked, and the third sub-layer is an AlGaN layer.
8. The method for manufacturing a HEMT epitaxial wafer according to claim 7, wherein MoSe is deposited 2 After the layer at H 2 Annealing treatment is carried out in the atmosphere, the annealing treatment temperature is 500-700 ℃, and the annealing treatment time is 1-5 min.
9. The method for manufacturing a HEMT epitaxial wafer according to claim 7, wherein CVD is usedPreparation of MoSe 2 The layer is loaded with Mo source and Se source respectively by Ar as carrier gas, and the growth atmosphere is H 2 The growth temperature is 400-700 ℃, the growth pressure is 40-150 mbar, H 2 The flow ratio of Ar is 1 (5-15).
10. The method for manufacturing a HEMT epitaxial wafer according to claim 7, wherein the low-temperature AlN layer and the high-temperature AlN layer are manufactured by MOCVD; the growth temperature of the low-temperature AlN layer is 600-700 ℃, and the growth pressure is 50-100 mbar; the growth temperature of the high-temperature AlN layer is 1000-1200 ℃, and the growth pressure is 50-100 mbar.
CN202311541159.XA 2023-11-20 2023-11-20 HEMT epitaxial wafer and preparation method thereof Pending CN117253918A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9634151B1 (en) * 2015-11-06 2017-04-25 Zing Semiconductor Corporation High voltage junctionless field effect device and its method of fabrication
CN115565876A (en) * 2022-11-07 2023-01-03 湖南三安半导体有限责任公司 Nitride epitaxial structure based on silicon substrate, manufacturing method thereof and semiconductor device
CN116914044A (en) * 2023-05-26 2023-10-20 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9634151B1 (en) * 2015-11-06 2017-04-25 Zing Semiconductor Corporation High voltage junctionless field effect device and its method of fabrication
CN115565876A (en) * 2022-11-07 2023-01-03 湖南三安半导体有限责任公司 Nitride epitaxial structure based on silicon substrate, manufacturing method thereof and semiconductor device
CN116914044A (en) * 2023-05-26 2023-10-20 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

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