US20170104135A1 - Light Emitting Diode Mounting Structure - Google Patents
Light Emitting Diode Mounting Structure Download PDFInfo
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- US20170104135A1 US20170104135A1 US15/291,169 US201615291169A US2017104135A1 US 20170104135 A1 US20170104135 A1 US 20170104135A1 US 201615291169 A US201615291169 A US 201615291169A US 2017104135 A1 US2017104135 A1 US 2017104135A1
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- heatsink
- mounting structure
- optoelectronic
- optoelectronic device
- electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/642—Heat extraction or cooling elements characterized by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0075—Processes relating to semiconductor body packages relating to heat extraction or cooling elements
Definitions
- the disclosure relates generally to light emitting diodes, and more particularly, to a mounting structure for a set of light emitting diodes.
- the light-emitting diodes are often mounted using flip-chip technology onto a ceramic substrate, a printed-circuit board (PCB), or a similar type of mount.
- PCB printed-circuit board
- a mounting structure for a set of optoelectronic devices includes: a body formed of an insulating material; and a heatsink element embedded within the body. A heatsink is located adjacent to the mounting structure. The set of optoelectronic devices are mounted on a side of the mounting structure opposite of the heatsink.
- a first aspect of the invention provides a device comprising: a set of optoelectronic devices; a mounting structure for the set of optoelectronic devices, wherein the mounting structure includes: a body formed of an insulating material; and a heatsink element embedded within the body; and a heatsink located adjacent to the mounting structure.
- a second aspect of the invention provides a device comprising: a first optoelectronic device mounted on a first mounting structure; a second optoelectronic device mounted on a second mounting structure, wherein each mounting structure includes: a body formed of an insulating material; and a heatsink element embedded within the body; and a heatsink, wherein the first mounting structure and the second mounting structure are located on opposite sides of the heatsink.
- a third aspect of the invention provides a method comprising: providing a heatsink including an embedded heatsink element protruding from a lateral surface of the heatsink; depositing an insulating material over the heatsink to form a mounting structure; and mounting an optoelectronic device onto the mounting structure.
- the illustrative aspects of the invention are designed to solve one or more of the problems herein described and/or one or more other problems not discussed.
- FIG. 1 shows a schematic structure of an optoelectronic device according to the prior art.
- FIG. 2A shows a schematic structure of an optoelectronic device according to the prior art
- FIGS. 2B-2E show other examples of flip-chip technologies and mounting structures according to the prior art.
- FIG. 3 shows a schematic structure of an optoelectronic device according to an embodiment.
- FIG. 4 shows a schematic structure of a set of optoelectronic devices according to an embodiment.
- FIG. 5 shows a schematic structure of a set of optoelectronic devices according to an embodiment.
- FIGS. 6A and 6B shows an illustrative heatsink including cooling channels according to an embodiment.
- FIG. 7 shows a schematic structure of an optoelectronic device according to an embodiment.
- FIG. 8 shows a schematic structure of an optoelectronic device according to an embodiment.
- FIGS. 9A and 9B show a top view and a bottom view of an optoelectronic device array according to an embodiment.
- FIG. 10 shows a three-dimensional perspective view of a set of optoelectronic devices according to an embodiment.
- FIG. 11 shows a schematic structure of an optoelectronic device according to an embodiment.
- FIG. 12 shows an illustrative flow diagram for fabricating a circuit that comprises an optoelectronic module according to one the various embodiments described herein.
- a mounting structure for a set of optoelectronic devices includes: a body formed of an insulating material; and a heatsink element embedded within the body. A heatsink is located adjacent to the mounting structure. The set of optoelectronic devices are mounted on a side of the mounting structure opposite of the heatsink.
- the term “set” means one or more (i.e., at least one) and the phrase “any solution” means any now known or later developed solution. It is understood that, unless otherwise specified, each value is approximate and each range of values included herein is inclusive of the end values defining the range. As used herein, unless otherwise noted, the term “approximately” is inclusive of values within +/ ⁇ ten percent of the stated value, while the term “substantially” is inclusive of values within +/ ⁇ five percent of the stated value. Unless otherwise stated, two values are “similar” when the smaller value is within +/ ⁇ twenty-five percent of the larger value. A value, y, is on the order of a stated value, x, when the value y satisfies the formula 0.1x ⁇ y ⁇ 10x.
- a layer is a transparent layer when the layer allows at least ten percent of radiation having a target wavelength, which is radiated at a normal incidence to an interface of the layer, to pass there through.
- a layer is a reflective layer when the layer reflects at least ten percent of radiation having a target wavelength, which is radiated at a normal incidence to an interface of the layer.
- the target wavelength of the radiation corresponds to a wavelength of radiation emitted or sensed (e.g., peak wavelength+/ ⁇ five nanometers) by an active region of an optoelectronic device during operation of the device.
- the wavelength can be measured in a material of consideration and can depend on a refractive index of the material.
- a contact is considered “ohmic” when the contact exhibits close to linear current-voltage behavior over a relevant range of currents/voltages to enable use of a linear dependence to approximate the current-voltage relation through the contact region within the relevant range of currents/voltages to a desired accuracy (e.g., +/ ⁇ one percent).
- FIG. 1 shows a schematic structure of an optoelectronic device 10 according to prior art.
- the optoelectronic device 10 is configured to operate as an emitting device, such as a light emitting diode (LED), UV LEDs, a laser diode (LD), photodiodes, high electron mobility transistors (HEMTs), and/or the like.
- the optoelectronic device 10 can be any type of diode that can be flip-chip mounted under normal operating conditions.
- application of a bias comparable to the band gap results in the emission of electromagnetic radiation from an active region 18 of the optoelectronic device 10 .
- the electromagnetic radiation emitted (or sensed) by the optoelectronic device 10 can have a peak wavelength within any range of wavelengths, including visible light, ultraviolet radiation, deep ultraviolet radiation, infrared light, and/or the like.
- the device 10 is configured to emit (or sense) radiation having a dominant wavelength within the ultraviolet range of wavelengths.
- the dominant wavelength is within a range of wavelengths between approximately 210 and approximately 360 nanometers.
- the optoelectronic device 10 includes a heterostructure 11 comprising a substrate 12 , a buffer layer 14 adjacent to the substrate 12 , an n-type layer 16 (e.g., a cladding layer, electron supply layer, contact layer, and/or the like) adjacent to the buffer layer 14 , and an active region 18 having an n-type side adjacent to the n-type layer 16 .
- a heterostructure 11 comprising a substrate 12 , a buffer layer 14 adjacent to the substrate 12 , an n-type layer 16 (e.g., a cladding layer, electron supply layer, contact layer, and/or the like) adjacent to the buffer layer 14 , and an active region 18 having an n-type side adjacent to the n-type layer 16 .
- n-type layer 16 e.g., a cladding layer, electron supply layer, contact layer, and/or the like
- the heterostructure 11 of the optoelectronic device 10 includes a first p-type layer 20 (e.g., an electron blocking layer, a cladding layer, hole supply layer, and/or the like) adjacent to a p-type side of the active region 18 and a second p-type layer 22 (e.g., a cladding layer, hole supply layer, contact layer, and/or the like) adjacent to the first p-type layer 20 .
- a first p-type layer 20 e.g., an electron blocking layer, a cladding layer, hole supply layer, and/or the like
- a second p-type layer 22 e.g., a cladding layer, hole supply layer, contact layer, and/or the like
- the optoelectronic device 10 is a group III-V materials based device, in which some or all of the various layers are formed of elements selected from the group III-V materials system.
- the various layers of the optoelectronic device 10 are formed of group III nitride based materials.
- Illustrative group III nitride materials include binary, ternary and quaternary alloys such as, AlN, GaN, InN, BN, AlGaN, AlInN, AlBN, AlGaInN, AlGaBN, AlInBN, and AlGaInBN with any molar fraction of group III elements.
- An illustrative embodiment of a group III nitride based optoelectronic device 10 includes an active region 18 (e.g., a series of alternating quantum wells and barriers) composed of In y Al x Ga 1-x-y N, Ga z In y Al x B 1-x-y-z N, an Al x Ga 1-x N semiconductor alloy, or the like.
- the n-type layer 16 , the first p-type layer 20 , and the second p-type layer 22 can be composed of an In y Al x Ga 1-x-y N alloy, a Ga z In y Al x B 1-x-y-z N alloy, or the like.
- the molar fractions given by x, y, and z can vary between the various layers 16 , 18 , 20 , and 22 .
- the substrate 12 and buffer layer 14 should be transparent to the target electromagnetic radiation.
- an embodiment of the substrate 12 is formed of sapphire, and the buffer layer 14 can be composed of AlN, an AlGaN/AlN superlattice, and/or the like.
- the substrate 12 can be formed of any suitable material including, for example, silicon carbide (SiC), silicon (Si), bulk GaN, bulk AlN, bulk or a film of AlGaN, bulk or a film of BN, AlON, LiGaO 2 , LiAlO 2 , aluminum oxinitride (AlO x N y ), MgAl 2 O 4 , GaAs, Ge, or another suitable material.
- a surface of the substrate 12 can be substantially flat or patterned using any solution.
- the optoelectronic device 10 can further include a p-type contact 24 , which can form an ohmic contact to the second p-type layer 22 , and a p-type electrode 26 can be attached to the p-type contact 24 .
- the optoelectronic device 10 can include an n-type contact 28 , which can form an ohmic contact to the n-type layer 16 , and an n-type electrode 30 can be attached to the n-type contact 28 .
- the p-type contact 24 and the n-type contact 28 can form ohmic contacts to the corresponding layers 22 , 16 , respectively.
- the p-type contact 24 and the n-type contact 28 each comprise several conductive and reflective metal layers, while the n-type electrode 30 and the p-type electrode 26 each comprise highly conductive metal.
- the second p-type layer 22 and/or the p-type electrode 26 can be transparent to the electromagnetic radiation generated by the active region 18 .
- the second p-type layer 22 and/or the p-type electrode 26 can comprise a short period superlattice lattice structure, such as an at least partially transparent magnesium (Mg)-doped AlGaN/AlGaN short period superlattice structure (SPSL).
- the p-type electrode 26 and/or the n-type electrode 30 can be reflective of the electromagnetic radiation generated by the active region 18 .
- the n-type layer 16 and/or the n-type electrode 30 can be formed of a short period superlattice, such as an AlGaN SPSL, which is transparent to the electromagnetic radiation generated by the active region 18 .
- the device 10 can be mounted to a submount 36 via the electrodes 26 , 30 in a flip chip configuration.
- the substrate 12 is located on the top of the optoelectronic device 10 .
- the p-type electrode 26 and the n-type electrode 30 can both be attached to a submount 36 via contact pads 32 , 34 , respectively.
- the submount 36 can be formed of aluminum nitride (AlN), silicon carbide (SiC), and/or the like.
- the optoelectronic device 10 can also be mounted on a ceramic substrate mount, a printed circuit board (PCB), and/or the like.
- PCB printed circuit board
- FIG. 2A a schematic structure of a prior art optoelectronic device 40 is shown.
- the optoelectronic device 40 is similar to the device 10 shown in FIG. 1 , but the device 40 is mounted on a PCB 46 .
- the optoelectronic device 40 can comprise a Wafer Integrated Chip on PCB (WICOP) structure by Seoul Semiconductor. Heat 48 is generated and transferred from the contacts 24 , 28 to the PCB 46 .
- WICOP Wafer Integrated Chip on PCB
- FIGS. 2B-2E show other examples of flip-chip technologies and mounting structures.
- FIG. 2B shows a flip chip LED structure by Genesis Photonics. The LED contacts are terminated with metal mounting bumps mated to the metallized pattern formed on the package substrate.
- FIG. 2C shows an LED array by Sem icon West where each LED is flip-chip mounted on a patterned holder.
- FIG. 2D shows a LED chip by LUXEON FlipChip Royal Blue.
- the chip contains two metal bumps terminated with soldering material which provides the ability to flip chip mount the LED on a package or sub-holder.
- FIG. 2E shows an example of a Samsung flip-chip mounted multi-LED structure. The LEDs are mounted on a ceramic substrate. A common issue with all the presented prior art examples is that the substrate or package material present a significant thermal resistance for heat removal from the mounted LEDs.
- FIG. 3 a schematic structure of an illustrative optoelectronic device 50 according to an embodiment is shown.
- the optoelectronic device 50 is configured similar to the optoelectronic devices 10 , 40 shown in FIGS. 1 and 2A .
- the optoelectronic device 50 includes a mounting structure 52 that is formed of an insulating material with high thermal conductivity, such as silicon carbide (SiC), diamond film, aluminum nitride (AlN) ceramic, and/or the like.
- the mounting structure 52 is a thin layer, e.g., approximately tens of microns to a few millimeters.
- the p-type electrode 26 and the n-type electrode 30 are connected to the mounting structure 52 by a set of metal contacts 54 A, 54 B.
- the metal contacts 54 A, 54 B can be formed of any metallic material that is conductive with chemical stability and low oxidation, such as copper, gold, nickel and/or the like.
- the metal contacts 54 A, 54 B can form a set of biasing lines that can connect the electrodes 26 , 30 of different optoelectronic devices 50 .
- An embedded heatsink element 56 is located within the mounting structure 52 and connects the p-type electrode 26 to a heatsink 58 for heat removal.
- the p-type electrode 26 is connected to the p-contact 24 and an active region 18 of the optoelectronic device 50 .
- n-type electrode 30 is not connected to the embedded heatsink element 56 in order to avoid a short-circuit between the n-type electrode 30 and the p-type electrode 26 .
- this is only illustrative and the n-type electrode 30 can be connected to the embedded heatsink element 56 when the n-type electrode 30 provides a more direct path to the active region 18 .
- the heatsink 58 has a thermal resistance to the ambient that is comparable to the total thermal resistance of the device and device junctions.
- the surface of the heatsink 58 can include a plurality of protrusions (not shown) which increases the surface area between the heatsink 58 and the mounting structure 52 in order to further facilitate the heat removal.
- the embedded heatsink element 56 can be formed by making via-holes in the mounting structure 52 and filling the via-hole with a metal material, such as copper, gold, a material with high thermal conductivity, such as AlN, and/or the like.
- the embedded heatsink element 56 can be formed by fabricating a heatsink 58 with the embedded heatsink element 56 and depositing an insulating material to form the mounting structure 52 .
- the embedded heatsink element 56 can be soldered to the heatsink 58 prior to depositing the insulating material for the mounting structure 52 .
- the material of the electrodes 26 , 30 and the embedded heatsink element 56 can include a magnetic component to facilitate automatic alignment of the optoelectronic device 50 with the set of metal contacts 54 A, 54 B.
- the magnetic component can be formed of a material containing iron, or a similarly ferromagnetic metallic element, such as nickel, cobalt, neodymium, alloys of nickel, cobalt, or neodymium, and/or the like.
- the surface of the set of metal contacts 54 A, 54 B can be polished to provide an adequate contact area.
- the magnetic component in the electrodes 26 , 30 and the embedded heatsink element 56 can be for placement guidance only and soldering can be used to connect the electrodes 26 , 30 to the set of metal contacts 54 A, 54 B.
- soldering can be used to connect the electrodes 26 , 30 to the set of metal contacts 54 A, 54 B.
- a soldering material can be applied to the surface of the set of metal contacts 54 A, 54 B and to the surface of the electrodes 26 , 30 .
- the magnetic force between the electrodes 26 , 30 and the embedded heatsink element 56 can be used to guide the electrodes 26 , 30 and the set of metal contacts 54 A, 54 B together.
- the electrodes 26 , 30 and the set of metal contacts 54 A, 54 B can include a set of electric connectors, such as universal serial bus (USB) connectors, and/or the like, to provide accurate contact.
- USB universal serial bus
- the p-type electrode 26 and the n-type electrode 30 are electrically isolated from one another and from the heatsink 58 , which can likely conduct electricity since it can comprise a metallic material, without having a dielectric layer that acts as a barrier to the heat extraction.
- the arrangement of the electrodes 26 , 30 in the mesa region of the optoelectronic device 50 is for exemplary purposes only and that the electrodes 26 , 30 can be arranged in any orientation. Also, the mesa structure of the optoelectronic device 50 can include any shape.
- multiple optoelectronic devices can be connected to a single heatsink.
- a first optoelectronic device 50 A and a second optoelectronic device 50 B are mounted on opposing sides of a heatsink 58 .
- Each optoelectronic device 50 A, 50 B can include all the features of the optoelectronic device 50 shown in FIG. 3 .
- a heatsink 68 that is connected to the first and second optoelectronic devices 50 A, 50 B can include a plurality of cooling channels 62 .
- the cooling channels 62 can be configured to accommodate a cooling gas and/or liquid.
- the embedded channels 62 can be formed using any solution.
- the heatsink 68 can be fabricated by forming a top component 681 and a bottom component 682 with at least one of these components having a plurality of grooves 683 .
- the top and bottom components 681 , 682 also include a plurality of metallized and/or soldered regions 684 that are located between each of the plurality of grooves 683 .
- the top and bottom components 681 , 682 can be soldered together, connected together by fusion, and/or the like so that the channels 62 are formed by the plurality of grooves 683 .
- the channels 62 can be formed by drilling or etching into the heatsink 68 .
- the heatsink 68 can be formed of a porous material, such as carbon, AlN, silicon or nickel powder, and/or the like, that naturally has a plurality of channels 62 .
- the heatsink 68 can be formed of a porous metallic material that is obtained any solution, such as metallic powder sintering, and/or the like.
- a heatsink 68 including a plurality of cooling channels 62 can also include a means for cooling, which can include a fan configured to move air through the channels 62 .
- FIG. 7 a schematic structure of an illustrative optoelectronic device 70 according to an embodiment is shown.
- the mounting structure 72 is similar to the mounting structure 52 shown in FIG. 3 .
- a set of integrated circuit (IC) control components 73 A, 73 B are located between the mounting structure 72 and a heatsink 78 .
- Each of the IC control components 73 A, 73 B include at least the circuitry and contact pads.
- the set of IC control components 73 A, 73 B are configured to allow for the capability to switch the device 70 on or off.
- This on/off switch capability can be important especially in cases when multiple devices are mounted on a heatsink (e.g., devices 50 A, 50 B in FIGS. 4 and 5 ) and require optimal operation.
- the set of IC control components 73 A, 73 B can be located at different locations of the optoelectronic device 70 .
- the sequence of device fabrication can incorporate fabrication of the set of IC control components 73 A, 73 B at different stages.
- the set of IC control components 73 A, 73 B are located on the mounting structure 72 on a side opposite of the set of metal contacts 74 A, 74 B.
- at least one of the set of IC control components 73 A, 73 B can be connected to the heatsink 78 via a set of bumpers 75 A, 75 B. This connection between the IC control components 73 A, 73 B and the heatsink 78 allows for heat removal as well as ground connection for the IC control components 73 A, 73 B.
- the set of IC control components 73 A, 73 B are located on the heatsink 78 .
- the IC control components 73 A, 73 B s are fabricated over an insulating substrate (not shown), such as silicon-on insulator, high-res silicon, sapphire, ceramics, and/or the like, or the IC control components 73 A, 73 B can each have an insulating layer, such as silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), and/or the like, which is deposited on the bottom side of the IC control component.
- the optoelectronic device array 80 can include a plurality of optoelectronic devices 50 that are similar to the device 50 shown in FIG. 3 .
- the devices 50 are mounted on a mounting structure 82 and can be connected in a thin film transistor (TFT) active matrix arrangement, where each optoelectronic device 50 is addressable and can be individually turned on or off.
- TFT thin film transistor
- the device array 80 can include a plurality of bias buses 84 A, 84 B that connect a plurality of IC control components 86 to the plurality of optoelectronic devices 50 .
- the plurality of bias buses 84 A, 84 B form a biasing circuit that can connect or disconnect individual devices 50 to form an array 80 that emits light in various combinations.
- the device array 80 can also include a heatsink (e.g., heatsinks 58 , 68 , 78 shown in FIGS. 5-7 ) but is omitted from FIGS. 9A and 9B for clarity.
- FIG. 10 a three-dimensional perspective view of a set of optoelectronic devices 90 A, 90 B according to an embodiment is shown.
- the set of optoelectronic devices 90 A, 90 B are positioned similar to the optoelectronic devices 50 A, 50 B shown in FIGS. 4 and 5 .
- a heatsink 91 is provided between each of the optoelectronic devices 90 A, 90 B and is used as both a heatsink and a mounting structure.
- the heatsink 91 is fabricated using insulating materials with high thermal conductivity, such as aluminum nitride, boron nitride, diamond and/or the like.
- the optoelectronic devices 90 A, 90 B have common electrodes (e.g. p-type electrodes 97 A, 97 B) connected by an embedded heatsink element 96 .
- the heatsink 91 extends laterally in both directions into a first heatsink domain 98 A and a second heatsink domain 98 B.
- Each heatsink domain 98 A, 98 B can include a plurality of fins 92 that are configured to provide improved convective heat cooling.
- fans and/or other cooling devices can be included for further improved convective cooling.
- only a single heatsink domain can be provided.
- the heatsink domains 98 A, 98 B can be formed of the same or different materials.
- the heatsink domains 98 A, 98 B can be different structures.
- the first heatsink domain 98 A can be formed of a porous metallic material (e.g., with cooling channels), while the second heatsink domain 98 B includes the plurality of fins 92 . Regardless, it is understood that the heatsink domains 98 A, 98 B can include any number of fins 92 .
- the devices 90 A, 90 B can be positioned arbitrarily over the heatsink 91 , depending on the arrangement of the electrodes of the devices 90 A, 90 B.
- the n-type electrode 94 A, 94 B of each device 90 A, 90 B are positioned laterally along the heatsink 91 .
- the embedded heatsink element 96 which is formed of a thermally conductive filler material, can be deposited to improve heat extraction from each device 90 A, 90 B.
- the thermally conductive filler material for the embedded heatsink element 96 can be any material that is electrically insulating, such as amorphous AlN ceramics, SiC, diamond powder, diamond base grease, and/or the like.
- the embedded heatsink element 96 has a thermal conductivity of at least ten percent of the thermal conductivity of the heatsink 91 .
- the thermally conductive filler material can be formed of any metal material that is electrically conductive.
- FIG. 11 a schematic structure of an illustrative optoelectronic device 100 according to an embodiment in shown.
- the n-type electrode 130 and the p-type electrode 126 are electrically isolated by an insulator layer 190 .
- the insulator layer 190 is formed of a material that UV transparent, UV reflective, or both.
- a thermally conductive filler material 196 is deposited adjacent to the insulator layer 190 .
- the thermally conductive filler material 196 is formed of a material that is UV reflective.
- an additional temperature control module can infer a junction temperature of the optoelectronic device by measuring the temperature at at least one point in the heatsink and alter the operation of the optoelectronic device to maintain an acceptable heating level and/or thermal load.
- the temperature control module can include an algorithm for temporal adjustment of the intensity of each optoelectronic device to maintain acceptable thermal loads and/or heating levels for each device while maintaining the largest possible emission requirement for the array of optoelectronic devices.
- the intensity of the operation of the optoelectronic devices can vary with time to maintain an acceptable thermal load.
- the time dependent intensity can vary, but still maintain a continuous emission of radiation.
- the temperature control module can be configured to provide recorded data of the thermal loads and intensity of each optoelectronic device as a function of time.
- a signaling module can also be provided to indicate the temperature of the optoelectronic device.
- the signaling module can comprise an optical visible mission source where the intensity of the emission correlates to the heating of the optoelectronic device.
- the invention provides a method of designing and/or fabricating a circuit that includes one or more of the devices designed and fabricated as described herein.
- FIG. 12 shows an illustrative flow diagram for fabricating a circuit 1026 according to an embodiment.
- a user can utilize a device design system 1010 to generate a device design 1012 for a semiconductor device as described herein.
- the device design 1012 can comprise program code, which can be used by a device fabrication system 1014 to generate a set of physical devices 1016 according to the features defined by the device design 1012 .
- the device design 1012 can be provided to a circuit design system 1020 (e.g., as an available component for use in circuits), which a user can utilize to generate a circuit design 1022 (e.g., by connecting one or more inputs and outputs to various devices included in a circuit).
- the circuit design 1022 can comprise program code that includes a device designed as described herein.
- the circuit design 1022 and/or one or more physical devices 1016 can be provided to a circuit fabrication system 1024 , which can generate a physical circuit 1026 according to the circuit design 1022 .
- the physical circuit 1026 can include one or more devices 1016 designed as described herein.
- the invention provides a device design system 1010 for designing and/or a device fabrication system 1014 for fabricating a semiconductor device 1016 as described herein.
- the system 1010 , 1014 can comprise a general purpose computing device, which is programmed to implement a method of designing and/or fabricating the semiconductor device 1016 as described herein.
- an embodiment of the invention provides a circuit design system 1020 for designing and/or a circuit fabrication system 1024 for fabricating a circuit 1026 that includes at least one device 1016 designed and/or fabricated as described herein.
- the system 1020 , 1024 can comprise a general purpose computing device, which is programmed to implement a method of designing and/or fabricating the circuit 1026 including at least one semiconductor device 1016 as described herein.
- the invention provides a computer program fixed in at least one computer-readable medium, which when executed, enables a computer system to implement a method of designing and/or fabricating a semiconductor device as described herein.
- the computer program can enable the device design system 1010 to generate the device design 1012 as described herein.
- the computer-readable medium includes program code, which implements some or all of a process described herein when executed by the computer system. It is understood that the term “computer-readable medium” comprises one or more of any type of tangible medium of expression, now known or later developed, from which a stored copy of the program code can be perceived, reproduced, or otherwise communicated by a computing device.
- the invention provides a method of providing a copy of program code, which implements some or all of a process described herein when executed by a computer system.
- a computer system can process a copy of the program code to generate and transmit, for reception at a second, distinct location, a set of data signals that has one or more of its characteristics set and/or changed in such a manner as to encode a copy of the program code in the set of data signals.
- an embodiment of the invention provides a method of acquiring a copy of program code that implements some or all of a process described herein, which includes a computer system receiving the set of data signals described herein, and translating the set of data signals into a copy of the computer program fixed in at least one computer-readable medium. In either case, the set of data signals can be transmitted/received using any type of communications link.
- the invention provides a method of generating a device design system 1010 for designing and/or a device fabrication system 1014 for fabricating a semiconductor device as described herein.
- a computer system can be obtained (e.g., created, maintained, made available, etc.) and one or more components for performing a process described herein can be obtained (e.g., created, purchased, used, modified, etc.) and deployed to the computer system.
- the deployment can comprise one or more of: (1) installing program code on a computing device; (2) adding one or more computing and/or I/O devices to the computer system; (3) incorporating and/or modifying the computer system to enable it to perform a process described herein; and/or the like.
Abstract
A mounting structure for mounting a set of optoelectronic devices is provided. A mounting structure for a set of optoelectronic devices can include: a body formed of an insulating material; and a heatsink element embedded within the body. A heatsink can be located adjacent to the mounting structure. The set of optoelectronic devices can be mounted on a side of the mounting structure opposite of the heatsink.
Description
- The current application claims the benefit of U.S. Provisional Application No. 62/240,585, which was filed on 13 Oct. 2015, and which is hereby incorporated by reference.
- The disclosure relates generally to light emitting diodes, and more particularly, to a mounting structure for a set of light emitting diodes.
- A great deal of interest has been focused on light emitting diodes and lasers, in particular those that emit light in the blue and deep ultraviolet (UV) wavelengths. These devices may be capable of being incorporated into various applications, including solid-state lighting, biochemical detection, high-density data storage, and the like.
- To increase the light output, the light-emitting diodes (LED) are often mounted using flip-chip technology onto a ceramic substrate, a printed-circuit board (PCB), or a similar type of mount. Although this technology helps light extraction and has high yield and production efficiency, it does not provide a path for heat removal that is as efficient as metal or metal-ceramic packages.
- Aspects of the invention provide a mounting structure for mounting a set of optoelectronic devices. In an embodiment, a mounting structure for a set of optoelectronic devices includes: a body formed of an insulating material; and a heatsink element embedded within the body. A heatsink is located adjacent to the mounting structure. The set of optoelectronic devices are mounted on a side of the mounting structure opposite of the heatsink.
- A first aspect of the invention provides a device comprising: a set of optoelectronic devices; a mounting structure for the set of optoelectronic devices, wherein the mounting structure includes: a body formed of an insulating material; and a heatsink element embedded within the body; and a heatsink located adjacent to the mounting structure.
- A second aspect of the invention provides a device comprising: a first optoelectronic device mounted on a first mounting structure; a second optoelectronic device mounted on a second mounting structure, wherein each mounting structure includes: a body formed of an insulating material; and a heatsink element embedded within the body; and a heatsink, wherein the first mounting structure and the second mounting structure are located on opposite sides of the heatsink.
- A third aspect of the invention provides a method comprising: providing a heatsink including an embedded heatsink element protruding from a lateral surface of the heatsink; depositing an insulating material over the heatsink to form a mounting structure; and mounting an optoelectronic device onto the mounting structure.
- The illustrative aspects of the invention are designed to solve one or more of the problems herein described and/or one or more other problems not discussed.
- These and other features of the disclosure will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various aspects of the invention.
-
FIG. 1 shows a schematic structure of an optoelectronic device according to the prior art. -
FIG. 2A shows a schematic structure of an optoelectronic device according to the prior art, whileFIGS. 2B-2E show other examples of flip-chip technologies and mounting structures according to the prior art. -
FIG. 3 shows a schematic structure of an optoelectronic device according to an embodiment. -
FIG. 4 shows a schematic structure of a set of optoelectronic devices according to an embodiment. -
FIG. 5 shows a schematic structure of a set of optoelectronic devices according to an embodiment. -
FIGS. 6A and 6B shows an illustrative heatsink including cooling channels according to an embodiment. -
FIG. 7 shows a schematic structure of an optoelectronic device according to an embodiment. -
FIG. 8 shows a schematic structure of an optoelectronic device according to an embodiment. -
FIGS. 9A and 9B show a top view and a bottom view of an optoelectronic device array according to an embodiment. -
FIG. 10 shows a three-dimensional perspective view of a set of optoelectronic devices according to an embodiment. -
FIG. 11 shows a schematic structure of an optoelectronic device according to an embodiment. -
FIG. 12 shows an illustrative flow diagram for fabricating a circuit that comprises an optoelectronic module according to one the various embodiments described herein. - It is noted that the drawings may not be to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings.
- As indicated above, aspects of the invention provide a mounting structure for mounting a set of optoelectronic devices. In an embodiment, a mounting structure for a set of optoelectronic devices includes: a body formed of an insulating material; and a heatsink element embedded within the body. A heatsink is located adjacent to the mounting structure. The set of optoelectronic devices are mounted on a side of the mounting structure opposite of the heatsink.
- As used herein, unless otherwise noted, the term “set” means one or more (i.e., at least one) and the phrase “any solution” means any now known or later developed solution. It is understood that, unless otherwise specified, each value is approximate and each range of values included herein is inclusive of the end values defining the range. As used herein, unless otherwise noted, the term “approximately” is inclusive of values within +/−ten percent of the stated value, while the term “substantially” is inclusive of values within +/−five percent of the stated value. Unless otherwise stated, two values are “similar” when the smaller value is within +/−twenty-five percent of the larger value. A value, y, is on the order of a stated value, x, when the value y satisfies the formula 0.1x≦y≦10x.
- As also used herein, a layer is a transparent layer when the layer allows at least ten percent of radiation having a target wavelength, which is radiated at a normal incidence to an interface of the layer, to pass there through. Furthermore, as used herein, a layer is a reflective layer when the layer reflects at least ten percent of radiation having a target wavelength, which is radiated at a normal incidence to an interface of the layer. In an embodiment, the target wavelength of the radiation corresponds to a wavelength of radiation emitted or sensed (e.g., peak wavelength+/−five nanometers) by an active region of an optoelectronic device during operation of the device. For a given layer, the wavelength can be measured in a material of consideration and can depend on a refractive index of the material. Additionally, as used herein, a contact is considered “ohmic” when the contact exhibits close to linear current-voltage behavior over a relevant range of currents/voltages to enable use of a linear dependence to approximate the current-voltage relation through the contact region within the relevant range of currents/voltages to a desired accuracy (e.g., +/−one percent).
- Turning to the drawings,
FIG. 1 shows a schematic structure of anoptoelectronic device 10 according to prior art. In a more particular embodiment, theoptoelectronic device 10 is configured to operate as an emitting device, such as a light emitting diode (LED), UV LEDs, a laser diode (LD), photodiodes, high electron mobility transistors (HEMTs), and/or the like. More generally, theoptoelectronic device 10 can be any type of diode that can be flip-chip mounted under normal operating conditions. In any case, during operation of theoptoelectronic device 10, application of a bias comparable to the band gap results in the emission of electromagnetic radiation from anactive region 18 of theoptoelectronic device 10. The electromagnetic radiation emitted (or sensed) by theoptoelectronic device 10 can have a peak wavelength within any range of wavelengths, including visible light, ultraviolet radiation, deep ultraviolet radiation, infrared light, and/or the like. In an embodiment, thedevice 10 is configured to emit (or sense) radiation having a dominant wavelength within the ultraviolet range of wavelengths. In a more specific embodiment, the dominant wavelength is within a range of wavelengths between approximately 210 and approximately 360 nanometers. - The
optoelectronic device 10 includes aheterostructure 11 comprising asubstrate 12, abuffer layer 14 adjacent to thesubstrate 12, an n-type layer 16 (e.g., a cladding layer, electron supply layer, contact layer, and/or the like) adjacent to thebuffer layer 14, and anactive region 18 having an n-type side adjacent to the n-type layer 16. Furthermore, theheterostructure 11 of theoptoelectronic device 10 includes a first p-type layer 20 (e.g., an electron blocking layer, a cladding layer, hole supply layer, and/or the like) adjacent to a p-type side of theactive region 18 and a second p-type layer 22 (e.g., a cladding layer, hole supply layer, contact layer, and/or the like) adjacent to the first p-type layer 20. - In a more particular illustrative embodiment, the
optoelectronic device 10 is a group III-V materials based device, in which some or all of the various layers are formed of elements selected from the group III-V materials system. In a still more particular illustrative embodiment, the various layers of theoptoelectronic device 10 are formed of group III nitride based materials. Group III nitride materials comprise one or more group III elements (e.g., boron (B), aluminum (Al), gallium (Ga), and indium (In)) and nitrogen (N), such that BWAlXGaYInZN, where 0≦W, X, Y, Z≦1, and W+X+Y+Z=1. Illustrative group III nitride materials include binary, ternary and quaternary alloys such as, AlN, GaN, InN, BN, AlGaN, AlInN, AlBN, AlGaInN, AlGaBN, AlInBN, and AlGaInBN with any molar fraction of group III elements. - An illustrative embodiment of a group III nitride based
optoelectronic device 10 includes an active region 18 (e.g., a series of alternating quantum wells and barriers) composed of InyAlxGa1-x-yN, GazInyAlxB1-x-y-zN, an AlxGa1-xN semiconductor alloy, or the like. Similarly, the n-type layer 16, the first p-type layer 20, and the second p-type layer 22 can be composed of an InyAlxGa1-x-yN alloy, a GazInyAlxB1-x-y-zN alloy, or the like. The molar fractions given by x, y, and z can vary between thevarious layers optoelectronic device 10 is configured to be operated in a flip chip configuration, such as shown inFIG. 1 , thesubstrate 12 andbuffer layer 14 should be transparent to the target electromagnetic radiation. To this extent, an embodiment of thesubstrate 12 is formed of sapphire, and thebuffer layer 14 can be composed of AlN, an AlGaN/AlN superlattice, and/or the like. However, it is understood that thesubstrate 12 can be formed of any suitable material including, for example, silicon carbide (SiC), silicon (Si), bulk GaN, bulk AlN, bulk or a film of AlGaN, bulk or a film of BN, AlON, LiGaO2, LiAlO2, aluminum oxinitride (AlOxNy), MgAl2O4, GaAs, Ge, or another suitable material. Furthermore, a surface of thesubstrate 12 can be substantially flat or patterned using any solution. - The
optoelectronic device 10 can further include a p-type contact 24, which can form an ohmic contact to the second p-type layer 22, and a p-type electrode 26 can be attached to the p-type contact 24. Similarly, theoptoelectronic device 10 can include an n-type contact 28, which can form an ohmic contact to the n-type layer 16, and an n-type electrode 30 can be attached to the n-type contact 28. The p-type contact 24 and the n-type contact 28 can form ohmic contacts to thecorresponding layers - In an embodiment, the p-
type contact 24 and the n-type contact 28 each comprise several conductive and reflective metal layers, while the n-type electrode 30 and the p-type electrode 26 each comprise highly conductive metal. In an embodiment, the second p-type layer 22 and/or the p-type electrode 26 can be transparent to the electromagnetic radiation generated by theactive region 18. For example, the second p-type layer 22 and/or the p-type electrode 26 can comprise a short period superlattice lattice structure, such as an at least partially transparent magnesium (Mg)-doped AlGaN/AlGaN short period superlattice structure (SPSL). Furthermore, the p-type electrode 26 and/or the n-type electrode 30 can be reflective of the electromagnetic radiation generated by theactive region 18. In another embodiment, the n-type layer 16 and/or the n-type electrode 30 can be formed of a short period superlattice, such as an AlGaN SPSL, which is transparent to the electromagnetic radiation generated by theactive region 18. - As further shown with respect to the
optoelectronic device 10, thedevice 10 can be mounted to asubmount 36 via theelectrodes substrate 12 is located on the top of theoptoelectronic device 10. To this extent, the p-type electrode 26 and the n-type electrode 30 can both be attached to asubmount 36 viacontact pads submount 36 can be formed of aluminum nitride (AlN), silicon carbide (SiC), and/or the like. - As mentioned above, to increase the light output, the
optoelectronic device 10 can also be mounted on a ceramic substrate mount, a printed circuit board (PCB), and/or the like. For example, inFIG. 2A , a schematic structure of a priorart optoelectronic device 40 is shown. Theoptoelectronic device 40 is similar to thedevice 10 shown inFIG. 1 , but thedevice 40 is mounted on aPCB 46. Theoptoelectronic device 40 can comprise a Wafer Integrated Chip on PCB (WICOP) structure by Seoul Semiconductor.Heat 48 is generated and transferred from thecontacts PCB 46. The main disadvantage of thisdevice 40 is that thecontacts FIGS. 2B-2E show other examples of flip-chip technologies and mounting structures.FIG. 2B shows a flip chip LED structure by Genesis Photonics. The LED contacts are terminated with metal mounting bumps mated to the metallized pattern formed on the package substrate.FIG. 2C shows an LED array by Sem icon West where each LED is flip-chip mounted on a patterned holder.FIG. 2D shows a LED chip by LUXEON FlipChip Royal Blue. The chip contains two metal bumps terminated with soldering material which provides the ability to flip chip mount the LED on a package or sub-holder.FIG. 2E shows an example of a Samsung flip-chip mounted multi-LED structure. The LEDs are mounted on a ceramic substrate. A common issue with all the presented prior art examples is that the substrate or package material present a significant thermal resistance for heat removal from the mounted LEDs. - Turning now to
FIG. 3 , a schematic structure of an illustrativeoptoelectronic device 50 according to an embodiment is shown. Theoptoelectronic device 50 is configured similar to theoptoelectronic devices FIGS. 1 and 2A . However, theoptoelectronic device 50 includes a mountingstructure 52 that is formed of an insulating material with high thermal conductivity, such as silicon carbide (SiC), diamond film, aluminum nitride (AlN) ceramic, and/or the like. The mountingstructure 52 is a thin layer, e.g., approximately tens of microns to a few millimeters. - The p-
type electrode 26 and the n-type electrode 30 are connected to the mountingstructure 52 by a set ofmetal contacts metal contacts metal contacts electrodes optoelectronic devices 50. An embeddedheatsink element 56 is located within the mountingstructure 52 and connects the p-type electrode 26 to aheatsink 58 for heat removal. The p-type electrode 26 is connected to the p-contact 24 and anactive region 18 of theoptoelectronic device 50. This arrangement provides the shortest path and the smallest thermal resistance from the deviceactive region 18 to theheatsink 58. The n-type electrode 30 is not connected to the embeddedheatsink element 56 in order to avoid a short-circuit between the n-type electrode 30 and the p-type electrode 26. However, it is understood that this is only illustrative and the n-type electrode 30 can be connected to the embeddedheatsink element 56 when the n-type electrode 30 provides a more direct path to theactive region 18. - The
heatsink 58 has a thermal resistance to the ambient that is comparable to the total thermal resistance of the device and device junctions. The surface of theheatsink 58 can include a plurality of protrusions (not shown) which increases the surface area between theheatsink 58 and the mountingstructure 52 in order to further facilitate the heat removal. In an embodiment, the embeddedheatsink element 56 can be formed by making via-holes in the mountingstructure 52 and filling the via-hole with a metal material, such as copper, gold, a material with high thermal conductivity, such as AlN, and/or the like. In another embodiment, the embeddedheatsink element 56 can be formed by fabricating aheatsink 58 with the embeddedheatsink element 56 and depositing an insulating material to form the mountingstructure 52. In another embodiment, the embeddedheatsink element 56 can be soldered to theheatsink 58 prior to depositing the insulating material for the mountingstructure 52. - In an embodiment, the material of the
electrodes heatsink element 56 can include a magnetic component to facilitate automatic alignment of theoptoelectronic device 50 with the set ofmetal contacts metal contacts electrodes heatsink element 56 can be for placement guidance only and soldering can be used to connect theelectrodes metal contacts metal contacts electrodes electrodes heatsink element 56 can be used to guide theelectrodes metal contacts electrodes metal contacts - By having a mounting
structure 52, the p-type electrode 26 and the n-type electrode 30 are electrically isolated from one another and from theheatsink 58, which can likely conduct electricity since it can comprise a metallic material, without having a dielectric layer that acts as a barrier to the heat extraction. - It is understood that the arrangement of the
electrodes optoelectronic device 50 is for exemplary purposes only and that theelectrodes optoelectronic device 50 can include any shape. - In an embodiment, multiple optoelectronic devices can be connected to a single heatsink. For example, as shown in
FIG. 4 , a firstoptoelectronic device 50A and a secondoptoelectronic device 50B are mounted on opposing sides of aheatsink 58. Eachoptoelectronic device optoelectronic device 50 shown inFIG. 3 . - In another embodiment, as seen in
FIG. 5 , aheatsink 68 that is connected to the first and secondoptoelectronic devices cooling channels 62. The coolingchannels 62 can be configured to accommodate a cooling gas and/or liquid. The embeddedchannels 62 can be formed using any solution. - In an illustrative example shown in
FIGS. 6A and 6B , theheatsink 68 can be fabricated by forming atop component 681 and abottom component 682 with at least one of these components having a plurality ofgrooves 683. The top andbottom components regions 684 that are located between each of the plurality ofgrooves 683. The top andbottom components channels 62 are formed by the plurality ofgrooves 683. In another embodiment, thechannels 62 can be formed by drilling or etching into theheatsink 68. In another embodiment, theheatsink 68 can be formed of a porous material, such as carbon, AlN, silicon or nickel powder, and/or the like, that naturally has a plurality ofchannels 62. For example, theheatsink 68 can be formed of a porous metallic material that is obtained any solution, such as metallic powder sintering, and/or the like. Aheatsink 68 including a plurality ofcooling channels 62 can also include a means for cooling, which can include a fan configured to move air through thechannels 62. - Turning now to
FIG. 7 , a schematic structure of an illustrativeoptoelectronic device 70 according to an embodiment is shown. In this embodiment, the mountingstructure 72 is similar to the mountingstructure 52 shown inFIG. 3 . However, inFIG. 7 , a set of integrated circuit (IC)control components structure 72 and aheatsink 78. Each of theIC control components IC control components device 70 on or off. This on/off switch capability can be important especially in cases when multiple devices are mounted on a heatsink (e.g.,devices FIGS. 4 and 5 ) and require optimal operation. The set ofIC control components optoelectronic device 70. - The sequence of device fabrication can incorporate fabrication of the set of
IC control components FIG. 7 , the set ofIC control components structure 72 on a side opposite of the set ofmetal contacts IC control components heatsink 78 via a set ofbumpers IC control components heatsink 78 allows for heat removal as well as ground connection for theIC control components - In another embodiment shown in
FIG. 8 , the set ofIC control components heatsink 78. In this embodiment, theIC control components IC control components - Turning now to
FIGS. 9A and 9B , a top view and a bottom view of an illustrativeoptoelectronic device array 80 according to an embodiment is shown. Theoptoelectronic device array 80 can include a plurality ofoptoelectronic devices 50 that are similar to thedevice 50 shown inFIG. 3 . Thedevices 50 are mounted on a mountingstructure 82 and can be connected in a thin film transistor (TFT) active matrix arrangement, where eachoptoelectronic device 50 is addressable and can be individually turned on or off. The bottom view of thedevice array 80 is shown inFIG. 9B . Thedevice array 80 can include a plurality ofbias buses IC control components 86 to the plurality ofoptoelectronic devices 50. The plurality ofbias buses individual devices 50 to form anarray 80 that emits light in various combinations. Thedevice array 80 can also include a heatsink (e.g.,heatsinks FIGS. 5-7 ) but is omitted fromFIGS. 9A and 9B for clarity. - Turning now to
FIG. 10 , a three-dimensional perspective view of a set ofoptoelectronic devices 90A, 90B according to an embodiment is shown. The set ofoptoelectronic devices 90A, 90B are positioned similar to theoptoelectronic devices FIGS. 4 and 5 . In this embodiment, aheatsink 91 is provided between each of theoptoelectronic devices 90A, 90B and is used as both a heatsink and a mounting structure. To provide electrical isolation, theheatsink 91 is fabricated using insulating materials with high thermal conductivity, such as aluminum nitride, boron nitride, diamond and/or the like. - The
optoelectronic devices 90A, 90B have common electrodes (e.g. p-type electrodes heatsink element 96. Theheatsink 91 extends laterally in both directions into afirst heatsink domain 98A and asecond heatsink domain 98B. Eachheatsink domain fins 92 that are configured to provide improved convective heat cooling. In an embodiment, fans and/or other cooling devices can be included for further improved convective cooling. In another embodiment, only a single heatsink domain can be provided. For example, only one of thefirst heatsink domain 98A or thesecond heatsink domain 98B can be included between theoptoelectronic devices 90A, 90B. In an embodiment, theheatsink domains heatsink domains first heatsink domain 98A can be formed of a porous metallic material (e.g., with cooling channels), while thesecond heatsink domain 98B includes the plurality offins 92. Regardless, it is understood that theheatsink domains fins 92. - The
devices 90A, 90B can be positioned arbitrarily over theheatsink 91, depending on the arrangement of the electrodes of thedevices 90A, 90B. For example, inFIG. 10 , the n-type electrode device 90A, 90B are positioned laterally along theheatsink 91. Between the p-type electrodes device 90A, 90B, the embeddedheatsink element 96, which is formed of a thermally conductive filler material, can be deposited to improve heat extraction from eachdevice 90A, 90B. The thermally conductive filler material for the embeddedheatsink element 96 can be any material that is electrically insulating, such as amorphous AlN ceramics, SiC, diamond powder, diamond base grease, and/or the like. In an embodiment, the embeddedheatsink element 96 has a thermal conductivity of at least ten percent of the thermal conductivity of theheatsink 91. - In another embodiment, the thermally conductive filler material can be formed of any metal material that is electrically conductive. For example, in
FIG. 11 , a schematic structure of an illustrativeoptoelectronic device 100 according to an embodiment in shown. In this embodiment, the n-type electrode 130 and the p-type electrode 126 are electrically isolated by aninsulator layer 190. Theinsulator layer 190 is formed of a material that UV transparent, UV reflective, or both. A thermallyconductive filler material 196 is deposited adjacent to theinsulator layer 190. The thermallyconductive filler material 196 is formed of a material that is UV reflective. - In any of the embodiments provided, an additional temperature control module can infer a junction temperature of the optoelectronic device by measuring the temperature at at least one point in the heatsink and alter the operation of the optoelectronic device to maintain an acceptable heating level and/or thermal load. The temperature control module can include an algorithm for temporal adjustment of the intensity of each optoelectronic device to maintain acceptable thermal loads and/or heating levels for each device while maintaining the largest possible emission requirement for the array of optoelectronic devices. In an embodiment, the intensity of the operation of the optoelectronic devices can vary with time to maintain an acceptable thermal load. In a further embodiment, the time dependent intensity can vary, but still maintain a continuous emission of radiation. The temperature control module can be configured to provide recorded data of the thermal loads and intensity of each optoelectronic device as a function of time. A signaling module can also be provided to indicate the temperature of the optoelectronic device. The signaling module can comprise an optical visible mission source where the intensity of the emission correlates to the heating of the optoelectronic device.
- In one embodiment, the invention provides a method of designing and/or fabricating a circuit that includes one or more of the devices designed and fabricated as described herein. To this extent,
FIG. 12 shows an illustrative flow diagram for fabricating acircuit 1026 according to an embodiment. Initially, a user can utilize adevice design system 1010 to generate a device design 1012 for a semiconductor device as described herein. The device design 1012 can comprise program code, which can be used by adevice fabrication system 1014 to generate a set ofphysical devices 1016 according to the features defined by the device design 1012. Similarly, the device design 1012 can be provided to a circuit design system 1020 (e.g., as an available component for use in circuits), which a user can utilize to generate a circuit design 1022 (e.g., by connecting one or more inputs and outputs to various devices included in a circuit). Thecircuit design 1022 can comprise program code that includes a device designed as described herein. In any event, thecircuit design 1022 and/or one or morephysical devices 1016 can be provided to acircuit fabrication system 1024, which can generate aphysical circuit 1026 according to thecircuit design 1022. Thephysical circuit 1026 can include one ormore devices 1016 designed as described herein. - In another embodiment, the invention provides a
device design system 1010 for designing and/or adevice fabrication system 1014 for fabricating asemiconductor device 1016 as described herein. In this case, thesystem semiconductor device 1016 as described herein. Similarly, an embodiment of the invention provides acircuit design system 1020 for designing and/or acircuit fabrication system 1024 for fabricating acircuit 1026 that includes at least onedevice 1016 designed and/or fabricated as described herein. In this case, thesystem circuit 1026 including at least onesemiconductor device 1016 as described herein. - In still another embodiment, the invention provides a computer program fixed in at least one computer-readable medium, which when executed, enables a computer system to implement a method of designing and/or fabricating a semiconductor device as described herein. For example, the computer program can enable the
device design system 1010 to generate the device design 1012 as described herein. To this extent, the computer-readable medium includes program code, which implements some or all of a process described herein when executed by the computer system. It is understood that the term “computer-readable medium” comprises one or more of any type of tangible medium of expression, now known or later developed, from which a stored copy of the program code can be perceived, reproduced, or otherwise communicated by a computing device. - In another embodiment, the invention provides a method of providing a copy of program code, which implements some or all of a process described herein when executed by a computer system. In this case, a computer system can process a copy of the program code to generate and transmit, for reception at a second, distinct location, a set of data signals that has one or more of its characteristics set and/or changed in such a manner as to encode a copy of the program code in the set of data signals. Similarly, an embodiment of the invention provides a method of acquiring a copy of program code that implements some or all of a process described herein, which includes a computer system receiving the set of data signals described herein, and translating the set of data signals into a copy of the computer program fixed in at least one computer-readable medium. In either case, the set of data signals can be transmitted/received using any type of communications link.
- In still another embodiment, the invention provides a method of generating a
device design system 1010 for designing and/or adevice fabrication system 1014 for fabricating a semiconductor device as described herein. In this case, a computer system can be obtained (e.g., created, maintained, made available, etc.) and one or more components for performing a process described herein can be obtained (e.g., created, purchased, used, modified, etc.) and deployed to the computer system. To this extent, the deployment can comprise one or more of: (1) installing program code on a computing device; (2) adding one or more computing and/or I/O devices to the computer system; (3) incorporating and/or modifying the computer system to enable it to perform a process described herein; and/or the like. - The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to an individual in the art are included within the scope of the invention as defined by the accompanying claims.
Claims (20)
1. A device comprising:
a set of optoelectronic devices;
a mounting structure for the set of optoelectronic devices, wherein the mounting structure includes:
a body formed of an insulating material; and
a heatsink element embedded within the body; and
a heatsink located adjacent to the mounting structure.
2. The device of claim 1 , wherein the mounting structure further includes a set of metal contacts that are connected to a set of electrodes for each optoelectronic device.
3. The device of claim 2 , wherein the set of metal contacts connect the set of optoelectronic devices.
4. The device of claim 2 , wherein the set of electrodes and the embedded heatsink element each include a magnetic component configured to facilitate automatic alignment of each optoelectronic device on the mounting structure.
5. The device of claim 2 , further comprising a set of integrated circuit (IC) control components located between the mounting structure and the heatsink, wherein the set of IC control components are configured to control each optoelectronic device.
6. The device of claim 1 , further comprising a second set of optoelectronic devices and a second mounting structure, wherein the second set of optoelectronic devices and the second mounting structure are located on an opposite side of the heatsink as the set of optoelectronic devices and the mounting structure.
7. The device of claim 1 , wherein the set of optoelectronic devices form a thin film transistor (TFT) active matrix arrangement.
8. The device of claim 1 , wherein the heatsink includes a plurality of cooling channels.
9. The device of claim 1 , wherein the heatsink includes a first domain and a second domain and each domain includes a plurality of fins.
10. The device of claim 1 , wherein the set of optoelectronic devices include UV LEDs.
11. A device comprising:
a first optoelectronic device mounted on a first mounting structure;
a second optoelectronic device mounted on a second mounting structure, wherein each mounting structure includes:
a body formed of an insulating material; and
a heatsink element embedded within the body; and
a heatsink, wherein the first mounting structure and the second mounting structure are located on opposite sides of the heatsink.
12. The device of claim 11 , wherein the first and second mounting structures each include a set of metal contacts that are connected to a set of electrodes for each optoelectronic device.
13. The device of claim 12 , wherein the set of electrodes and the embedded heatsink element each include a magnetic component configured to facilitate automatic alignment of each optoelectronic device on the each mounting structure.
14. The device of claim 11 , wherein the heatsink includes a plurality of cooling channels.
15. The device of claim 14 , wherein the heatsink is formed of a porous material.
16. The device of claim 11 , wherein the heatsink includes a first domain and a second domain and each domain includes a plurality of fins.
17. A method comprising:
providing a heatsink including an embedded heatsink element protruding from a lateral surface of the heatsink;
depositing an insulating material over the heatsink to form a mounting structure; and
mounting an optoelectronic device onto the mounting structure.
18. The method of claim 17 , further comprising depositing a set of metal contacts onto a surface of the mounting structure prior to mounting the optoelectronic device.
19. The method of claim 18 , wherein mounting the optoelectronic device includes electrically connecting a set of electrodes of the optoelectronic device to the set of metal contacts.
20. The method of claim 19 , wherein electrically connecting the set of electrodes of the optoelectronic device to the set of metal contacts includes soldering.
Priority Applications (3)
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US15/291,169 US20170104135A1 (en) | 2015-10-13 | 2016-10-12 | Light Emitting Diode Mounting Structure |
US15/926,166 US11329196B2 (en) | 2015-10-13 | 2018-03-20 | Optoelectronic device mounting structure with embedded heatsink element |
US17/715,238 US20220231199A1 (en) | 2015-10-13 | 2022-04-07 | Optoelectronic Device Mounting Structure with Embedded Heatsink Element |
Applications Claiming Priority (2)
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US201562240585P | 2015-10-13 | 2015-10-13 | |
US15/291,169 US20170104135A1 (en) | 2015-10-13 | 2016-10-12 | Light Emitting Diode Mounting Structure |
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US15/926,166 Continuation US11329196B2 (en) | 2015-10-13 | 2018-03-20 | Optoelectronic device mounting structure with embedded heatsink element |
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US20170104135A1 true US20170104135A1 (en) | 2017-04-13 |
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US15/926,166 Active US11329196B2 (en) | 2015-10-13 | 2018-03-20 | Optoelectronic device mounting structure with embedded heatsink element |
US17/715,238 Pending US20220231199A1 (en) | 2015-10-13 | 2022-04-07 | Optoelectronic Device Mounting Structure with Embedded Heatsink Element |
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US15/926,166 Active US11329196B2 (en) | 2015-10-13 | 2018-03-20 | Optoelectronic device mounting structure with embedded heatsink element |
US17/715,238 Pending US20220231199A1 (en) | 2015-10-13 | 2022-04-07 | Optoelectronic Device Mounting Structure with Embedded Heatsink Element |
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Also Published As
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US20180219137A1 (en) | 2018-08-02 |
US11329196B2 (en) | 2022-05-10 |
US20220231199A1 (en) | 2022-07-21 |
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