US20170092723A1 - High-k spacer for extension-free cmos devices with high mobility channel materials - Google Patents

High-k spacer for extension-free cmos devices with high mobility channel materials Download PDF

Info

Publication number
US20170092723A1
US20170092723A1 US14/869,282 US201514869282A US2017092723A1 US 20170092723 A1 US20170092723 A1 US 20170092723A1 US 201514869282 A US201514869282 A US 201514869282A US 2017092723 A1 US2017092723 A1 US 2017092723A1
Authority
US
United States
Prior art keywords
field effect
recited
inner spacer
region
spacer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US14/869,282
Other versions
US9608066B1 (en
Inventor
Takashi Ando
Pouya Hashemi
Vijay Narayanan
Yanning Sun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elpis Technologies Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US14/869,282 priority Critical patent/US9608066B1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SUN, YANNING, ANDO, TAKASHI, HASHEMI, POUYA, NARAYANAN, VIJAY
Application granted granted Critical
Publication of US9608066B1 publication Critical patent/US9608066B1/en
Publication of US20170092723A1 publication Critical patent/US20170092723A1/en
Assigned to ELPIS TECHNOLOGIES INC. reassignment ELPIS TECHNOLOGIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

Definitions

  • the present invention relates to high mobility channel devices, and more particularly to devices and methods for forming complementary metal oxide semiconductor (CMOS) devices without extension doping below gate structures.
  • CMOS complementary metal oxide semiconductor
  • High mobility channel devices are useful in high speed applications, such as, e.g., communications and high speed computing. Due to their high speed operation, defects in high mobility devices have a larger impact on device function. To ensure proper operation, in one example, low temperature processes (less than 650 degrees C.) need to be employed due to thermal instability of channel materials. The low temperature regimes limit dopant diffusion to/from the channel. In addition, extension dopant processes to extend the channel under spacer structures employ higher temperature implantation steps that may cause collateral damage and undesirable diffusion. Further, if source/drain (S/D) junctions are formed with an in-situ doped epitaxial process, it is difficult to link the S/D region to the channel due to the presence of spacer structures, which protect the gate during the epitaxial process.
  • S/D source/drain
  • a field effect transistor device includes a gate structure formed over a channel region in a semiconductor material.
  • An inner spacer is formed on sidewalls of the gate structure and over an extension region of the semiconductor material.
  • the inner spacer includes charge or dipoles.
  • a source/drain region is formed adjacent to the gate structure.
  • An inversion layer is formed in the extension region induced by the inner spacer to form a conductive link between the channel region and the source/drain region.
  • CMOS complementary metal oxide semiconductor
  • NFETs n-type field effect transistors
  • PFETs p-type field effect transistors
  • the first and second semiconductor materials are formed from different materials on a same substrate.
  • Gate structures are formed over channel regions in the first and second semiconductor materials.
  • First inner spacers are formed on sidewalls of the gate structures of NFETS and over extension regions of the first semiconductor material.
  • the first inner spacers include positive charge or dipoles.
  • Second inner spacers are formed on sidewalls of the gate structures of PFETS and over extension regions of the second semiconductor material.
  • the second inner spacers include negative charge or dipoles.
  • Source/drain regions are formed adjacent to the gate structures.
  • Inversion layers are formed in the extension regions between the channel regions and the source/drain regions. The inversion layers are induced by the first and second inner spacers to form a conductive link between the channel regions and the source/drain regions.
  • a method for fabrication of field effect transistor device includes forming a gate structure over a channel region in a semiconductor material; forming an inner spacer on sidewalls of the gate structure and over an extension region of the semiconductor material, the inner spacer including charge or dipoles; forming a source/drain region adjacent to the gate structure; and inducing an inversion layer in the extension region using the inner spacer to form an conductive link between the channel region and the source/drain region.
  • FIG. 1 is a cross-sectional view of a complementary metal oxide semiconductor (CMOS) device having charged inner spacers to induce inversion layers to form a channel link in accordance with the present principles;
  • CMOS complementary metal oxide semiconductor
  • FIG. 2 is a cross-sectional view of a substrate that provides different substrate material in accordance with one illustrative embodiment
  • FIG. 3 is a cross-sectional view of the substrate of FIG. 2 showing a bulk substrate exposed in accordance with the present principles
  • FIG. 4 is a cross-sectional view of the substrate of FIG. 3 showing a gate dielectric and gate conductor formed in accordance with the present principles
  • FIG. 6 is a cross-sectional view of the substrate of FIG. 5 showing a first inner spacer layer formed in accordance with one embodiment
  • FIG. 8 is a cross-sectional view of the substrate of FIG. 7 showing first and second inner spacers and an outer spacer formed in accordance with one embodiment
  • FIG. 9 is a cross-sectional view of the substrate of FIG. 8 showing source and drain regions formed and inversion layers formed as induced by the first and second inner spacers in accordance with one embodiment.
  • FIG. 10 is a block/flow diagram showing methods for forming a field effect transistor device in accordance with illustrative embodiments.
  • CMOS devices include high mobility channels that are linked or connected to source/drain (S/D) regions without employing extension regions.
  • S/D regions may be in-situ doped, and dopant implantation may be removed altogether.
  • CMOS integration may include different substrate/channel materials for n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs). Material differences between NFETs and PFETs may be needed for continued size scaling of integrated circuits.
  • III-V materials may be employed for NFET channels and (Si)Ge for PFET channels on the same device.
  • the present principles provide structures and materials to link high mobility channels (e.g., InGaAs for NFETs and (Si)Ge for PFETs) and in-situ doped S/D regions without relying on dopant implantation.
  • III-V materials and (Si)Ge materials are provided on or in a same substrate, and in-situ doped raised S/D structures are formed for both NFETs and PFETs.
  • the electrical link between the channels and S/D regions is provided by fixed charge or dipoles embedded in spacers adjacent to gates.
  • the charge or dipoles may be present in the materials selected for the spacers. For example, pre-existing fixed charge and/or dipoles may be intrinsic to the spacer materials employed.
  • the charger density may include charge in the range of about 1 ⁇ 10 12 to about 1 ⁇ 10 14 /cm 2 .
  • the spacers induce an inversion layer in the substrate in contact with the spacer.
  • the inversion layer reduces any barrier to conduction and permits charge flow to form the electrical link.
  • the NFET spacer may include an inner layer having positive fixed charge or electric dipoles having equivalent effects and an optional outer layer to protect the inner layer during S/D epitaxial growth.
  • the inner NFET spacer may include dielectric materials with a dielectric constant (k-value) greater than that of SiN (e.g., k ⁇ ⁇ 7), oxides of the lanthanide series (e.g., La, Lu, etc.), oxides of alkaline earth metals (e.g., MgO), HfON, etc.
  • the outer NFET spacer may include, e.g., SiN.
  • the PFET spacer may include an inner layer having negative fixed charge or electric dipoles having equivalent effects and an optional outer layer to protect the layer during S/D epitaxial growth.
  • the inner PFET spacer may include dielectric materials with a k-value greater than that of SiN (e.g., k ⁇ ⁇ 7), Al 2 O 3 , TiO 2 , HfO 2 , etc.
  • the outer PFET spacer may include, e.g., SiN.
  • the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
  • the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections).
  • the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product.
  • the end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
  • any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B).
  • such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C).
  • This may be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.
  • the PFET spacer 52 , 54 is formed separately from the NFET spacer 22 , 24 and includes different materials.
  • NFET and PFET spacers are formed using a same material that is processed differently.
  • the spacers 22 and 52 may be formed with a deposition of HfO 2 , and the spacer of the NFET 10 is subjected to a selective nitridation process of the HfO 2 to form HfON to create more positive fixed charge.
  • the nitridation may be performed via plasma nitridation or nitrogen implantation.
  • the spacer 52 of the PFET 40 may be blocked during the nitridation processing of the spacer 22 .
  • the inner spacer 52 of the PFET 40 includes a negative fixed charge or electric dipoles having equivalent effects.
  • the outer spacer 54 may be formed to protect the inner spacer 52 during S/D epitaxial growth.
  • the inner spacer 52 may include dielectric materials with a k-value greater than that of SiN (e.g., k ⁇ ⁇ 7), e.g., Al 2 O 3 , TiO 2 , HfO 2 , etc.
  • the outer spacer 54 may include, e.g., SiN.
  • the inner spacer 52 includes negative fixed charge or dipoles by material selection or may be doped during formation to increase the negative charge in the inner spacer 52 .
  • the negative charge (or dipoles) in the inner spacer 52 induce a hole inversion layer 56 in the substrate 64 (in a channel 42 of the PFET 40 ).
  • the hole inversion layer 56 provides an electrical link or connection to S/D regions 58 formed adjacent to the spacer 52 , 54 .
  • the S/D regions 58 are p+ doped.
  • the doping of the S/D regions 58 is preferably performed during formation (in-situ doping). In this way, no implanting or external doping (no extension doping) is needed in the high mobility channel region 42 . This results in a higher quality channel and preserves the high charge mobility needed.
  • a semiconductor-on-insulator substrate (SOI) 200 is shown in accordance with one illustrative embodiment.
  • the present principles include CMOS technology and preferably employ different substrate materials for NFETs and PFETs.
  • SiGe may be grown on III-V material or III-V material may be grown on SiGe.
  • the SOI substrate 200 may be employed to provide two types of defect-free monocrystalline materials.
  • the SOI substrate 200 includes a bulk substrate material 202 , a buried dielectric layer 204 and a semiconductor layer 206 .
  • the bulk substrate material 202 may include a III-V material while the semiconductor layer 206 may include SiGe, or vice versa.
  • the bulk substrate material 202 includes III-V material for an NFET while the semiconductor layer 206 includes SiGe for a PFET.
  • the buried dielectric layer 204 may include an oxide, although other dielectric materials may be employed.
  • a lithography process may be performed to expose a portion of the bulk substrate 202 for NFET processing.
  • the semiconductor layer 206 is protected during an etching process to remove both the semiconductor layer 206 and the buried dielectric layer 204 from the NFET area.
  • the semiconductor layer 206 and the bulk substrate 202 may be processed to form three-dimensional structures like fins or nanowires.
  • the present embodiment will be described in terms of planar field effect transistors.
  • a gate dielectric 210 is deposited in an NFET area 214 and in a PFET area 216 .
  • the gate dielectric layer 210 may include a high-k dielectric material (e.g., HfO 2 , or the like), although other suitable dielectric materials may be employed.
  • a gate conductor 212 is formed in a gate-first process.
  • the gate conductor 212 may include, e.g., W, Al, Ti, TiN, TiC, etc.
  • the gate conductor 212 may instead include dummy gate material employed for a gate-last process.
  • the gate conductor 212 may include one or more different metal materials (e.g., a work function metal and main conductor).
  • gate structures 220 are patterned in the NFET area 214 and in the PFET area 216 .
  • the gate structures 220 may be formed using a lithographic mask and etch process.
  • the etch process may include a reactive ion etch (RIE).
  • an inner spacer layer 222 is formed in the NFET area 214 .
  • the inner spacer layer 222 may be deposited only in the NFET area 214 or may be deposited across the NFET area 214 and the PFET area 216 and then removed from the PFET area 216 .
  • the inner spacer layer 222 is deposited across the NFET area 214 and the PFET area 216 from a same material and then treated or processed differently to apply the appropriate charge or dipole for forming inversion layers in the corresponding substrate region.
  • the other of the PFET area 216 and the NFET area 214 can be blocked by a blocking layer (not shown).
  • the blocking layer or layers may include a thin dielectric material or resist to protect the covered portion during processing of other areas of the device.
  • the inner spacer layer 222 is deposited as HfO 2 in the NFET area 214 and the PFET area 216 , and then subjected to a selective nitridation of the HfO 2 in the NFET area 214 to create more positive fixed charge.
  • the nitridation may be performed via plasma nitridation or nitrogen implantation.
  • the PFET area 216 is protected from the nitridation process and remains as HfO 2 .
  • an inner spacer layer 224 is formed in the PFET area 216 (if formed from a different material than the NFET area 214 inner spacer 222 ). It should be noted that, in some embodiments, the inner spacer 224 may be formed before the inner spacer 222 . In other embodiments, the inner spacer layer 224 may be deposited only in the PFET area 214 or may be deposited across the NFET area 214 and the PFET area 216 and then removed from the NFET area 214 . When processing one of the NFET area 214 or the PFET area 216 , the other of the PFET area 216 and the NFET area 214 can be blocked by a blocking layer (not shown).
  • the inner spacer layer 224 may include a material having a negative fixed charge or electric dipoles having equivalent effects.
  • the inner spacer layer 224 may include dielectric materials with a k-value greater than that of SiN (e.g., k ⁇ ⁇ 7), e.g., Al 2 O 3 , TiO 2 , HfO 2 , etc.
  • An outer spacer layer 226 may optionally be formed to protect the inner spacer 222 , 224 during S/D epitaxial growth in later steps.
  • the outer spacer 226 may include, e.g., SiN.
  • a reactive ion etch (RIE) process is performed to remove horizontal portions of the inner spacer layers 222 , 224 and outer spacer layer 226 . This forms inner spacer 228 in the NFET area 214 and inner spacer 232 in the PFET area 216 .
  • An outer spacer 230 may be formed in both the NFET area 214 and the PFET area 216 .
  • S/D regions 238 are formed using an epitaxial growth process, such as molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD). S/D regions 238 are preferably doped in-situ (n+ doped). In this way, no doping processes need to be performed to create channel extension regions.
  • MBE molecular beam epitaxy
  • MOCVD metal organic chemical vapor deposition
  • the inner spacer 228 includes the positive fixed charge or dipoles by material selection or may be doped during formation to increase the positive charge in the inner spacer 228 .
  • the positive charge (or dipoles) in the inner spacer 228 induces an electron inversion layer 236 in a channel region 234 for NFETs.
  • the electron inversion layer 236 provides an electrical link or connection to S/D regions 238 formed adjacent to the spacer 228 .
  • the doping of the S/D regions 238 is preferably performed during formation (in-situ doping). In this way, no implanting or external doping (no extension doping) is needed in the high mobility channel region 234 . This results in a higher quality channel and preserves the high charge mobility needed.
  • S/D regions 248 are formed using an epitaxial growth process, such as molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD). S/D regions 248 are preferably doped in-situ (p+ doped). In this way, no doping processes need to be performed to create channel extension regions.
  • the S/D regions 238 and 248 are formed separately since different material or dopants are employed, especially if these regions are doped in-situ.
  • the inner spacer 232 includes the negative fixed charge or dipoles by material selection or may be doped during formation to increase the negative charge in the inner spacer 232 .
  • the negative charge (or dipoles) in the inner spacer 232 induces a hole inversion layer 246 in a channel region 244 for PFETs.
  • the hole inversion layer 246 provides an electrical link or connection to S/D regions 248 formed adjacent to the spacer 232 .
  • the doping of the S/D regions 248 is preferably performed during formation (in-situ doping). In this way, no implanting or external doping (no extension doping) is needed in the high mobility channel region 244 . This results in a higher quality channel and preserves the high charge mobility needed.
  • CMOS transistors a method for forming high mobility CMOS transistors is shown in accordance with illustrative embodiments.
  • the functions noted in the blocks may occur out of the order noted in the figures.
  • two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
  • each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
  • a gate structure is formed over a channel region in a semiconductor material.
  • an inner spacer is formed on sidewalls of the gate structure and in an extension region of the semiconductor material.
  • the inner spacer includes charge or dipoles.
  • the inner spacer includes positive charge or dipoles and the inversion layer includes an electron inversion layer for NFETs formed from one of an oxide of the lanthanide series, an oxide of an alkaline earth metals or HfON.
  • the inner spacer includes negative charge or dipoles and the inversion layer includes a hole inversion layer for PFETs formed from one of Al 2 O 3 , TiO 2 , or HfO 2 for a p-type field effect transistor.
  • an outer spacer(s) may be formed on PFETs and NFETs.
  • S/D regions are formed adjacent to the gate structure.
  • the S/D regions may be formed with in-situ doping to avoid dopant processing in the extension region (and/or the channel region).
  • the device is formed without dopant implantation at all to preserve the channel region for high mobility operation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A field effect transistor device includes a gate structure formed over a channel region in a semiconductor material. An inner spacer is formed on sidewalls of the gate structure and over an extension region of the semiconductor material. The inner spacer includes charge or dipoles. A source/drain region is formed adjacent to the gate structure. An inversion layer is formed in the extension region induced by the inner spacer to form a conductive link between the channel region and the source/drain region.

Description

    BACKGROUND
  • Technical Field
  • The present invention relates to high mobility channel devices, and more particularly to devices and methods for forming complementary metal oxide semiconductor (CMOS) devices without extension doping below gate structures.
  • Description of the Related Art
  • High mobility channel devices are useful in high speed applications, such as, e.g., communications and high speed computing. Due to their high speed operation, defects in high mobility devices have a larger impact on device function. To ensure proper operation, in one example, low temperature processes (less than 650 degrees C.) need to be employed due to thermal instability of channel materials. The low temperature regimes limit dopant diffusion to/from the channel. In addition, extension dopant processes to extend the channel under spacer structures employ higher temperature implantation steps that may cause collateral damage and undesirable diffusion. Further, if source/drain (S/D) junctions are formed with an in-situ doped epitaxial process, it is difficult to link the S/D region to the channel due to the presence of spacer structures, which protect the gate during the epitaxial process.
    • SUMMARY
  • A field effect transistor device includes a gate structure formed over a channel region in a semiconductor material. An inner spacer is formed on sidewalls of the gate structure and over an extension region of the semiconductor material. The inner spacer includes charge or dipoles. A source/drain region is formed adjacent to the gate structure. An inversion layer is formed in the extension region induced by the inner spacer to form a conductive link between the channel region and the source/drain region.
  • Another field effect transistor device includes a complementary metal oxide semiconductor (CMOS) device having a first semiconductor material for forming n-type field effect transistors (NFETs) and a second semiconductor material for forming p-type field effect transistors (PFETs). The first and second semiconductor materials are formed from different materials on a same substrate. Gate structures are formed over channel regions in the first and second semiconductor materials. First inner spacers are formed on sidewalls of the gate structures of NFETS and over extension regions of the first semiconductor material. The first inner spacers include positive charge or dipoles. Second inner spacers are formed on sidewalls of the gate structures of PFETS and over extension regions of the second semiconductor material. The second inner spacers include negative charge or dipoles. Source/drain regions are formed adjacent to the gate structures. Inversion layers are formed in the extension regions between the channel regions and the source/drain regions. The inversion layers are induced by the first and second inner spacers to form a conductive link between the channel regions and the source/drain regions.
  • A method for fabrication of field effect transistor device includes forming a gate structure over a channel region in a semiconductor material; forming an inner spacer on sidewalls of the gate structure and over an extension region of the semiconductor material, the inner spacer including charge or dipoles; forming a source/drain region adjacent to the gate structure; and inducing an inversion layer in the extension region using the inner spacer to form an conductive link between the channel region and the source/drain region.
  • These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
    • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:
  • FIG. 1 is a cross-sectional view of a complementary metal oxide semiconductor (CMOS) device having charged inner spacers to induce inversion layers to form a channel link in accordance with the present principles;
  • FIG. 2 is a cross-sectional view of a substrate that provides different substrate material in accordance with one illustrative embodiment;
  • FIG. 3 is a cross-sectional view of the substrate of FIG. 2 showing a bulk substrate exposed in accordance with the present principles;
  • FIG. 4 is a cross-sectional view of the substrate of FIG. 3 showing a gate dielectric and gate conductor formed in accordance with the present principles;
  • FIG. 5 is a cross-sectional view of the substrate of FIG. 4 showing the gate dielectric and gate conductor patterned to form gate structures in accordance with the present principles;
  • FIG. 6 is a cross-sectional view of the substrate of FIG. 5 showing a first inner spacer layer formed in accordance with one embodiment;
  • FIG. 7 is a cross-sectional view of the substrate of FIG. 6 showing first and second inner spacer layers formed and an outer spacer layer formed in accordance with one embodiment;
  • FIG. 8 is a cross-sectional view of the substrate of FIG. 7 showing first and second inner spacers and an outer spacer formed in accordance with one embodiment;
  • FIG. 9 is a cross-sectional view of the substrate of FIG. 8 showing source and drain regions formed and inversion layers formed as induced by the first and second inner spacers in accordance with one embodiment; and
  • FIG. 10 is a block/flow diagram showing methods for forming a field effect transistor device in accordance with illustrative embodiments.
    •  DETAILED DESCRIPTION
  • In accordance with the present principles, complementary metal oxide semiconductor (CMOS) devices include high mobility channels that are linked or connected to source/drain (S/D) regions without employing extension regions. In one particularly useful embodiment, S/D regions may be in-situ doped, and dopant implantation may be removed altogether. In useful embodiments, CMOS integration may include different substrate/channel materials for n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs). Material differences between NFETs and PFETs may be needed for continued size scaling of integrated circuits. In one embodiment, III-V materials may be employed for NFET channels and (Si)Ge for PFET channels on the same device. III-V materials may include, e.g., InGaAs, GaAs, InP, GaInP, AlGaAs, etc. (Si)Ge includes silicon doped Ge; however, the amount of Si may be varied to include SiGe with a high Ge content or a high Si content.
  • The present principles provide structures and materials to link high mobility channels (e.g., InGaAs for NFETs and (Si)Ge for PFETs) and in-situ doped S/D regions without relying on dopant implantation. III-V materials and (Si)Ge materials are provided on or in a same substrate, and in-situ doped raised S/D structures are formed for both NFETs and PFETs. The electrical link between the channels and S/D regions is provided by fixed charge or dipoles embedded in spacers adjacent to gates. The charge or dipoles may be present in the materials selected for the spacers. For example, pre-existing fixed charge and/or dipoles may be intrinsic to the spacer materials employed. Therefore, no additional processing is needed to introduce charge except for the case where one material is converted to another, e.g, HfO2 (for PFETs) converted to HfON (for NFETs) via nitridation. The charger density may include charge in the range of about 1×1012 to about 1×1014/cm2.
  • The spacers induce an inversion layer in the substrate in contact with the spacer. The inversion layer reduces any barrier to conduction and permits charge flow to form the electrical link. The NFET spacer may include an inner layer having positive fixed charge or electric dipoles having equivalent effects and an optional outer layer to protect the inner layer during S/D epitaxial growth. The inner NFET spacer may include dielectric materials with a dielectric constant (k-value) greater than that of SiN (e.g., k≧˜7), oxides of the lanthanide series (e.g., La, Lu, etc.), oxides of alkaline earth metals (e.g., MgO), HfON, etc. The outer NFET spacer may include, e.g., SiN.
  • The PFET spacer may include an inner layer having negative fixed charge or electric dipoles having equivalent effects and an optional outer layer to protect the layer during S/D epitaxial growth. The inner PFET spacer may include dielectric materials with a k-value greater than that of SiN (e.g., k≧˜7), Al2O3, TiO2, HfO2, etc. The outer PFET spacer may include, e.g., SiN.
  • It is to be understood that the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps may be varied within the scope of the present invention.
  • It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
  • The present embodiments may include a design for an integrated circuit chip, which may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer may transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
  • Methods as described herein may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
  • It should also be understood that material compounds will be described in terms of listed elements, e.g., GaInP, InGaAs or SiGe. These compounds include different proportions of the elements within the compound, e.g., InGaAs includes Inx,Ga1-xAs, where x is less than or equal to 1, or SiGe includes SixGe1-x where x is less than or equal to 1, etc. In addition, other elements may be included in the compound, such as, e.g., AlInGaAs, and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.
  • Reference in the specification to “one embodiment” or “an embodiment” of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
  • It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.
  • Referring now to the drawings in which like numerals represent the same or similar elements and initially to FIG. 1, a CMOS device 100 is shown in cross-section in accordance with one illustrative embodiment. The CMOS device 100 includes NFETs 10 and PFETs 40, each on a different substrate material. The NFET 10 is formed on a substrate material 34, which preferably includes a III-V material, such as, e.g., InGaAs, GaAs, AlGaAs, InGaP, InP, or other suitable materials, especially for high charge mobility devices. The PFET 40 is formed on a substrate material 44, which preferably includes a Si or Ge material, and in particularly useful embodiments includes SiGe or other suitable material for high charge mobility devices.
  • A gate structure 20 of the NFET device 10 includes a gate dielectric 32 and a gate conductor 30. The gate dielectric 32 may include a high-k dielectric material, such as HfO2, although other suitable gate dielectrics may be employed. The gate conductor 30 may include any suitable conductor, such as W, Ti, TiN, TiC, Al, etc. The gate structure 20 includes an inner spacer 22 and an optional outer spacer 24.
  • In one embodiment, the NFET spacer 22, 24 is formed separately from the PFET spacer 52, 54 and includes different materials. In another embodiment, NFET and PFET spacers are formed using a same material that is processed differently for each device type.
  • The inner spacer 22 of the NFET 10 includes a positive fixed charge or electric dipoles having equivalent effects. The outer spacer 24 may be formed to protect the inner spacer 22 during S/D epitaxial growth. The inner spacer 22 may include dielectric materials with a k-value greater than that of SiN (e.g., k≧˜7), e.g., oxides of the lanthanide series (e.g., La, Lu, etc.), oxides of alkaline earth metals (e.g., MgO), HfON, etc. The outer spacer 24 may include, e.g., SiN.
  • The inner spacer 22 includes positive fixed charge or dipoles by material selection or may be doped during formation to increase the positive charge in the inner spacer 22. The positive charge (or dipoles) in the inner spacer 22 induce an electron inversion layer 26 in the substrate 34 (in a channel 12 of the NFET 10). The electron inversion layer 26 provides an electrical link or connection to S/D regions 28 formed adjacent to the spacer 22, 24. In this case, the S/D regions 28 are n+ doped. The doping of the S/D regions 28 is preferably performed during formation (in-situ doping). In this way, no implanting or external doping (no extension doping) is needed in the high mobility channel region 12. This results in a higher quality channel and preserves the high charge mobility needed.
  • A gate structure 50 of the PFET device 40 includes a gate dielectric 62 and a gate conductor 60. The gate dielectric 62 may include a high-k dielectric material, such as HfO2, although other suitable gate dielectrics may be employed. The gate conductor 60 may include any suitable conductor, such as W, Ti, TiN, TiC, Al, etc. The gate structure 50 includes an inner spacer 52 and an optional outer spacer 54.
  • In one embodiment, the PFET spacer 52, 54 is formed separately from the NFET spacer 22, 24 and includes different materials. In another embodiment, NFET and PFET spacers are formed using a same material that is processed differently. For example, in one embodiment, the spacers 22 and 52 may be formed with a deposition of HfO2, and the spacer of the NFET 10 is subjected to a selective nitridation process of the HfO2 to form HfON to create more positive fixed charge. The nitridation may be performed via plasma nitridation or nitrogen implantation. The spacer 52 of the PFET 40 may be blocked during the nitridation processing of the spacer 22.
  • The inner spacer 52 of the PFET 40 includes a negative fixed charge or electric dipoles having equivalent effects. The outer spacer 54 may be formed to protect the inner spacer 52 during S/D epitaxial growth. The inner spacer 52 may include dielectric materials with a k-value greater than that of SiN (e.g., k≧˜7), e.g., Al2O3, TiO2, HfO2, etc. The outer spacer 54 may include, e.g., SiN.
  • The inner spacer 52 includes negative fixed charge or dipoles by material selection or may be doped during formation to increase the negative charge in the inner spacer 52. The negative charge (or dipoles) in the inner spacer 52 induce a hole inversion layer 56 in the substrate 64 (in a channel 42 of the PFET 40). The hole inversion layer 56 provides an electrical link or connection to S/D regions 58 formed adjacent to the spacer 52, 54. In this case, the S/D regions 58 are p+ doped. The doping of the S/D regions 58 is preferably performed during formation (in-situ doping). In this way, no implanting or external doping (no extension doping) is needed in the high mobility channel region 42. This results in a higher quality channel and preserves the high charge mobility needed.
  • The present principles may be formed using different processing techniques, e.g., FIG. 1 shows planar gate-first structures; however, the present principles are applicable to any device structure. For example, the present principles are applicable to 3-D structures (e.g., finFET, nanowires, etc.), gate-last process structures, etc.
  • Referring to FIG. 2, a semiconductor-on-insulator substrate (SOI) 200 is shown in accordance with one illustrative embodiment. The present principles include CMOS technology and preferably employ different substrate materials for NFETs and PFETs. In one embodiment, SiGe may be grown on III-V material or III-V material may be grown on SiGe. However, such growth may need interstitial buffer layers to handle lattice mismatches between the different materials. While such an approach is contemplated by the present principles, the SOI substrate 200 may be employed to provide two types of defect-free monocrystalline materials. The SOI substrate 200 includes a bulk substrate material 202, a buried dielectric layer 204 and a semiconductor layer 206. The bulk substrate material 202 may include a III-V material while the semiconductor layer 206 may include SiGe, or vice versa. For purposes of explanation, the bulk substrate material 202 includes III-V material for an NFET while the semiconductor layer 206 includes SiGe for a PFET. The buried dielectric layer 204 may include an oxide, although other dielectric materials may be employed.
  • Referring to FIG. 3, a lithography process may be performed to expose a portion of the bulk substrate 202 for NFET processing. The semiconductor layer 206 is protected during an etching process to remove both the semiconductor layer 206 and the buried dielectric layer 204 from the NFET area. In one embodiment, the semiconductor layer 206 and the bulk substrate 202 may be processed to form three-dimensional structures like fins or nanowires. However, the present embodiment will be described in terms of planar field effect transistors.
  • Referring to FIG. 4, a gate dielectric 210 is deposited in an NFET area 214 and in a PFET area 216. The gate dielectric layer 210 may include a high-k dielectric material (e.g., HfO2, or the like), although other suitable dielectric materials may be employed. A gate conductor 212 is formed in a gate-first process. The gate conductor 212 may include, e.g., W, Al, Ti, TiN, TiC, etc. As noted, the gate conductor 212 may instead include dummy gate material employed for a gate-last process. Also, the gate conductor 212 may include one or more different metal materials (e.g., a work function metal and main conductor).
  • Referring to FIG. 5, gate structures 220 are patterned in the NFET area 214 and in the PFET area 216. The gate structures 220 may be formed using a lithographic mask and etch process. The etch process may include a reactive ion etch (RIE).
  • Referring to FIG. 6, an inner spacer layer 222 is formed in the NFET area 214. The inner spacer layer 222 may be deposited only in the NFET area 214 or may be deposited across the NFET area 214 and the PFET area 216 and then removed from the PFET area 216. In one embodiment, the inner spacer layer 222 is deposited across the NFET area 214 and the PFET area 216 from a same material and then treated or processed differently to apply the appropriate charge or dipole for forming inversion layers in the corresponding substrate region.
  • When processing one of the NFET area 214 or the PFET area 216, the other of the PFET area 216 and the NFET area 214 can be blocked by a blocking layer (not shown). The blocking layer or layers may include a thin dielectric material or resist to protect the covered portion during processing of other areas of the device.
  • The inner spacer layer 222 may include a material having a positive fixed charge or electric dipoles having equivalent effects. The inner spacer layer 222 may include dielectric materials with a k-value greater than that of SiN (e.g., k≧˜7), e.g., oxides of the lanthanide series (e.g., La, Lu, etc.), oxides of alkaline earth metals (e.g., MgO), HfON, etc. If HfON is employed, the inner spacer layer 222 is deposited as HfO2 in the NFET area 214 and the PFET area 216, and then subjected to a selective nitridation of the HfO2 in the NFET area 214 to create more positive fixed charge. The nitridation may be performed via plasma nitridation or nitrogen implantation. The PFET area 216 is protected from the nitridation process and remains as HfO2.
  • Referring to FIG. 7, an inner spacer layer 224 is formed in the PFET area 216 (if formed from a different material than the NFET area 214 inner spacer 222). It should be noted that, in some embodiments, the inner spacer 224 may be formed before the inner spacer 222. In other embodiments, the inner spacer layer 224 may be deposited only in the PFET area 214 or may be deposited across the NFET area 214 and the PFET area 216 and then removed from the NFET area 214. When processing one of the NFET area 214 or the PFET area 216, the other of the PFET area 216 and the NFET area 214 can be blocked by a blocking layer (not shown).
  • The inner spacer layer 224 may include a material having a negative fixed charge or electric dipoles having equivalent effects. The inner spacer layer 224 may include dielectric materials with a k-value greater than that of SiN (e.g., k≧˜7), e.g., Al2O3, TiO2, HfO2, etc.
  • An outer spacer layer 226 may optionally be formed to protect the inner spacer 222, 224 during S/D epitaxial growth in later steps. The outer spacer 226 may include, e.g., SiN.
  • Referring to FIG. 8, a reactive ion etch (RIE) process is performed to remove horizontal portions of the inner spacer layers 222, 224 and outer spacer layer 226. This forms inner spacer 228 in the NFET area 214 and inner spacer 232 in the PFET area 216. An outer spacer 230 may be formed in both the NFET area 214 and the PFET area 216.
  • Referring to FIG. 9, S/D regions 238 are formed using an epitaxial growth process, such as molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD). S/D regions 238 are preferably doped in-situ (n+ doped). In this way, no doping processes need to be performed to create channel extension regions.
  • The inner spacer 228 includes the positive fixed charge or dipoles by material selection or may be doped during formation to increase the positive charge in the inner spacer 228. The positive charge (or dipoles) in the inner spacer 228 induces an electron inversion layer 236 in a channel region 234 for NFETs. The electron inversion layer 236 provides an electrical link or connection to S/D regions 238 formed adjacent to the spacer 228. The doping of the S/D regions 238 is preferably performed during formation (in-situ doping). In this way, no implanting or external doping (no extension doping) is needed in the high mobility channel region 234. This results in a higher quality channel and preserves the high charge mobility needed.
  • S/D regions 248 are formed using an epitaxial growth process, such as molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD). S/D regions 248 are preferably doped in-situ (p+ doped). In this way, no doping processes need to be performed to create channel extension regions. The S/ D regions 238 and 248 are formed separately since different material or dopants are employed, especially if these regions are doped in-situ.
  • The inner spacer 232 includes the negative fixed charge or dipoles by material selection or may be doped during formation to increase the negative charge in the inner spacer 232. The negative charge (or dipoles) in the inner spacer 232 induces a hole inversion layer 246 in a channel region 244 for PFETs. The hole inversion layer 246 provides an electrical link or connection to S/D regions 248 formed adjacent to the spacer 232. The doping of the S/D regions 248 is preferably performed during formation (in-situ doping). In this way, no implanting or external doping (no extension doping) is needed in the high mobility channel region 244. This results in a higher quality channel and preserves the high charge mobility needed.
  • Referring to FIG. 10, a method for forming high mobility CMOS transistors is shown in accordance with illustrative embodiments. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
  • In block 302, a gate structure is formed over a channel region in a semiconductor material. In block 304, an inner spacer is formed on sidewalls of the gate structure and in an extension region of the semiconductor material. The inner spacer includes charge or dipoles. In useful embodiments, the inner spacer includes positive charge or dipoles and the inversion layer includes an electron inversion layer for NFETs formed from one of an oxide of the lanthanide series, an oxide of an alkaline earth metals or HfON. The inner spacer includes negative charge or dipoles and the inversion layer includes a hole inversion layer for PFETs formed from one of Al2O3, TiO2, or HfO2 for a p-type field effect transistor.
  • In block 306, the inner spacer may include a single material over gate structures of NFETs and PFETs, which is processed to provide the needed charge type material. In one example, HfO2 is deposited over gate structures of NFETs and PFETs, and a nitridation process is performed to form HfON on the NFET inner spacer.
  • In block 308, an outer spacer(s) may be formed on PFETs and NFETs. In block 310, S/D regions are formed adjacent to the gate structure. The S/D regions may be formed with in-situ doping to avoid dopant processing in the extension region (and/or the channel region). In one embodiment, the device is formed without dopant implantation at all to preserve the channel region for high mobility operation.
  • In block 312, an inversion layer is induced in the extension region using the inner spacer to form a conductive link between the channel region and the source/drain region. The charge formed in the inner spacer creates the inversion regions to increase conductivity in what would otherwise be a dead zone below the spacer dielectric (where no gate conductor is present). In block 314, processing continues to complete the device(s) including forming interlevel dielectric layers, contacts, metallizations, etc.
  • Having described preferred embodiments for a high-k spacer for extension-free CMOS devices with high mobility channel materials (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.

Claims (20)

1. A field effect transistor device, comprising:
a gate structure formed over a channel region in a semiconductor material;
an inner spacer formed directly on sidewalls of the gate structure and over an extension region of the semiconductor material, where the inner spacer is a dielectric material with a dielectric constant greater than about 7, and the inner spacer including charge or dipoles;
a source/drain region formed adjacent to the gate structure; and
an inversion layer formed in the extension region induced by the inner spacer to form a conductive link between the channel region and the source/drain region.
2. The device as recited in claim 1, further comprising an outer spacer formed on the inner spacer.
3. (canceled)
4. The device as recited in claim 1, wherein the inner spacer includes one of an oxide of the lanthanide series, an oxide of an alkaline earth metals or HfON for an n-type field effect transistor.
5. The device as recited in claim 1, wherein the inner spacer includes one of Al2O3, TiO2, or HfO2 for a p-type field effect transistor.
6. The device as recited in claim 1, wherein the source/drain region includes an in-situ doped region to avoid dopant processing in the extension region and the channel region.
7. The device as recited in claim 1, wherein the transistor includes a complementary metal oxide semiconductor (CMOS) device and the semiconductor material includes a first semiconductor layer for forming n-type field effect transistors (NFETs) and a second semiconductor layer for forming p-type field effect transistors (PFETs).
8. The device as recited in claim 7, wherein the first semiconductor layer includes a III-V material and the second semiconductor layer includes SiGe.
9. The device as recited in claim 1, wherein the inner spacer includes positive charge or dipoles and the inversion layer includes an electron inversion layer for n-type field effect transistors.
10. The device as recited in claim 1, wherein the inner spacer includes negative charge or dipoles and the inversion layer includes a hole inversion layer for p-type field effect transistors.
11. A field effect transistor device, comprising:
a complementary metal oxide semiconductor (CMOS) device having a first semiconductor material for forming n-type field effect transistors (NFETs) and a second semiconductor material for forming p-type field effect transistors (PFETs), the first and second semiconductor materials being formed from different materials on a same substrate;
gate structures formed over channel regions in the first and second semiconductor materials;
first inner spacers formed directly on sidewalls of the gate structures of NFETS and over extension regions of the first semiconductor material, the first inner spacers including positive charge or dipoles;
second inner spacers formed directly on sidewalls of the gate structures of PFETS and over extension regions of the second semiconductor material, the second inner spacers including negative charge or dipoles, wherein the first and second inner spacers include a dielectric material with a dielectric constant greater than about 7;
source/drain regions formed adjacent to the gate structures; and
inversion layers formed in the extension regions between the channel regions and the source/drain regions, the inversion layers being induced by the first and second inner spacers to form a conductive link between the channel regions and the source/drain regions.
12. The device as recited in claim 11, further comprising an outer spacer formed on the first and second inner spacers.
13. (canceled)
14. The device as recited in claim 11, wherein the first inner spacers include one of an oxide of the lanthanide series, an oxide of an alkaline earth metals or HfON for an n-type field effect transistor.
15. The device as recited in claim 11, wherein the second inner spacers include one of Al2O3, TiO2, or HfO2 for a p-type field effect transistor.
16. The device as recited in claim 11, wherein the source/drain regions include in-situ doped regions to avoid dopant processing in the extension region and the channel region.
17. The transistor as recited in claim 11, wherein the first semiconductor material includes a III-V material and the second semiconductor material includes SiGe.
18. A method for fabrication of field effect transistor device, comprising:
forming a gate structure over a channel region in a semiconductor material;
forming an inner spacer on sidewalls of the gate structure and over an extension region of the semiconductor material, the inner spacer including charge or dipoles;
forming a source/drain region adjacent to the gate structure; and
inducing an inversion layer in the extension region using the inner spacer to form a conductive link between the channel region and the source/drain region.
19. The method as recited in claim 18, wherein the inner spacer includes positive charge or dipoles and the inversion layer includes an electron inversion layer for n-type field effect transistors (NFETs) formed from one of an oxide of the lanthanide series, an oxide of an alkaline earth metals or HfON and wherein the inner spacer includes negative charge or dipoles, and the inversion layer includes a hole inversion layer for p-type field effect transistors (PFETs) formed from one of Al2O3, TiO2, or HfO2 for a p-type field effect transistor.
20. The device as recited in claim 18, wherein the source/drain region includes an in-situ doped region to avoid dopant processing in the extension region and the channel region.
US14/869,282 2015-09-29 2015-09-29 High-K spacer for extension-free CMOS devices with high mobility channel materials Expired - Fee Related US9608066B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/869,282 US9608066B1 (en) 2015-09-29 2015-09-29 High-K spacer for extension-free CMOS devices with high mobility channel materials

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/869,282 US9608066B1 (en) 2015-09-29 2015-09-29 High-K spacer for extension-free CMOS devices with high mobility channel materials

Publications (2)

Publication Number Publication Date
US9608066B1 US9608066B1 (en) 2017-03-28
US20170092723A1 true US20170092723A1 (en) 2017-03-30

Family

ID=58360058

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/869,282 Expired - Fee Related US9608066B1 (en) 2015-09-29 2015-09-29 High-K spacer for extension-free CMOS devices with high mobility channel materials

Country Status (1)

Country Link
US (1) US9608066B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI720283B (en) * 2017-10-03 2021-03-01 新加坡商格羅方德半導體私人有限公司 Sidewall engineering for enhanced device performance in advanced devices
TWI758821B (en) * 2020-02-19 2022-03-21 日商鎧俠股份有限公司 Semiconductor device and method of manufacturing the same

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113644109B (en) * 2020-05-11 2023-06-09 北京华碳元芯电子科技有限责任公司 Transistor and preparation method thereof
CN114914292A (en) * 2020-05-11 2022-08-16 北京华碳元芯电子科技有限责任公司 Transistor
CN113644110B (en) * 2020-05-11 2024-07-02 北京华碳元芯电子科技有限责任公司 Transistor and preparation method thereof
CN113644112B (en) * 2020-05-11 2022-07-15 北京华碳元芯电子科技有限责任公司 Transistor and manufacturing method

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5274261A (en) * 1990-07-31 1993-12-28 Texas Instruments Incorporated Integrated circuit degradation resistant structure
EP0490535B1 (en) * 1990-12-07 1996-08-21 AT&T Corp. Transistor with inverse silicide T-gate structure
KR940005293B1 (en) * 1991-05-23 1994-06-15 삼성전자 주식회사 Mosfet and fabricating method thereof
WO1993009567A1 (en) * 1991-10-31 1993-05-13 Vlsi Technology, Inc. Auxiliary gate lightly doped drain (agldd) structure with dielectric sidewalls
US5759901A (en) * 1995-04-06 1998-06-02 Vlsi Technology, Inc. Fabrication method for sub-half micron CMOS transistor
US5714413A (en) * 1995-12-11 1998-02-03 Intel Corporation Method of making a transistor having a deposited dual-layer spacer structure
US5710054A (en) * 1996-08-26 1998-01-20 Advanced Micro Devices, Inc. Method of forming a shallow junction by diffusion from a silicon-based spacer
US5789298A (en) * 1996-11-04 1998-08-04 Advanced Micro Devices, Inc. High performance mosfet structure having asymmetrical spacer formation and method of making the same
US5763311A (en) * 1996-11-04 1998-06-09 Advanced Micro Devices, Inc. High performance asymmetrical MOSFET structure and method of making the same
JP2956626B2 (en) * 1996-12-12 1999-10-04 日本電気株式会社 Method for manufacturing MOS type semiconductor device
US5817562A (en) * 1997-01-24 1998-10-06 Taiwan Semiconductor Manufacturing Company, Ltd Method for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC)
KR100206985B1 (en) * 1997-03-14 1999-07-01 구본준 Flash memory device and fabrication method of the same
US5736446A (en) * 1997-05-21 1998-04-07 Powerchip Semiconductor Corp. Method of fabricating a MOS device having a gate-side air-gap structure
US6180988B1 (en) * 1997-12-04 2001-01-30 Texas Instruments-Acer Incorporated Self-aligned silicided MOSFETS with a graded S/D junction and gate-side air-gap structure
US5989966A (en) * 1997-12-15 1999-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method and a deep sub-micron field effect transistor structure for suppressing short channel effects
US5811342A (en) * 1998-01-26 1998-09-22 Texas Instruments - Acer Incorporated Method for forming a semiconductor device with a graded lightly-doped drain structure
TW387151B (en) * 1998-02-07 2000-04-11 United Microelectronics Corp Field effect transistor structure of integrated circuit and the manufacturing method thereof
US6194272B1 (en) * 1998-05-19 2001-02-27 Mosel Vitelic, Inc. Split gate flash cell with extremely small cell size
US6144071A (en) * 1998-09-03 2000-11-07 Advanced Micro Devices, Inc. Ultrathin silicon nitride containing sidewall spacers for improved transistor performance
US6187645B1 (en) * 1999-01-19 2001-02-13 United Microelectronics Corp. Method for manufacturing semiconductor device capable of preventing gate-to-drain capacitance and eliminating birds beak formation
US6501134B1 (en) 2001-01-09 2002-12-31 Advanced Micro Devices, Inc. Ultra thin SOI devices with improved short-channel control
US6680233B2 (en) 2001-10-09 2004-01-20 Advanced Micro Devices, Inc. Semiconductor device formed with disposable spacer and liner using high-K material and method of fabrication
JP2004348789A (en) * 2003-05-20 2004-12-09 Sharp Corp Semiconductor memory device and portable electronic equipment
JP2004349308A (en) * 2003-05-20 2004-12-09 Sharp Corp Semiconductor memory device
US7492006B2 (en) * 2004-08-30 2009-02-17 Samsung Electronics Co., Ltd. Semiconductor transistors having surface insulation layers and methods of fabricating such transistors
TWI287868B (en) * 2005-11-17 2007-10-01 Ememory Technology Inc Single-poly non-volatile memory device
TWI333691B (en) * 2006-05-23 2010-11-21 Ememory Technology Inc Nonvolatile memory with twin gate and method of operating the same
JP5040286B2 (en) * 2006-12-13 2012-10-03 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method of semiconductor device
US7696036B2 (en) 2007-06-14 2010-04-13 International Business Machines Corporation CMOS transistors with differential oxygen content high-k dielectrics
KR101129835B1 (en) 2009-09-21 2012-03-23 주식회사 하이닉스반도체 Semiconductor Device And Method for Manufacturing the same
KR20130117130A (en) 2012-04-17 2013-10-25 삼성전자주식회사 Gate structure in non-volatile memory device
US9029959B2 (en) 2012-06-29 2015-05-12 International Business Machines Corporation Composite high-k gate dielectric stack for reducing gate leakage
US9034703B2 (en) 2012-09-13 2015-05-19 International Business Machines Corporation Self aligned contact with improved robustness

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI720283B (en) * 2017-10-03 2021-03-01 新加坡商格羅方德半導體私人有限公司 Sidewall engineering for enhanced device performance in advanced devices
TWI758821B (en) * 2020-02-19 2022-03-21 日商鎧俠股份有限公司 Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
US9608066B1 (en) 2017-03-28

Similar Documents

Publication Publication Date Title
US11410993B2 (en) Method of manufacturing semiconductor device
US10971406B2 (en) Method of forming source/drain regions of transistors
US9608066B1 (en) High-K spacer for extension-free CMOS devices with high mobility channel materials
US11139215B2 (en) Hybrid gate stack integration for stacked vertical transport field-effect transistors
US9698057B2 (en) Method of manufacturing strained source/drain structures
US9558946B2 (en) FinFETs and methods of forming FinFETs
US9349831B2 (en) Integrated circuit device with well controlled surface proximity and method of manufacturing same
US9543209B2 (en) Non-planar transistors with replacement fins and methods of forming the same
US8216906B2 (en) Method of manufacturing integrated circuit device with well controlled surface proximity
US20190214343A1 (en) Replacement metal gate processes for vertical transport field-effect transistor
US10734504B2 (en) Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures
US20160268256A1 (en) Complementary metal-oxide semiconductor (cmos) transistor and tunnel field-effect transistor (tfet) on a single substrate
US20130119370A1 (en) Strained structures of semiconductor devices
US10134760B2 (en) FinFETs with various fin height
KR20150130984A (en) Leakage reduction structures for nanowire transistors
US9865505B2 (en) Method for reducing N-type FinFET source and drain resistance
US20140264493A1 (en) Semiconductor Device and Fabricating the Same
US9437740B2 (en) Epitaxially forming a set of fins in a semiconductor device
US9899273B1 (en) Semiconductor structure with dopants diffuse protection and method for forming the same
US20150287600A1 (en) Hybrid III-V Technology to Support Multiple Supply Voltages and Off State Currents on Same Chip
US10811322B1 (en) Different gate widths for upper and lower transistors in a stacked vertical transport field-effect transistor structure

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ANDO, TAKASHI;HASHEMI, POUYA;NARAYANAN, VIJAY;AND OTHERS;SIGNING DATES FROM 20150924 TO 20150925;REEL/FRAME:036683/0801

STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: ELPIS TECHNOLOGIES INC., CANADA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:052620/0961

Effective date: 20200306

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20210328